/*************************************************************************
 * @file     soc_bitfield.h
 * @brief    
 * @version  V1.8.0
 * @date     31-Dec-2021
 *
 * @note
 * Copyright (c) [2014-2021] Spintrol Limited. All Rights Reserved. 
 *
 * @attention
 * THIS SOFTWARE JUST PROVIDES CUSTOMERS WITH CODING INFORMATION
 * REGARDING THEIR PRODUCTS, WHICH AIMS AT SAVING TIME FOR THEM.
 * SPINTROL SHALL NOT BE LIABLE FOR THE USE OF THE SOFTWARE. SPINTROL
 * DOES NOT GUARANTEE THE CORRECTNESS OF THIS SOFTWARE AND RESERVES THE
 * RIGHT TO MODIFY THE SOFTWARE WITHOUT NOTIFICATION.
 * 
 ************************************************************************/


#ifndef __SPC1168_BITFIELD_H__
#define __SPC1168_BITFIELD_H__


#ifndef SPC1168_BITFIELD_H
#define SPC1168_BITFIELD_H

#ifdef __cplusplus
extern "C" {
#endif



/********************************************************************************
*
* Module Name     SYSTEM
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          CID0            VAL
 *  @access     SYSTEM->CID0.bit.VAL
 *  @brief      32 LSBs of the 64-bit chip ID
 */
#define CID0_ALL_VAL_Pos (0)
#define CID0_ALL_VAL_Msk (0xFFFFFFFFUL << CID0_ALL_VAL_Pos)

#define CID0_BIT_VAL

#define CID0_ALL_VAL_(x) ((x) << CID0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          CID1            VAL
 *  @access     SYSTEM->CID1.bit.VAL
 *  @brief      32 MSBs of the 64-bit chip ID
 */
#define CID1_ALL_VAL_Pos (0)
#define CID1_ALL_VAL_Msk (0xFFFFFFFFUL << CID1_ALL_VAL_Pos)

#define CID1_BIT_VAL

#define CID1_ALL_VAL_(x) ((x) << CID1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          UID0            VAL
 *  @access     SYSTEM->UID0.bit.VAL
 *  @brief      32 LSBs of the 64-bit unique ID
 */
#define UID0_ALL_VAL_Pos (0)
#define UID0_ALL_VAL_Msk (0xFFFFFFFFUL << UID0_ALL_VAL_Pos)

#define UID0_BIT_VAL

#define UID0_ALL_VAL_(x) ((x) << UID0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          UID1            VAL
 *  @access     SYSTEM->UID1.bit.VAL
 *  @brief      32 MSBs of the 64-bit unique ID
 */
#define UID1_ALL_VAL_Pos (0)
#define UID1_ALL_VAL_Msk (0xFFFFFFFFUL << UID1_ALL_VAL_Pos)

#define UID1_BIT_VAL

#define UID1_ALL_VAL_(x) ((x) << UID1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RND0            VAL
 *  @access     SYSTEM->RND0.bit.VAL
 *  @brief      32 LSBs of the 64-bit random number
 */
#define RND0_ALL_VAL_Pos (0)
#define RND0_ALL_VAL_Msk (0xFFFFFFFFUL << RND0_ALL_VAL_Pos)

#define RND0_BIT_VAL

#define RND0_ALL_VAL_(x) ((x) << RND0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RND1            VAL
 *  @access     SYSTEM->RND1.bit.VAL
 *  @brief      32 MSBs of the 64-bit random number
 */
#define RND1_ALL_VAL_Pos (0)
#define RND1_ALL_VAL_Msk (0xFFFFFFFFUL << RND1_ALL_VAL_Pos)

#define RND1_BIT_VAL

#define RND1_ALL_VAL_(x) ((x) << RND1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          REV0            VAL
 *  @access     SYSTEM->REV0.bit.VAL
 *  @brief      32 LSBs of the 64-bit revision number
 */
#define REV0_ALL_VAL_Pos (0)
#define REV0_ALL_VAL_Msk (0xFFFFFFFFUL << REV0_ALL_VAL_Pos)

#define REV0_BIT_VAL

#define REV0_ALL_VAL_(x) ((x) << REV0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          REV1            VAL
 *  @access     SYSTEM->REV1.bit.VAL
 *  @brief      32 MSBs of the 64-bit revision number
 */
#define REV1_ALL_VAL_Pos (0)
#define REV1_ALL_VAL_Msk (0xFFFFFFFFUL << REV1_ALL_VAL_Pos)

#define REV1_BIT_VAL

#define REV1_ALL_VAL_(x) ((x) << REV1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIF           ROM1ERR
 *  @access     SYSTEM->MEMIF.bit.ROM1ERR
 *  @brief      Latched ROM ECC 1-bit error flag
 */
#define MEMIF_ALL_ROM1ERR_Pos (0)
#define MEMIF_ALL_ROM1ERR_Msk (0x1UL << MEMIF_ALL_ROM1ERR_Pos)

typedef enum
{
    MEMIF_BIT_ROM1ERR_NOT_OCCUR     = 0,  /*!< ROM1ERR interrupt not occur   */
    MEMIF_BIT_ROM1ERR_OCCUR         = 1,  /*!< ROM1ERR interrupt occurred    */
} MEMIF_BIT_ROM1ERR;

#define MEMIF_ALL_ROM1ERR_NOT_OCCUR     ((0x0UL) << MEMIF_ALL_ROM1ERR_Pos)
#define MEMIF_ALL_ROM1ERR_OCCUR         ((0x1UL) << MEMIF_ALL_ROM1ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIF           ROM2ERR
 *  @access     SYSTEM->MEMIF.bit.ROM2ERR
 *  @brief      Latched ROM ECC 2-bit error flag
 */
#define MEMIF_ALL_ROM2ERR_Pos (1)
#define MEMIF_ALL_ROM2ERR_Msk (0x1UL << MEMIF_ALL_ROM2ERR_Pos)

typedef enum
{
    MEMIF_BIT_ROM2ERR_NOT_OCCUR     = 0,  /*!< ROM2ERR interrupt not occur   */
    MEMIF_BIT_ROM2ERR_OCCUR         = 1,  /*!< ROM2ERR interrupt occurred    */
} MEMIF_BIT_ROM2ERR;

#define MEMIF_ALL_ROM2ERR_NOT_OCCUR     ((0x0UL) << MEMIF_ALL_ROM2ERR_Pos)
#define MEMIF_ALL_ROM2ERR_OCCUR         ((0x1UL) << MEMIF_ALL_ROM2ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIF           FLASH1ERR
 *  @access     SYSTEM->MEMIF.bit.FLASH1ERR
 *  @brief      Latched flash ECC 1-bit error flag
 */
#define MEMIF_ALL_FLASH1ERR_Pos (2)
#define MEMIF_ALL_FLASH1ERR_Msk (0x1UL << MEMIF_ALL_FLASH1ERR_Pos)

typedef enum
{
    MEMIF_BIT_FLASH1ERR_NOT_OCCUR     = 0,  /*!< FLASH1ERR interrupt not occur   */
    MEMIF_BIT_FLASH1ERR_OCCUR         = 1,  /*!< FLASH1ERR interrupt occurred    */
} MEMIF_BIT_FLASH1ERR;

#define MEMIF_ALL_FLASH1ERR_NOT_OCCUR     ((0x0UL) << MEMIF_ALL_FLASH1ERR_Pos)
#define MEMIF_ALL_FLASH1ERR_OCCUR         ((0x1UL) << MEMIF_ALL_FLASH1ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIF           FLASH2ERR
 *  @access     SYSTEM->MEMIF.bit.FLASH2ERR
 *  @brief      Latched flash ECC 2-bit error flag
 */
#define MEMIF_ALL_FLASH2ERR_Pos (3)
#define MEMIF_ALL_FLASH2ERR_Msk (0x1UL << MEMIF_ALL_FLASH2ERR_Pos)

typedef enum
{
    MEMIF_BIT_FLASH2ERR_NOT_OCCUR     = 0,  /*!< FLASH2ERR interrupt not occur   */
    MEMIF_BIT_FLASH2ERR_OCCUR         = 1,  /*!< FLASH2ERR interrupt occurred    */
} MEMIF_BIT_FLASH2ERR;

#define MEMIF_ALL_FLASH2ERR_NOT_OCCUR     ((0x0UL) << MEMIF_ALL_FLASH2ERR_Pos)
#define MEMIF_ALL_FLASH2ERR_OCCUR         ((0x1UL) << MEMIF_ALL_FLASH2ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIF           IRAMERR
 *  @access     SYSTEM->MEMIF.bit.IRAMERR
 *  @brief      Latched instruction RAM parity error flag
 */
#define MEMIF_ALL_IRAMERR_Pos (4)
#define MEMIF_ALL_IRAMERR_Msk (0x1UL << MEMIF_ALL_IRAMERR_Pos)

typedef enum
{
    MEMIF_BIT_IRAMERR_NOT_OCCUR     = 0,  /*!< IRAMERR interrupt not occur   */
    MEMIF_BIT_IRAMERR_OCCUR         = 1,  /*!< IRAMERR interrupt occurred    */
} MEMIF_BIT_IRAMERR;

#define MEMIF_ALL_IRAMERR_NOT_OCCUR     ((0x0UL) << MEMIF_ALL_IRAMERR_Pos)
#define MEMIF_ALL_IRAMERR_OCCUR         ((0x1UL) << MEMIF_ALL_IRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIF           DRAMERR
 *  @access     SYSTEM->MEMIF.bit.DRAMERR
 *  @brief      Latched data RAM parity error flag
 */
#define MEMIF_ALL_DRAMERR_Pos (5)
#define MEMIF_ALL_DRAMERR_Msk (0x1UL << MEMIF_ALL_DRAMERR_Pos)

typedef enum
{
    MEMIF_BIT_DRAMERR_NOT_OCCUR     = 0,  /*!< DRAMERR interrupt not occur   */
    MEMIF_BIT_DRAMERR_OCCUR         = 1,  /*!< DRAMERR interrupt occurred    */
} MEMIF_BIT_DRAMERR;

#define MEMIF_ALL_DRAMERR_NOT_OCCUR     ((0x0UL) << MEMIF_ALL_DRAMERR_Pos)
#define MEMIF_ALL_DRAMERR_OCCUR         ((0x1UL) << MEMIF_ALL_DRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIF           SIOERR
 *  @access     SYSTEM->MEMIF.bit.SIOERR
 *  @brief      Latched SIO memory parity error flag
 */
#define MEMIF_ALL_SIOERR_Pos (6)
#define MEMIF_ALL_SIOERR_Msk (0x1UL << MEMIF_ALL_SIOERR_Pos)

typedef enum
{
    MEMIF_BIT_SIOERR_NOT_OCCUR     = 0,  /*!< SIOERR interrupt not occur   */
    MEMIF_BIT_SIOERR_OCCUR         = 1,  /*!< SIOERR interrupt occurred    */
} MEMIF_BIT_SIOERR;

#define MEMIF_ALL_SIOERR_NOT_OCCUR     ((0x0UL) << MEMIF_ALL_SIOERR_Pos)
#define MEMIF_ALL_SIOERR_OCCUR         ((0x1UL) << MEMIF_ALL_SIOERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIF           MEMINT
 *  @access     SYSTEM->MEMIF.bit.MEMINT
 *  @brief      Memory error interrupt flag
 */
#define MEMIF_ALL_MEMINT_Pos (7)
#define MEMIF_ALL_MEMINT_Msk (0x1UL << MEMIF_ALL_MEMINT_Pos)

typedef enum
{
    MEMIF_BIT_MEMINT_NOT_OCCUR     = 0,  /*!< Memory error interrupt not occur   */
    MEMIF_BIT_MEMINT_OCCUR         = 1,  /*!< Memory error interrupt occurred    */
} MEMIF_BIT_MEMINT;

#define MEMIF_ALL_MEMINT_NOT_OCCUR     ((0x0UL) << MEMIF_ALL_MEMINT_Pos)
#define MEMIF_ALL_MEMINT_OCCUR         ((0x1UL) << MEMIF_ALL_MEMINT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIC           ROM1ERR
 *  @access     SYSTEM->MEMIC.bit.ROM1ERR
 *  @brief      ROM access one-bit error occurred flag clear
 */
#define MEMIC_ALL_ROM1ERR_Pos (0)
#define MEMIC_ALL_ROM1ERR_Msk (0x1UL << MEMIC_ALL_ROM1ERR_Pos)

typedef enum
{
    MEMIC_BIT_ROM1ERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.        
                                               Always readback 0.               */
    MEMIC_BIT_ROM1ERR_CLEAR         = 1,  /*!< Write a 1 clear the flag.       
                                               This bit is self-cleared to 0.   */
} MEMIC_BIT_ROM1ERR;

#define MEMIC_ALL_ROM1ERR_NO_EFFECT     ((0x0UL) << MEMIC_ALL_ROM1ERR_Pos)
#define MEMIC_ALL_ROM1ERR_CLEAR         ((0x1UL) << MEMIC_ALL_ROM1ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIC           ROM2ERR
 *  @access     SYSTEM->MEMIC.bit.ROM2ERR
 *  @brief      ROM access two-bit error occurred flag clear
 */
#define MEMIC_ALL_ROM2ERR_Pos (1)
#define MEMIC_ALL_ROM2ERR_Msk (0x1UL << MEMIC_ALL_ROM2ERR_Pos)

typedef enum
{
    MEMIC_BIT_ROM2ERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.        
                                               Always readback 0.               */
    MEMIC_BIT_ROM2ERR_CLEAR         = 1,  /*!< Write a 1 clear the flag.       
                                               This bit is self-cleared to 0.   */
} MEMIC_BIT_ROM2ERR;

#define MEMIC_ALL_ROM2ERR_NO_EFFECT     ((0x0UL) << MEMIC_ALL_ROM2ERR_Pos)
#define MEMIC_ALL_ROM2ERR_CLEAR         ((0x1UL) << MEMIC_ALL_ROM2ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIC           FLASH1ERR
 *  @access     SYSTEM->MEMIC.bit.FLASH1ERR
 *  @brief      Flash access one-bit error occurred flag clear
 */
#define MEMIC_ALL_FLASH1ERR_Pos (2)
#define MEMIC_ALL_FLASH1ERR_Msk (0x1UL << MEMIC_ALL_FLASH1ERR_Pos)

typedef enum
{
    MEMIC_BIT_FLASH1ERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.        
                                                 Always readback 0.               */
    MEMIC_BIT_FLASH1ERR_CLEAR         = 1,  /*!< Write a 1 clear the flag.       
                                                 This bit is self-cleared to 0.   */
} MEMIC_BIT_FLASH1ERR;

#define MEMIC_ALL_FLASH1ERR_NO_EFFECT     ((0x0UL) << MEMIC_ALL_FLASH1ERR_Pos)
#define MEMIC_ALL_FLASH1ERR_CLEAR         ((0x1UL) << MEMIC_ALL_FLASH1ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIC           FLASH2ERR
 *  @access     SYSTEM->MEMIC.bit.FLASH2ERR
 *  @brief      Flash access two-bit error occurred flag clear
 */
#define MEMIC_ALL_FLASH2ERR_Pos (3)
#define MEMIC_ALL_FLASH2ERR_Msk (0x1UL << MEMIC_ALL_FLASH2ERR_Pos)

typedef enum
{
    MEMIC_BIT_FLASH2ERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.        
                                                 Always readback 0.               */
    MEMIC_BIT_FLASH2ERR_CLEAR         = 1,  /*!< Write a 1 clear the flag.       
                                                 This bit is self-cleared to 0.   */
} MEMIC_BIT_FLASH2ERR;

#define MEMIC_ALL_FLASH2ERR_NO_EFFECT     ((0x0UL) << MEMIC_ALL_FLASH2ERR_Pos)
#define MEMIC_ALL_FLASH2ERR_CLEAR         ((0x1UL) << MEMIC_ALL_FLASH2ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIC           IRAMERR
 *  @access     SYSTEM->MEMIC.bit.IRAMERR
 *  @brief      Instruction RAM parity error occurred flag clear
 */
#define MEMIC_ALL_IRAMERR_Pos (4)
#define MEMIC_ALL_IRAMERR_Msk (0x1UL << MEMIC_ALL_IRAMERR_Pos)

typedef enum
{
    MEMIC_BIT_IRAMERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.        
                                               Always readback 0.               */
    MEMIC_BIT_IRAMERR_CLEAR         = 1,  /*!< Write a 1 clear the flag.       
                                               This bit is self-cleared to 0.   */
} MEMIC_BIT_IRAMERR;

#define MEMIC_ALL_IRAMERR_NO_EFFECT     ((0x0UL) << MEMIC_ALL_IRAMERR_Pos)
#define MEMIC_ALL_IRAMERR_CLEAR         ((0x1UL) << MEMIC_ALL_IRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIC           DRAMERR
 *  @access     SYSTEM->MEMIC.bit.DRAMERR
 *  @brief      Data RAM parity error occurred flag clear
 */
#define MEMIC_ALL_DRAMERR_Pos (5)
#define MEMIC_ALL_DRAMERR_Msk (0x1UL << MEMIC_ALL_DRAMERR_Pos)

typedef enum
{
    MEMIC_BIT_DRAMERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.        
                                               Always readback 0.               */
    MEMIC_BIT_DRAMERR_CLEAR         = 1,  /*!< Write a 1 clear the flag.       
                                               This bit is self-cleared to 0.   */
} MEMIC_BIT_DRAMERR;

#define MEMIC_ALL_DRAMERR_NO_EFFECT     ((0x0UL) << MEMIC_ALL_DRAMERR_Pos)
#define MEMIC_ALL_DRAMERR_CLEAR         ((0x1UL) << MEMIC_ALL_DRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIC           SIOERR
 *  @access     SYSTEM->MEMIC.bit.SIOERR
 *  @brief      SIO access parity error occurred flag clear
 */
#define MEMIC_ALL_SIOERR_Pos (6)
#define MEMIC_ALL_SIOERR_Msk (0x1UL << MEMIC_ALL_SIOERR_Pos)

typedef enum
{
    MEMIC_BIT_SIOERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.        
                                              Always readback 0.               */
    MEMIC_BIT_SIOERR_CLEAR         = 1,  /*!< Write a 1 clear the flag.       
                                              This bit is self-cleared to 0.   */
} MEMIC_BIT_SIOERR;

#define MEMIC_ALL_SIOERR_NO_EFFECT     ((0x0UL) << MEMIC_ALL_SIOERR_Pos)
#define MEMIC_ALL_SIOERR_CLEAR         ((0x1UL) << MEMIC_ALL_SIOERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIC           MEMINT
 *  @access     SYSTEM->MEMIC.bit.MEMINT
 *  @brief      Memory error interrupt clear
 */
#define MEMIC_ALL_MEMINT_Pos (7)
#define MEMIC_ALL_MEMINT_Msk (0x1UL << MEMIC_ALL_MEMINT_Pos)

typedef enum
{
    MEMIC_BIT_MEMINT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                              Always readback 0.                           */
    MEMIC_BIT_MEMINT_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                              This bit is self-cleared to 0.               */
} MEMIC_BIT_MEMINT;

#define MEMIC_ALL_MEMINT_NO_EFFECT     ((0x0UL) << MEMIC_ALL_MEMINT_Pos)
#define MEMIC_ALL_MEMINT_CLEAR         ((0x1UL) << MEMIC_ALL_MEMINT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIE           ROM1ERR
 *  @access     SYSTEM->MEMIE.bit.ROM1ERR
 *  @brief      ROM access one-bit error interrupt enable
 */
#define MEMIE_ALL_ROM1ERR_Pos (0)
#define MEMIE_ALL_ROM1ERR_Msk (0x1UL << MEMIE_ALL_ROM1ERR_Pos)

typedef enum
{
    MEMIE_BIT_ROM1ERR_DISABLE     = 0,  /*!< Disable   */
    MEMIE_BIT_ROM1ERR_ENABLE      = 1,  /*!< Enable    */
} MEMIE_BIT_ROM1ERR;

#define MEMIE_ALL_ROM1ERR_DISABLE     ((0x0UL) << MEMIE_ALL_ROM1ERR_Pos)
#define MEMIE_ALL_ROM1ERR_ENABLE      ((0x1UL) << MEMIE_ALL_ROM1ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIE           ROM2ERR
 *  @access     SYSTEM->MEMIE.bit.ROM2ERR
 *  @brief      ROM access two-bit error interrupt enable
 */
#define MEMIE_ALL_ROM2ERR_Pos (1)
#define MEMIE_ALL_ROM2ERR_Msk (0x1UL << MEMIE_ALL_ROM2ERR_Pos)

typedef enum
{
    MEMIE_BIT_ROM2ERR_DISABLE     = 0,  /*!< Disable   */
    MEMIE_BIT_ROM2ERR_ENABLE      = 1,  /*!< Enable    */
} MEMIE_BIT_ROM2ERR;

#define MEMIE_ALL_ROM2ERR_DISABLE     ((0x0UL) << MEMIE_ALL_ROM2ERR_Pos)
#define MEMIE_ALL_ROM2ERR_ENABLE      ((0x1UL) << MEMIE_ALL_ROM2ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIE           FLASH1ERR
 *  @access     SYSTEM->MEMIE.bit.FLASH1ERR
 *  @brief      Flash access one-bit error interrupt enable
 */
#define MEMIE_ALL_FLASH1ERR_Pos (2)
#define MEMIE_ALL_FLASH1ERR_Msk (0x1UL << MEMIE_ALL_FLASH1ERR_Pos)

typedef enum
{
    MEMIE_BIT_FLASH1ERR_DISABLE     = 0,  /*!< Disable   */
    MEMIE_BIT_FLASH1ERR_ENABLE      = 1,  /*!< Enable    */
} MEMIE_BIT_FLASH1ERR;

#define MEMIE_ALL_FLASH1ERR_DISABLE     ((0x0UL) << MEMIE_ALL_FLASH1ERR_Pos)
#define MEMIE_ALL_FLASH1ERR_ENABLE      ((0x1UL) << MEMIE_ALL_FLASH1ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIE           FLASH2ERR
 *  @access     SYSTEM->MEMIE.bit.FLASH2ERR
 *  @brief      Flash access two-bit error interrupt enable
 */
#define MEMIE_ALL_FLASH2ERR_Pos (3)
#define MEMIE_ALL_FLASH2ERR_Msk (0x1UL << MEMIE_ALL_FLASH2ERR_Pos)

typedef enum
{
    MEMIE_BIT_FLASH2ERR_DISABLE     = 0,  /*!< Disable   */
    MEMIE_BIT_FLASH2ERR_ENABLE      = 1,  /*!< Enable    */
} MEMIE_BIT_FLASH2ERR;

#define MEMIE_ALL_FLASH2ERR_DISABLE     ((0x0UL) << MEMIE_ALL_FLASH2ERR_Pos)
#define MEMIE_ALL_FLASH2ERR_ENABLE      ((0x1UL) << MEMIE_ALL_FLASH2ERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIE           IRAMERR
 *  @access     SYSTEM->MEMIE.bit.IRAMERR
 *  @brief      Instruction RAM parity error interrupt enable
 */
#define MEMIE_ALL_IRAMERR_Pos (4)
#define MEMIE_ALL_IRAMERR_Msk (0x1UL << MEMIE_ALL_IRAMERR_Pos)

typedef enum
{
    MEMIE_BIT_IRAMERR_DISABLE     = 0,  /*!< Disable   */
    MEMIE_BIT_IRAMERR_ENABLE      = 1,  /*!< Enable    */
} MEMIE_BIT_IRAMERR;

#define MEMIE_ALL_IRAMERR_DISABLE     ((0x0UL) << MEMIE_ALL_IRAMERR_Pos)
#define MEMIE_ALL_IRAMERR_ENABLE      ((0x1UL) << MEMIE_ALL_IRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIE           DRAMERR
 *  @access     SYSTEM->MEMIE.bit.DRAMERR
 *  @brief      Data RAM parity error interrupt enable
 */
#define MEMIE_ALL_DRAMERR_Pos (5)
#define MEMIE_ALL_DRAMERR_Msk (0x1UL << MEMIE_ALL_DRAMERR_Pos)

typedef enum
{
    MEMIE_BIT_DRAMERR_DISABLE     = 0,  /*!< Disable   */
    MEMIE_BIT_DRAMERR_ENABLE      = 1,  /*!< Enable    */
} MEMIE_BIT_DRAMERR;

#define MEMIE_ALL_DRAMERR_DISABLE     ((0x0UL) << MEMIE_ALL_DRAMERR_Pos)
#define MEMIE_ALL_DRAMERR_ENABLE      ((0x1UL) << MEMIE_ALL_DRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMIE           SIOERR
 *  @access     SYSTEM->MEMIE.bit.SIOERR
 *  @brief      SIO access parity error interrupt enable
 */
#define MEMIE_ALL_SIOERR_Pos (6)
#define MEMIE_ALL_SIOERR_Msk (0x1UL << MEMIE_ALL_SIOERR_Pos)

typedef enum
{
    MEMIE_BIT_SIOERR_DISABLE     = 0,  /*!< Disable   */
    MEMIE_BIT_SIOERR_ENABLE      = 1,  /*!< Enable    */
} MEMIE_BIT_SIOERR;

#define MEMIE_ALL_SIOERR_DISABLE     ((0x0UL) << MEMIE_ALL_SIOERR_Pos)
#define MEMIE_ALL_SIOERR_ENABLE      ((0x1UL) << MEMIE_ALL_SIOERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMECCEN        ROMECC
 *  @access     SYSTEM->MEMECCEN.bit.ROMECC
 *  @brief      ROM ECC enable
 */
#define MEMECCEN_ALL_ROMECC_Pos (0)
#define MEMECCEN_ALL_ROMECC_Msk (0x1UL << MEMECCEN_ALL_ROMECC_Pos)

typedef enum
{
    MEMECCEN_BIT_ROMECC_DISABLE     = 0,  /*!< Disable   */
    MEMECCEN_BIT_ROMECC_ENABLE      = 1,  /*!< Enable    */
} MEMECCEN_BIT_ROMECC;

#define MEMECCEN_ALL_ROMECC_DISABLE     ((0x0UL) << MEMECCEN_ALL_ROMECC_Pos)
#define MEMECCEN_ALL_ROMECC_ENABLE      ((0x1UL) << MEMECCEN_ALL_ROMECC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMECCEN        FLASHECC
 *  @access     SYSTEM->MEMECCEN.bit.FLASHECC
 *  @brief      FLASH ECC enable
 */
#define MEMECCEN_ALL_FLASHECC_Pos (1)
#define MEMECCEN_ALL_FLASHECC_Msk (0x1UL << MEMECCEN_ALL_FLASHECC_Pos)

typedef enum
{
    MEMECCEN_BIT_FLASHECC_DISABLE     = 0,  /*!< Disable   */
    MEMECCEN_BIT_FLASHECC_ENABLE      = 1,  /*!< Enable    */
} MEMECCEN_BIT_FLASHECC;

#define MEMECCEN_ALL_FLASHECC_DISABLE     ((0x0UL) << MEMECCEN_ALL_FLASHECC_Pos)
#define MEMECCEN_ALL_FLASHECC_ENABLE      ((0x1UL) << MEMECCEN_ALL_FLASHECC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      FLASH0
 *  @access     SYSTEM->MEMLOCKSTS.bit.FLASH0
 *  @brief      FLASH region 0
 */
#define MEMLOCKSTS_ALL_FLASH0_Pos (0)
#define MEMLOCKSTS_ALL_FLASH0_Msk (0x1UL << MEMLOCKSTS_ALL_FLASH0_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_FLASH0_UNLOCK     = 0,  /*!< Can read/write content and execute         */
    MEMLOCKSTS_BIT_FLASH0_LOCK       = 1,  /*!< Can not read/write content, just execute   */
} MEMLOCKSTS_BIT_FLASH0;

#define MEMLOCKSTS_ALL_FLASH0_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_FLASH0_Pos)
#define MEMLOCKSTS_ALL_FLASH0_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_FLASH0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      FLASH1
 *  @access     SYSTEM->MEMLOCKSTS.bit.FLASH1
 *  @brief      FLASH region 1
 */
#define MEMLOCKSTS_ALL_FLASH1_Pos (1)
#define MEMLOCKSTS_ALL_FLASH1_Msk (0x1UL << MEMLOCKSTS_ALL_FLASH1_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_FLASH1_UNLOCK     = 0,  /*!< Can read/write content and execute         */
    MEMLOCKSTS_BIT_FLASH1_LOCK       = 1,  /*!< Can not read/write content, just execute   */
} MEMLOCKSTS_BIT_FLASH1;

#define MEMLOCKSTS_ALL_FLASH1_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_FLASH1_Pos)
#define MEMLOCKSTS_ALL_FLASH1_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_FLASH1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      FLASH2
 *  @access     SYSTEM->MEMLOCKSTS.bit.FLASH2
 *  @brief      FLASH region 2
 */
#define MEMLOCKSTS_ALL_FLASH2_Pos (2)
#define MEMLOCKSTS_ALL_FLASH2_Msk (0x1UL << MEMLOCKSTS_ALL_FLASH2_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_FLASH2_UNLOCK     = 0,  /*!< Can read/write content and execute         */
    MEMLOCKSTS_BIT_FLASH2_LOCK       = 1,  /*!< Can not read/write content, just execute   */
} MEMLOCKSTS_BIT_FLASH2;

#define MEMLOCKSTS_ALL_FLASH2_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_FLASH2_Pos)
#define MEMLOCKSTS_ALL_FLASH2_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_FLASH2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      FLASH3
 *  @access     SYSTEM->MEMLOCKSTS.bit.FLASH3
 *  @brief      FLASH region 3
 */
#define MEMLOCKSTS_ALL_FLASH3_Pos (3)
#define MEMLOCKSTS_ALL_FLASH3_Msk (0x1UL << MEMLOCKSTS_ALL_FLASH3_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_FLASH3_UNLOCK     = 0,  /*!< Can read/write content and execute         */
    MEMLOCKSTS_BIT_FLASH3_LOCK       = 1,  /*!< Can not read/write content, just execute   */
} MEMLOCKSTS_BIT_FLASH3;

#define MEMLOCKSTS_ALL_FLASH3_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_FLASH3_Pos)
#define MEMLOCKSTS_ALL_FLASH3_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_FLASH3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      USER0INFO
 *  @access     SYSTEM->MEMLOCKSTS.bit.USER0INFO
 *  @brief      Lock Flash NVR4
 */
#define MEMLOCKSTS_ALL_USER0INFO_Pos (4)
#define MEMLOCKSTS_ALL_USER0INFO_Msk (0x1UL << MEMLOCKSTS_ALL_USER0INFO_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_USER0INFO_UNLOCK     = 0,  /*!< Can read, write and erase            */
    MEMLOCKSTS_BIT_USER0INFO_LOCK       = 1,  /*!< Read and erase only, can not write   */
} MEMLOCKSTS_BIT_USER0INFO;

#define MEMLOCKSTS_ALL_USER0INFO_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_USER0INFO_Pos)
#define MEMLOCKSTS_ALL_USER0INFO_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_USER0INFO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      USER1INFO
 *  @access     SYSTEM->MEMLOCKSTS.bit.USER1INFO
 *  @brief      Lock Flash NVR4
 */
#define MEMLOCKSTS_ALL_USER1INFO_Pos (5)
#define MEMLOCKSTS_ALL_USER1INFO_Msk (0x1UL << MEMLOCKSTS_ALL_USER1INFO_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_USER1INFO_UNLOCK     = 0,  /*!< Can read, write and erase            */
    MEMLOCKSTS_BIT_USER1INFO_LOCK       = 1,  /*!< Read and erase only, can not write   */
} MEMLOCKSTS_BIT_USER1INFO;

#define MEMLOCKSTS_ALL_USER1INFO_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_USER1INFO_Pos)
#define MEMLOCKSTS_ALL_USER1INFO_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_USER1INFO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      USER2INFO
 *  @access     SYSTEM->MEMLOCKSTS.bit.USER2INFO
 *  @brief      Lock Flash NVR4
 */
#define MEMLOCKSTS_ALL_USER2INFO_Pos (6)
#define MEMLOCKSTS_ALL_USER2INFO_Msk (0x1UL << MEMLOCKSTS_ALL_USER2INFO_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_USER2INFO_UNLOCK     = 0,  /*!< Can read, write and erase            */
    MEMLOCKSTS_BIT_USER2INFO_LOCK       = 1,  /*!< Read and erase only, can not write   */
} MEMLOCKSTS_BIT_USER2INFO;

#define MEMLOCKSTS_ALL_USER2INFO_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_USER2INFO_Pos)
#define MEMLOCKSTS_ALL_USER2INFO_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_USER2INFO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      USER3INFO
 *  @access     SYSTEM->MEMLOCKSTS.bit.USER3INFO
 *  @brief      Lock Flash NVR4
 */
#define MEMLOCKSTS_ALL_USER3INFO_Pos (7)
#define MEMLOCKSTS_ALL_USER3INFO_Msk (0x1UL << MEMLOCKSTS_ALL_USER3INFO_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_USER3INFO_UNLOCK     = 0,  /*!< Can read, write and erase            */
    MEMLOCKSTS_BIT_USER3INFO_LOCK       = 1,  /*!< Read and erase only, can not write   */
} MEMLOCKSTS_BIT_USER3INFO;

#define MEMLOCKSTS_ALL_USER3INFO_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_USER3INFO_Pos)
#define MEMLOCKSTS_ALL_USER3INFO_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_USER3INFO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      FLASHOTP
 *  @access     SYSTEM->MEMLOCKSTS.bit.FLASHOTP
 *  @brief      Lock Flash NVR3
 */
#define MEMLOCKSTS_ALL_FLASHOTP_Pos (8)
#define MEMLOCKSTS_ALL_FLASHOTP_Msk (0x1UL << MEMLOCKSTS_ALL_FLASHOTP_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_FLASHOTP_UNLOCK     = 0,  /*!< Can read, write and erase FLASHNVR3   */
    MEMLOCKSTS_BIT_FLASHOTP_LOCK       = 1,  /*!< FLASHNVR3 is read-only                */
} MEMLOCKSTS_BIT_FLASHOTP;

#define MEMLOCKSTS_ALL_FLASHOTP_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_FLASHOTP_Pos)
#define MEMLOCKSTS_ALL_FLASHOTP_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_FLASHOTP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      RAM0
 *  @access     SYSTEM->MEMLOCKSTS.bit.RAM0
 *  @brief      RAM region 0
 */
#define MEMLOCKSTS_ALL_RAM0_Pos (9)
#define MEMLOCKSTS_ALL_RAM0_Msk (0x1UL << MEMLOCKSTS_ALL_RAM0_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_RAM0_UNLOCK     = 0,  /*!< Can read/write content and execute         */
    MEMLOCKSTS_BIT_RAM0_LOCK       = 1,  /*!< Can not read/write content, just execute   */
} MEMLOCKSTS_BIT_RAM0;

#define MEMLOCKSTS_ALL_RAM0_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_RAM0_Pos)
#define MEMLOCKSTS_ALL_RAM0_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_RAM0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      RAM1
 *  @access     SYSTEM->MEMLOCKSTS.bit.RAM1
 *  @brief      RAM region 1
 */
#define MEMLOCKSTS_ALL_RAM1_Pos (10)
#define MEMLOCKSTS_ALL_RAM1_Msk (0x1UL << MEMLOCKSTS_ALL_RAM1_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_RAM1_UNLOCK     = 0,  /*!< Can read/write content and execute         */
    MEMLOCKSTS_BIT_RAM1_LOCK       = 1,  /*!< Can not read/write content, just execute   */
} MEMLOCKSTS_BIT_RAM1;

#define MEMLOCKSTS_ALL_RAM1_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_RAM1_Pos)
#define MEMLOCKSTS_ALL_RAM1_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_RAM1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      RAM2
 *  @access     SYSTEM->MEMLOCKSTS.bit.RAM2
 *  @brief      RAM region 2
 */
#define MEMLOCKSTS_ALL_RAM2_Pos (11)
#define MEMLOCKSTS_ALL_RAM2_Msk (0x1UL << MEMLOCKSTS_ALL_RAM2_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_RAM2_UNLOCK     = 0,  /*!< Can read/write content and execute         */
    MEMLOCKSTS_BIT_RAM2_LOCK       = 1,  /*!< Can not read/write content, just execute   */
} MEMLOCKSTS_BIT_RAM2;

#define MEMLOCKSTS_ALL_RAM2_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_RAM2_Pos)
#define MEMLOCKSTS_ALL_RAM2_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_RAM2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          MEMLOCKSTS      RAM3
 *  @access     SYSTEM->MEMLOCKSTS.bit.RAM3
 *  @brief      RAM region 3
 */
#define MEMLOCKSTS_ALL_RAM3_Pos (12)
#define MEMLOCKSTS_ALL_RAM3_Msk (0x1UL << MEMLOCKSTS_ALL_RAM3_Pos)

typedef enum
{
    MEMLOCKSTS_BIT_RAM3_UNLOCK     = 0,  /*!< Can read/write content and execute         */
    MEMLOCKSTS_BIT_RAM3_LOCK       = 1,  /*!< Can not read/write content, just execute   */
} MEMLOCKSTS_BIT_RAM3;

#define MEMLOCKSTS_ALL_RAM3_UNLOCK     ((0x0UL) << MEMLOCKSTS_ALL_RAM3_Pos)
#define MEMLOCKSTS_ALL_RAM3_LOCK       ((0x1UL) << MEMLOCKSTS_ALL_RAM3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       ROMERR
 *  @access     SYSTEM->RSTEVTSTS.bit.ROMERR
 *  @brief      Latched reset triggered by 2-bit error during ROM access
 */
#define RSTEVTSTS_ALL_ROMERR_Pos (0)
#define RSTEVTSTS_ALL_ROMERR_Msk (0x1UL << RSTEVTSTS_ALL_ROMERR_Pos)

typedef enum
{
    RSTEVTSTS_BIT_ROMERR_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_ROMERR_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_ROMERR;

#define RSTEVTSTS_ALL_ROMERR_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_ROMERR_Pos)
#define RSTEVTSTS_ALL_ROMERR_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_ROMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       FLASHERR
 *  @access     SYSTEM->RSTEVTSTS.bit.FLASHERR
 *  @brief      Latched reset triggered by 2-bit error during flash access
 */
#define RSTEVTSTS_ALL_FLASHERR_Pos (1)
#define RSTEVTSTS_ALL_FLASHERR_Msk (0x1UL << RSTEVTSTS_ALL_FLASHERR_Pos)

typedef enum
{
    RSTEVTSTS_BIT_FLASHERR_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_FLASHERR_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_FLASHERR;

#define RSTEVTSTS_ALL_FLASHERR_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_FLASHERR_Pos)
#define RSTEVTSTS_ALL_FLASHERR_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_FLASHERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       IRAMERR
 *  @access     SYSTEM->RSTEVTSTS.bit.IRAMERR
 *  @brief      Latched reset triggered by parity error during instruction RAM access
 */
#define RSTEVTSTS_ALL_IRAMERR_Pos (2)
#define RSTEVTSTS_ALL_IRAMERR_Msk (0x1UL << RSTEVTSTS_ALL_IRAMERR_Pos)

typedef enum
{
    RSTEVTSTS_BIT_IRAMERR_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_IRAMERR_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_IRAMERR;

#define RSTEVTSTS_ALL_IRAMERR_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_IRAMERR_Pos)
#define RSTEVTSTS_ALL_IRAMERR_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_IRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       DRAMERR
 *  @access     SYSTEM->RSTEVTSTS.bit.DRAMERR
 *  @brief      Latched reset triggered by parity error during data RAM access
 */
#define RSTEVTSTS_ALL_DRAMERR_Pos (3)
#define RSTEVTSTS_ALL_DRAMERR_Msk (0x1UL << RSTEVTSTS_ALL_DRAMERR_Pos)

typedef enum
{
    RSTEVTSTS_BIT_DRAMERR_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_DRAMERR_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_DRAMERR;

#define RSTEVTSTS_ALL_DRAMERR_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_DRAMERR_Pos)
#define RSTEVTSTS_ALL_DRAMERR_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_DRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       SIOERR
 *  @access     SYSTEM->RSTEVTSTS.bit.SIOERR
 *  @brief      Latched reset triggered by parity error during SIO access
 */
#define RSTEVTSTS_ALL_SIOERR_Pos (4)
#define RSTEVTSTS_ALL_SIOERR_Msk (0x1UL << RSTEVTSTS_ALL_SIOERR_Pos)

typedef enum
{
    RSTEVTSTS_BIT_SIOERR_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_SIOERR_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_SIOERR;

#define RSTEVTSTS_ALL_SIOERR_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_SIOERR_Pos)
#define RSTEVTSTS_ALL_SIOERR_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_SIOERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       VDD12L0
 *  @access     SYSTEM->RSTEVTSTS.bit.VDD12L0
 *  @brief      Latched reset triggered by VDD12L0 event
 */
#define RSTEVTSTS_ALL_VDD12L0_Pos (5)
#define RSTEVTSTS_ALL_VDD12L0_Msk (0x1UL << RSTEVTSTS_ALL_VDD12L0_Pos)

typedef enum
{
    RSTEVTSTS_BIT_VDD12L0_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_VDD12L0_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_VDD12L0;

#define RSTEVTSTS_ALL_VDD12L0_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_VDD12L0_Pos)
#define RSTEVTSTS_ALL_VDD12L0_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_VDD12L0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       VDD12L1
 *  @access     SYSTEM->RSTEVTSTS.bit.VDD12L1
 *  @brief      Latched reset triggered by VDD12L1 event
 */
#define RSTEVTSTS_ALL_VDD12L1_Pos (6)
#define RSTEVTSTS_ALL_VDD12L1_Msk (0x1UL << RSTEVTSTS_ALL_VDD12L1_Pos)

typedef enum
{
    RSTEVTSTS_BIT_VDD12L1_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_VDD12L1_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_VDD12L1;

#define RSTEVTSTS_ALL_VDD12L1_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_VDD12L1_Pos)
#define RSTEVTSTS_ALL_VDD12L1_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_VDD12L1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       VDD12H
 *  @access     SYSTEM->RSTEVTSTS.bit.VDD12H
 *  @brief      Latched reset triggered by VDD12H event
 */
#define RSTEVTSTS_ALL_VDD12H_Pos (7)
#define RSTEVTSTS_ALL_VDD12H_Msk (0x1UL << RSTEVTSTS_ALL_VDD12H_Pos)

typedef enum
{
    RSTEVTSTS_BIT_VDD12H_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_VDD12H_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_VDD12H;

#define RSTEVTSTS_ALL_VDD12H_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_VDD12H_Pos)
#define RSTEVTSTS_ALL_VDD12H_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_VDD12H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       VDD33L
 *  @access     SYSTEM->RSTEVTSTS.bit.VDD33L
 *  @brief      Latched reset triggered by VDD33L event
 */
#define RSTEVTSTS_ALL_VDD33L_Pos (8)
#define RSTEVTSTS_ALL_VDD33L_Msk (0x1UL << RSTEVTSTS_ALL_VDD33L_Pos)

typedef enum
{
    RSTEVTSTS_BIT_VDD33L_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_VDD33L_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_VDD33L;

#define RSTEVTSTS_ALL_VDD33L_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_VDD33L_Pos)
#define RSTEVTSTS_ALL_VDD33L_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_VDD33L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       VDD33H
 *  @access     SYSTEM->RSTEVTSTS.bit.VDD33H
 *  @brief      Latched reset triggered by VDD33H event
 */
#define RSTEVTSTS_ALL_VDD33H_Pos (9)
#define RSTEVTSTS_ALL_VDD33H_Msk (0x1UL << RSTEVTSTS_ALL_VDD33H_Pos)

typedef enum
{
    RSTEVTSTS_BIT_VDD33H_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_VDD33H_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_VDD33H;

#define RSTEVTSTS_ALL_VDD33H_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_VDD33H_Pos)
#define RSTEVTSTS_ALL_VDD33H_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_VDD33H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       PLLUNLOCK
 *  @access     SYSTEM->RSTEVTSTS.bit.PLLUNLOCK
 *  @brief      Latched reset triggered by PLL unlock event
 */
#define RSTEVTSTS_ALL_PLLUNLOCK_Pos (10)
#define RSTEVTSTS_ALL_PLLUNLOCK_Msk (0x1UL << RSTEVTSTS_ALL_PLLUNLOCK_Pos)

typedef enum
{
    RSTEVTSTS_BIT_PLLUNLOCK_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_PLLUNLOCK_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_PLLUNLOCK;

#define RSTEVTSTS_ALL_PLLUNLOCK_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_PLLUNLOCK_Pos)
#define RSTEVTSTS_ALL_PLLUNLOCK_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_PLLUNLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       CLKDETERR
 *  @access     SYSTEM->RSTEVTSTS.bit.CLKDETERR
 *  @brief      Latched reset triggered by CLKDETERR event
 */
#define RSTEVTSTS_ALL_CLKDETERR_Pos (11)
#define RSTEVTSTS_ALL_CLKDETERR_Msk (0x1UL << RSTEVTSTS_ALL_CLKDETERR_Pos)

typedef enum
{
    RSTEVTSTS_BIT_CLKDETERR_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_CLKDETERR_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_CLKDETERR;

#define RSTEVTSTS_ALL_CLKDETERR_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_CLKDETERR_Pos)
#define RSTEVTSTS_ALL_CLKDETERR_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_CLKDETERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       WDT0RST
 *  @access     SYSTEM->RSTEVTSTS.bit.WDT0RST
 *  @brief      Latched reset triggered by WDT0 reset event
 */
#define RSTEVTSTS_ALL_WDT0RST_Pos (12)
#define RSTEVTSTS_ALL_WDT0RST_Msk (0x1UL << RSTEVTSTS_ALL_WDT0RST_Pos)

typedef enum
{
    RSTEVTSTS_BIT_WDT0RST_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_WDT0RST_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_WDT0RST;

#define RSTEVTSTS_ALL_WDT0RST_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_WDT0RST_Pos)
#define RSTEVTSTS_ALL_WDT0RST_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_WDT0RST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       WDT1RST
 *  @access     SYSTEM->RSTEVTSTS.bit.WDT1RST
 *  @brief      Latched reset triggered by WDT1 reset event
 */
#define RSTEVTSTS_ALL_WDT1RST_Pos (13)
#define RSTEVTSTS_ALL_WDT1RST_Msk (0x1UL << RSTEVTSTS_ALL_WDT1RST_Pos)

typedef enum
{
    RSTEVTSTS_BIT_WDT1RST_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_WDT1RST_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_WDT1RST;

#define RSTEVTSTS_ALL_WDT1RST_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_WDT1RST_Pos)
#define RSTEVTSTS_ALL_WDT1RST_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_WDT1RST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTSTS       SYSRESET
 *  @access     SYSTEM->RSTEVTSTS.bit.SYSRESET
 *  @brief      Latched reset triggered by system reset event
 */
#define RSTEVTSTS_ALL_SYSRESET_Pos (14)
#define RSTEVTSTS_ALL_SYSRESET_Msk (0x1UL << RSTEVTSTS_ALL_SYSRESET_Pos)

typedef enum
{
    RSTEVTSTS_BIT_SYSRESET_NOT_OCCUR     = 0,  /*!< Specified reset not happen   */
    RSTEVTSTS_BIT_SYSRESET_OCCUR         = 1,  /*!< Specified reset happened     */
} RSTEVTSTS_BIT_SYSRESET;

#define RSTEVTSTS_ALL_SYSRESET_NOT_OCCUR     ((0x0UL) << RSTEVTSTS_ALL_SYSRESET_Pos)
#define RSTEVTSTS_ALL_SYSRESET_OCCUR         ((0x1UL) << RSTEVTSTS_ALL_SYSRESET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       ROMERR
 *  @access     SYSTEM->RSTEVTCLR.bit.ROMERR
 *  @brief      Clear reset status happened upon 2-bit error during ROM access
 */
#define RSTEVTCLR_ALL_ROMERR_Pos (0)
#define RSTEVTCLR_ALL_ROMERR_Msk (0x1UL << RSTEVTCLR_ALL_ROMERR_Pos)

typedef enum
{
    RSTEVTCLR_BIT_ROMERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    RSTEVTCLR_BIT_ROMERR_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                  This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_ROMERR;

#define RSTEVTCLR_ALL_ROMERR_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_ROMERR_Pos)
#define RSTEVTCLR_ALL_ROMERR_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_ROMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       FLASHERR
 *  @access     SYSTEM->RSTEVTCLR.bit.FLASHERR
 *  @brief      Clear reset status happened upon 2-bit error during flash access
 */
#define RSTEVTCLR_ALL_FLASHERR_Pos (1)
#define RSTEVTCLR_ALL_FLASHERR_Msk (0x1UL << RSTEVTCLR_ALL_FLASHERR_Pos)

typedef enum
{
    RSTEVTCLR_BIT_FLASHERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                    Always readback 0.                           */
    RSTEVTCLR_BIT_FLASHERR_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                    This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_FLASHERR;

#define RSTEVTCLR_ALL_FLASHERR_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_FLASHERR_Pos)
#define RSTEVTCLR_ALL_FLASHERR_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_FLASHERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       IRAMERR
 *  @access     SYSTEM->RSTEVTCLR.bit.IRAMERR
 *  @brief      Clear reset status happened upon parity error during instruction RAM access
 */
#define RSTEVTCLR_ALL_IRAMERR_Pos (2)
#define RSTEVTCLR_ALL_IRAMERR_Msk (0x1UL << RSTEVTCLR_ALL_IRAMERR_Pos)

typedef enum
{
    RSTEVTCLR_BIT_IRAMERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                   Always readback 0.                           */
    RSTEVTCLR_BIT_IRAMERR_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                   This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_IRAMERR;

#define RSTEVTCLR_ALL_IRAMERR_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_IRAMERR_Pos)
#define RSTEVTCLR_ALL_IRAMERR_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_IRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       DRAMERR
 *  @access     SYSTEM->RSTEVTCLR.bit.DRAMERR
 *  @brief      Clear reset status happened upon parity error during data RAM access
 */
#define RSTEVTCLR_ALL_DRAMERR_Pos (3)
#define RSTEVTCLR_ALL_DRAMERR_Msk (0x1UL << RSTEVTCLR_ALL_DRAMERR_Pos)

typedef enum
{
    RSTEVTCLR_BIT_DRAMERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                   Always readback 0.                           */
    RSTEVTCLR_BIT_DRAMERR_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                   This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_DRAMERR;

#define RSTEVTCLR_ALL_DRAMERR_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_DRAMERR_Pos)
#define RSTEVTCLR_ALL_DRAMERR_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_DRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       SIOERR
 *  @access     SYSTEM->RSTEVTCLR.bit.SIOERR
 *  @brief      Clear reset status happened upon parity error during SIO access
 */
#define RSTEVTCLR_ALL_SIOERR_Pos (4)
#define RSTEVTCLR_ALL_SIOERR_Msk (0x1UL << RSTEVTCLR_ALL_SIOERR_Pos)

typedef enum
{
    RSTEVTCLR_BIT_SIOERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    RSTEVTCLR_BIT_SIOERR_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                  This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_SIOERR;

#define RSTEVTCLR_ALL_SIOERR_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_SIOERR_Pos)
#define RSTEVTCLR_ALL_SIOERR_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_SIOERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       VDD12L0
 *  @access     SYSTEM->RSTEVTCLR.bit.VDD12L0
 *  @brief      Clear reset status happened upon VDD12L0 event
 */
#define RSTEVTCLR_ALL_VDD12L0_Pos (5)
#define RSTEVTCLR_ALL_VDD12L0_Msk (0x1UL << RSTEVTCLR_ALL_VDD12L0_Pos)

typedef enum
{
    RSTEVTCLR_BIT_VDD12L0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                   Always readback 0.                           */
    RSTEVTCLR_BIT_VDD12L0_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                   This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_VDD12L0;

#define RSTEVTCLR_ALL_VDD12L0_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_VDD12L0_Pos)
#define RSTEVTCLR_ALL_VDD12L0_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_VDD12L0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       VDD12L1
 *  @access     SYSTEM->RSTEVTCLR.bit.VDD12L1
 *  @brief      Clear reset status happened upon VDD12L1 event
 */
#define RSTEVTCLR_ALL_VDD12L1_Pos (6)
#define RSTEVTCLR_ALL_VDD12L1_Msk (0x1UL << RSTEVTCLR_ALL_VDD12L1_Pos)

typedef enum
{
    RSTEVTCLR_BIT_VDD12L1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                   Always readback 0.                           */
    RSTEVTCLR_BIT_VDD12L1_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                   This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_VDD12L1;

#define RSTEVTCLR_ALL_VDD12L1_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_VDD12L1_Pos)
#define RSTEVTCLR_ALL_VDD12L1_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_VDD12L1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       VDD12H
 *  @access     SYSTEM->RSTEVTCLR.bit.VDD12H
 *  @brief      Clear reset status happened upon VDD12H event
 */
#define RSTEVTCLR_ALL_VDD12H_Pos (7)
#define RSTEVTCLR_ALL_VDD12H_Msk (0x1UL << RSTEVTCLR_ALL_VDD12H_Pos)

typedef enum
{
    RSTEVTCLR_BIT_VDD12H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    RSTEVTCLR_BIT_VDD12H_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                  This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_VDD12H;

#define RSTEVTCLR_ALL_VDD12H_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_VDD12H_Pos)
#define RSTEVTCLR_ALL_VDD12H_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_VDD12H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       VDD33L
 *  @access     SYSTEM->RSTEVTCLR.bit.VDD33L
 *  @brief      Clear reset status happened upon VDD33L event
 */
#define RSTEVTCLR_ALL_VDD33L_Pos (8)
#define RSTEVTCLR_ALL_VDD33L_Msk (0x1UL << RSTEVTCLR_ALL_VDD33L_Pos)

typedef enum
{
    RSTEVTCLR_BIT_VDD33L_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    RSTEVTCLR_BIT_VDD33L_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                  This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_VDD33L;

#define RSTEVTCLR_ALL_VDD33L_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_VDD33L_Pos)
#define RSTEVTCLR_ALL_VDD33L_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_VDD33L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       VDD33H
 *  @access     SYSTEM->RSTEVTCLR.bit.VDD33H
 *  @brief      Clear reset status happened upon VDD33H event
 */
#define RSTEVTCLR_ALL_VDD33H_Pos (9)
#define RSTEVTCLR_ALL_VDD33H_Msk (0x1UL << RSTEVTCLR_ALL_VDD33H_Pos)

typedef enum
{
    RSTEVTCLR_BIT_VDD33H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    RSTEVTCLR_BIT_VDD33H_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                  This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_VDD33H;

#define RSTEVTCLR_ALL_VDD33H_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_VDD33H_Pos)
#define RSTEVTCLR_ALL_VDD33H_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_VDD33H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       PLLUNLOCK
 *  @access     SYSTEM->RSTEVTCLR.bit.PLLUNLOCK
 *  @brief      Clear reset status happened upon PLL unlock event
 */
#define RSTEVTCLR_ALL_PLLUNLOCK_Pos (10)
#define RSTEVTCLR_ALL_PLLUNLOCK_Msk (0x1UL << RSTEVTCLR_ALL_PLLUNLOCK_Pos)

typedef enum
{
    RSTEVTCLR_BIT_PLLUNLOCK_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                     Always readback 0.                           */
    RSTEVTCLR_BIT_PLLUNLOCK_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                     This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_PLLUNLOCK;

#define RSTEVTCLR_ALL_PLLUNLOCK_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_PLLUNLOCK_Pos)
#define RSTEVTCLR_ALL_PLLUNLOCK_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_PLLUNLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       CLKDETERR
 *  @access     SYSTEM->RSTEVTCLR.bit.CLKDETERR
 *  @brief      Clear reset status happened upon CLKDETERR event
 */
#define RSTEVTCLR_ALL_CLKDETERR_Pos (11)
#define RSTEVTCLR_ALL_CLKDETERR_Msk (0x1UL << RSTEVTCLR_ALL_CLKDETERR_Pos)

typedef enum
{
    RSTEVTCLR_BIT_CLKDETERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                     Always readback 0.                           */
    RSTEVTCLR_BIT_CLKDETERR_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                     This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_CLKDETERR;

#define RSTEVTCLR_ALL_CLKDETERR_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_CLKDETERR_Pos)
#define RSTEVTCLR_ALL_CLKDETERR_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_CLKDETERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       WDT0RST
 *  @access     SYSTEM->RSTEVTCLR.bit.WDT0RST
 *  @brief      Clear reset status happened upon WDT0 reset event
 */
#define RSTEVTCLR_ALL_WDT0RST_Pos (12)
#define RSTEVTCLR_ALL_WDT0RST_Msk (0x1UL << RSTEVTCLR_ALL_WDT0RST_Pos)

typedef enum
{
    RSTEVTCLR_BIT_WDT0RST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                   Always readback 0.                           */
    RSTEVTCLR_BIT_WDT0RST_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                   This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_WDT0RST;

#define RSTEVTCLR_ALL_WDT0RST_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_WDT0RST_Pos)
#define RSTEVTCLR_ALL_WDT0RST_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_WDT0RST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       WDT1RST
 *  @access     SYSTEM->RSTEVTCLR.bit.WDT1RST
 *  @brief      Clear reset status happened upon WDT1 reset event
 */
#define RSTEVTCLR_ALL_WDT1RST_Pos (13)
#define RSTEVTCLR_ALL_WDT1RST_Msk (0x1UL << RSTEVTCLR_ALL_WDT1RST_Pos)

typedef enum
{
    RSTEVTCLR_BIT_WDT1RST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                   Always readback 0.                           */
    RSTEVTCLR_BIT_WDT1RST_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                   This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_WDT1RST;

#define RSTEVTCLR_ALL_WDT1RST_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_WDT1RST_Pos)
#define RSTEVTCLR_ALL_WDT1RST_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_WDT1RST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTCLR       SYSRESET
 *  @access     SYSTEM->RSTEVTCLR.bit.SYSRESET
 *  @brief      Clear reset status happened upon system reset event
 */
#define RSTEVTCLR_ALL_SYSRESET_Pos (14)
#define RSTEVTCLR_ALL_SYSRESET_Msk (0x1UL << RSTEVTCLR_ALL_SYSRESET_Pos)

typedef enum
{
    RSTEVTCLR_BIT_SYSRESET_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                    Always readback 0.                           */
    RSTEVTCLR_BIT_SYSRESET_CLEAR         = 1,  /*!< Write a 1 clear the interrupt and the flag  
                                                    This bit is self-cleared to 0.               */
} RSTEVTCLR_BIT_SYSRESET;

#define RSTEVTCLR_ALL_SYSRESET_NO_EFFECT     ((0x0UL) << RSTEVTCLR_ALL_SYSRESET_Pos)
#define RSTEVTCLR_ALL_SYSRESET_CLEAR         ((0x1UL) << RSTEVTCLR_ALL_SYSRESET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        ROMERR
 *  @access     SYSTEM->RSTEVTEN.bit.ROMERR
 *  @brief      Enable reset on 2-bit error during ROM access
 */
#define RSTEVTEN_ALL_ROMERR_Pos (0)
#define RSTEVTEN_ALL_ROMERR_Msk (0x1UL << RSTEVTEN_ALL_ROMERR_Pos)

typedef enum
{
    RSTEVTEN_BIT_ROMERR_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_ROMERR_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_ROMERR;

#define RSTEVTEN_ALL_ROMERR_DISABLE     ((0x0UL) << RSTEVTEN_ALL_ROMERR_Pos)
#define RSTEVTEN_ALL_ROMERR_ENABLE      ((0x1UL) << RSTEVTEN_ALL_ROMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        FLASHERR
 *  @access     SYSTEM->RSTEVTEN.bit.FLASHERR
 *  @brief      Enable reset on 2-bit error during flash access
 */
#define RSTEVTEN_ALL_FLASHERR_Pos (1)
#define RSTEVTEN_ALL_FLASHERR_Msk (0x1UL << RSTEVTEN_ALL_FLASHERR_Pos)

typedef enum
{
    RSTEVTEN_BIT_FLASHERR_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_FLASHERR_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_FLASHERR;

#define RSTEVTEN_ALL_FLASHERR_DISABLE     ((0x0UL) << RSTEVTEN_ALL_FLASHERR_Pos)
#define RSTEVTEN_ALL_FLASHERR_ENABLE      ((0x1UL) << RSTEVTEN_ALL_FLASHERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        IRAMERR
 *  @access     SYSTEM->RSTEVTEN.bit.IRAMERR
 *  @brief      Enable reset on parity error during instruction RAM access
 */
#define RSTEVTEN_ALL_IRAMERR_Pos (2)
#define RSTEVTEN_ALL_IRAMERR_Msk (0x1UL << RSTEVTEN_ALL_IRAMERR_Pos)

typedef enum
{
    RSTEVTEN_BIT_IRAMERR_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_IRAMERR_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_IRAMERR;

#define RSTEVTEN_ALL_IRAMERR_DISABLE     ((0x0UL) << RSTEVTEN_ALL_IRAMERR_Pos)
#define RSTEVTEN_ALL_IRAMERR_ENABLE      ((0x1UL) << RSTEVTEN_ALL_IRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        DRAMERR
 *  @access     SYSTEM->RSTEVTEN.bit.DRAMERR
 *  @brief      Enable reset on parity error during data RAM access
 */
#define RSTEVTEN_ALL_DRAMERR_Pos (3)
#define RSTEVTEN_ALL_DRAMERR_Msk (0x1UL << RSTEVTEN_ALL_DRAMERR_Pos)

typedef enum
{
    RSTEVTEN_BIT_DRAMERR_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_DRAMERR_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_DRAMERR;

#define RSTEVTEN_ALL_DRAMERR_DISABLE     ((0x0UL) << RSTEVTEN_ALL_DRAMERR_Pos)
#define RSTEVTEN_ALL_DRAMERR_ENABLE      ((0x1UL) << RSTEVTEN_ALL_DRAMERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        SIOERR
 *  @access     SYSTEM->RSTEVTEN.bit.SIOERR
 *  @brief      Enable reset on parity error during SIO access
 */
#define RSTEVTEN_ALL_SIOERR_Pos (4)
#define RSTEVTEN_ALL_SIOERR_Msk (0x1UL << RSTEVTEN_ALL_SIOERR_Pos)

typedef enum
{
    RSTEVTEN_BIT_SIOERR_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_SIOERR_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_SIOERR;

#define RSTEVTEN_ALL_SIOERR_DISABLE     ((0x0UL) << RSTEVTEN_ALL_SIOERR_Pos)
#define RSTEVTEN_ALL_SIOERR_ENABLE      ((0x1UL) << RSTEVTEN_ALL_SIOERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        VDD12L0
 *  @access     SYSTEM->RSTEVTEN.bit.VDD12L0
 *  @brief      Enable reset on VDD12L0 event
 */
#define RSTEVTEN_ALL_VDD12L0_Pos (5)
#define RSTEVTEN_ALL_VDD12L0_Msk (0x1UL << RSTEVTEN_ALL_VDD12L0_Pos)

typedef enum
{
    RSTEVTEN_BIT_VDD12L0_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_VDD12L0_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_VDD12L0;

#define RSTEVTEN_ALL_VDD12L0_DISABLE     ((0x0UL) << RSTEVTEN_ALL_VDD12L0_Pos)
#define RSTEVTEN_ALL_VDD12L0_ENABLE      ((0x1UL) << RSTEVTEN_ALL_VDD12L0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        VDD12L1
 *  @access     SYSTEM->RSTEVTEN.bit.VDD12L1
 *  @brief      Enable reset on VDD12L1 event
 */
#define RSTEVTEN_ALL_VDD12L1_Pos (6)
#define RSTEVTEN_ALL_VDD12L1_Msk (0x1UL << RSTEVTEN_ALL_VDD12L1_Pos)

typedef enum
{
    RSTEVTEN_BIT_VDD12L1_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_VDD12L1_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_VDD12L1;

#define RSTEVTEN_ALL_VDD12L1_DISABLE     ((0x0UL) << RSTEVTEN_ALL_VDD12L1_Pos)
#define RSTEVTEN_ALL_VDD12L1_ENABLE      ((0x1UL) << RSTEVTEN_ALL_VDD12L1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        VDD12H
 *  @access     SYSTEM->RSTEVTEN.bit.VDD12H
 *  @brief      Enable reset on VDD12H event
 */
#define RSTEVTEN_ALL_VDD12H_Pos (7)
#define RSTEVTEN_ALL_VDD12H_Msk (0x1UL << RSTEVTEN_ALL_VDD12H_Pos)

typedef enum
{
    RSTEVTEN_BIT_VDD12H_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_VDD12H_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_VDD12H;

#define RSTEVTEN_ALL_VDD12H_DISABLE     ((0x0UL) << RSTEVTEN_ALL_VDD12H_Pos)
#define RSTEVTEN_ALL_VDD12H_ENABLE      ((0x1UL) << RSTEVTEN_ALL_VDD12H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        VDD33L
 *  @access     SYSTEM->RSTEVTEN.bit.VDD33L
 *  @brief      Enable reset on VDD33L event
 */
#define RSTEVTEN_ALL_VDD33L_Pos (8)
#define RSTEVTEN_ALL_VDD33L_Msk (0x1UL << RSTEVTEN_ALL_VDD33L_Pos)

typedef enum
{
    RSTEVTEN_BIT_VDD33L_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_VDD33L_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_VDD33L;

#define RSTEVTEN_ALL_VDD33L_DISABLE     ((0x0UL) << RSTEVTEN_ALL_VDD33L_Pos)
#define RSTEVTEN_ALL_VDD33L_ENABLE      ((0x1UL) << RSTEVTEN_ALL_VDD33L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        VDD33H
 *  @access     SYSTEM->RSTEVTEN.bit.VDD33H
 *  @brief      Enable reset on VDD33H event
 */
#define RSTEVTEN_ALL_VDD33H_Pos (9)
#define RSTEVTEN_ALL_VDD33H_Msk (0x1UL << RSTEVTEN_ALL_VDD33H_Pos)

typedef enum
{
    RSTEVTEN_BIT_VDD33H_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_VDD33H_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_VDD33H;

#define RSTEVTEN_ALL_VDD33H_DISABLE     ((0x0UL) << RSTEVTEN_ALL_VDD33H_Pos)
#define RSTEVTEN_ALL_VDD33H_ENABLE      ((0x1UL) << RSTEVTEN_ALL_VDD33H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        PLLUNLOCK
 *  @access     SYSTEM->RSTEVTEN.bit.PLLUNLOCK
 *  @brief      Enable reset on PLL unlock event
 */
#define RSTEVTEN_ALL_PLLUNLOCK_Pos (10)
#define RSTEVTEN_ALL_PLLUNLOCK_Msk (0x1UL << RSTEVTEN_ALL_PLLUNLOCK_Pos)

typedef enum
{
    RSTEVTEN_BIT_PLLUNLOCK_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_PLLUNLOCK_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_PLLUNLOCK;

#define RSTEVTEN_ALL_PLLUNLOCK_DISABLE     ((0x0UL) << RSTEVTEN_ALL_PLLUNLOCK_Pos)
#define RSTEVTEN_ALL_PLLUNLOCK_ENABLE      ((0x1UL) << RSTEVTEN_ALL_PLLUNLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          RSTEVTEN        CLKDETERR
 *  @access     SYSTEM->RSTEVTEN.bit.CLKDETERR
 *  @brief      Enable reset on CLKDETERR event
 */
#define RSTEVTEN_ALL_CLKDETERR_Pos (11)
#define RSTEVTEN_ALL_CLKDETERR_Msk (0x1UL << RSTEVTEN_ALL_CLKDETERR_Pos)

typedef enum
{
    RSTEVTEN_BIT_CLKDETERR_DISABLE     = 0,  /*!< Disable   */
    RSTEVTEN_BIT_CLKDETERR_ENABLE      = 1,  /*!< Enable    */
} RSTEVTEN_BIT_CLKDETERR;

#define RSTEVTEN_ALL_CLKDETERR_DISABLE     ((0x0UL) << RSTEVTEN_ALL_CLKDETERR_Pos)
#define RSTEVTEN_ALL_CLKDETERR_ENABLE      ((0x1UL) << RSTEVTEN_ALL_CLKDETERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          SYSINFO         FLASHSIZE
 *  @access     SYSTEM->SYSINFO.bit.FLASHSIZE
 *  @brief      FLASH size
 */
#define SYSINFO_ALL_FLASHSIZE_Pos (0)
#define SYSINFO_ALL_FLASHSIZE_Msk (0x3UL << SYSINFO_ALL_FLASHSIZE_Pos)

typedef enum
{
    SYSINFO_BIT_FLASHSIZE_32KB      = 0,  /*!< 32kB Flash    */
    SYSINFO_BIT_FLASHSIZE_64KB      = 1,  /*!< 64kB Flash    */
    SYSINFO_BIT_FLASHSIZE_96KB      = 2,  /*!< 96kB Flash    */
    SYSINFO_BIT_FLASHSIZE_128KB     = 3,  /*!< 128kB Flash   */
} SYSINFO_BIT_FLASHSIZE;

#define SYSINFO_ALL_FLASHSIZE_32KB      ((0x0UL) << SYSINFO_ALL_FLASHSIZE_Pos)
#define SYSINFO_ALL_FLASHSIZE_64KB      ((0x1UL) << SYSINFO_ALL_FLASHSIZE_Pos)
#define SYSINFO_ALL_FLASHSIZE_96KB      ((0x2UL) << SYSINFO_ALL_FLASHSIZE_Pos)
#define SYSINFO_ALL_FLASHSIZE_128KB     ((0x3UL) << SYSINFO_ALL_FLASHSIZE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          SYSINFO         RAMSIZE
 *  @access     SYSTEM->SYSINFO.bit.RAMSIZE
 *  @brief      RAM size
 */
#define SYSINFO_ALL_RAMSIZE_Pos (2)
#define SYSINFO_ALL_RAMSIZE_Msk (0x3UL << SYSINFO_ALL_RAMSIZE_Pos)

typedef enum
{
    SYSINFO_BIT_RAMSIZE_16KB     = 0,  /*!< 16kB start at 0x20000000   */
    SYSINFO_BIT_RAMSIZE_32KB     = 1,  /*!< 32kB start at 0x1FFFC000   */
    SYSINFO_BIT_RAMSIZE_48KB     = 2,  /*!< 48kB start at 0x1FFF8000   */
    SYSINFO_BIT_RAMSIZE_64KB     = 3,  /*!< 64kB start at 0x1FFF4000   */
} SYSINFO_BIT_RAMSIZE;

#define SYSINFO_ALL_RAMSIZE_16KB     ((0x0UL) << SYSINFO_ALL_RAMSIZE_Pos)
#define SYSINFO_ALL_RAMSIZE_32KB     ((0x1UL) << SYSINFO_ALL_RAMSIZE_Pos)
#define SYSINFO_ALL_RAMSIZE_48KB     ((0x2UL) << SYSINFO_ALL_RAMSIZE_Pos)
#define SYSINFO_ALL_RAMSIZE_64KB     ((0x3UL) << SYSINFO_ALL_RAMSIZE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          SYSINFO         CLKOPT
 *  @access     SYSTEM->SYSINFO.bit.CLKOPT
 *  @brief      Clock option
 */
#define SYSINFO_ALL_CLKOPT_Pos (4)
#define SYSINFO_ALL_CLKOPT_Msk (0x7UL << SYSINFO_ALL_CLKOPT_Pos)

typedef enum
{
    SYSINFO_BIT_CLKOPT_50MHz_NO_XO      = 0,  /*!< Minimum PLL output dividing ratio is 12 and XO is unavailable   */
    SYSINFO_BIT_CLKOPT_100MHz_NO_XO     = 1,  /*!< Minimum PLL output dividing ratio is 6 and XO is unavailable    */
    SYSINFO_BIT_CLKOPT_150MHz_NO_XO     = 2,  /*!< Minimum PLL output dividing ratio is 4 and XO is unavailable    */
    SYSINFO_BIT_CLKOPT_50MHZ            = 3,  /*!< Minimum PLL output dividing ratio is 12 and XO is available     */
    SYSINFO_BIT_CLKOPT_100MHZ           = 4,  /*!< Minimum PLL output dividing ratio is 6 and XO is available      */
    SYSINFO_BIT_CLKOPT_150MHZ           = 5,  /*!< Minimum PLL output dividing ratio is 4 and XO available         */
    SYSINFO_BIT_CLKOPT_200MHZ           = 6,  /*!< Minimum PLL output dividing ratio is 3 and XO is available      */
    SYSINFO_BIT_CLKOPT_NOLIMIT          = 7,  /*!< No limitation                                                   */
} SYSINFO_BIT_CLKOPT;

#define SYSINFO_ALL_CLKOPT_50MHz_NO_XO      ((0x0UL) << SYSINFO_ALL_CLKOPT_Pos)
#define SYSINFO_ALL_CLKOPT_100MHz_NO_XO     ((0x1UL) << SYSINFO_ALL_CLKOPT_Pos)
#define SYSINFO_ALL_CLKOPT_150MHz_NO_XO     ((0x2UL) << SYSINFO_ALL_CLKOPT_Pos)
#define SYSINFO_ALL_CLKOPT_50MHZ            ((0x3UL) << SYSINFO_ALL_CLKOPT_Pos)
#define SYSINFO_ALL_CLKOPT_100MHZ           ((0x4UL) << SYSINFO_ALL_CLKOPT_Pos)
#define SYSINFO_ALL_CLKOPT_150MHZ           ((0x5UL) << SYSINFO_ALL_CLKOPT_Pos)
#define SYSINFO_ALL_CLKOPT_200MHZ           ((0x6UL) << SYSINFO_ALL_CLKOPT_Pos)
#define SYSINFO_ALL_CLKOPT_NOLIMIT          ((0x7UL) << SYSINFO_ALL_CLKOPT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          SYSINFO         ADCBIT
 *  @access     SYSTEM->SYSINFO.bit.ADCBIT
 *  @brief      ADC bit width
 */
#define SYSINFO_ALL_ADCBIT_Pos (7)
#define SYSINFO_ALL_ADCBIT_Msk (0x3UL << SYSINFO_ALL_ADCBIT_Pos)

typedef enum
{
    SYSINFO_BIT_ADCBIT_10     = 0,  /*!< 10 bit   */
    SYSINFO_BIT_ADCBIT_11     = 1,  /*!< 11 bit   */
    SYSINFO_BIT_ADCBIT_12     = 2,  /*!< 12 bit   */
    SYSINFO_BIT_ADCBIT_14     = 3,  /*!< 14 bit   */
} SYSINFO_BIT_ADCBIT;

#define SYSINFO_ALL_ADCBIT_10     ((0x0UL) << SYSINFO_ALL_ADCBIT_Pos)
#define SYSINFO_ALL_ADCBIT_11     ((0x1UL) << SYSINFO_ALL_ADCBIT_Pos)
#define SYSINFO_ALL_ADCBIT_12     ((0x2UL) << SYSINFO_ALL_ADCBIT_Pos)
#define SYSINFO_ALL_ADCBIT_14     ((0x3UL) << SYSINFO_ALL_ADCBIT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SYSTEM          SYSREGKEY       KEY
 *  @access     SYSTEM->SYSREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected system registers
 */
#define SYSREGKEY_ALL_KEY_Pos (0)
#define SYSREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << SYSREGKEY_ALL_KEY_Pos)

#define SYSREGKEY_BIT_KEY

#define SYSREGKEY_ALL_KEY_(x) ((x) << SYSREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     POWER
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           PWRSTS          FLASHREGRDY
 *  @access     POWER->PWRSTS.bit.FLASHREGRDY
 *  @brief      Flash regulator ready indicator
 */
#define PWRSTS_ALL_FLASHREGRDY_Pos (0)
#define PWRSTS_ALL_FLASHREGRDY_Msk (0x1UL << PWRSTS_ALL_FLASHREGRDY_Pos)

typedef enum
{
    PWRSTS_BIT_FLASHREGRDY_NOT_READY     = 0,  /*!< Not ready   */
    PWRSTS_BIT_FLASHREGRDY_READY         = 1,  /*!< Ready       */
} PWRSTS_BIT_FLASHREGRDY;

#define PWRSTS_ALL_FLASHREGRDY_NOT_READY     ((0x0UL) << PWRSTS_ALL_FLASHREGRDY_Pos)
#define PWRSTS_ALL_FLASHREGRDY_READY         ((0x1UL) << PWRSTS_ALL_FLASHREGRDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           LDOCTL          VREFTRIM
 *  @access     POWER->LDOCTL.bit.VREFTRIM
 *  @brief      Reference voltage trim for LDO
 */
#define LDOCTL_ALL_VREFTRIM_Pos (0)
#define LDOCTL_ALL_VREFTRIM_Msk (0xFUL << LDOCTL_ALL_VREFTRIM_Pos)

typedef enum
{
    LDOCTL_BIT_VREFTRIM_1dot06_V     = 0,  /*!< 1.06V   */
    LDOCTL_BIT_VREFTRIM_1dot08_V     = 1,  /*!< 1.08V   */
    LDOCTL_BIT_VREFTRIM_1dot10_V     = 2,  /*!< 1.10V   */
    LDOCTL_BIT_VREFTRIM_1dot12_V     = 3,  /*!< 1.12V   */
    LDOCTL_BIT_VREFTRIM_1dot14_V     = 4,  /*!< 1.14V   */
    LDOCTL_BIT_VREFTRIM_1dot16_V     = 5,  /*!< 1.16V   */
    LDOCTL_BIT_VREFTRIM_1dot18_V     = 6,  /*!< 1.18V   */
    LDOCTL_BIT_VREFTRIM_1dot20_V     = 7,  /*!< 1.20V   */
    LDOCTL_BIT_VREFTRIM_1dot22_V     = 8,  /*!< 1.22V   */
    LDOCTL_BIT_VREFTRIM_1dot24_V     = 9,  /*!< 1.24V   */
    LDOCTL_BIT_VREFTRIM_1dot26_V     = 10,  /*!< 1.26V   */
    LDOCTL_BIT_VREFTRIM_1dot28_V     = 11,  /*!< 1.28V   */
    LDOCTL_BIT_VREFTRIM_1dot30_V     = 12,  /*!< 1.30V   */
    LDOCTL_BIT_VREFTRIM_1dot32_V     = 13,  /*!< 1.32V   */
    LDOCTL_BIT_VREFTRIM_1dot34_V     = 14,  /*!< 1.34V   */
    LDOCTL_BIT_VREFTRIM_1dot36_V     = 15,  /*!< 1.36V   */
} LDOCTL_BIT_VREFTRIM;

#define LDOCTL_ALL_VREFTRIM_1dot06_V     ((0x00UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot08_V     ((0x01UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot10_V     ((0x02UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot12_V     ((0x03UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot14_V     ((0x04UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot16_V     ((0x05UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot18_V     ((0x06UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot20_V     ((0x07UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot22_V     ((0x08UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot24_V     ((0x09UL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot26_V     ((0x0AUL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot28_V     ((0x0BUL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot30_V     ((0x0CUL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot32_V     ((0x0DUL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot34_V     ((0x0EUL) << LDOCTL_ALL_VREFTRIM_Pos)
#define LDOCTL_ALL_VREFTRIM_1dot36_V     ((0x0FUL) << LDOCTL_ALL_VREFTRIM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           PORCTL          XRSTFILT
 *  @access     POWER->PORCTL.bit.XRSTFILT
 *  @brief      External reset input deglitch filtering window
 */
#define PORCTL_ALL_XRSTFILT_Pos (0)
#define PORCTL_ALL_XRSTFILT_Msk (0x3UL << PORCTL_ALL_XRSTFILT_Pos)

typedef enum
{
    PORCTL_BIT_XRSTFILT_500_US     = 0,  /*!< 500us   */
    PORCTL_BIT_XRSTFILT_1_MS       = 1,  /*!< 1ms     */
    PORCTL_BIT_XRSTFILT_2_MS       = 2,  /*!< 2ms     */
    PORCTL_BIT_XRSTFILT_4_MS       = 3,  /*!< 4ms     */
} PORCTL_BIT_XRSTFILT;

#define PORCTL_ALL_XRSTFILT_500_US     ((0x0UL) << PORCTL_ALL_XRSTFILT_Pos)
#define PORCTL_ALL_XRSTFILT_1_MS       ((0x1UL) << PORCTL_ALL_XRSTFILT_Pos)
#define PORCTL_ALL_XRSTFILT_2_MS       ((0x2UL) << PORCTL_ALL_XRSTFILT_Pos)
#define PORCTL_ALL_XRSTFILT_4_MS       ((0x3UL) << PORCTL_ALL_XRSTFILT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIF           VDD12L0
 *  @access     POWER->BODIF.bit.VDD12L0
 *  @brief      Latched VDD12L0 assertion
 */
#define BODIF_ALL_VDD12L0_Pos (0)
#define BODIF_ALL_VDD12L0_Msk (0x1UL << BODIF_ALL_VDD12L0_Pos)

typedef enum
{
    BODIF_BIT_VDD12L0_NOT_OCCUR     = 0,  /*!< VDD12L0 is never asserted   */
    BODIF_BIT_VDD12L0_OCCUR         = 1,  /*!< VDD12L0 has been asserted   */
} BODIF_BIT_VDD12L0;

#define BODIF_ALL_VDD12L0_NOT_OCCUR     ((0x0UL) << BODIF_ALL_VDD12L0_Pos)
#define BODIF_ALL_VDD12L0_OCCUR         ((0x1UL) << BODIF_ALL_VDD12L0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIF           VDD12L1
 *  @access     POWER->BODIF.bit.VDD12L1
 *  @brief      Latched VDD12L1 assertion
 */
#define BODIF_ALL_VDD12L1_Pos (1)
#define BODIF_ALL_VDD12L1_Msk (0x1UL << BODIF_ALL_VDD12L1_Pos)

typedef enum
{
    BODIF_BIT_VDD12L1_NOT_OCCUR     = 0,  /*!< VDD12L1 is never asserted   */
    BODIF_BIT_VDD12L1_OCCUR         = 1,  /*!< VDD12L1 has been asserted   */
} BODIF_BIT_VDD12L1;

#define BODIF_ALL_VDD12L1_NOT_OCCUR     ((0x0UL) << BODIF_ALL_VDD12L1_Pos)
#define BODIF_ALL_VDD12L1_OCCUR         ((0x1UL) << BODIF_ALL_VDD12L1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIF           VDD12H
 *  @access     POWER->BODIF.bit.VDD12H
 *  @brief      Latched VDD12H assertion
 */
#define BODIF_ALL_VDD12H_Pos (2)
#define BODIF_ALL_VDD12H_Msk (0x1UL << BODIF_ALL_VDD12H_Pos)

typedef enum
{
    BODIF_BIT_VDD12H_NOT_OCCUR     = 0,  /*!< VDD12H is never asserted   */
    BODIF_BIT_VDD12H_OCCUR         = 1,  /*!< VDD12H has been asserted   */
} BODIF_BIT_VDD12H;

#define BODIF_ALL_VDD12H_NOT_OCCUR     ((0x0UL) << BODIF_ALL_VDD12H_Pos)
#define BODIF_ALL_VDD12H_OCCUR         ((0x1UL) << BODIF_ALL_VDD12H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIF           VDD33L
 *  @access     POWER->BODIF.bit.VDD33L
 *  @brief      Latched VDD33L assertion
 */
#define BODIF_ALL_VDD33L_Pos (3)
#define BODIF_ALL_VDD33L_Msk (0x1UL << BODIF_ALL_VDD33L_Pos)

typedef enum
{
    BODIF_BIT_VDD33L_NOT_OCCUR     = 0,  /*!< VDD33L is never asserted   */
    BODIF_BIT_VDD33L_OCCUR         = 1,  /*!< VDD33L has been asserted   */
} BODIF_BIT_VDD33L;

#define BODIF_ALL_VDD33L_NOT_OCCUR     ((0x0UL) << BODIF_ALL_VDD33L_Pos)
#define BODIF_ALL_VDD33L_OCCUR         ((0x1UL) << BODIF_ALL_VDD33L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIF           VDD33H
 *  @access     POWER->BODIF.bit.VDD33H
 *  @brief      Latched VDD33H assertion
 */
#define BODIF_ALL_VDD33H_Pos (4)
#define BODIF_ALL_VDD33H_Msk (0x1UL << BODIF_ALL_VDD33H_Pos)

typedef enum
{
    BODIF_BIT_VDD33H_NOT_OCCUR     = 0,  /*!< VDD33H is never asserted   */
    BODIF_BIT_VDD33H_OCCUR         = 1,  /*!< VDD33H has been asserted   */
} BODIF_BIT_VDD33H;

#define BODIF_ALL_VDD33H_NOT_OCCUR     ((0x0UL) << BODIF_ALL_VDD33H_Pos)
#define BODIF_ALL_VDD33H_OCCUR         ((0x1UL) << BODIF_ALL_VDD33H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIF           BODINT
 *  @access     POWER->BODIF.bit.BODINT
 *  @brief      Latched BOD interrupt flag
 */
#define BODIF_ALL_BODINT_Pos (5)
#define BODIF_ALL_BODINT_Msk (0x1UL << BODIF_ALL_BODINT_Pos)

typedef enum
{
    BODIF_BIT_BODINT_NOT_OCCUR     = 0,  /*!< BOD interrupt is deasserted   */
    BODIF_BIT_BODINT_OCCUR         = 1,  /*!< BOD interrupt is asserted     */
} BODIF_BIT_BODINT;

#define BODIF_ALL_BODINT_NOT_OCCUR     ((0x0UL) << BODIF_ALL_BODINT_Pos)
#define BODIF_ALL_BODINT_OCCUR         ((0x1UL) << BODIF_ALL_BODINT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIC           VDD12L0
 *  @access     POWER->BODIC.bit.VDD12L0
 *  @brief      VDD12L0 interrupt flag clear
 */
#define BODIC_ALL_VDD12L0_Pos (0)
#define BODIC_ALL_VDD12L0_Msk (0x1UL << BODIC_ALL_VDD12L0_Pos)

typedef enum
{
    BODIC_BIT_VDD12L0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0   */
    BODIC_BIT_VDD12L0_CLEAR         = 1,  /*!< Write a 1 clear the BODIF.VDD12L0.              
                                               This bit is self-cleared to 0.                   */
} BODIC_BIT_VDD12L0;

#define BODIC_ALL_VDD12L0_NO_EFFECT     ((0x0UL) << BODIC_ALL_VDD12L0_Pos)
#define BODIC_ALL_VDD12L0_CLEAR         ((0x1UL) << BODIC_ALL_VDD12L0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIC           VDD12L1
 *  @access     POWER->BODIC.bit.VDD12L1
 *  @brief      VDD12L1 interrupt flag clear
 */
#define BODIC_ALL_VDD12L1_Pos (1)
#define BODIC_ALL_VDD12L1_Msk (0x1UL << BODIC_ALL_VDD12L1_Pos)

typedef enum
{
    BODIC_BIT_VDD12L1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0   */
    BODIC_BIT_VDD12L1_CLEAR         = 1,  /*!< Write a 1 clear the BODIF.VDD12L1.              
                                               This bit is self-cleared to 0.                   */
} BODIC_BIT_VDD12L1;

#define BODIC_ALL_VDD12L1_NO_EFFECT     ((0x0UL) << BODIC_ALL_VDD12L1_Pos)
#define BODIC_ALL_VDD12L1_CLEAR         ((0x1UL) << BODIC_ALL_VDD12L1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIC           VDD12H
 *  @access     POWER->BODIC.bit.VDD12H
 *  @brief      VDD12H interrupt flag clear
 */
#define BODIC_ALL_VDD12H_Pos (2)
#define BODIC_ALL_VDD12H_Msk (0x1UL << BODIC_ALL_VDD12H_Pos)

typedef enum
{
    BODIC_BIT_VDD12H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0   */
    BODIC_BIT_VDD12H_CLEAR         = 1,  /*!< Write a 1 clear the BODIF.VDD12H.               
                                              This bit is self-cleared to 0.                   */
} BODIC_BIT_VDD12H;

#define BODIC_ALL_VDD12H_NO_EFFECT     ((0x0UL) << BODIC_ALL_VDD12H_Pos)
#define BODIC_ALL_VDD12H_CLEAR         ((0x1UL) << BODIC_ALL_VDD12H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIC           VDD33L
 *  @access     POWER->BODIC.bit.VDD33L
 *  @brief      VDD33L interrupt flag clear
 */
#define BODIC_ALL_VDD33L_Pos (3)
#define BODIC_ALL_VDD33L_Msk (0x1UL << BODIC_ALL_VDD33L_Pos)

typedef enum
{
    BODIC_BIT_VDD33L_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0   */
    BODIC_BIT_VDD33L_CLEAR         = 1,  /*!< Write a 1 clear the BODIF.VDD33L.               
                                              This bit is self-cleared to 0.                   */
} BODIC_BIT_VDD33L;

#define BODIC_ALL_VDD33L_NO_EFFECT     ((0x0UL) << BODIC_ALL_VDD33L_Pos)
#define BODIC_ALL_VDD33L_CLEAR         ((0x1UL) << BODIC_ALL_VDD33L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIC           VDD33H
 *  @access     POWER->BODIC.bit.VDD33H
 *  @brief      VDD33H interrupt flag clear
 */
#define BODIC_ALL_VDD33H_Pos (4)
#define BODIC_ALL_VDD33H_Msk (0x1UL << BODIC_ALL_VDD33H_Pos)

typedef enum
{
    BODIC_BIT_VDD33H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0   */
    BODIC_BIT_VDD33H_CLEAR         = 1,  /*!< Write a 1 clear the BODIF.VDD33H.               
                                              This bit is self-cleared to 0.                   */
} BODIC_BIT_VDD33H;

#define BODIC_ALL_VDD33H_NO_EFFECT     ((0x0UL) << BODIC_ALL_VDD33H_Pos)
#define BODIC_ALL_VDD33H_CLEAR         ((0x1UL) << BODIC_ALL_VDD33H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIC           BODINT
 *  @access     POWER->BODIC.bit.BODINT
 *  @brief      BOD interrupt clear
 */
#define BODIC_ALL_BODINT_Pos (5)
#define BODIC_ALL_BODINT_Msk (0x1UL << BODIC_ALL_BODINT_Pos)

typedef enum
{
    BODIC_BIT_BODINT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0   */
    BODIC_BIT_BODINT_CLEAR         = 1,  /*!< Write a 1 clear the BODIF.BODINT.               
                                              This bit is self-cleared to 0.                   */
} BODIC_BIT_BODINT;

#define BODIC_ALL_BODINT_NO_EFFECT     ((0x0UL) << BODIC_ALL_BODINT_Pos)
#define BODIC_ALL_BODINT_CLEAR         ((0x1UL) << BODIC_ALL_BODINT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIE           VDD12L0
 *  @access     POWER->BODIE.bit.VDD12L0
 *  @brief      VDD12L0 interrupt enable
 */
#define BODIE_ALL_VDD12L0_Pos (0)
#define BODIE_ALL_VDD12L0_Msk (0x1UL << BODIE_ALL_VDD12L0_Pos)

typedef enum
{
    BODIE_BIT_VDD12L0_DISABLE     = 0,  /*!< VDD12L0 event does not generate interrupt   */
    BODIE_BIT_VDD12L0_ENABLE      = 1,  /*!< VDD12L0 event generates interrupt           */
} BODIE_BIT_VDD12L0;

#define BODIE_ALL_VDD12L0_DISABLE     ((0x0UL) << BODIE_ALL_VDD12L0_Pos)
#define BODIE_ALL_VDD12L0_ENABLE      ((0x1UL) << BODIE_ALL_VDD12L0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIE           VDD12L1
 *  @access     POWER->BODIE.bit.VDD12L1
 *  @brief      VDD12L1 interrupt enable
 */
#define BODIE_ALL_VDD12L1_Pos (1)
#define BODIE_ALL_VDD12L1_Msk (0x1UL << BODIE_ALL_VDD12L1_Pos)

typedef enum
{
    BODIE_BIT_VDD12L1_DISABLE     = 0,  /*!< VDD12L1 event does not generate interrupt   */
    BODIE_BIT_VDD12L1_ENABLE      = 1,  /*!< VDD12L1 event generates interrupt           */
} BODIE_BIT_VDD12L1;

#define BODIE_ALL_VDD12L1_DISABLE     ((0x0UL) << BODIE_ALL_VDD12L1_Pos)
#define BODIE_ALL_VDD12L1_ENABLE      ((0x1UL) << BODIE_ALL_VDD12L1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIE           VDD12H
 *  @access     POWER->BODIE.bit.VDD12H
 *  @brief      VDD12H interrupt enable
 */
#define BODIE_ALL_VDD12H_Pos (2)
#define BODIE_ALL_VDD12H_Msk (0x1UL << BODIE_ALL_VDD12H_Pos)

typedef enum
{
    BODIE_BIT_VDD12H_DISABLE     = 0,  /*!< VDD12H event does not generate interrupt   */
    BODIE_BIT_VDD12H_ENABLE      = 1,  /*!< VDD12H event generates interrupt           */
} BODIE_BIT_VDD12H;

#define BODIE_ALL_VDD12H_DISABLE     ((0x0UL) << BODIE_ALL_VDD12H_Pos)
#define BODIE_ALL_VDD12H_ENABLE      ((0x1UL) << BODIE_ALL_VDD12H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIE           VDD33L
 *  @access     POWER->BODIE.bit.VDD33L
 *  @brief      VDD33L interrupt enable
 */
#define BODIE_ALL_VDD33L_Pos (3)
#define BODIE_ALL_VDD33L_Msk (0x1UL << BODIE_ALL_VDD33L_Pos)

typedef enum
{
    BODIE_BIT_VDD33L_DISABLE     = 0,  /*!< VDD33L event does not generate interrupt   */
    BODIE_BIT_VDD33L_ENABLE      = 1,  /*!< VDD33L event generates interrupt           */
} BODIE_BIT_VDD33L;

#define BODIE_ALL_VDD33L_DISABLE     ((0x0UL) << BODIE_ALL_VDD33L_Pos)
#define BODIE_ALL_VDD33L_ENABLE      ((0x1UL) << BODIE_ALL_VDD33L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODIE           VDD33H
 *  @access     POWER->BODIE.bit.VDD33H
 *  @brief      VDD33H interrupt enable
 */
#define BODIE_ALL_VDD33H_Pos (4)
#define BODIE_ALL_VDD33H_Msk (0x1UL << BODIE_ALL_VDD33H_Pos)

typedef enum
{
    BODIE_BIT_VDD33H_DISABLE     = 0,  /*!< VDD33H event does not generate interrupt   */
    BODIE_BIT_VDD33H_ENABLE      = 1,  /*!< VDD33H event generates interrupt           */
} BODIE_BIT_VDD33H;

#define BODIE_ALL_VDD33H_DISABLE     ((0x0UL) << BODIE_ALL_VDD33H_Pos)
#define BODIE_ALL_VDD33H_ENABLE      ((0x1UL) << BODIE_ALL_VDD33H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BODCTL          VREFTRIM
 *  @access     POWER->BODCTL.bit.VREFTRIM
 *  @brief      BOD reference voltage trim
 */
#define BODCTL_ALL_VREFTRIM_Pos (0)
#define BODCTL_ALL_VREFTRIM_Msk (0xFUL << BODCTL_ALL_VREFTRIM_Pos)

typedef enum
{
    BODCTL_BIT_VREFTRIM_1dot062_V     = 0,  /*!< 1.062V   */
    BODCTL_BIT_VREFTRIM_1dot082_V     = 1,  /*!< 1.082V   */
    BODCTL_BIT_VREFTRIM_1dot102_V     = 2,  /*!< 1.102V   */
    BODCTL_BIT_VREFTRIM_1dot122_V     = 3,  /*!< 1.122V   */
    BODCTL_BIT_VREFTRIM_1dot143_V     = 4,  /*!< 1.143V   */
    BODCTL_BIT_VREFTRIM_1dot163_V     = 5,  /*!< 1.163V   */
    BODCTL_BIT_VREFTRIM_1dot183_V     = 6,  /*!< 1.183V   */
    BODCTL_BIT_VREFTRIM_1dot203_V     = 7,  /*!< 1.203V   */
    BODCTL_BIT_VREFTRIM_1dot223_V     = 8,  /*!< 1.223V   */
    BODCTL_BIT_VREFTRIM_1dot243_V     = 9,  /*!< 1.243V   */
    BODCTL_BIT_VREFTRIM_1dot263_V     = 10,  /*!< 1.263V   */
    BODCTL_BIT_VREFTRIM_1dot283_V     = 11,  /*!< 1.283V   */
    BODCTL_BIT_VREFTRIM_1dot303_V     = 12,  /*!< 1.303V   */
    BODCTL_BIT_VREFTRIM_1dot323_V     = 13,  /*!< 1.323V   */
    BODCTL_BIT_VREFTRIM_1dot343_V     = 14,  /*!< 1.343V   */
    BODCTL_BIT_VREFTRIM_1dot363_V     = 15,  /*!< 1.363V   */
} BODCTL_BIT_VREFTRIM;

#define BODCTL_ALL_VREFTRIM_1dot062_V     ((0x00UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot082_V     ((0x01UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot102_V     ((0x02UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot122_V     ((0x03UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot143_V     ((0x04UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot163_V     ((0x05UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot183_V     ((0x06UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot203_V     ((0x07UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot223_V     ((0x08UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot243_V     ((0x09UL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot263_V     ((0x0AUL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot283_V     ((0x0BUL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot303_V     ((0x0CUL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot323_V     ((0x0DUL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot343_V     ((0x0EUL) << BODCTL_ALL_VREFTRIM_Pos)
#define BODCTL_ALL_VREFTRIM_1dot363_V     ((0x0FUL) << BODCTL_ALL_VREFTRIM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD33CTL        ENL
 *  @access     POWER->BOD33CTL.bit.ENL
 *  @brief      VDD33L BOD enable
 */
#define BOD33CTL_ALL_ENL_Pos (0)
#define BOD33CTL_ALL_ENL_Msk (0x1UL << BOD33CTL_ALL_ENL_Pos)

typedef enum
{
    BOD33CTL_BIT_ENL_DISABLE     = 0,  /*!< Disable   */
    BOD33CTL_BIT_ENL_ENABLE      = 1,  /*!< Enable    */
} BOD33CTL_BIT_ENL;

#define BOD33CTL_ALL_ENL_DISABLE     ((0x0UL) << BOD33CTL_ALL_ENL_Pos)
#define BOD33CTL_ALL_ENL_ENABLE      ((0x1UL) << BOD33CTL_ALL_ENL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD33CTL        ASVTHL
 *  @access     POWER->BOD33CTL.bit.ASVTHL
 *  @brief      Select the threshold voltage to assert VDD33L when 3.3V supply is going low
 */
#define BOD33CTL_ALL_ASVTHL_Pos (1)
#define BOD33CTL_ALL_ASVTHL_Msk (0x7UL << BOD33CTL_ALL_ASVTHL_Pos)

typedef enum
{
    BOD33CTL_BIT_ASVTHL_2dot58_V     = 0,  /*!< 2.58V   */
    BOD33CTL_BIT_ASVTHL_2dot65_V     = 1,  /*!< 2.65V   */
    BOD33CTL_BIT_ASVTHL_2dot72_V     = 2,  /*!< 2.72V   */
    BOD33CTL_BIT_ASVTHL_2dot79_V     = 3,  /*!< 2.79V   */
    BOD33CTL_BIT_ASVTHL_2dot86_V     = 4,  /*!< 2.86V   */
    BOD33CTL_BIT_ASVTHL_2dot94_V     = 5,  /*!< 2.94V   */
    BOD33CTL_BIT_ASVTHL_3dot03_V     = 6,  /*!< 3.03V   */
    BOD33CTL_BIT_ASVTHL_3dot12_V     = 7,  /*!< 3.12V   */
} BOD33CTL_BIT_ASVTHL;

#define BOD33CTL_ALL_ASVTHL_2dot58_V     ((0x0UL) << BOD33CTL_ALL_ASVTHL_Pos)
#define BOD33CTL_ALL_ASVTHL_2dot65_V     ((0x1UL) << BOD33CTL_ALL_ASVTHL_Pos)
#define BOD33CTL_ALL_ASVTHL_2dot72_V     ((0x2UL) << BOD33CTL_ALL_ASVTHL_Pos)
#define BOD33CTL_ALL_ASVTHL_2dot79_V     ((0x3UL) << BOD33CTL_ALL_ASVTHL_Pos)
#define BOD33CTL_ALL_ASVTHL_2dot86_V     ((0x4UL) << BOD33CTL_ALL_ASVTHL_Pos)
#define BOD33CTL_ALL_ASVTHL_2dot94_V     ((0x5UL) << BOD33CTL_ALL_ASVTHL_Pos)
#define BOD33CTL_ALL_ASVTHL_3dot03_V     ((0x6UL) << BOD33CTL_ALL_ASVTHL_Pos)
#define BOD33CTL_ALL_ASVTHL_3dot12_V     ((0x7UL) << BOD33CTL_ALL_ASVTHL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD33CTL        DEVTHL
 *  @access     POWER->BOD33CTL.bit.DEVTHL
 *  @brief      Select the threshold voltage to deassert VDD33L when 3.3V supply is going high
 */
#define BOD33CTL_ALL_DEVTHL_Pos (4)
#define BOD33CTL_ALL_DEVTHL_Msk (0x7UL << BOD33CTL_ALL_DEVTHL_Pos)

typedef enum
{
    BOD33CTL_BIT_DEVTHL_2dot58_V     = 0,  /*!< 2.58V   */
    BOD33CTL_BIT_DEVTHL_2dot65_V     = 1,  /*!< 2.65V   */
    BOD33CTL_BIT_DEVTHL_2dot72_V     = 2,  /*!< 2.72V   */
    BOD33CTL_BIT_DEVTHL_2dot79_V     = 3,  /*!< 2.79V   */
    BOD33CTL_BIT_DEVTHL_2dot86_V     = 4,  /*!< 2.86V   */
    BOD33CTL_BIT_DEVTHL_2dot94_V     = 5,  /*!< 2.94V   */
    BOD33CTL_BIT_DEVTHL_3dot03_V     = 6,  /*!< 3.03V   */
    BOD33CTL_BIT_DEVTHL_3dot12_V     = 7,  /*!< 3.12V   */
} BOD33CTL_BIT_DEVTHL;

#define BOD33CTL_ALL_DEVTHL_2dot58_V     ((0x0UL) << BOD33CTL_ALL_DEVTHL_Pos)
#define BOD33CTL_ALL_DEVTHL_2dot65_V     ((0x1UL) << BOD33CTL_ALL_DEVTHL_Pos)
#define BOD33CTL_ALL_DEVTHL_2dot72_V     ((0x2UL) << BOD33CTL_ALL_DEVTHL_Pos)
#define BOD33CTL_ALL_DEVTHL_2dot79_V     ((0x3UL) << BOD33CTL_ALL_DEVTHL_Pos)
#define BOD33CTL_ALL_DEVTHL_2dot86_V     ((0x4UL) << BOD33CTL_ALL_DEVTHL_Pos)
#define BOD33CTL_ALL_DEVTHL_2dot94_V     ((0x5UL) << BOD33CTL_ALL_DEVTHL_Pos)
#define BOD33CTL_ALL_DEVTHL_3dot03_V     ((0x6UL) << BOD33CTL_ALL_DEVTHL_Pos)
#define BOD33CTL_ALL_DEVTHL_3dot12_V     ((0x7UL) << BOD33CTL_ALL_DEVTHL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD33CTL        ENH
 *  @access     POWER->BOD33CTL.bit.ENH
 *  @brief      VDD33H BOD enable
 */
#define BOD33CTL_ALL_ENH_Pos (8)
#define BOD33CTL_ALL_ENH_Msk (0x1UL << BOD33CTL_ALL_ENH_Pos)

typedef enum
{
    BOD33CTL_BIT_ENH_DISABLE     = 0,  /*!< Disable   */
    BOD33CTL_BIT_ENH_ENABLE      = 1,  /*!< Enable    */
} BOD33CTL_BIT_ENH;

#define BOD33CTL_ALL_ENH_DISABLE     ((0x0UL) << BOD33CTL_ALL_ENH_Pos)
#define BOD33CTL_ALL_ENH_ENABLE      ((0x1UL) << BOD33CTL_ALL_ENH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD33CTL        ASVTHH
 *  @access     POWER->BOD33CTL.bit.ASVTHH
 *  @brief      Select the threshold voltage to assert VDD33H when 3.3V supply is going high
 */
#define BOD33CTL_ALL_ASVTHH_Pos (9)
#define BOD33CTL_ALL_ASVTHH_Msk (0x7UL << BOD33CTL_ALL_ASVTHH_Pos)

typedef enum
{
    BOD33CTL_BIT_ASVTHH_3dot31_V     = 0,  /*!< 3.31V   */
    BOD33CTL_BIT_ASVTHH_3dot42_V     = 1,  /*!< 3.42V   */
    BOD33CTL_BIT_ASVTHH_3dot53_V     = 2,  /*!< 3.53V   */
    BOD33CTL_BIT_ASVTHH_3dot66_V     = 3,  /*!< 3.66V   */
    BOD33CTL_BIT_ASVTHH_3dot79_V     = 4,  /*!< 3.79V   */
    BOD33CTL_BIT_ASVTHH_3dot93_V     = 5,  /*!< 3.93V   */
    BOD33CTL_BIT_ASVTHH_4dot08_V     = 6,  /*!< 4.08V   */
    BOD33CTL_BIT_ASVTHH_4dot24_V     = 7,  /*!< 4.24V   */
} BOD33CTL_BIT_ASVTHH;

#define BOD33CTL_ALL_ASVTHH_3dot31_V     ((0x0UL) << BOD33CTL_ALL_ASVTHH_Pos)
#define BOD33CTL_ALL_ASVTHH_3dot42_V     ((0x1UL) << BOD33CTL_ALL_ASVTHH_Pos)
#define BOD33CTL_ALL_ASVTHH_3dot53_V     ((0x2UL) << BOD33CTL_ALL_ASVTHH_Pos)
#define BOD33CTL_ALL_ASVTHH_3dot66_V     ((0x3UL) << BOD33CTL_ALL_ASVTHH_Pos)
#define BOD33CTL_ALL_ASVTHH_3dot79_V     ((0x4UL) << BOD33CTL_ALL_ASVTHH_Pos)
#define BOD33CTL_ALL_ASVTHH_3dot93_V     ((0x5UL) << BOD33CTL_ALL_ASVTHH_Pos)
#define BOD33CTL_ALL_ASVTHH_4dot08_V     ((0x6UL) << BOD33CTL_ALL_ASVTHH_Pos)
#define BOD33CTL_ALL_ASVTHH_4dot24_V     ((0x7UL) << BOD33CTL_ALL_ASVTHH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD33CTL        DEVTHH
 *  @access     POWER->BOD33CTL.bit.DEVTHH
 *  @brief      Select the threshold voltage to deassert VDD33H when 3.3V supply is going low
 */
#define BOD33CTL_ALL_DEVTHH_Pos (12)
#define BOD33CTL_ALL_DEVTHH_Msk (0x7UL << BOD33CTL_ALL_DEVTHH_Pos)

typedef enum
{
    BOD33CTL_BIT_DEVTHH_3dot31_V     = 0,  /*!< 3.31V   */
    BOD33CTL_BIT_DEVTHH_3dot42_V     = 1,  /*!< 3.42V   */
    BOD33CTL_BIT_DEVTHH_3dot53_V     = 2,  /*!< 3.53V   */
    BOD33CTL_BIT_DEVTHH_3dot66_V     = 3,  /*!< 3.66V   */
    BOD33CTL_BIT_DEVTHH_3dot79_V     = 4,  /*!< 3.79V   */
    BOD33CTL_BIT_DEVTHH_3dot93_V     = 5,  /*!< 3.93V   */
    BOD33CTL_BIT_DEVTHH_4dot08_V     = 6,  /*!< 4.08V   */
    BOD33CTL_BIT_DEVTHH_4dot24_V     = 7,  /*!< 4.24V   */
} BOD33CTL_BIT_DEVTHH;

#define BOD33CTL_ALL_DEVTHH_3dot31_V     ((0x0UL) << BOD33CTL_ALL_DEVTHH_Pos)
#define BOD33CTL_ALL_DEVTHH_3dot42_V     ((0x1UL) << BOD33CTL_ALL_DEVTHH_Pos)
#define BOD33CTL_ALL_DEVTHH_3dot53_V     ((0x2UL) << BOD33CTL_ALL_DEVTHH_Pos)
#define BOD33CTL_ALL_DEVTHH_3dot66_V     ((0x3UL) << BOD33CTL_ALL_DEVTHH_Pos)
#define BOD33CTL_ALL_DEVTHH_3dot79_V     ((0x4UL) << BOD33CTL_ALL_DEVTHH_Pos)
#define BOD33CTL_ALL_DEVTHH_3dot93_V     ((0x5UL) << BOD33CTL_ALL_DEVTHH_Pos)
#define BOD33CTL_ALL_DEVTHH_4dot08_V     ((0x6UL) << BOD33CTL_ALL_DEVTHH_Pos)
#define BOD33CTL_ALL_DEVTHH_4dot24_V     ((0x7UL) << BOD33CTL_ALL_DEVTHH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        ENL0
 *  @access     POWER->BOD12CTL.bit.ENL0
 *  @brief      VDD12L0 BOD enable
 */
#define BOD12CTL_ALL_ENL0_Pos (0)
#define BOD12CTL_ALL_ENL0_Msk (0x1UL << BOD12CTL_ALL_ENL0_Pos)

typedef enum
{
    BOD12CTL_BIT_ENL0_DISABLE     = 0,  /*!< Disable   */
    BOD12CTL_BIT_ENL0_ENABLE      = 1,  /*!< Enable    */
} BOD12CTL_BIT_ENL0;

#define BOD12CTL_ALL_ENL0_DISABLE     ((0x0UL) << BOD12CTL_ALL_ENL0_Pos)
#define BOD12CTL_ALL_ENL0_ENABLE      ((0x1UL) << BOD12CTL_ALL_ENL0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        ASVTHL0
 *  @access     POWER->BOD12CTL.bit.ASVTHL0
 *  @brief      Select the threshold voltage to assert VDD12L0 when 1.2V supply is going low
 */
#define BOD12CTL_ALL_ASVTHL0_Pos (1)
#define BOD12CTL_ALL_ASVTHL0_Msk (0x7UL << BOD12CTL_ALL_ASVTHL0_Pos)

typedef enum
{
    BOD12CTL_BIT_ASVTHL0_0dot94_V     = 0,  /*!< 0.94V   */
    BOD12CTL_BIT_ASVTHL0_0dot97_V     = 1,  /*!< 0.97V   */
    BOD12CTL_BIT_ASVTHL0_0dot99_V     = 2,  /*!< 0.99V   */
    BOD12CTL_BIT_ASVTHL0_1dot02_V     = 3,  /*!< 1.02V   */
    BOD12CTL_BIT_ASVTHL0_1dot04_V     = 4,  /*!< 1.04V   */
    BOD12CTL_BIT_ASVTHL0_1dot07_V     = 5,  /*!< 1.07V   */
    BOD12CTL_BIT_ASVTHL0_1dot10_V     = 6,  /*!< 1.10V   */
    BOD12CTL_BIT_ASVTHL0_1dot14_V     = 7,  /*!< 1.14V   */
} BOD12CTL_BIT_ASVTHL0;

#define BOD12CTL_ALL_ASVTHL0_0dot94_V     ((0x0UL) << BOD12CTL_ALL_ASVTHL0_Pos)
#define BOD12CTL_ALL_ASVTHL0_0dot97_V     ((0x1UL) << BOD12CTL_ALL_ASVTHL0_Pos)
#define BOD12CTL_ALL_ASVTHL0_0dot99_V     ((0x2UL) << BOD12CTL_ALL_ASVTHL0_Pos)
#define BOD12CTL_ALL_ASVTHL0_1dot02_V     ((0x3UL) << BOD12CTL_ALL_ASVTHL0_Pos)
#define BOD12CTL_ALL_ASVTHL0_1dot04_V     ((0x4UL) << BOD12CTL_ALL_ASVTHL0_Pos)
#define BOD12CTL_ALL_ASVTHL0_1dot07_V     ((0x5UL) << BOD12CTL_ALL_ASVTHL0_Pos)
#define BOD12CTL_ALL_ASVTHL0_1dot10_V     ((0x6UL) << BOD12CTL_ALL_ASVTHL0_Pos)
#define BOD12CTL_ALL_ASVTHL0_1dot14_V     ((0x7UL) << BOD12CTL_ALL_ASVTHL0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        DEVTHL0
 *  @access     POWER->BOD12CTL.bit.DEVTHL0
 *  @brief      Select the threshold voltage to deassert VDD12L0 when 1.2V supply is going high
 */
#define BOD12CTL_ALL_DEVTHL0_Pos (4)
#define BOD12CTL_ALL_DEVTHL0_Msk (0x7UL << BOD12CTL_ALL_DEVTHL0_Pos)

typedef enum
{
    BOD12CTL_BIT_DEVTHL0_0dot94_V     = 0,  /*!< 0.94V   */
    BOD12CTL_BIT_DEVTHL0_0dot97_V     = 1,  /*!< 0.97V   */
    BOD12CTL_BIT_DEVTHL0_0dot99_V     = 2,  /*!< 0.99V   */
    BOD12CTL_BIT_DEVTHL0_1dot02_V     = 3,  /*!< 1.02V   */
    BOD12CTL_BIT_DEVTHL0_1dot04_V     = 4,  /*!< 1.04V   */
    BOD12CTL_BIT_DEVTHL0_1dot07_V     = 5,  /*!< 1.07V   */
    BOD12CTL_BIT_DEVTHL0_1dot10_V     = 6,  /*!< 1.10V   */
    BOD12CTL_BIT_DEVTHL0_1dot14_V     = 7,  /*!< 1.14V   */
} BOD12CTL_BIT_DEVTHL0;

#define BOD12CTL_ALL_DEVTHL0_0dot94_V     ((0x0UL) << BOD12CTL_ALL_DEVTHL0_Pos)
#define BOD12CTL_ALL_DEVTHL0_0dot97_V     ((0x1UL) << BOD12CTL_ALL_DEVTHL0_Pos)
#define BOD12CTL_ALL_DEVTHL0_0dot99_V     ((0x2UL) << BOD12CTL_ALL_DEVTHL0_Pos)
#define BOD12CTL_ALL_DEVTHL0_1dot02_V     ((0x3UL) << BOD12CTL_ALL_DEVTHL0_Pos)
#define BOD12CTL_ALL_DEVTHL0_1dot04_V     ((0x4UL) << BOD12CTL_ALL_DEVTHL0_Pos)
#define BOD12CTL_ALL_DEVTHL0_1dot07_V     ((0x5UL) << BOD12CTL_ALL_DEVTHL0_Pos)
#define BOD12CTL_ALL_DEVTHL0_1dot10_V     ((0x6UL) << BOD12CTL_ALL_DEVTHL0_Pos)
#define BOD12CTL_ALL_DEVTHL0_1dot14_V     ((0x7UL) << BOD12CTL_ALL_DEVTHL0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        ENL1
 *  @access     POWER->BOD12CTL.bit.ENL1
 *  @brief      VDD12L1 BOD enable
 */
#define BOD12CTL_ALL_ENL1_Pos (8)
#define BOD12CTL_ALL_ENL1_Msk (0x1UL << BOD12CTL_ALL_ENL1_Pos)

typedef enum
{
    BOD12CTL_BIT_ENL1_DISABLE     = 0,  /*!< Disable   */
    BOD12CTL_BIT_ENL1_ENABLE      = 1,  /*!< Enable    */
} BOD12CTL_BIT_ENL1;

#define BOD12CTL_ALL_ENL1_DISABLE     ((0x0UL) << BOD12CTL_ALL_ENL1_Pos)
#define BOD12CTL_ALL_ENL1_ENABLE      ((0x1UL) << BOD12CTL_ALL_ENL1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        ASVTHL1
 *  @access     POWER->BOD12CTL.bit.ASVTHL1
 *  @brief      Select the threshold voltage to assert VDD12L1 when 1.2V supply is going low
 */
#define BOD12CTL_ALL_ASVTHL1_Pos (9)
#define BOD12CTL_ALL_ASVTHL1_Msk (0x7UL << BOD12CTL_ALL_ASVTHL1_Pos)

typedef enum
{
    BOD12CTL_BIT_ASVTHL1_0dot94_V     = 0,  /*!< 0.94V   */
    BOD12CTL_BIT_ASVTHL1_0dot97_V     = 1,  /*!< 0.97V   */
    BOD12CTL_BIT_ASVTHL1_0dot99_V     = 2,  /*!< 0.99V   */
    BOD12CTL_BIT_ASVTHL1_1dot02_V     = 3,  /*!< 1.02V   */
    BOD12CTL_BIT_ASVTHL1_1dot04_V     = 4,  /*!< 1.04V   */
    BOD12CTL_BIT_ASVTHL1_1dot07_V     = 5,  /*!< 1.07V   */
    BOD12CTL_BIT_ASVTHL1_1dot10_V     = 6,  /*!< 1.10V   */
    BOD12CTL_BIT_ASVTHL1_1dot14_V     = 7,  /*!< 1.14V   */
} BOD12CTL_BIT_ASVTHL1;

#define BOD12CTL_ALL_ASVTHL1_0dot94_V     ((0x0UL) << BOD12CTL_ALL_ASVTHL1_Pos)
#define BOD12CTL_ALL_ASVTHL1_0dot97_V     ((0x1UL) << BOD12CTL_ALL_ASVTHL1_Pos)
#define BOD12CTL_ALL_ASVTHL1_0dot99_V     ((0x2UL) << BOD12CTL_ALL_ASVTHL1_Pos)
#define BOD12CTL_ALL_ASVTHL1_1dot02_V     ((0x3UL) << BOD12CTL_ALL_ASVTHL1_Pos)
#define BOD12CTL_ALL_ASVTHL1_1dot04_V     ((0x4UL) << BOD12CTL_ALL_ASVTHL1_Pos)
#define BOD12CTL_ALL_ASVTHL1_1dot07_V     ((0x5UL) << BOD12CTL_ALL_ASVTHL1_Pos)
#define BOD12CTL_ALL_ASVTHL1_1dot10_V     ((0x6UL) << BOD12CTL_ALL_ASVTHL1_Pos)
#define BOD12CTL_ALL_ASVTHL1_1dot14_V     ((0x7UL) << BOD12CTL_ALL_ASVTHL1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        DEVTHL1
 *  @access     POWER->BOD12CTL.bit.DEVTHL1
 *  @brief      Select the threshold voltage to deassert VDD12L1 when 1.2V supply is going high
 */
#define BOD12CTL_ALL_DEVTHL1_Pos (12)
#define BOD12CTL_ALL_DEVTHL1_Msk (0x7UL << BOD12CTL_ALL_DEVTHL1_Pos)

typedef enum
{
    BOD12CTL_BIT_DEVTHL1_0dot94_V     = 0,  /*!< 0.94V   */
    BOD12CTL_BIT_DEVTHL1_0dot97_V     = 1,  /*!< 0.97V   */
    BOD12CTL_BIT_DEVTHL1_0dot99_V     = 2,  /*!< 0.99V   */
    BOD12CTL_BIT_DEVTHL1_1dot02_V     = 3,  /*!< 1.02V   */
    BOD12CTL_BIT_DEVTHL1_1dot04_V     = 4,  /*!< 1.04V   */
    BOD12CTL_BIT_DEVTHL1_1dot07_V     = 5,  /*!< 1.07V   */
    BOD12CTL_BIT_DEVTHL1_1dot10_V     = 6,  /*!< 1.10V   */
    BOD12CTL_BIT_DEVTHL1_1dot14_V     = 7,  /*!< 1.14V   */
} BOD12CTL_BIT_DEVTHL1;

#define BOD12CTL_ALL_DEVTHL1_0dot94_V     ((0x0UL) << BOD12CTL_ALL_DEVTHL1_Pos)
#define BOD12CTL_ALL_DEVTHL1_0dot97_V     ((0x1UL) << BOD12CTL_ALL_DEVTHL1_Pos)
#define BOD12CTL_ALL_DEVTHL1_0dot99_V     ((0x2UL) << BOD12CTL_ALL_DEVTHL1_Pos)
#define BOD12CTL_ALL_DEVTHL1_1dot02_V     ((0x3UL) << BOD12CTL_ALL_DEVTHL1_Pos)
#define BOD12CTL_ALL_DEVTHL1_1dot04_V     ((0x4UL) << BOD12CTL_ALL_DEVTHL1_Pos)
#define BOD12CTL_ALL_DEVTHL1_1dot07_V     ((0x5UL) << BOD12CTL_ALL_DEVTHL1_Pos)
#define BOD12CTL_ALL_DEVTHL1_1dot10_V     ((0x6UL) << BOD12CTL_ALL_DEVTHL1_Pos)
#define BOD12CTL_ALL_DEVTHL1_1dot14_V     ((0x7UL) << BOD12CTL_ALL_DEVTHL1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        ENH
 *  @access     POWER->BOD12CTL.bit.ENH
 *  @brief      VDD12H BOD enable
 */
#define BOD12CTL_ALL_ENH_Pos (16)
#define BOD12CTL_ALL_ENH_Msk (0x1UL << BOD12CTL_ALL_ENH_Pos)

typedef enum
{
    BOD12CTL_BIT_ENH_DISABLE     = 0,  /*!< Disable   */
    BOD12CTL_BIT_ENH_ENABLE      = 1,  /*!< Enable    */
} BOD12CTL_BIT_ENH;

#define BOD12CTL_ALL_ENH_DISABLE     ((0x0UL) << BOD12CTL_ALL_ENH_Pos)
#define BOD12CTL_ALL_ENH_ENABLE      ((0x1UL) << BOD12CTL_ALL_ENH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        ASVTHH
 *  @access     POWER->BOD12CTL.bit.ASVTHH
 *  @brief      Select the threshold voltage to assert VDD12H when 1.2V supply is going high
 */
#define BOD12CTL_ALL_ASVTHH_Pos (17)
#define BOD12CTL_ALL_ASVTHH_Msk (0x7UL << BOD12CTL_ALL_ASVTHH_Pos)

typedef enum
{
    BOD12CTL_BIT_ASVTHH_1dot31_V     = 0,  /*!< 1.31V   */
    BOD12CTL_BIT_ASVTHH_1dot33_V     = 1,  /*!< 1.33V   */
    BOD12CTL_BIT_ASVTHH_1dot36_V     = 2,  /*!< 1.36V   */
    BOD12CTL_BIT_ASVTHH_1dot38_V     = 3,  /*!< 1.38V   */
    BOD12CTL_BIT_ASVTHH_1dot41_V     = 4,  /*!< 1.41V   */
    BOD12CTL_BIT_ASVTHH_1dot43_V     = 5,  /*!< 1.43V   */
    BOD12CTL_BIT_ASVTHH_1dot46_V     = 6,  /*!< 1.46V   */
    BOD12CTL_BIT_ASVTHH_1dot49_V     = 7,  /*!< 1.49V   */
} BOD12CTL_BIT_ASVTHH;

#define BOD12CTL_ALL_ASVTHH_1dot31_V     ((0x0UL) << BOD12CTL_ALL_ASVTHH_Pos)
#define BOD12CTL_ALL_ASVTHH_1dot33_V     ((0x1UL) << BOD12CTL_ALL_ASVTHH_Pos)
#define BOD12CTL_ALL_ASVTHH_1dot36_V     ((0x2UL) << BOD12CTL_ALL_ASVTHH_Pos)
#define BOD12CTL_ALL_ASVTHH_1dot38_V     ((0x3UL) << BOD12CTL_ALL_ASVTHH_Pos)
#define BOD12CTL_ALL_ASVTHH_1dot41_V     ((0x4UL) << BOD12CTL_ALL_ASVTHH_Pos)
#define BOD12CTL_ALL_ASVTHH_1dot43_V     ((0x5UL) << BOD12CTL_ALL_ASVTHH_Pos)
#define BOD12CTL_ALL_ASVTHH_1dot46_V     ((0x6UL) << BOD12CTL_ALL_ASVTHH_Pos)
#define BOD12CTL_ALL_ASVTHH_1dot49_V     ((0x7UL) << BOD12CTL_ALL_ASVTHH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           BOD12CTL        DEVTHH
 *  @access     POWER->BOD12CTL.bit.DEVTHH
 *  @brief      Select the threshold voltage to deassert VDD12H when 1.2V supply is going low
 */
#define BOD12CTL_ALL_DEVTHH_Pos (20)
#define BOD12CTL_ALL_DEVTHH_Msk (0x7UL << BOD12CTL_ALL_DEVTHH_Pos)

typedef enum
{
    BOD12CTL_BIT_DEVTHH_1dot31_V     = 0,  /*!< 1.31V   */
    BOD12CTL_BIT_DEVTHH_1dot33_V     = 1,  /*!< 1.33V   */
    BOD12CTL_BIT_DEVTHH_1dot36_V     = 2,  /*!< 1.36V   */
    BOD12CTL_BIT_DEVTHH_1dot38_V     = 3,  /*!< 1.38V   */
    BOD12CTL_BIT_DEVTHH_1dot41_V     = 4,  /*!< 1.41V   */
    BOD12CTL_BIT_DEVTHH_1dot43_V     = 5,  /*!< 1.43V   */
    BOD12CTL_BIT_DEVTHH_1dot46_V     = 6,  /*!< 1.46V   */
    BOD12CTL_BIT_DEVTHH_1dot49_V     = 7,  /*!< 1.49V   */
} BOD12CTL_BIT_DEVTHH;

#define BOD12CTL_ALL_DEVTHH_1dot31_V     ((0x0UL) << BOD12CTL_ALL_DEVTHH_Pos)
#define BOD12CTL_ALL_DEVTHH_1dot33_V     ((0x1UL) << BOD12CTL_ALL_DEVTHH_Pos)
#define BOD12CTL_ALL_DEVTHH_1dot36_V     ((0x2UL) << BOD12CTL_ALL_DEVTHH_Pos)
#define BOD12CTL_ALL_DEVTHH_1dot38_V     ((0x3UL) << BOD12CTL_ALL_DEVTHH_Pos)
#define BOD12CTL_ALL_DEVTHH_1dot41_V     ((0x4UL) << BOD12CTL_ALL_DEVTHH_Pos)
#define BOD12CTL_ALL_DEVTHH_1dot43_V     ((0x5UL) << BOD12CTL_ALL_DEVTHH_Pos)
#define BOD12CTL_ALL_DEVTHH_1dot46_V     ((0x6UL) << BOD12CTL_ALL_DEVTHH_Pos)
#define BOD12CTL_ALL_DEVTHH_1dot49_V     ((0x7UL) << BOD12CTL_ALL_DEVTHH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           DPSLPKEY        KEY
 *  @access     POWER->DPSLPKEY.bit.KEY
 *  @brief      Write 0x51ee9 to force the system go into deep sleep
 */
#define DPSLPKEY_ALL_KEY_Pos (0)
#define DPSLPKEY_ALL_KEY_Msk (0xFFFFFFFFUL << DPSLPKEY_ALL_KEY_Pos)

#define DPSLPKEY_BIT_KEY

#define DPSLPKEY_ALL_KEY_(x) ((x) << DPSLPKEY_ALL_KEY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   POWER           PWRREGKEY       KEY
 *  @access     POWER->PWRREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected power registers
 */
#define PWRREGKEY_ALL_KEY_Pos (0)
#define PWRREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << PWRREGKEY_ALL_KEY_Pos)

#define PWRREGKEY_BIT_KEY

#define PWRREGKEY_ALL_KEY_(x) ((x) << PWRREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     CLOCK
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          RCO0RDY
 *  @access     CLOCK->CLKSTS.bit.RCO0RDY
 *  @brief      RCO0 clock ready indicator
 */
#define CLKSTS_ALL_RCO0RDY_Pos (0)
#define CLKSTS_ALL_RCO0RDY_Msk (0x1UL << CLKSTS_ALL_RCO0RDY_Pos)

typedef enum
{
    CLKSTS_BIT_RCO0RDY_NOT_READY     = 0,  /*!< Not ready   */
    CLKSTS_BIT_RCO0RDY_READY         = 1,  /*!< Ready       */
} CLKSTS_BIT_RCO0RDY;

#define CLKSTS_ALL_RCO0RDY_NOT_READY     ((0x0UL) << CLKSTS_ALL_RCO0RDY_Pos)
#define CLKSTS_ALL_RCO0RDY_READY         ((0x1UL) << CLKSTS_ALL_RCO0RDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          RCO1RDY
 *  @access     CLOCK->CLKSTS.bit.RCO1RDY
 *  @brief      RCO1 clock ready indicator
 */
#define CLKSTS_ALL_RCO1RDY_Pos (1)
#define CLKSTS_ALL_RCO1RDY_Msk (0x1UL << CLKSTS_ALL_RCO1RDY_Pos)

typedef enum
{
    CLKSTS_BIT_RCO1RDY_NOT_READY     = 0,  /*!< Not ready   */
    CLKSTS_BIT_RCO1RDY_READY         = 1,  /*!< Ready       */
} CLKSTS_BIT_RCO1RDY;

#define CLKSTS_ALL_RCO1RDY_NOT_READY     ((0x0UL) << CLKSTS_ALL_RCO1RDY_Pos)
#define CLKSTS_ALL_RCO1RDY_READY         ((0x1UL) << CLKSTS_ALL_RCO1RDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          XORDY
 *  @access     CLOCK->CLKSTS.bit.XORDY
 *  @brief      XO clock ready indicator
 */
#define CLKSTS_ALL_XORDY_Pos (2)
#define CLKSTS_ALL_XORDY_Msk (0x1UL << CLKSTS_ALL_XORDY_Pos)

typedef enum
{
    CLKSTS_BIT_XORDY_NOT_READY     = 0,  /*!< Not ready   */
    CLKSTS_BIT_XORDY_READY         = 1,  /*!< Ready       */
} CLKSTS_BIT_XORDY;

#define CLKSTS_ALL_XORDY_NOT_READY     ((0x0UL) << CLKSTS_ALL_XORDY_Pos)
#define CLKSTS_ALL_XORDY_READY         ((0x1UL) << CLKSTS_ALL_XORDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          PLLRDY
 *  @access     CLOCK->CLKSTS.bit.PLLRDY
 *  @brief      PLL analog clock ready indicator
 */
#define CLKSTS_ALL_PLLRDY_Pos (3)
#define CLKSTS_ALL_PLLRDY_Msk (0x1UL << CLKSTS_ALL_PLLRDY_Pos)

typedef enum
{
    CLKSTS_BIT_PLLRDY_NOT_READY     = 0,  /*!< Not ready   */
    CLKSTS_BIT_PLLRDY_READY         = 1,  /*!< Ready       */
} CLKSTS_BIT_PLLRDY;

#define CLKSTS_ALL_PLLRDY_NOT_READY     ((0x0UL) << CLKSTS_ALL_PLLRDY_Pos)
#define CLKSTS_ALL_PLLRDY_READY         ((0x1UL) << CLKSTS_ALL_PLLRDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          VCOFREQ
 *  @access     CLOCK->CLKSTS.bit.VCOFREQ
 *  @brief      VCO frequency flag for trimming
 */
#define CLKSTS_ALL_VCOFREQ_Pos (4)
#define CLKSTS_ALL_VCOFREQ_Msk (0x1UL << CLKSTS_ALL_VCOFREQ_Pos)

typedef enum
{
    CLKSTS_BIT_VCOFREQ_TOO_SLOW     = 0,  /*!< VCO in PLL is too slow   */
    CLKSTS_BIT_VCOFREQ_TOO_FAST     = 1,  /*!< VCO in PLL is too fast   */
} CLKSTS_BIT_VCOFREQ;

#define CLKSTS_ALL_VCOFREQ_TOO_SLOW     ((0x0UL) << CLKSTS_ALL_VCOFREQ_Pos)
#define CLKSTS_ALL_VCOFREQ_TOO_FAST     ((0x1UL) << CLKSTS_ALL_VCOFREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          VCOFREQVLD
 *  @access     CLOCK->CLKSTS.bit.VCOFREQVLD
 *  @brief      VCOFREQ flag valid indicator
 */
#define CLKSTS_ALL_VCOFREQVLD_Pos (5)
#define CLKSTS_ALL_VCOFREQVLD_Msk (0x1UL << CLKSTS_ALL_VCOFREQVLD_Pos)

typedef enum
{
    CLKSTS_BIT_VCOFREQVLD_INVALID     = 0,  /*!< VCOFREQ is invalid   */
    CLKSTS_BIT_VCOFREQVLD_VALID       = 1,  /*!< VCOFREQ is valid     */
} CLKSTS_BIT_VCOFREQVLD;

#define CLKSTS_ALL_VCOFREQVLD_INVALID     ((0x0UL) << CLKSTS_ALL_VCOFREQVLD_Pos)
#define CLKSTS_ALL_VCOFREQVLD_VALID       ((0x1UL) << CLKSTS_ALL_VCOFREQVLD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          PLLFAST
 *  @access     CLOCK->CLKSTS.bit.PLLFAST
 *  @brief      Indicate PLL is unlocked and faster than expected.
 *              Possible reason can be:
 *              1. Fin/NIN*NFB/65536 is lower than 400MHz (lower boundary of VCO free-running frequency)
 *              2. The reference clock input is somehow missing
 *              3. Malfunction of feedback divider so that the equivalent dividing ratio is lower
 *              than expected.
 */
#define CLKSTS_ALL_PLLFAST_Pos (6)
#define CLKSTS_ALL_PLLFAST_Msk (0x1UL << CLKSTS_ALL_PLLFAST_Pos)

typedef enum
{
    CLKSTS_BIT_PLLFAST_NOT_OCCUR     = 0,  /*!<    */
    CLKSTS_BIT_PLLFAST_OCCUR         = 1,  /*!<    */
} CLKSTS_BIT_PLLFAST;

#define CLKSTS_ALL_PLLFAST_NOT_OCCUR     ((0x0UL) << CLKSTS_ALL_PLLFAST_Pos)
#define CLKSTS_ALL_PLLFAST_OCCUR         ((0x1UL) << CLKSTS_ALL_PLLFAST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          PLLSLOW
 *  @access     CLOCK->CLKSTS.bit.PLLSLOW
 *  @brief      Indicate PLL is unlocked and slower than expected.
 *              Possible reason can be:
 *              1. Fin/NIN*NFB/65536 is higher than 600MHz (upper boundary of VCO free-running frequency)
 *              2. VCO fails to oscillate
 *              3. Malfunction of feedback divider so that there is no output or the equivalent dividing
 *              ratio is higher than expected
 */
#define CLKSTS_ALL_PLLSLOW_Pos (7)
#define CLKSTS_ALL_PLLSLOW_Msk (0x1UL << CLKSTS_ALL_PLLSLOW_Pos)

typedef enum
{
    CLKSTS_BIT_PLLSLOW_NOT_OCCUR     = 0,  /*!<    */
    CLKSTS_BIT_PLLSLOW_OCCUR         = 1,  /*!<    */
} CLKSTS_BIT_PLLSLOW;

#define CLKSTS_ALL_PLLSLOW_NOT_OCCUR     ((0x0UL) << CLKSTS_ALL_PLLSLOW_Pos)
#define CLKSTS_ALL_PLLSLOW_OCCUR         ((0x1UL) << CLKSTS_ALL_PLLSLOW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKSTS          CLKDETERR
 *  @access     CLOCK->CLKSTS.bit.CLKDETERR
 *  @brief      Indicate error detected by CLKDET
 */
#define CLKSTS_ALL_CLKDETERR_Pos (8)
#define CLKSTS_ALL_CLKDETERR_Msk (0x1UL << CLKSTS_ALL_CLKDETERR_Pos)

typedef enum
{
    CLKSTS_BIT_CLKDETERR_NOT_OCCUR     = 0,  /*!<    */
    CLKSTS_BIT_CLKDETERR_OCCUR         = 1,  /*!<    */
} CLKSTS_BIT_CLKDETERR;

#define CLKSTS_ALL_CLKDETERR_NOT_OCCUR     ((0x0UL) << CLKSTS_ALL_CLKDETERR_Pos)
#define CLKSTS_ALL_CLKDETERR_OCCUR         ((0x1UL) << CLKSTS_ALL_CLKDETERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           RCO0CTL         EN
 *  @access     CLOCK->RCO0CTL.bit.EN
 *  @brief      RCO0 enable
 */
#define RCO0CTL_ALL_EN_Pos (0)
#define RCO0CTL_ALL_EN_Msk (0x1UL << RCO0CTL_ALL_EN_Pos)

typedef enum
{
    RCO0CTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    RCO0CTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} RCO0CTL_BIT_EN;

#define RCO0CTL_ALL_EN_DISABLE     ((0x0UL) << RCO0CTL_ALL_EN_Pos)
#define RCO0CTL_ALL_EN_ENABLE      ((0x1UL) << RCO0CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           RCO0CTL         LFMODE
 *  @access     CLOCK->RCO0CTL.bit.LFMODE
 *  @brief      RCO0 low frequency mode
 */
#define RCO0CTL_ALL_LFMODE_Pos (1)
#define RCO0CTL_ALL_LFMODE_Msk (0x1UL << RCO0CTL_ALL_LFMODE_Pos)

typedef enum
{
    RCO0CTL_BIT_LFMODE_DISABLE     = 0,  /*!< Normal 32MHz mode (Trimmed)        */
    RCO0CTL_BIT_LFMODE_ENABLE      = 1,  /*!< Low frequency mode (Not trimmed)   */
} RCO0CTL_BIT_LFMODE;

#define RCO0CTL_ALL_LFMODE_DISABLE     ((0x0UL) << RCO0CTL_ALL_LFMODE_Pos)
#define RCO0CTL_ALL_LFMODE_ENABLE      ((0x1UL) << RCO0CTL_ALL_LFMODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           RCO0CTL         FREQTRIM
 *  @access     CLOCK->RCO0CTL.bit.FREQTRIM
 *  @brief      RCO0 frequency trimming
 *              Frequency increases for larger code
 */
#define RCO0CTL_ALL_FREQTRIM_Pos (2)
#define RCO0CTL_ALL_FREQTRIM_Msk (0x1FFUL << RCO0CTL_ALL_FREQTRIM_Pos)

#define RCO0CTL_BIT_FREQTRIM

#define RCO0CTL_ALL_FREQTRIM_(x) ((x) << RCO0CTL_ALL_FREQTRIM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           XOCTL           EN
 *  @access     CLOCK->XOCTL.bit.EN
 *  @brief      Crystal oscillator clock enable
 */
#define XOCTL_ALL_EN_Pos (0)
#define XOCTL_ALL_EN_Msk (0x1UL << XOCTL_ALL_EN_Pos)

typedef enum
{
    XOCTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    XOCTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} XOCTL_BIT_EN;

#define XOCTL_ALL_EN_DISABLE     ((0x0UL) << XOCTL_ALL_EN_Pos)
#define XOCTL_ALL_EN_ENABLE      ((0x1UL) << XOCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           XOCTL           FASTEN
 *  @access     CLOCK->XOCTL.bit.FASTEN
 *  @brief      Enable noise injection for fast startup
 */
#define XOCTL_ALL_FASTEN_Pos (1)
#define XOCTL_ALL_FASTEN_Msk (0x1UL << XOCTL_ALL_FASTEN_Pos)

typedef enum
{
    XOCTL_BIT_FASTEN_DISABLE     = 0,  /*!< Disable   */
    XOCTL_BIT_FASTEN_ENABLE      = 1,  /*!< Enable    */
} XOCTL_BIT_FASTEN;

#define XOCTL_ALL_FASTEN_DISABLE     ((0x0UL) << XOCTL_ALL_FASTEN_Pos)
#define XOCTL_ALL_FASTEN_ENABLE      ((0x1UL) << XOCTL_ALL_FASTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           XOCTL           PRECNT
 *  @access     CLOCK->XOCTL.bit.PRECNT
 *  @brief      Pre-counted target value before XO clock is regarded as ready: Target = 1024 * PRECNT
 */
#define XOCTL_ALL_PRECNT_Pos (4)
#define XOCTL_ALL_PRECNT_Msk (0xFFUL << XOCTL_ALL_PRECNT_Pos)

#define XOCTL_BIT_PRECNT

#define XOCTL_ALL_PRECNT_(x) ((x) << XOCTL_ALL_PRECNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           XOCTL           EXTRFB
 *  @access     CLOCK->XOCTL.bit.EXTRFB
 *  @brief      Use external feedback resistor
 */
#define XOCTL_ALL_EXTRFB_Pos (12)
#define XOCTL_ALL_EXTRFB_Msk (0x1UL << XOCTL_ALL_EXTRFB_Pos)

typedef enum
{
    XOCTL_BIT_EXTRFB_DISABLE     = 0,  /*!< Use internal feedback resistor   */
    XOCTL_BIT_EXTRFB_ENABLE      = 1,  /*!< Use external feedback resistor   */
} XOCTL_BIT_EXTRFB;

#define XOCTL_ALL_EXTRFB_DISABLE     ((0x0UL) << XOCTL_ALL_EXTRFB_Pos)
#define XOCTL_ALL_EXTRFB_ENABLE      ((0x1UL) << XOCTL_ALL_EXTRFB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           XOCTL           FEEDXIO
 *  @access     CLOCK->XOCTL.bit.FEEDXIO
 *  @brief      External clock feed into XIO pin
 */
#define XOCTL_ALL_FEEDXIO_Pos (13)
#define XOCTL_ALL_FEEDXIO_Msk (0x1UL << XOCTL_ALL_FEEDXIO_Pos)

typedef enum
{
    XOCTL_BIT_FEEDXIO_DISABLE     = 0,  /*!< External clock feed into XIN pin   */
    XOCTL_BIT_FEEDXIO_ENABLE      = 1,  /*!< External clock feed into XIO pin   */
} XOCTL_BIT_FEEDXIO;

#define XOCTL_ALL_FEEDXIO_DISABLE     ((0x0UL) << XOCTL_ALL_FEEDXIO_Pos)
#define XOCTL_ALL_FEEDXIO_ENABLE      ((0x1UL) << XOCTL_ALL_FEEDXIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL0         EN
 *  @access     CLOCK->PLLCTL0.bit.EN
 *  @brief      PLL enable
 */
#define PLLCTL0_ALL_EN_Pos (0)
#define PLLCTL0_ALL_EN_Msk (0x1UL << PLLCTL0_ALL_EN_Pos)

typedef enum
{
    PLLCTL0_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    PLLCTL0_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} PLLCTL0_BIT_EN;

#define PLLCTL0_ALL_EN_DISABLE     ((0x0UL) << PLLCTL0_ALL_EN_Pos)
#define PLLCTL0_ALL_EN_ENABLE      ((0x1UL) << PLLCTL0_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL0         OE
 *  @access     CLOCK->PLLCTL0.bit.OE
 *  @brief      PLL digital clock output enable
 */
#define PLLCTL0_ALL_OE_Pos (1)
#define PLLCTL0_ALL_OE_Msk (0x1UL << PLLCTL0_ALL_OE_Pos)

typedef enum
{
    PLLCTL0_BIT_OE_DISABLE     = 0,  /*!< Disable   */
    PLLCTL0_BIT_OE_ENABLE      = 1,  /*!< Enable    */
} PLLCTL0_BIT_OE;

#define PLLCTL0_ALL_OE_DISABLE     ((0x0UL) << PLLCTL0_ALL_OE_Pos)
#define PLLCTL0_ALL_OE_ENABLE      ((0x1UL) << PLLCTL0_ALL_OE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL0         FCALEN
 *  @access     CLOCK->PLLCTL0.bit.FCALEN
 *  @brief      PLL frequency calibration enable
 */
#define PLLCTL0_ALL_FCALEN_Pos (2)
#define PLLCTL0_ALL_FCALEN_Msk (0x1UL << PLLCTL0_ALL_FCALEN_Pos)

typedef enum
{
    PLLCTL0_BIT_FCALEN_DISABLE     = 0,  /*!< Disable   */
    PLLCTL0_BIT_FCALEN_ENABLE      = 1,  /*!< Enable    */
} PLLCTL0_BIT_FCALEN;

#define PLLCTL0_ALL_FCALEN_DISABLE     ((0x0UL) << PLLCTL0_ALL_FCALEN_Pos)
#define PLLCTL0_ALL_FCALEN_ENABLE      ((0x1UL) << PLLCTL0_ALL_FCALEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL0         FCALWIN
 *  @access     CLOCK->PLLCTL0.bit.FCALWIN
 *  @brief      PLL frequency calibration time window
 *              For each calibration cycle, keep it as 1 until VCOFREQVLD=1 and release it as 0
 */
#define PLLCTL0_ALL_FCALWIN_Pos (3)
#define PLLCTL0_ALL_FCALWIN_Msk (0x1UL << PLLCTL0_ALL_FCALWIN_Pos)

typedef enum
{
    PLLCTL0_BIT_FCALWIN_DISABLE     = 0,  /*!< Window is disabled   */
    PLLCTL0_BIT_FCALWIN_ENABLE      = 1,  /*!< Window is enabled    */
} PLLCTL0_BIT_FCALWIN;

#define PLLCTL0_ALL_FCALWIN_DISABLE     ((0x0UL) << PLLCTL0_ALL_FCALWIN_Pos)
#define PLLCTL0_ALL_FCALWIN_ENABLE      ((0x1UL) << PLLCTL0_ALL_FCALWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL0         VCOTRIM
 *  @access     CLOCK->PLLCTL0.bit.VCOTRIM
 *  @brief      VCO frequency trimming
 *              VCO free-run frequency increases with larger code
 */
#define PLLCTL0_ALL_VCOTRIM_Pos (4)
#define PLLCTL0_ALL_VCOTRIM_Msk (0x7UL << PLLCTL0_ALL_VCOTRIM_Pos)

#define PLLCTL0_BIT_VCOTRIM

#define PLLCTL0_ALL_VCOTRIM_(x) ((x) << PLLCTL0_ALL_VCOTRIM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL0         RCLKSELXO
 *  @access     CLOCK->PLLCTL0.bit.RCLKSELXO
 *  @brief      PLL reference clock select
 */
#define PLLCTL0_ALL_RCLKSELXO_Pos (7)
#define PLLCTL0_ALL_RCLKSELXO_Msk (0x1UL << PLLCTL0_ALL_RCLKSELXO_Pos)

typedef enum
{
    PLLCTL0_BIT_RCLKSELXO_RCO0     = 0,  /*!< CLK_RCO0 (RC oscillator 0)    */
    PLLCTL0_BIT_RCLKSELXO_XO       = 1,  /*!< CLK_XO (Crystal oscillator)   */
} PLLCTL0_BIT_RCLKSELXO;

#define PLLCTL0_ALL_RCLKSELXO_RCO0     ((0x0UL) << PLLCTL0_ALL_RCLKSELXO_Pos)
#define PLLCTL0_ALL_RCLKSELXO_XO       ((0x1UL) << PLLCTL0_ALL_RCLKSELXO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL0         OPENLOOP
 *  @access     CLOCK->PLLCTL0.bit.OPENLOOP
 *  @brief      PLL open-loop mode (to trim vco)
 */
#define PLLCTL0_ALL_OPENLOOP_Pos (8)
#define PLLCTL0_ALL_OPENLOOP_Msk (0x1UL << PLLCTL0_ALL_OPENLOOP_Pos)

typedef enum
{
    PLLCTL0_BIT_OPENLOOP_CLOSE_LOOP     = 0,  /*!< Close loop   */
    PLLCTL0_BIT_OPENLOOP_OPEN_LOOP      = 1,  /*!< Open loop    */
} PLLCTL0_BIT_OPENLOOP;

#define PLLCTL0_ALL_OPENLOOP_CLOSE_LOOP     ((0x0UL) << PLLCTL0_ALL_OPENLOOP_Pos)
#define PLLCTL0_ALL_OPENLOOP_OPEN_LOOP      ((0x1UL) << PLLCTL0_ALL_OPENLOOP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL0         ICP
 *  @access     CLOCK->PLLCTL0.bit.ICP
 *  @brief      PLL charge pump current setting
 *              Must be set to 0.96*NFB/(14-VCOTRIM), where NFB is the PLL feedback factor in real
 *              number
 */
#define PLLCTL0_ALL_ICP_Pos (9)
#define PLLCTL0_ALL_ICP_Msk (0x1FUL << PLLCTL0_ALL_ICP_Pos)

#define PLLCTL0_BIT_ICP

#define PLLCTL0_ALL_ICP_(x) ((x) << PLLCTL0_ALL_ICP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL1         NFB
 *  @access     CLOCK->PLLCTL1.bit.NFB
 *  @brief      Feedback dividing ratio (Fvco/Fpfd)
 */
#define PLLCTL1_ALL_NFB_Pos (0)
#define PLLCTL1_ALL_NFB_Msk (0xFFFFFFUL << PLLCTL1_ALL_NFB_Pos)

#define PLLCTL1_BIT_NFB

#define PLLCTL1_ALL_NFB_(x) ((x) << PLLCTL1_ALL_NFB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL1         NIN
 *  @access     CLOCK->PLLCTL1.bit.NIN
 *  @brief      PLL input clock dividing ratio (Fin/Fpfd)
 */
#define PLLCTL1_ALL_NIN_Pos (24)
#define PLLCTL1_ALL_NIN_Msk (0x7UL << PLLCTL1_ALL_NIN_Pos)

typedef enum
{
    PLLCTL1_BIT_NIN_1     = 1,  /*!< Set to 1 if Fin(MHz) is in [4, 8]:   Fin/Fpfd=1     */
    PLLCTL1_BIT_NIN_2     = 2,  /*!< Set to 2 if Fin(MHz) is in (8, 16]:   Fin/Fpfd=2    */
    PLLCTL1_BIT_NIN_3     = 3,  /*!< Set to 3 if Fin(MHz) is in (16, 24]:   Fin/Fpfd=3   */
    PLLCTL1_BIT_NIN_4     = 4,  /*!< Set to 4 if Fin(MHz) is in (24, 32]:   Fin/Fpfd=4   */
    PLLCTL1_BIT_NIN_5     = 5,  /*!< Set to 5 if Fin(MHz) is in (32, 40]:   Fin/Fpfd=5   */
    PLLCTL1_BIT_NIN_6     = 6,  /*!< Set to 6 if Fin(MHz) is in (40, 48]:   Fin/Fpfd=6   */
    PLLCTL1_BIT_NIN_7     = 7,  /*!< Set to 1 if Fin(MHz) is in (48, 56]:   Fin/Fpfd=7   */
} PLLCTL1_BIT_NIN;

#define PLLCTL1_ALL_NIN_1     ((0x1UL) << PLLCTL1_ALL_NIN_Pos)
#define PLLCTL1_ALL_NIN_2     ((0x2UL) << PLLCTL1_ALL_NIN_Pos)
#define PLLCTL1_ALL_NIN_3     ((0x3UL) << PLLCTL1_ALL_NIN_Pos)
#define PLLCTL1_ALL_NIN_4     ((0x4UL) << PLLCTL1_ALL_NIN_Pos)
#define PLLCTL1_ALL_NIN_5     ((0x5UL) << PLLCTL1_ALL_NIN_Pos)
#define PLLCTL1_ALL_NIN_6     ((0x6UL) << PLLCTL1_ALL_NIN_Pos)
#define PLLCTL1_ALL_NIN_7     ((0x7UL) << PLLCTL1_ALL_NIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PLLCTL1         NOUT
 *  @access     CLOCK->PLLCTL1.bit.NOUT
 *  @brief      VCO to digital clock dividing ratio (Fvco/Fout)
 */
#define PLLCTL1_ALL_NOUT_Pos (27)
#define PLLCTL1_ALL_NOUT_Msk (0xFUL << PLLCTL1_ALL_NOUT_Pos)

#define PLLCTL1_BIT_NOUT

#define PLLCTL1_ALL_NOUT_(x) ((x) << PLLCTL1_ALL_NOUT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKDETCTL       RCLKSEL
 *  @access     CLOCK->CLKDETCTL.bit.RCLKSEL
 *  @brief      Reference clock select
 */
#define CLKDETCTL_ALL_RCLKSEL_Pos (0)
#define CLKDETCTL_ALL_RCLKSEL_Msk (0x3UL << CLKDETCTL_ALL_RCLKSEL_Pos)

typedef enum
{
    CLKDETCTL_BIT_RCLKSEL_RCO0     = 0,  /*!< CLK_RCO0   */
    CLKDETCTL_BIT_RCLKSEL_RCO1     = 1,  /*!< CLK_RCO1   */
    CLKDETCTL_BIT_RCLKSEL_XO       = 2,  /*!< CLK_XO     */
    CLKDETCTL_BIT_RCLKSEL_PLL      = 3,  /*!< CLK_PLL    */
} CLKDETCTL_BIT_RCLKSEL;

#define CLKDETCTL_ALL_RCLKSEL_RCO0     ((0x0UL) << CLKDETCTL_ALL_RCLKSEL_Pos)
#define CLKDETCTL_ALL_RCLKSEL_RCO1     ((0x1UL) << CLKDETCTL_ALL_RCLKSEL_Pos)
#define CLKDETCTL_ALL_RCLKSEL_XO       ((0x2UL) << CLKDETCTL_ALL_RCLKSEL_Pos)
#define CLKDETCTL_ALL_RCLKSEL_PLL      ((0x3UL) << CLKDETCTL_ALL_RCLKSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKDETCTL       RCLKDIV
 *  @access     CLOCK->CLKDETCTL.bit.RCLKDIV
 *  @brief      Reference clock dividing ratio
 */
#define CLKDETCTL_ALL_RCLKDIV_Pos (2)
#define CLKDETCTL_ALL_RCLKDIV_Msk (0x7UL << CLKDETCTL_ALL_RCLKDIV_Pos)

typedef enum
{
    CLKDETCTL_BIT_RCLKDIV_1       = 0,  /*!< Divide by 1     */
    CLKDETCTL_BIT_RCLKDIV_2       = 1,  /*!< Divide by 2     */
    CLKDETCTL_BIT_RCLKDIV_4       = 2,  /*!< Divide by 4     */
    CLKDETCTL_BIT_RCLKDIV_8       = 3,  /*!< Divide by 8     */
    CLKDETCTL_BIT_RCLKDIV_16      = 4,  /*!< Divide by 16    */
    CLKDETCTL_BIT_RCLKDIV_32      = 5,  /*!< Divide by 32    */
    CLKDETCTL_BIT_RCLKDIV_64      = 6,  /*!< Divide by 64    */
    CLKDETCTL_BIT_RCLKDIV_128     = 7,  /*!< Divide by 128   */
} CLKDETCTL_BIT_RCLKDIV;

#define CLKDETCTL_ALL_RCLKDIV_1       ((0x0UL) << CLKDETCTL_ALL_RCLKDIV_Pos)
#define CLKDETCTL_ALL_RCLKDIV_2       ((0x1UL) << CLKDETCTL_ALL_RCLKDIV_Pos)
#define CLKDETCTL_ALL_RCLKDIV_4       ((0x2UL) << CLKDETCTL_ALL_RCLKDIV_Pos)
#define CLKDETCTL_ALL_RCLKDIV_8       ((0x3UL) << CLKDETCTL_ALL_RCLKDIV_Pos)
#define CLKDETCTL_ALL_RCLKDIV_16      ((0x4UL) << CLKDETCTL_ALL_RCLKDIV_Pos)
#define CLKDETCTL_ALL_RCLKDIV_32      ((0x5UL) << CLKDETCTL_ALL_RCLKDIV_Pos)
#define CLKDETCTL_ALL_RCLKDIV_64      ((0x6UL) << CLKDETCTL_ALL_RCLKDIV_Pos)
#define CLKDETCTL_ALL_RCLKDIV_128     ((0x7UL) << CLKDETCTL_ALL_RCLKDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKDETCTL       DCLKSEL
 *  @access     CLOCK->CLKDETCTL.bit.DCLKSEL
 *  @brief      Detected clock select
 */
#define CLKDETCTL_ALL_DCLKSEL_Pos (5)
#define CLKDETCTL_ALL_DCLKSEL_Msk (0x3UL << CLKDETCTL_ALL_DCLKSEL_Pos)

typedef enum
{
    CLKDETCTL_BIT_DCLKSEL_RCO0     = 0,  /*!< CLK_RCO0   */
    CLKDETCTL_BIT_DCLKSEL_RCO1     = 1,  /*!< CLK_RCO1   */
    CLKDETCTL_BIT_DCLKSEL_XO       = 2,  /*!< CLK_XO     */
    CLKDETCTL_BIT_DCLKSEL_PLL      = 3,  /*!< CLK_PLL    */
} CLKDETCTL_BIT_DCLKSEL;

#define CLKDETCTL_ALL_DCLKSEL_RCO0     ((0x0UL) << CLKDETCTL_ALL_DCLKSEL_Pos)
#define CLKDETCTL_ALL_DCLKSEL_RCO1     ((0x1UL) << CLKDETCTL_ALL_DCLKSEL_Pos)
#define CLKDETCTL_ALL_DCLKSEL_XO       ((0x2UL) << CLKDETCTL_ALL_DCLKSEL_Pos)
#define CLKDETCTL_ALL_DCLKSEL_PLL      ((0x3UL) << CLKDETCTL_ALL_DCLKSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKDETCTL       DCLKDIV
 *  @access     CLOCK->CLKDETCTL.bit.DCLKDIV
 *  @brief      Detected clock dividing ratio
 */
#define CLKDETCTL_ALL_DCLKDIV_Pos (7)
#define CLKDETCTL_ALL_DCLKDIV_Msk (0x7UL << CLKDETCTL_ALL_DCLKDIV_Pos)

typedef enum
{
    CLKDETCTL_BIT_DCLKDIV_1       = 0,  /*!< Divide by 1     */
    CLKDETCTL_BIT_DCLKDIV_2       = 1,  /*!< Divide by 2     */
    CLKDETCTL_BIT_DCLKDIV_4       = 2,  /*!< Divide by 4     */
    CLKDETCTL_BIT_DCLKDIV_8       = 3,  /*!< Divide by 8     */
    CLKDETCTL_BIT_DCLKDIV_16      = 4,  /*!< Divide by 16    */
    CLKDETCTL_BIT_DCLKDIV_32      = 5,  /*!< Divide by 32    */
    CLKDETCTL_BIT_DCLKDIV_64      = 6,  /*!< Divide by 64    */
    CLKDETCTL_BIT_DCLKDIV_128     = 7,  /*!< Divide by 128   */
} CLKDETCTL_BIT_DCLKDIV;

#define CLKDETCTL_ALL_DCLKDIV_1       ((0x0UL) << CLKDETCTL_ALL_DCLKDIV_Pos)
#define CLKDETCTL_ALL_DCLKDIV_2       ((0x1UL) << CLKDETCTL_ALL_DCLKDIV_Pos)
#define CLKDETCTL_ALL_DCLKDIV_4       ((0x2UL) << CLKDETCTL_ALL_DCLKDIV_Pos)
#define CLKDETCTL_ALL_DCLKDIV_8       ((0x3UL) << CLKDETCTL_ALL_DCLKDIV_Pos)
#define CLKDETCTL_ALL_DCLKDIV_16      ((0x4UL) << CLKDETCTL_ALL_DCLKDIV_Pos)
#define CLKDETCTL_ALL_DCLKDIV_32      ((0x5UL) << CLKDETCTL_ALL_DCLKDIV_Pos)
#define CLKDETCTL_ALL_DCLKDIV_64      ((0x6UL) << CLKDETCTL_ALL_DCLKDIV_Pos)
#define CLKDETCTL_ALL_DCLKDIV_128     ((0x7UL) << CLKDETCTL_ALL_DCLKDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKDETCTL       EN
 *  @access     CLOCK->CLKDETCTL.bit.EN
 *  @brief      Clock detection enable
 *              When disabled, the interrupts and the clock error events will be cleared
 */
#define CLKDETCTL_ALL_EN_Pos (10)
#define CLKDETCTL_ALL_EN_Msk (0x1UL << CLKDETCTL_ALL_EN_Pos)

typedef enum
{
    CLKDETCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock detection   */
    CLKDETCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock detection    */
} CLKDETCTL_BIT_EN;

#define CLKDETCTL_ALL_EN_DISABLE     ((0x0UL) << CLKDETCTL_ALL_EN_Pos)
#define CLKDETCTL_ALL_EN_ENABLE      ((0x1UL) << CLKDETCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKDETCTH       LO
 *  @access     CLOCK->CLKDETCTH.bit.LO
 *  @brief      Lower counter threshold for clock detect
 *              If the final counter value < LO, a trip-zone event will be generated for PWM
 */
#define CLKDETCTH_ALL_LO_Pos (0)
#define CLKDETCTH_ALL_LO_Msk (0xFFFFUL << CLKDETCTH_ALL_LO_Pos)

#define CLKDETCTH_BIT_LO

#define CLKDETCTH_ALL_LO_(x) ((x) << CLKDETCTH_ALL_LO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKDETCTH       HI
 *  @access     CLOCK->CLKDETCTH.bit.HI
 *  @brief      Upper counter threshold for clock detect
 *              If the final counter value > HI, a trip-zone event will be generated for PWM
 */
#define CLKDETCTH_ALL_HI_Pos (16)
#define CLKDETCTH_ALL_HI_Msk (0xFFFFUL << CLKDETCTH_ALL_HI_Pos)

#define CLKDETCTH_BIT_HI

#define CLKDETCTH_ALL_HI_(x) ((x) << CLKDETCTH_ALL_HI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKDETCNT       VAL
 *  @access     CLOCK->CLKDETCNT.bit.VAL
 *  @brief      Final counter value of the clock detect
 */
#define CLKDETCNT_ALL_VAL_Pos (0)
#define CLKDETCNT_ALL_VAL_Msk (0xFFFFUL << CLKDETCNT_ALL_VAL_Pos)

#define CLKDETCNT_BIT_VAL

#define CLKDETCNT_ALL_VAL_(x) ((x) << CLKDETCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKIF           PLLUNLOCK
 *  @access     CLOCK->CLKIF.bit.PLLUNLOCK
 *  @brief      Latched PLL unlock flag
 *              Detailed reason can be referred to CLKSTS[PLLFAST] and CLKSTS[PLLSLOW]
 */
#define CLKIF_ALL_PLLUNLOCK_Pos (0)
#define CLKIF_ALL_PLLUNLOCK_Msk (0x1UL << CLKIF_ALL_PLLUNLOCK_Pos)

typedef enum
{
    CLKIF_BIT_PLLUNLOCK_NOT_OCCUR     = 0,  /*!< PLL is locked     */
    CLKIF_BIT_PLLUNLOCK_OCCUR         = 1,  /*!< PLL is unlocked   */
} CLKIF_BIT_PLLUNLOCK;

#define CLKIF_ALL_PLLUNLOCK_NOT_OCCUR     ((0x0UL) << CLKIF_ALL_PLLUNLOCK_Pos)
#define CLKIF_ALL_PLLUNLOCK_OCCUR         ((0x1UL) << CLKIF_ALL_PLLUNLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKIF           CLKDETERR
 *  @access     CLOCK->CLKIF.bit.CLKDETERR
 *  @brief      Latched CLKDET error flag, namely the CLKDETCNT is out of the range defined by CLKDETCTH
 */
#define CLKIF_ALL_CLKDETERR_Pos (1)
#define CLKIF_ALL_CLKDETERR_Msk (0x1UL << CLKIF_ALL_CLKDETERR_Pos)

typedef enum
{
    CLKIF_BIT_CLKDETERR_NOT_OCCUR     = 0,  /*!< CLKDETCNT is within the expected range   */
    CLKIF_BIT_CLKDETERR_OCCUR         = 1,  /*!< CLKDETCNT is out of the expected range   */
} CLKIF_BIT_CLKDETERR;

#define CLKIF_ALL_CLKDETERR_NOT_OCCUR     ((0x0UL) << CLKIF_ALL_CLKDETERR_Pos)
#define CLKIF_ALL_CLKDETERR_OCCUR         ((0x1UL) << CLKIF_ALL_CLKDETERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKIF           CLKINT
 *  @access     CLOCK->CLKIF.bit.CLKINT
 *  @brief      Latched clock interrupt
 */
#define CLKIF_ALL_CLKINT_Pos (2)
#define CLKIF_ALL_CLKINT_Msk (0x1UL << CLKIF_ALL_CLKINT_Pos)

typedef enum
{
    CLKIF_BIT_CLKINT_NOT_OCCUR     = 0,  /*!< No clock interrupt occurred   */
    CLKIF_BIT_CLKINT_OCCUR         = 1,  /*!< Clock interrupt occurred      */
} CLKIF_BIT_CLKINT;

#define CLKIF_ALL_CLKINT_NOT_OCCUR     ((0x0UL) << CLKIF_ALL_CLKINT_Pos)
#define CLKIF_ALL_CLKINT_OCCUR         ((0x1UL) << CLKIF_ALL_CLKINT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKIC           PLLUNLOCK
 *  @access     CLOCK->CLKIC.bit.PLLUNLOCK
 *  @brief      PLL unlock interrupt flag clear
 */
#define CLKIC_ALL_PLLUNLOCK_Pos (0)
#define CLKIC_ALL_PLLUNLOCK_Msk (0x1UL << CLKIC_ALL_PLLUNLOCK_Pos)

typedef enum
{
    CLKIC_BIT_PLLUNLOCK_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0                         */
    CLKIC_BIT_PLLUNLOCK_CLEAR         = 1,  /*!< Write a 1 clear the CLKIF.PLLUNLOCK, CLKSTS.PLLFAST, CLKSTS.PLLSLOW.  
                                                 This bit is self-cleared to 0.                                         */
} CLKIC_BIT_PLLUNLOCK;

#define CLKIC_ALL_PLLUNLOCK_NO_EFFECT     ((0x0UL) << CLKIC_ALL_PLLUNLOCK_Pos)
#define CLKIC_ALL_PLLUNLOCK_CLEAR         ((0x1UL) << CLKIC_ALL_PLLUNLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKIC           CLKDETERR
 *  @access     CLOCK->CLKIC.bit.CLKDETERR
 *  @brief      CLKDET error interrupt flag clear
 */
#define CLKIC_ALL_CLKDETERR_Pos (1)
#define CLKIC_ALL_CLKDETERR_Msk (0x1UL << CLKIC_ALL_CLKDETERR_Pos)

typedef enum
{
    CLKIC_BIT_CLKDETERR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0   */
    CLKIC_BIT_CLKDETERR_CLEAR         = 1,  /*!< Write a 1 clear the CLKIF.CLKDETERR.            
                                                 This bit is self-cleared to 0.                   */
} CLKIC_BIT_CLKDETERR;

#define CLKIC_ALL_CLKDETERR_NO_EFFECT     ((0x0UL) << CLKIC_ALL_CLKDETERR_Pos)
#define CLKIC_ALL_CLKDETERR_CLEAR         ((0x1UL) << CLKIC_ALL_CLKDETERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKIC           CLKINT
 *  @access     CLOCK->CLKIC.bit.CLKINT
 *  @brief      Clock interrupt clear
 *              A new clock interrupt will be immediately issued if CLKIF is not zero after the clear
 */
#define CLKIC_ALL_CLKINT_Pos (2)
#define CLKIC_ALL_CLKINT_Msk (0x1UL << CLKIC_ALL_CLKINT_Pos)

typedef enum
{
    CLKIC_BIT_CLKINT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always read back 0   */
    CLKIC_BIT_CLKINT_CLEAR         = 1,  /*!< Write a 1 clear the CLKIF.CLKINT.               
                                              This bit is self-cleared to 0.                   */
} CLKIC_BIT_CLKINT;

#define CLKIC_ALL_CLKINT_NO_EFFECT     ((0x0UL) << CLKIC_ALL_CLKINT_Pos)
#define CLKIC_ALL_CLKINT_CLEAR         ((0x1UL) << CLKIC_ALL_CLKINT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKIE           PLLUNLOCK
 *  @access     CLOCK->CLKIE.bit.PLLUNLOCK
 *  @brief      PLL unlock interrupt enable
 */
#define CLKIE_ALL_PLLUNLOCK_Pos (0)
#define CLKIE_ALL_PLLUNLOCK_Msk (0x1UL << CLKIE_ALL_PLLUNLOCK_Pos)

typedef enum
{
    CLKIE_BIT_PLLUNLOCK_DISABLE     = 0,  /*!< PLL unlock event will not trigger clock interrupt   */
    CLKIE_BIT_PLLUNLOCK_ENABLE      = 1,  /*!< PLL unlock event will trigger clock interrupt       */
} CLKIE_BIT_PLLUNLOCK;

#define CLKIE_ALL_PLLUNLOCK_DISABLE     ((0x0UL) << CLKIE_ALL_PLLUNLOCK_Pos)
#define CLKIE_ALL_PLLUNLOCK_ENABLE      ((0x1UL) << CLKIE_ALL_PLLUNLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKIE           CLKDETERR
 *  @access     CLOCK->CLKIE.bit.CLKDETERR
 *  @brief      CLKDET error interrupt enable
 */
#define CLKIE_ALL_CLKDETERR_Pos (1)
#define CLKIE_ALL_CLKDETERR_Msk (0x1UL << CLKIE_ALL_CLKDETERR_Pos)

typedef enum
{
    CLKIE_BIT_CLKDETERR_DISABLE     = 0,  /*!< CLKDET error will not trigger clock interrupt   */
    CLKIE_BIT_CLKDETERR_ENABLE      = 1,  /*!< CLKDET error will trigger clock interrupt       */
} CLKIE_BIT_CLKDETERR;

#define CLKIE_ALL_CLKDETERR_DISABLE     ((0x0UL) << CLKIE_ALL_CLKDETERR_Pos)
#define CLKIE_ALL_CLKDETERR_ENABLE      ((0x1UL) << CLKIE_ALL_CLKDETERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKTZE          PLLUNLOCK
 *  @access     CLOCK->CLKTZE.bit.PLLUNLOCK
 *  @brief      PLL unlock trip-zone event enable
 */
#define CLKTZE_ALL_PLLUNLOCK_Pos (0)
#define CLKTZE_ALL_PLLUNLOCK_Msk (0x1UL << CLKTZE_ALL_PLLUNLOCK_Pos)

typedef enum
{
    CLKTZE_BIT_PLLUNLOCK_DISABLE     = 0,  /*!< PLL unlock will not trigger PWM trip-zone   */
    CLKTZE_BIT_PLLUNLOCK_ENABLE      = 1,  /*!< PLL unlock will trigger PWM trip-zone       */
} CLKTZE_BIT_PLLUNLOCK;

#define CLKTZE_ALL_PLLUNLOCK_DISABLE     ((0x0UL) << CLKTZE_ALL_PLLUNLOCK_Pos)
#define CLKTZE_ALL_PLLUNLOCK_ENABLE      ((0x1UL) << CLKTZE_ALL_PLLUNLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKTZE          CLKDETERR
 *  @access     CLOCK->CLKTZE.bit.CLKDETERR
 *  @brief      CLKDET error trip-zone event enable
 */
#define CLKTZE_ALL_CLKDETERR_Pos (1)
#define CLKTZE_ALL_CLKDETERR_Msk (0x1UL << CLKTZE_ALL_CLKDETERR_Pos)

typedef enum
{
    CLKTZE_BIT_CLKDETERR_DISABLE     = 0,  /*!< CLKDET error will not trigger PWM trip-zone   */
    CLKTZE_BIT_CLKDETERR_ENABLE      = 1,  /*!< CLKDET error will trigger PWM trip-zone       */
} CLKTZE_BIT_CLKDETERR;

#define CLKTZE_ALL_CLKDETERR_DISABLE     ((0x0UL) << CLKTZE_ALL_CLKDETERR_Pos)
#define CLKTZE_ALL_CLKDETERR_ENABLE      ((0x1UL) << CLKTZE_ALL_CLKDETERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           SYSCLK0CTL      SRC
 *  @access     CLOCK->SYSCLK0CTL.bit.SRC
 *  @brief      Clock source select
 */
#define SYSCLK0CTL_ALL_SRC_Pos (9)
#define SYSCLK0CTL_ALL_SRC_Msk (0x3UL << SYSCLK0CTL_ALL_SRC_Pos)

typedef enum
{
    SYSCLK0CTL_BIT_SRC_RCO0     = 0,  /*!< RCO0   */
    SYSCLK0CTL_BIT_SRC_RCO1     = 1,  /*!< RCO1   */
    SYSCLK0CTL_BIT_SRC_XO       = 2,  /*!< XO     */
    SYSCLK0CTL_BIT_SRC_PLL      = 3,  /*!< PLL    */
} SYSCLK0CTL_BIT_SRC;

#define SYSCLK0CTL_ALL_SRC_RCO0     ((0x0UL) << SYSCLK0CTL_ALL_SRC_Pos)
#define SYSCLK0CTL_ALL_SRC_RCO1     ((0x1UL) << SYSCLK0CTL_ALL_SRC_Pos)
#define SYSCLK0CTL_ALL_SRC_XO       ((0x2UL) << SYSCLK0CTL_ALL_SRC_Pos)
#define SYSCLK0CTL_ALL_SRC_PLL      ((0x3UL) << SYSCLK0CTL_ALL_SRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           HCLKCTL         DIV
 *  @access     CLOCK->HCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio from system clock
 */
#define HCLKCTL_ALL_DIV_Pos (0)
#define HCLKCTL_ALL_DIV_Msk (0xFFUL << HCLKCTL_ALL_DIV_Pos)

#define HCLKCTL_BIT_DIV

#define HCLKCTL_ALL_DIV_(x) ((x) << HCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           ADCCLKCTL       DIV
 *  @access     CLOCK->ADCCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define ADCCLKCTL_ALL_DIV_Pos (0)
#define ADCCLKCTL_ALL_DIV_Msk (0xFFUL << ADCCLKCTL_ALL_DIV_Pos)

#define ADCCLKCTL_BIT_DIV

#define ADCCLKCTL_ALL_DIV_(x) ((x) << ADCCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           ADCCLKCTL       EN
 *  @access     CLOCK->ADCCLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define ADCCLKCTL_ALL_EN_Pos (8)
#define ADCCLKCTL_ALL_EN_Msk (0x1UL << ADCCLKCTL_ALL_EN_Pos)

typedef enum
{
    ADCCLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    ADCCLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} ADCCLKCTL_BIT_EN;

#define ADCCLKCTL_ALL_EN_DISABLE     ((0x0UL) << ADCCLKCTL_ALL_EN_Pos)
#define ADCCLKCTL_ALL_EN_ENABLE      ((0x1UL) << ADCCLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PWMCLKCTL       DIV
 *  @access     CLOCK->PWMCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define PWMCLKCTL_ALL_DIV_Pos (0)
#define PWMCLKCTL_ALL_DIV_Msk (0xFFUL << PWMCLKCTL_ALL_DIV_Pos)

#define PWMCLKCTL_BIT_DIV

#define PWMCLKCTL_ALL_DIV_(x) ((x) << PWMCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PWMCLKCTL       EN
 *  @access     CLOCK->PWMCLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define PWMCLKCTL_ALL_EN_Pos (8)
#define PWMCLKCTL_ALL_EN_Msk (0x1UL << PWMCLKCTL_ALL_EN_Pos)

typedef enum
{
    PWMCLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    PWMCLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} PWMCLKCTL_BIT_EN;

#define PWMCLKCTL_ALL_EN_DISABLE     ((0x0UL) << PWMCLKCTL_ALL_EN_Pos)
#define PWMCLKCTL_ALL_EN_ENABLE      ((0x1UL) << PWMCLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           ECAPCLKCTL      DIV
 *  @access     CLOCK->ECAPCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define ECAPCLKCTL_ALL_DIV_Pos (0)
#define ECAPCLKCTL_ALL_DIV_Msk (0xFFUL << ECAPCLKCTL_ALL_DIV_Pos)

#define ECAPCLKCTL_BIT_DIV

#define ECAPCLKCTL_ALL_DIV_(x) ((x) << ECAPCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           ECAPCLKCTL      EN
 *  @access     CLOCK->ECAPCLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define ECAPCLKCTL_ALL_EN_Pos (8)
#define ECAPCLKCTL_ALL_EN_Msk (0x1UL << ECAPCLKCTL_ALL_EN_Pos)

typedef enum
{
    ECAPCLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    ECAPCLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} ECAPCLKCTL_BIT_EN;

#define ECAPCLKCTL_ALL_EN_DISABLE     ((0x0UL) << ECAPCLKCTL_ALL_EN_Pos)
#define ECAPCLKCTL_ALL_EN_ENABLE      ((0x1UL) << ECAPCLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           TMR0CLKCTL      DIV
 *  @access     CLOCK->TMR0CLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define TMR0CLKCTL_ALL_DIV_Pos (0)
#define TMR0CLKCTL_ALL_DIV_Msk (0xFFUL << TMR0CLKCTL_ALL_DIV_Pos)

#define TMR0CLKCTL_BIT_DIV

#define TMR0CLKCTL_ALL_DIV_(x) ((x) << TMR0CLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           TMR0CLKCTL      EN
 *  @access     CLOCK->TMR0CLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define TMR0CLKCTL_ALL_EN_Pos (8)
#define TMR0CLKCTL_ALL_EN_Msk (0x1UL << TMR0CLKCTL_ALL_EN_Pos)

typedef enum
{
    TMR0CLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    TMR0CLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} TMR0CLKCTL_BIT_EN;

#define TMR0CLKCTL_ALL_EN_DISABLE     ((0x0UL) << TMR0CLKCTL_ALL_EN_Pos)
#define TMR0CLKCTL_ALL_EN_ENABLE      ((0x1UL) << TMR0CLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           TMR1CLKCTL      DIV
 *  @access     CLOCK->TMR1CLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define TMR1CLKCTL_ALL_DIV_Pos (0)
#define TMR1CLKCTL_ALL_DIV_Msk (0xFFUL << TMR1CLKCTL_ALL_DIV_Pos)

#define TMR1CLKCTL_BIT_DIV

#define TMR1CLKCTL_ALL_DIV_(x) ((x) << TMR1CLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           TMR1CLKCTL      EN
 *  @access     CLOCK->TMR1CLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define TMR1CLKCTL_ALL_EN_Pos (8)
#define TMR1CLKCTL_ALL_EN_Msk (0x1UL << TMR1CLKCTL_ALL_EN_Pos)

typedef enum
{
    TMR1CLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    TMR1CLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} TMR1CLKCTL_BIT_EN;

#define TMR1CLKCTL_ALL_EN_DISABLE     ((0x0UL) << TMR1CLKCTL_ALL_EN_Pos)
#define TMR1CLKCTL_ALL_EN_ENABLE      ((0x1UL) << TMR1CLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           TMR2CLKCTL      DIV
 *  @access     CLOCK->TMR2CLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define TMR2CLKCTL_ALL_DIV_Pos (0)
#define TMR2CLKCTL_ALL_DIV_Msk (0xFFUL << TMR2CLKCTL_ALL_DIV_Pos)

#define TMR2CLKCTL_BIT_DIV

#define TMR2CLKCTL_ALL_DIV_(x) ((x) << TMR2CLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           TMR2CLKCTL      EN
 *  @access     CLOCK->TMR2CLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define TMR2CLKCTL_ALL_EN_Pos (8)
#define TMR2CLKCTL_ALL_EN_Msk (0x1UL << TMR2CLKCTL_ALL_EN_Pos)

typedef enum
{
    TMR2CLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    TMR2CLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} TMR2CLKCTL_BIT_EN;

#define TMR2CLKCTL_ALL_EN_DISABLE     ((0x0UL) << TMR2CLKCTL_ALL_EN_Pos)
#define TMR2CLKCTL_ALL_EN_ENABLE      ((0x1UL) << TMR2CLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           SIOCLKCTL       DIV
 *  @access     CLOCK->SIOCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define SIOCLKCTL_ALL_DIV_Pos (0)
#define SIOCLKCTL_ALL_DIV_Msk (0xFFUL << SIOCLKCTL_ALL_DIV_Pos)

#define SIOCLKCTL_BIT_DIV

#define SIOCLKCTL_ALL_DIV_(x) ((x) << SIOCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           SIOCLKCTL       EN
 *  @access     CLOCK->SIOCLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define SIOCLKCTL_ALL_EN_Pos (8)
#define SIOCLKCTL_ALL_EN_Msk (0x1UL << SIOCLKCTL_ALL_EN_Pos)

typedef enum
{
    SIOCLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    SIOCLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} SIOCLKCTL_BIT_EN;

#define SIOCLKCTL_ALL_EN_DISABLE     ((0x0UL) << SIOCLKCTL_ALL_EN_Pos)
#define SIOCLKCTL_ALL_EN_ENABLE      ((0x1UL) << SIOCLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           SYSCLK1CTL      SRC
 *  @access     CLOCK->SYSCLK1CTL.bit.SRC
 *  @brief      Clock source select
 */
#define SYSCLK1CTL_ALL_SRC_Pos (9)
#define SYSCLK1CTL_ALL_SRC_Msk (0x3UL << SYSCLK1CTL_ALL_SRC_Pos)

typedef enum
{
    SYSCLK1CTL_BIT_SRC_RCO0     = 0,  /*!< RCO0   */
    SYSCLK1CTL_BIT_SRC_RCO1     = 1,  /*!< RCO1   */
    SYSCLK1CTL_BIT_SRC_XO       = 2,  /*!< XO     */
    SYSCLK1CTL_BIT_SRC_PLL      = 3,  /*!< PLL    */
} SYSCLK1CTL_BIT_SRC;

#define SYSCLK1CTL_ALL_SRC_RCO0     ((0x0UL) << SYSCLK1CTL_ALL_SRC_Pos)
#define SYSCLK1CTL_ALL_SRC_RCO1     ((0x1UL) << SYSCLK1CTL_ALL_SRC_Pos)
#define SYSCLK1CTL_ALL_SRC_XO       ((0x2UL) << SYSCLK1CTL_ALL_SRC_Pos)
#define SYSCLK1CTL_ALL_SRC_PLL      ((0x3UL) << SYSCLK1CTL_ALL_SRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           PCLKCTL         DIV
 *  @access     CLOCK->PCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio from system clock
 */
#define PCLKCTL_ALL_DIV_Pos (0)
#define PCLKCTL_ALL_DIV_Msk (0xFFUL << PCLKCTL_ALL_DIV_Pos)

#define PCLKCTL_BIT_DIV

#define PCLKCTL_ALL_DIV_(x) ((x) << PCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           DGCLKCTL        DIV
 *  @access     CLOCK->DGCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define DGCLKCTL_ALL_DIV_Pos (0)
#define DGCLKCTL_ALL_DIV_Msk (0xFFUL << DGCLKCTL_ALL_DIV_Pos)

#define DGCLKCTL_BIT_DIV

#define DGCLKCTL_ALL_DIV_(x) ((x) << DGCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           DGCLKCTL        PDIV
 *  @access     CLOCK->DGCLKCTL.bit.PDIV
 *  @brief      Clock binary pre-dividing ratio from system clock
 */
#define DGCLKCTL_ALL_PDIV_Pos (8)
#define DGCLKCTL_ALL_PDIV_Msk (0x7UL << DGCLKCTL_ALL_PDIV_Pos)

typedef enum
{
    DGCLKCTL_BIT_PDIV_1       = 0,  /*!< Divide by 1     */
    DGCLKCTL_BIT_PDIV_2       = 1,  /*!< Divide by 2     */
    DGCLKCTL_BIT_PDIV_4       = 2,  /*!< Divide by 4     */
    DGCLKCTL_BIT_PDIV_8       = 3,  /*!< Divide by 8     */
    DGCLKCTL_BIT_PDIV_16      = 4,  /*!< Divide by 16    */
    DGCLKCTL_BIT_PDIV_32      = 5,  /*!< Divide by 32    */
    DGCLKCTL_BIT_PDIV_64      = 6,  /*!< Divide by 64    */
    DGCLKCTL_BIT_PDIV_128     = 7,  /*!< Divide by 128   */
} DGCLKCTL_BIT_PDIV;

#define DGCLKCTL_ALL_PDIV_1       ((0x0UL) << DGCLKCTL_ALL_PDIV_Pos)
#define DGCLKCTL_ALL_PDIV_2       ((0x1UL) << DGCLKCTL_ALL_PDIV_Pos)
#define DGCLKCTL_ALL_PDIV_4       ((0x2UL) << DGCLKCTL_ALL_PDIV_Pos)
#define DGCLKCTL_ALL_PDIV_8       ((0x3UL) << DGCLKCTL_ALL_PDIV_Pos)
#define DGCLKCTL_ALL_PDIV_16      ((0x4UL) << DGCLKCTL_ALL_PDIV_Pos)
#define DGCLKCTL_ALL_PDIV_32      ((0x5UL) << DGCLKCTL_ALL_PDIV_Pos)
#define DGCLKCTL_ALL_PDIV_64      ((0x6UL) << DGCLKCTL_ALL_PDIV_Pos)
#define DGCLKCTL_ALL_PDIV_128     ((0x7UL) << DGCLKCTL_ALL_PDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           UARTCLKCTL      DIV
 *  @access     CLOCK->UARTCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define UARTCLKCTL_ALL_DIV_Pos (0)
#define UARTCLKCTL_ALL_DIV_Msk (0xFFUL << UARTCLKCTL_ALL_DIV_Pos)

#define UARTCLKCTL_BIT_DIV

#define UARTCLKCTL_ALL_DIV_(x) ((x) << UARTCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           UARTCLKCTL      EN
 *  @access     CLOCK->UARTCLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define UARTCLKCTL_ALL_EN_Pos (8)
#define UARTCLKCTL_ALL_EN_Msk (0x1UL << UARTCLKCTL_ALL_EN_Pos)

typedef enum
{
    UARTCLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    UARTCLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} UARTCLKCTL_BIT_EN;

#define UARTCLKCTL_ALL_EN_DISABLE     ((0x0UL) << UARTCLKCTL_ALL_EN_Pos)
#define UARTCLKCTL_ALL_EN_ENABLE      ((0x1UL) << UARTCLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           SSPCLKCTL       DIV
 *  @access     CLOCK->SSPCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define SSPCLKCTL_ALL_DIV_Pos (0)
#define SSPCLKCTL_ALL_DIV_Msk (0xFFFFUL << SSPCLKCTL_ALL_DIV_Pos)

#define SSPCLKCTL_BIT_DIV

#define SSPCLKCTL_ALL_DIV_(x) ((x) << SSPCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           SSPCLKCTL       EN
 *  @access     CLOCK->SSPCLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define SSPCLKCTL_ALL_EN_Pos (16)
#define SSPCLKCTL_ALL_EN_Msk (0x1UL << SSPCLKCTL_ALL_EN_Pos)

typedef enum
{
    SSPCLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    SSPCLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} SSPCLKCTL_BIT_EN;

#define SSPCLKCTL_ALL_EN_DISABLE     ((0x0UL) << SSPCLKCTL_ALL_EN_Pos)
#define SSPCLKCTL_ALL_EN_ENABLE      ((0x1UL) << SSPCLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           I2CCLKCTL       DIV
 *  @access     CLOCK->I2CCLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define I2CCLKCTL_ALL_DIV_Pos (0)
#define I2CCLKCTL_ALL_DIV_Msk (0xFFUL << I2CCLKCTL_ALL_DIV_Pos)

#define I2CCLKCTL_BIT_DIV

#define I2CCLKCTL_ALL_DIV_(x) ((x) << I2CCLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           I2CCLKCTL       EN
 *  @access     CLOCK->I2CCLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define I2CCLKCTL_ALL_EN_Pos (8)
#define I2CCLKCTL_ALL_EN_Msk (0x1UL << I2CCLKCTL_ALL_EN_Pos)

typedef enum
{
    I2CCLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    I2CCLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} I2CCLKCTL_BIT_EN;

#define I2CCLKCTL_ALL_EN_DISABLE     ((0x0UL) << I2CCLKCTL_ALL_EN_Pos)
#define I2CCLKCTL_ALL_EN_ENABLE      ((0x1UL) << I2CCLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           WDT0CLKCTL      DIV
 *  @access     CLOCK->WDT0CLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define WDT0CLKCTL_ALL_DIV_Pos (0)
#define WDT0CLKCTL_ALL_DIV_Msk (0xFFUL << WDT0CLKCTL_ALL_DIV_Pos)

#define WDT0CLKCTL_BIT_DIV

#define WDT0CLKCTL_ALL_DIV_(x) ((x) << WDT0CLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           WDT0CLKCTL      EN
 *  @access     CLOCK->WDT0CLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define WDT0CLKCTL_ALL_EN_Pos (8)
#define WDT0CLKCTL_ALL_EN_Msk (0x1UL << WDT0CLKCTL_ALL_EN_Pos)

typedef enum
{
    WDT0CLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    WDT0CLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} WDT0CLKCTL_BIT_EN;

#define WDT0CLKCTL_ALL_EN_DISABLE     ((0x0UL) << WDT0CLKCTL_ALL_EN_Pos)
#define WDT0CLKCTL_ALL_EN_ENABLE      ((0x1UL) << WDT0CLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           WDT0CLKCTL      SRC
 *  @access     CLOCK->WDT0CLKCTL.bit.SRC
 *  @brief      Clock source select
 */
#define WDT0CLKCTL_ALL_SRC_Pos (9)
#define WDT0CLKCTL_ALL_SRC_Msk (0x3UL << WDT0CLKCTL_ALL_SRC_Pos)

typedef enum
{
    WDT0CLKCTL_BIT_SRC_RCO0     = 0,  /*!< RCO0   */
    WDT0CLKCTL_BIT_SRC_RCO1     = 1,  /*!< RCO1   */
    WDT0CLKCTL_BIT_SRC_XO       = 2,  /*!< XO     */
    WDT0CLKCTL_BIT_SRC_PLL      = 3,  /*!< PLL    */
} WDT0CLKCTL_BIT_SRC;

#define WDT0CLKCTL_ALL_SRC_RCO0     ((0x0UL) << WDT0CLKCTL_ALL_SRC_Pos)
#define WDT0CLKCTL_ALL_SRC_RCO1     ((0x1UL) << WDT0CLKCTL_ALL_SRC_Pos)
#define WDT0CLKCTL_ALL_SRC_XO       ((0x2UL) << WDT0CLKCTL_ALL_SRC_Pos)
#define WDT0CLKCTL_ALL_SRC_PLL      ((0x3UL) << WDT0CLKCTL_ALL_SRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           WDT1CLKCTL      DIV
 *  @access     CLOCK->WDT1CLKCTL.bit.DIV
 *  @brief      Clock dividing ratio
 */
#define WDT1CLKCTL_ALL_DIV_Pos (0)
#define WDT1CLKCTL_ALL_DIV_Msk (0xFFUL << WDT1CLKCTL_ALL_DIV_Pos)

#define WDT1CLKCTL_BIT_DIV

#define WDT1CLKCTL_ALL_DIV_(x) ((x) << WDT1CLKCTL_ALL_DIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           WDT1CLKCTL      EN
 *  @access     CLOCK->WDT1CLKCTL.bit.EN
 *  @brief      Clock output enable
 */
#define WDT1CLKCTL_ALL_EN_Pos (8)
#define WDT1CLKCTL_ALL_EN_Msk (0x1UL << WDT1CLKCTL_ALL_EN_Pos)

typedef enum
{
    WDT1CLKCTL_BIT_EN_DISABLE     = 0,  /*!< Disable clock output   */
    WDT1CLKCTL_BIT_EN_ENABLE      = 1,  /*!< Enable clock output    */
} WDT1CLKCTL_BIT_EN;

#define WDT1CLKCTL_ALL_EN_DISABLE     ((0x0UL) << WDT1CLKCTL_ALL_EN_Pos)
#define WDT1CLKCTL_ALL_EN_ENABLE      ((0x1UL) << WDT1CLKCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           WDT1CLKCTL      SRC
 *  @access     CLOCK->WDT1CLKCTL.bit.SRC
 *  @brief      Clock source select
 */
#define WDT1CLKCTL_ALL_SRC_Pos (9)
#define WDT1CLKCTL_ALL_SRC_Msk (0x3UL << WDT1CLKCTL_ALL_SRC_Pos)

typedef enum
{
    WDT1CLKCTL_BIT_SRC_RCO0     = 0,  /*!< RCO0   */
    WDT1CLKCTL_BIT_SRC_RCO1     = 1,  /*!< RCO1   */
    WDT1CLKCTL_BIT_SRC_XO       = 2,  /*!< XO     */
    WDT1CLKCTL_BIT_SRC_PLL      = 3,  /*!< PLL    */
} WDT1CLKCTL_BIT_SRC;

#define WDT1CLKCTL_ALL_SRC_RCO0     ((0x0UL) << WDT1CLKCTL_ALL_SRC_Pos)
#define WDT1CLKCTL_ALL_SRC_RCO1     ((0x1UL) << WDT1CLKCTL_ALL_SRC_Pos)
#define WDT1CLKCTL_ALL_SRC_XO       ((0x2UL) << WDT1CLKCTL_ALL_SRC_Pos)
#define WDT1CLKCTL_ALL_SRC_PLL      ((0x3UL) << WDT1CLKCTL_ALL_SRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CLOCK           CLKREGKEY       KEY
 *  @access     CLOCK->CLKREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected clock registers
 */
#define CLKREGKEY_ALL_KEY_Pos (0)
#define CLKREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << CLKREGKEY_ALL_KEY_Pos)

#define CLKREGKEY_BIT_KEY

#define CLKREGKEY_ALL_KEY_(x) ((x) << CLKREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     PINMUX
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO0           MUXSEL
 *  @access     PINMUX->GPIO0.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO0_ALL_MUXSEL_Pos (0)
#define GPIO0_ALL_MUXSEL_Msk (0x7UL << GPIO0_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO0_BIT_MUXSEL_GPIO0      = 0,  /*!< GPIO0    */
    GPIO0_BIT_MUXSEL_ADC0       = 1,  /*!< ADC0     */
    GPIO0_BIT_MUXSEL_COMP0H     = 6,  /*!< COMP0H   */
    GPIO0_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO0_BIT_MUXSEL;

#define GPIO0_ALL_MUXSEL_GPIO0      ((0x0UL) << GPIO0_ALL_MUXSEL_Pos)
#define GPIO0_ALL_MUXSEL_ADC0       ((0x1UL) << GPIO0_ALL_MUXSEL_Pos)
#define GPIO0_ALL_MUXSEL_COMP0H     ((0x6UL) << GPIO0_ALL_MUXSEL_Pos)
#define GPIO0_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO0_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO0           IE
 *  @access     PINMUX->GPIO0.bit.IE
 *  @brief      Input enable
 */
#define GPIO0_ALL_IE_Pos (3)
#define GPIO0_ALL_IE_Msk (0x1UL << GPIO0_ALL_IE_Pos)

typedef enum
{
    GPIO0_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO0_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO0_BIT_IE;

#define GPIO0_ALL_IE_DISABLE     ((0x0UL) << GPIO0_ALL_IE_Pos)
#define GPIO0_ALL_IE_ENABLE      ((0x1UL) << GPIO0_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO0           SMT
 *  @access     PINMUX->GPIO0.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO0_ALL_SMT_Pos (4)
#define GPIO0_ALL_SMT_Msk (0x1UL << GPIO0_ALL_SMT_Pos)

typedef enum
{
    GPIO0_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO0_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO0_BIT_SMT;

#define GPIO0_ALL_SMT_NORMAL      ((0x0UL) << GPIO0_ALL_SMT_Pos)
#define GPIO0_ALL_SMT_SCHMITT     ((0x1UL) << GPIO0_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO0           DEGLITCH
 *  @access     PINMUX->GPIO0.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO0_ALL_DEGLITCH_Pos (5)
#define GPIO0_ALL_DEGLITCH_Msk (0x1UL << GPIO0_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO0_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO0_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO0_BIT_DEGLITCH;

#define GPIO0_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO0_ALL_DEGLITCH_Pos)
#define GPIO0_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO0_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO0           STRENGTH
 *  @access     PINMUX->GPIO0.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO0_ALL_STRENGTH_Pos (6)
#define GPIO0_ALL_STRENGTH_Msk (0x3UL << GPIO0_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO0_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO0_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO0_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO0_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO0_BIT_STRENGTH;

#define GPIO0_ALL_STRENGTH_5MA      ((0x0UL) << GPIO0_ALL_STRENGTH_Pos)
#define GPIO0_ALL_STRENGTH_10MA     ((0x1UL) << GPIO0_ALL_STRENGTH_Pos)
#define GPIO0_ALL_STRENGTH_15MA     ((0x2UL) << GPIO0_ALL_STRENGTH_Pos)
#define GPIO0_ALL_STRENGTH_20MA     ((0x3UL) << GPIO0_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO0           CHDFLTVAL
 *  @access     PINMUX->GPIO0.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO0_ALL_CHDFLTVAL_Pos (8)
#define GPIO0_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO0_ALL_CHDFLTVAL_Pos)

#define GPIO0_BIT_CHDFLTVAL

#define GPIO0_ALL_CHDFLTVAL_(x) ((x) << GPIO0_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO0           PD
 *  @access     PINMUX->GPIO0.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO0_ALL_PD_Pos (16)
#define GPIO0_ALL_PD_Msk (0xFFUL << GPIO0_ALL_PD_Pos)

#define GPIO0_BIT_PD

#define GPIO0_ALL_PD_(x) ((x) << GPIO0_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO0           PU
 *  @access     PINMUX->GPIO0.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO0_ALL_PU_Pos (24)
#define GPIO0_ALL_PU_Msk (0xFFUL << GPIO0_ALL_PU_Pos)

#define GPIO0_BIT_PU

#define GPIO0_ALL_PU_(x) ((x) << GPIO0_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO1           MUXSEL
 *  @access     PINMUX->GPIO1.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO1_ALL_MUXSEL_Pos (0)
#define GPIO1_ALL_MUXSEL_Msk (0x7UL << GPIO1_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO1_BIT_MUXSEL_GPIO1      = 0,  /*!< GPIO1    */
    GPIO1_BIT_MUXSEL_ADC1       = 1,  /*!< ADC1     */
    GPIO1_BIT_MUXSEL_COMP0L     = 6,  /*!< COMP0L   */
    GPIO1_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO1_BIT_MUXSEL;

#define GPIO1_ALL_MUXSEL_GPIO1      ((0x0UL) << GPIO1_ALL_MUXSEL_Pos)
#define GPIO1_ALL_MUXSEL_ADC1       ((0x1UL) << GPIO1_ALL_MUXSEL_Pos)
#define GPIO1_ALL_MUXSEL_COMP0L     ((0x6UL) << GPIO1_ALL_MUXSEL_Pos)
#define GPIO1_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO1_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO1           IE
 *  @access     PINMUX->GPIO1.bit.IE
 *  @brief      Input enable
 */
#define GPIO1_ALL_IE_Pos (3)
#define GPIO1_ALL_IE_Msk (0x1UL << GPIO1_ALL_IE_Pos)

typedef enum
{
    GPIO1_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO1_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO1_BIT_IE;

#define GPIO1_ALL_IE_DISABLE     ((0x0UL) << GPIO1_ALL_IE_Pos)
#define GPIO1_ALL_IE_ENABLE      ((0x1UL) << GPIO1_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO1           SMT
 *  @access     PINMUX->GPIO1.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO1_ALL_SMT_Pos (4)
#define GPIO1_ALL_SMT_Msk (0x1UL << GPIO1_ALL_SMT_Pos)

typedef enum
{
    GPIO1_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO1_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO1_BIT_SMT;

#define GPIO1_ALL_SMT_NORMAL      ((0x0UL) << GPIO1_ALL_SMT_Pos)
#define GPIO1_ALL_SMT_SCHMITT     ((0x1UL) << GPIO1_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO1           DEGLITCH
 *  @access     PINMUX->GPIO1.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO1_ALL_DEGLITCH_Pos (5)
#define GPIO1_ALL_DEGLITCH_Msk (0x1UL << GPIO1_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO1_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO1_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO1_BIT_DEGLITCH;

#define GPIO1_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO1_ALL_DEGLITCH_Pos)
#define GPIO1_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO1_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO1           STRENGTH
 *  @access     PINMUX->GPIO1.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO1_ALL_STRENGTH_Pos (6)
#define GPIO1_ALL_STRENGTH_Msk (0x3UL << GPIO1_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO1_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO1_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO1_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO1_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO1_BIT_STRENGTH;

#define GPIO1_ALL_STRENGTH_5MA      ((0x0UL) << GPIO1_ALL_STRENGTH_Pos)
#define GPIO1_ALL_STRENGTH_10MA     ((0x1UL) << GPIO1_ALL_STRENGTH_Pos)
#define GPIO1_ALL_STRENGTH_15MA     ((0x2UL) << GPIO1_ALL_STRENGTH_Pos)
#define GPIO1_ALL_STRENGTH_20MA     ((0x3UL) << GPIO1_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO1           CHDFLTVAL
 *  @access     PINMUX->GPIO1.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO1_ALL_CHDFLTVAL_Pos (8)
#define GPIO1_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO1_ALL_CHDFLTVAL_Pos)

#define GPIO1_BIT_CHDFLTVAL

#define GPIO1_ALL_CHDFLTVAL_(x) ((x) << GPIO1_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO1           PD
 *  @access     PINMUX->GPIO1.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO1_ALL_PD_Pos (16)
#define GPIO1_ALL_PD_Msk (0xFFUL << GPIO1_ALL_PD_Pos)

#define GPIO1_BIT_PD

#define GPIO1_ALL_PD_(x) ((x) << GPIO1_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO1           PU
 *  @access     PINMUX->GPIO1.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO1_ALL_PU_Pos (24)
#define GPIO1_ALL_PU_Msk (0xFFUL << GPIO1_ALL_PU_Pos)

#define GPIO1_BIT_PU

#define GPIO1_ALL_PU_(x) ((x) << GPIO1_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO2           MUXSEL
 *  @access     PINMUX->GPIO2.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO2_ALL_MUXSEL_Pos (0)
#define GPIO2_ALL_MUXSEL_Msk (0x7UL << GPIO2_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO2_BIT_MUXSEL_GPIO2      = 0,  /*!< GPIO2    */
    GPIO2_BIT_MUXSEL_ADC2       = 1,  /*!< ADC2     */
    GPIO2_BIT_MUXSEL_COMP1H     = 6,  /*!< COMP1H   */
    GPIO2_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO2_BIT_MUXSEL;

#define GPIO2_ALL_MUXSEL_GPIO2      ((0x0UL) << GPIO2_ALL_MUXSEL_Pos)
#define GPIO2_ALL_MUXSEL_ADC2       ((0x1UL) << GPIO2_ALL_MUXSEL_Pos)
#define GPIO2_ALL_MUXSEL_COMP1H     ((0x6UL) << GPIO2_ALL_MUXSEL_Pos)
#define GPIO2_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO2_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO2           IE
 *  @access     PINMUX->GPIO2.bit.IE
 *  @brief      Input enable
 */
#define GPIO2_ALL_IE_Pos (3)
#define GPIO2_ALL_IE_Msk (0x1UL << GPIO2_ALL_IE_Pos)

typedef enum
{
    GPIO2_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO2_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO2_BIT_IE;

#define GPIO2_ALL_IE_DISABLE     ((0x0UL) << GPIO2_ALL_IE_Pos)
#define GPIO2_ALL_IE_ENABLE      ((0x1UL) << GPIO2_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO2           SMT
 *  @access     PINMUX->GPIO2.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO2_ALL_SMT_Pos (4)
#define GPIO2_ALL_SMT_Msk (0x1UL << GPIO2_ALL_SMT_Pos)

typedef enum
{
    GPIO2_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO2_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO2_BIT_SMT;

#define GPIO2_ALL_SMT_NORMAL      ((0x0UL) << GPIO2_ALL_SMT_Pos)
#define GPIO2_ALL_SMT_SCHMITT     ((0x1UL) << GPIO2_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO2           DEGLITCH
 *  @access     PINMUX->GPIO2.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO2_ALL_DEGLITCH_Pos (5)
#define GPIO2_ALL_DEGLITCH_Msk (0x1UL << GPIO2_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO2_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO2_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO2_BIT_DEGLITCH;

#define GPIO2_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO2_ALL_DEGLITCH_Pos)
#define GPIO2_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO2_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO2           STRENGTH
 *  @access     PINMUX->GPIO2.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO2_ALL_STRENGTH_Pos (6)
#define GPIO2_ALL_STRENGTH_Msk (0x3UL << GPIO2_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO2_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO2_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO2_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO2_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO2_BIT_STRENGTH;

#define GPIO2_ALL_STRENGTH_5MA      ((0x0UL) << GPIO2_ALL_STRENGTH_Pos)
#define GPIO2_ALL_STRENGTH_10MA     ((0x1UL) << GPIO2_ALL_STRENGTH_Pos)
#define GPIO2_ALL_STRENGTH_15MA     ((0x2UL) << GPIO2_ALL_STRENGTH_Pos)
#define GPIO2_ALL_STRENGTH_20MA     ((0x3UL) << GPIO2_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO2           CHDFLTVAL
 *  @access     PINMUX->GPIO2.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO2_ALL_CHDFLTVAL_Pos (8)
#define GPIO2_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO2_ALL_CHDFLTVAL_Pos)

#define GPIO2_BIT_CHDFLTVAL

#define GPIO2_ALL_CHDFLTVAL_(x) ((x) << GPIO2_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO2           PD
 *  @access     PINMUX->GPIO2.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO2_ALL_PD_Pos (16)
#define GPIO2_ALL_PD_Msk (0xFFUL << GPIO2_ALL_PD_Pos)

#define GPIO2_BIT_PD

#define GPIO2_ALL_PD_(x) ((x) << GPIO2_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO2           PU
 *  @access     PINMUX->GPIO2.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO2_ALL_PU_Pos (24)
#define GPIO2_ALL_PU_Msk (0xFFUL << GPIO2_ALL_PU_Pos)

#define GPIO2_BIT_PU

#define GPIO2_ALL_PU_(x) ((x) << GPIO2_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO3           MUXSEL
 *  @access     PINMUX->GPIO3.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO3_ALL_MUXSEL_Pos (0)
#define GPIO3_ALL_MUXSEL_Msk (0x7UL << GPIO3_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO3_BIT_MUXSEL_GPIO3      = 0,  /*!< GPIO3    */
    GPIO3_BIT_MUXSEL_ADC3       = 1,  /*!< ADC3     */
    GPIO3_BIT_MUXSEL_COMP1L     = 6,  /*!< COMP1L   */
    GPIO3_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO3_BIT_MUXSEL;

#define GPIO3_ALL_MUXSEL_GPIO3      ((0x0UL) << GPIO3_ALL_MUXSEL_Pos)
#define GPIO3_ALL_MUXSEL_ADC3       ((0x1UL) << GPIO3_ALL_MUXSEL_Pos)
#define GPIO3_ALL_MUXSEL_COMP1L     ((0x6UL) << GPIO3_ALL_MUXSEL_Pos)
#define GPIO3_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO3_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO3           IE
 *  @access     PINMUX->GPIO3.bit.IE
 *  @brief      Input enable
 */
#define GPIO3_ALL_IE_Pos (3)
#define GPIO3_ALL_IE_Msk (0x1UL << GPIO3_ALL_IE_Pos)

typedef enum
{
    GPIO3_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO3_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO3_BIT_IE;

#define GPIO3_ALL_IE_DISABLE     ((0x0UL) << GPIO3_ALL_IE_Pos)
#define GPIO3_ALL_IE_ENABLE      ((0x1UL) << GPIO3_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO3           SMT
 *  @access     PINMUX->GPIO3.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO3_ALL_SMT_Pos (4)
#define GPIO3_ALL_SMT_Msk (0x1UL << GPIO3_ALL_SMT_Pos)

typedef enum
{
    GPIO3_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO3_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO3_BIT_SMT;

#define GPIO3_ALL_SMT_NORMAL      ((0x0UL) << GPIO3_ALL_SMT_Pos)
#define GPIO3_ALL_SMT_SCHMITT     ((0x1UL) << GPIO3_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO3           DEGLITCH
 *  @access     PINMUX->GPIO3.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO3_ALL_DEGLITCH_Pos (5)
#define GPIO3_ALL_DEGLITCH_Msk (0x1UL << GPIO3_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO3_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO3_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO3_BIT_DEGLITCH;

#define GPIO3_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO3_ALL_DEGLITCH_Pos)
#define GPIO3_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO3_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO3           STRENGTH
 *  @access     PINMUX->GPIO3.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO3_ALL_STRENGTH_Pos (6)
#define GPIO3_ALL_STRENGTH_Msk (0x3UL << GPIO3_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO3_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO3_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO3_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO3_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO3_BIT_STRENGTH;

#define GPIO3_ALL_STRENGTH_5MA      ((0x0UL) << GPIO3_ALL_STRENGTH_Pos)
#define GPIO3_ALL_STRENGTH_10MA     ((0x1UL) << GPIO3_ALL_STRENGTH_Pos)
#define GPIO3_ALL_STRENGTH_15MA     ((0x2UL) << GPIO3_ALL_STRENGTH_Pos)
#define GPIO3_ALL_STRENGTH_20MA     ((0x3UL) << GPIO3_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO3           CHDFLTVAL
 *  @access     PINMUX->GPIO3.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO3_ALL_CHDFLTVAL_Pos (8)
#define GPIO3_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO3_ALL_CHDFLTVAL_Pos)

#define GPIO3_BIT_CHDFLTVAL

#define GPIO3_ALL_CHDFLTVAL_(x) ((x) << GPIO3_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO3           PD
 *  @access     PINMUX->GPIO3.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO3_ALL_PD_Pos (16)
#define GPIO3_ALL_PD_Msk (0xFFUL << GPIO3_ALL_PD_Pos)

#define GPIO3_BIT_PD

#define GPIO3_ALL_PD_(x) ((x) << GPIO3_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO3           PU
 *  @access     PINMUX->GPIO3.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO3_ALL_PU_Pos (24)
#define GPIO3_ALL_PU_Msk (0xFFUL << GPIO3_ALL_PU_Pos)

#define GPIO3_BIT_PU

#define GPIO3_ALL_PU_(x) ((x) << GPIO3_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO4           MUXSEL
 *  @access     PINMUX->GPIO4.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO4_ALL_MUXSEL_Pos (0)
#define GPIO4_ALL_MUXSEL_Msk (0x7UL << GPIO4_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO4_BIT_MUXSEL_GPIO4      = 0,  /*!< GPIO4    */
    GPIO4_BIT_MUXSEL_ADC4       = 1,  /*!< ADC4     */
    GPIO4_BIT_MUXSEL_COMP2H     = 6,  /*!< COMP2H   */
    GPIO4_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO4_BIT_MUXSEL;

#define GPIO4_ALL_MUXSEL_GPIO4      ((0x0UL) << GPIO4_ALL_MUXSEL_Pos)
#define GPIO4_ALL_MUXSEL_ADC4       ((0x1UL) << GPIO4_ALL_MUXSEL_Pos)
#define GPIO4_ALL_MUXSEL_COMP2H     ((0x6UL) << GPIO4_ALL_MUXSEL_Pos)
#define GPIO4_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO4_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO4           IE
 *  @access     PINMUX->GPIO4.bit.IE
 *  @brief      Input enable
 */
#define GPIO4_ALL_IE_Pos (3)
#define GPIO4_ALL_IE_Msk (0x1UL << GPIO4_ALL_IE_Pos)

typedef enum
{
    GPIO4_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO4_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO4_BIT_IE;

#define GPIO4_ALL_IE_DISABLE     ((0x0UL) << GPIO4_ALL_IE_Pos)
#define GPIO4_ALL_IE_ENABLE      ((0x1UL) << GPIO4_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO4           SMT
 *  @access     PINMUX->GPIO4.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO4_ALL_SMT_Pos (4)
#define GPIO4_ALL_SMT_Msk (0x1UL << GPIO4_ALL_SMT_Pos)

typedef enum
{
    GPIO4_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO4_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO4_BIT_SMT;

#define GPIO4_ALL_SMT_NORMAL      ((0x0UL) << GPIO4_ALL_SMT_Pos)
#define GPIO4_ALL_SMT_SCHMITT     ((0x1UL) << GPIO4_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO4           DEGLITCH
 *  @access     PINMUX->GPIO4.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO4_ALL_DEGLITCH_Pos (5)
#define GPIO4_ALL_DEGLITCH_Msk (0x1UL << GPIO4_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO4_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO4_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO4_BIT_DEGLITCH;

#define GPIO4_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO4_ALL_DEGLITCH_Pos)
#define GPIO4_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO4_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO4           STRENGTH
 *  @access     PINMUX->GPIO4.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO4_ALL_STRENGTH_Pos (6)
#define GPIO4_ALL_STRENGTH_Msk (0x3UL << GPIO4_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO4_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO4_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO4_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO4_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO4_BIT_STRENGTH;

#define GPIO4_ALL_STRENGTH_5MA      ((0x0UL) << GPIO4_ALL_STRENGTH_Pos)
#define GPIO4_ALL_STRENGTH_10MA     ((0x1UL) << GPIO4_ALL_STRENGTH_Pos)
#define GPIO4_ALL_STRENGTH_15MA     ((0x2UL) << GPIO4_ALL_STRENGTH_Pos)
#define GPIO4_ALL_STRENGTH_20MA     ((0x3UL) << GPIO4_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO4           CHDFLTVAL
 *  @access     PINMUX->GPIO4.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO4_ALL_CHDFLTVAL_Pos (8)
#define GPIO4_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO4_ALL_CHDFLTVAL_Pos)

#define GPIO4_BIT_CHDFLTVAL

#define GPIO4_ALL_CHDFLTVAL_(x) ((x) << GPIO4_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO4           PD
 *  @access     PINMUX->GPIO4.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO4_ALL_PD_Pos (16)
#define GPIO4_ALL_PD_Msk (0xFFUL << GPIO4_ALL_PD_Pos)

#define GPIO4_BIT_PD

#define GPIO4_ALL_PD_(x) ((x) << GPIO4_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO4           PU
 *  @access     PINMUX->GPIO4.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO4_ALL_PU_Pos (24)
#define GPIO4_ALL_PU_Msk (0xFFUL << GPIO4_ALL_PU_Pos)

#define GPIO4_BIT_PU

#define GPIO4_ALL_PU_(x) ((x) << GPIO4_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO5           MUXSEL
 *  @access     PINMUX->GPIO5.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO5_ALL_MUXSEL_Pos (0)
#define GPIO5_ALL_MUXSEL_Msk (0x7UL << GPIO5_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO5_BIT_MUXSEL_GPIO5      = 0,  /*!< GPIO5    */
    GPIO5_BIT_MUXSEL_ADC5       = 1,  /*!< ADC5     */
    GPIO5_BIT_MUXSEL_COMP2L     = 6,  /*!< COMP2L   */
    GPIO5_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO5_BIT_MUXSEL;

#define GPIO5_ALL_MUXSEL_GPIO5      ((0x0UL) << GPIO5_ALL_MUXSEL_Pos)
#define GPIO5_ALL_MUXSEL_ADC5       ((0x1UL) << GPIO5_ALL_MUXSEL_Pos)
#define GPIO5_ALL_MUXSEL_COMP2L     ((0x6UL) << GPIO5_ALL_MUXSEL_Pos)
#define GPIO5_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO5_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO5           IE
 *  @access     PINMUX->GPIO5.bit.IE
 *  @brief      Input enable
 */
#define GPIO5_ALL_IE_Pos (3)
#define GPIO5_ALL_IE_Msk (0x1UL << GPIO5_ALL_IE_Pos)

typedef enum
{
    GPIO5_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO5_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO5_BIT_IE;

#define GPIO5_ALL_IE_DISABLE     ((0x0UL) << GPIO5_ALL_IE_Pos)
#define GPIO5_ALL_IE_ENABLE      ((0x1UL) << GPIO5_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO5           SMT
 *  @access     PINMUX->GPIO5.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO5_ALL_SMT_Pos (4)
#define GPIO5_ALL_SMT_Msk (0x1UL << GPIO5_ALL_SMT_Pos)

typedef enum
{
    GPIO5_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO5_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO5_BIT_SMT;

#define GPIO5_ALL_SMT_NORMAL      ((0x0UL) << GPIO5_ALL_SMT_Pos)
#define GPIO5_ALL_SMT_SCHMITT     ((0x1UL) << GPIO5_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO5           DEGLITCH
 *  @access     PINMUX->GPIO5.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO5_ALL_DEGLITCH_Pos (5)
#define GPIO5_ALL_DEGLITCH_Msk (0x1UL << GPIO5_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO5_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO5_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO5_BIT_DEGLITCH;

#define GPIO5_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO5_ALL_DEGLITCH_Pos)
#define GPIO5_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO5_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO5           STRENGTH
 *  @access     PINMUX->GPIO5.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO5_ALL_STRENGTH_Pos (6)
#define GPIO5_ALL_STRENGTH_Msk (0x3UL << GPIO5_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO5_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO5_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO5_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO5_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO5_BIT_STRENGTH;

#define GPIO5_ALL_STRENGTH_5MA      ((0x0UL) << GPIO5_ALL_STRENGTH_Pos)
#define GPIO5_ALL_STRENGTH_10MA     ((0x1UL) << GPIO5_ALL_STRENGTH_Pos)
#define GPIO5_ALL_STRENGTH_15MA     ((0x2UL) << GPIO5_ALL_STRENGTH_Pos)
#define GPIO5_ALL_STRENGTH_20MA     ((0x3UL) << GPIO5_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO5           CHDFLTVAL
 *  @access     PINMUX->GPIO5.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO5_ALL_CHDFLTVAL_Pos (8)
#define GPIO5_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO5_ALL_CHDFLTVAL_Pos)

#define GPIO5_BIT_CHDFLTVAL

#define GPIO5_ALL_CHDFLTVAL_(x) ((x) << GPIO5_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO5           PD
 *  @access     PINMUX->GPIO5.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO5_ALL_PD_Pos (16)
#define GPIO5_ALL_PD_Msk (0xFFUL << GPIO5_ALL_PD_Pos)

#define GPIO5_BIT_PD

#define GPIO5_ALL_PD_(x) ((x) << GPIO5_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO5           PU
 *  @access     PINMUX->GPIO5.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO5_ALL_PU_Pos (24)
#define GPIO5_ALL_PU_Msk (0xFFUL << GPIO5_ALL_PU_Pos)

#define GPIO5_BIT_PU

#define GPIO5_ALL_PU_(x) ((x) << GPIO5_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO6           MUXSEL
 *  @access     PINMUX->GPIO6.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO6_ALL_MUXSEL_Pos (0)
#define GPIO6_ALL_MUXSEL_Msk (0x7UL << GPIO6_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO6_BIT_MUXSEL_GPIO6     = 0,  /*!< GPIO6   */
    GPIO6_BIT_MUXSEL_ADC6      = 1,  /*!< ADC6    */
    GPIO6_BIT_MUXSEL_ECAPO     = 7,  /*!< ECAPO   */
} GPIO6_BIT_MUXSEL;

#define GPIO6_ALL_MUXSEL_GPIO6     ((0x0UL) << GPIO6_ALL_MUXSEL_Pos)
#define GPIO6_ALL_MUXSEL_ADC6      ((0x1UL) << GPIO6_ALL_MUXSEL_Pos)
#define GPIO6_ALL_MUXSEL_ECAPO     ((0x7UL) << GPIO6_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO6           IE
 *  @access     PINMUX->GPIO6.bit.IE
 *  @brief      Input enable
 */
#define GPIO6_ALL_IE_Pos (3)
#define GPIO6_ALL_IE_Msk (0x1UL << GPIO6_ALL_IE_Pos)

typedef enum
{
    GPIO6_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO6_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO6_BIT_IE;

#define GPIO6_ALL_IE_DISABLE     ((0x0UL) << GPIO6_ALL_IE_Pos)
#define GPIO6_ALL_IE_ENABLE      ((0x1UL) << GPIO6_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO6           SMT
 *  @access     PINMUX->GPIO6.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO6_ALL_SMT_Pos (4)
#define GPIO6_ALL_SMT_Msk (0x1UL << GPIO6_ALL_SMT_Pos)

typedef enum
{
    GPIO6_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO6_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO6_BIT_SMT;

#define GPIO6_ALL_SMT_NORMAL      ((0x0UL) << GPIO6_ALL_SMT_Pos)
#define GPIO6_ALL_SMT_SCHMITT     ((0x1UL) << GPIO6_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO6           DEGLITCH
 *  @access     PINMUX->GPIO6.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO6_ALL_DEGLITCH_Pos (5)
#define GPIO6_ALL_DEGLITCH_Msk (0x1UL << GPIO6_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO6_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO6_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO6_BIT_DEGLITCH;

#define GPIO6_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO6_ALL_DEGLITCH_Pos)
#define GPIO6_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO6_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO6           STRENGTH
 *  @access     PINMUX->GPIO6.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO6_ALL_STRENGTH_Pos (6)
#define GPIO6_ALL_STRENGTH_Msk (0x3UL << GPIO6_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO6_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO6_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO6_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO6_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO6_BIT_STRENGTH;

#define GPIO6_ALL_STRENGTH_5MA      ((0x0UL) << GPIO6_ALL_STRENGTH_Pos)
#define GPIO6_ALL_STRENGTH_10MA     ((0x1UL) << GPIO6_ALL_STRENGTH_Pos)
#define GPIO6_ALL_STRENGTH_15MA     ((0x2UL) << GPIO6_ALL_STRENGTH_Pos)
#define GPIO6_ALL_STRENGTH_20MA     ((0x3UL) << GPIO6_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO6           CHDFLTVAL
 *  @access     PINMUX->GPIO6.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO6_ALL_CHDFLTVAL_Pos (8)
#define GPIO6_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO6_ALL_CHDFLTVAL_Pos)

#define GPIO6_BIT_CHDFLTVAL

#define GPIO6_ALL_CHDFLTVAL_(x) ((x) << GPIO6_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO6           PD
 *  @access     PINMUX->GPIO6.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO6_ALL_PD_Pos (16)
#define GPIO6_ALL_PD_Msk (0xFFUL << GPIO6_ALL_PD_Pos)

#define GPIO6_BIT_PD

#define GPIO6_ALL_PD_(x) ((x) << GPIO6_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO6           PU
 *  @access     PINMUX->GPIO6.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO6_ALL_PU_Pos (24)
#define GPIO6_ALL_PU_Msk (0xFFUL << GPIO6_ALL_PU_Pos)

#define GPIO6_BIT_PU

#define GPIO6_ALL_PU_(x) ((x) << GPIO6_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO7           MUXSEL
 *  @access     PINMUX->GPIO7.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO7_ALL_MUXSEL_Pos (0)
#define GPIO7_ALL_MUXSEL_Msk (0x7UL << GPIO7_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO7_BIT_MUXSEL_GPIO7     = 0,  /*!< GPIO7   */
    GPIO7_BIT_MUXSEL_ADC7      = 1,  /*!< ADC7    */
    GPIO7_BIT_MUXSEL_ECAPO     = 7,  /*!< ECAPO   */
} GPIO7_BIT_MUXSEL;

#define GPIO7_ALL_MUXSEL_GPIO7     ((0x0UL) << GPIO7_ALL_MUXSEL_Pos)
#define GPIO7_ALL_MUXSEL_ADC7      ((0x1UL) << GPIO7_ALL_MUXSEL_Pos)
#define GPIO7_ALL_MUXSEL_ECAPO     ((0x7UL) << GPIO7_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO7           IE
 *  @access     PINMUX->GPIO7.bit.IE
 *  @brief      Input enable
 */
#define GPIO7_ALL_IE_Pos (3)
#define GPIO7_ALL_IE_Msk (0x1UL << GPIO7_ALL_IE_Pos)

typedef enum
{
    GPIO7_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO7_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO7_BIT_IE;

#define GPIO7_ALL_IE_DISABLE     ((0x0UL) << GPIO7_ALL_IE_Pos)
#define GPIO7_ALL_IE_ENABLE      ((0x1UL) << GPIO7_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO7           SMT
 *  @access     PINMUX->GPIO7.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO7_ALL_SMT_Pos (4)
#define GPIO7_ALL_SMT_Msk (0x1UL << GPIO7_ALL_SMT_Pos)

typedef enum
{
    GPIO7_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO7_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO7_BIT_SMT;

#define GPIO7_ALL_SMT_NORMAL      ((0x0UL) << GPIO7_ALL_SMT_Pos)
#define GPIO7_ALL_SMT_SCHMITT     ((0x1UL) << GPIO7_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO7           DEGLITCH
 *  @access     PINMUX->GPIO7.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO7_ALL_DEGLITCH_Pos (5)
#define GPIO7_ALL_DEGLITCH_Msk (0x1UL << GPIO7_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO7_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO7_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO7_BIT_DEGLITCH;

#define GPIO7_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO7_ALL_DEGLITCH_Pos)
#define GPIO7_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO7_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO7           STRENGTH
 *  @access     PINMUX->GPIO7.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO7_ALL_STRENGTH_Pos (6)
#define GPIO7_ALL_STRENGTH_Msk (0x3UL << GPIO7_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO7_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO7_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO7_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO7_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO7_BIT_STRENGTH;

#define GPIO7_ALL_STRENGTH_5MA      ((0x0UL) << GPIO7_ALL_STRENGTH_Pos)
#define GPIO7_ALL_STRENGTH_10MA     ((0x1UL) << GPIO7_ALL_STRENGTH_Pos)
#define GPIO7_ALL_STRENGTH_15MA     ((0x2UL) << GPIO7_ALL_STRENGTH_Pos)
#define GPIO7_ALL_STRENGTH_20MA     ((0x3UL) << GPIO7_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO7           CHDFLTVAL
 *  @access     PINMUX->GPIO7.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO7_ALL_CHDFLTVAL_Pos (8)
#define GPIO7_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO7_ALL_CHDFLTVAL_Pos)

#define GPIO7_BIT_CHDFLTVAL

#define GPIO7_ALL_CHDFLTVAL_(x) ((x) << GPIO7_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO7           PD
 *  @access     PINMUX->GPIO7.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO7_ALL_PD_Pos (16)
#define GPIO7_ALL_PD_Msk (0xFFUL << GPIO7_ALL_PD_Pos)

#define GPIO7_BIT_PD

#define GPIO7_ALL_PD_(x) ((x) << GPIO7_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO7           PU
 *  @access     PINMUX->GPIO7.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO7_ALL_PU_Pos (24)
#define GPIO7_ALL_PU_Msk (0xFFUL << GPIO7_ALL_PU_Pos)

#define GPIO7_BIT_PU

#define GPIO7_ALL_PU_(x) ((x) << GPIO7_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO8           MUXSEL
 *  @access     PINMUX->GPIO8.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO8_ALL_MUXSEL_Pos (0)
#define GPIO8_ALL_MUXSEL_Msk (0x7UL << GPIO8_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO8_BIT_MUXSEL_GPIO8        = 0,  /*!< GPIO8      */
    GPIO8_BIT_MUXSEL_ADC8         = 1,  /*!< ADC8       */
    GPIO8_BIT_MUXSEL_SPI_SCLK     = 2,  /*!< SPI_SCLK   */
    GPIO8_BIT_MUXSEL_PWMSOCO      = 3,  /*!< PWMSOCO    */
    GPIO8_BIT_MUXSEL_COMP3H       = 6,  /*!< COMP3H     */
    GPIO8_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO8_BIT_MUXSEL;

#define GPIO8_ALL_MUXSEL_GPIO8        ((0x0UL) << GPIO8_ALL_MUXSEL_Pos)
#define GPIO8_ALL_MUXSEL_ADC8         ((0x1UL) << GPIO8_ALL_MUXSEL_Pos)
#define GPIO8_ALL_MUXSEL_SPI_SCLK     ((0x2UL) << GPIO8_ALL_MUXSEL_Pos)
#define GPIO8_ALL_MUXSEL_PWMSOCO      ((0x3UL) << GPIO8_ALL_MUXSEL_Pos)
#define GPIO8_ALL_MUXSEL_COMP3H       ((0x6UL) << GPIO8_ALL_MUXSEL_Pos)
#define GPIO8_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO8_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO8           IE
 *  @access     PINMUX->GPIO8.bit.IE
 *  @brief      Input enable
 */
#define GPIO8_ALL_IE_Pos (3)
#define GPIO8_ALL_IE_Msk (0x1UL << GPIO8_ALL_IE_Pos)

typedef enum
{
    GPIO8_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO8_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO8_BIT_IE;

#define GPIO8_ALL_IE_DISABLE     ((0x0UL) << GPIO8_ALL_IE_Pos)
#define GPIO8_ALL_IE_ENABLE      ((0x1UL) << GPIO8_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO8           SMT
 *  @access     PINMUX->GPIO8.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO8_ALL_SMT_Pos (4)
#define GPIO8_ALL_SMT_Msk (0x1UL << GPIO8_ALL_SMT_Pos)

typedef enum
{
    GPIO8_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO8_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO8_BIT_SMT;

#define GPIO8_ALL_SMT_NORMAL      ((0x0UL) << GPIO8_ALL_SMT_Pos)
#define GPIO8_ALL_SMT_SCHMITT     ((0x1UL) << GPIO8_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO8           DEGLITCH
 *  @access     PINMUX->GPIO8.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO8_ALL_DEGLITCH_Pos (5)
#define GPIO8_ALL_DEGLITCH_Msk (0x1UL << GPIO8_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO8_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO8_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO8_BIT_DEGLITCH;

#define GPIO8_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO8_ALL_DEGLITCH_Pos)
#define GPIO8_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO8_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO8           STRENGTH
 *  @access     PINMUX->GPIO8.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO8_ALL_STRENGTH_Pos (6)
#define GPIO8_ALL_STRENGTH_Msk (0x3UL << GPIO8_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO8_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO8_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO8_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO8_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO8_BIT_STRENGTH;

#define GPIO8_ALL_STRENGTH_5MA      ((0x0UL) << GPIO8_ALL_STRENGTH_Pos)
#define GPIO8_ALL_STRENGTH_10MA     ((0x1UL) << GPIO8_ALL_STRENGTH_Pos)
#define GPIO8_ALL_STRENGTH_15MA     ((0x2UL) << GPIO8_ALL_STRENGTH_Pos)
#define GPIO8_ALL_STRENGTH_20MA     ((0x3UL) << GPIO8_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO8           CHDFLTVAL
 *  @access     PINMUX->GPIO8.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO8_ALL_CHDFLTVAL_Pos (8)
#define GPIO8_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO8_ALL_CHDFLTVAL_Pos)

#define GPIO8_BIT_CHDFLTVAL

#define GPIO8_ALL_CHDFLTVAL_(x) ((x) << GPIO8_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO8           PD
 *  @access     PINMUX->GPIO8.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO8_ALL_PD_Pos (16)
#define GPIO8_ALL_PD_Msk (0xFFUL << GPIO8_ALL_PD_Pos)

#define GPIO8_BIT_PD

#define GPIO8_ALL_PD_(x) ((x) << GPIO8_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO8           PU
 *  @access     PINMUX->GPIO8.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO8_ALL_PU_Pos (24)
#define GPIO8_ALL_PU_Msk (0xFFUL << GPIO8_ALL_PU_Pos)

#define GPIO8_BIT_PU

#define GPIO8_ALL_PU_(x) ((x) << GPIO8_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO9           MUXSEL
 *  @access     PINMUX->GPIO9.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO9_ALL_MUXSEL_Pos (0)
#define GPIO9_ALL_MUXSEL_Msk (0x7UL << GPIO9_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO9_BIT_MUXSEL_GPIO9        = 0,  /*!< GPIO9      */
    GPIO9_BIT_MUXSEL_ADC9         = 1,  /*!< ADC9       */
    GPIO9_BIT_MUXSEL_SPI_SFRM     = 2,  /*!< SPI_SFRM   */
    GPIO9_BIT_MUXSEL_COMP3L       = 6,  /*!< COMP3L     */
    GPIO9_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO9_BIT_MUXSEL;

#define GPIO9_ALL_MUXSEL_GPIO9        ((0x0UL) << GPIO9_ALL_MUXSEL_Pos)
#define GPIO9_ALL_MUXSEL_ADC9         ((0x1UL) << GPIO9_ALL_MUXSEL_Pos)
#define GPIO9_ALL_MUXSEL_SPI_SFRM     ((0x2UL) << GPIO9_ALL_MUXSEL_Pos)
#define GPIO9_ALL_MUXSEL_COMP3L       ((0x6UL) << GPIO9_ALL_MUXSEL_Pos)
#define GPIO9_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO9_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO9           IE
 *  @access     PINMUX->GPIO9.bit.IE
 *  @brief      Input enable
 */
#define GPIO9_ALL_IE_Pos (3)
#define GPIO9_ALL_IE_Msk (0x1UL << GPIO9_ALL_IE_Pos)

typedef enum
{
    GPIO9_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO9_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO9_BIT_IE;

#define GPIO9_ALL_IE_DISABLE     ((0x0UL) << GPIO9_ALL_IE_Pos)
#define GPIO9_ALL_IE_ENABLE      ((0x1UL) << GPIO9_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO9           SMT
 *  @access     PINMUX->GPIO9.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO9_ALL_SMT_Pos (4)
#define GPIO9_ALL_SMT_Msk (0x1UL << GPIO9_ALL_SMT_Pos)

typedef enum
{
    GPIO9_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO9_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO9_BIT_SMT;

#define GPIO9_ALL_SMT_NORMAL      ((0x0UL) << GPIO9_ALL_SMT_Pos)
#define GPIO9_ALL_SMT_SCHMITT     ((0x1UL) << GPIO9_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO9           DEGLITCH
 *  @access     PINMUX->GPIO9.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO9_ALL_DEGLITCH_Pos (5)
#define GPIO9_ALL_DEGLITCH_Msk (0x1UL << GPIO9_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO9_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO9_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO9_BIT_DEGLITCH;

#define GPIO9_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO9_ALL_DEGLITCH_Pos)
#define GPIO9_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO9_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO9           STRENGTH
 *  @access     PINMUX->GPIO9.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO9_ALL_STRENGTH_Pos (6)
#define GPIO9_ALL_STRENGTH_Msk (0x3UL << GPIO9_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO9_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO9_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO9_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO9_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO9_BIT_STRENGTH;

#define GPIO9_ALL_STRENGTH_5MA      ((0x0UL) << GPIO9_ALL_STRENGTH_Pos)
#define GPIO9_ALL_STRENGTH_10MA     ((0x1UL) << GPIO9_ALL_STRENGTH_Pos)
#define GPIO9_ALL_STRENGTH_15MA     ((0x2UL) << GPIO9_ALL_STRENGTH_Pos)
#define GPIO9_ALL_STRENGTH_20MA     ((0x3UL) << GPIO9_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO9           CHDFLTVAL
 *  @access     PINMUX->GPIO9.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO9_ALL_CHDFLTVAL_Pos (8)
#define GPIO9_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO9_ALL_CHDFLTVAL_Pos)

#define GPIO9_BIT_CHDFLTVAL

#define GPIO9_ALL_CHDFLTVAL_(x) ((x) << GPIO9_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO9           PD
 *  @access     PINMUX->GPIO9.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO9_ALL_PD_Pos (16)
#define GPIO9_ALL_PD_Msk (0xFFUL << GPIO9_ALL_PD_Pos)

#define GPIO9_BIT_PD

#define GPIO9_ALL_PD_(x) ((x) << GPIO9_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO9           PU
 *  @access     PINMUX->GPIO9.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO9_ALL_PU_Pos (24)
#define GPIO9_ALL_PU_Msk (0xFFUL << GPIO9_ALL_PU_Pos)

#define GPIO9_BIT_PU

#define GPIO9_ALL_PU_(x) ((x) << GPIO9_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO10          MUXSEL
 *  @access     PINMUX->GPIO10.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO10_ALL_MUXSEL_Pos (0)
#define GPIO10_ALL_MUXSEL_Msk (0x7UL << GPIO10_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO10_BIT_MUXSEL_GPIO10       = 0,  /*!< GPIO10     */
    GPIO10_BIT_MUXSEL_ADC10        = 1,  /*!< ADC10      */
    GPIO10_BIT_MUXSEL_SPI_MOSI     = 2,  /*!< SPI_MOSI   */
    GPIO10_BIT_MUXSEL_SPI_MISO     = 3,  /*!< SPI_MISO   */
    GPIO10_BIT_MUXSEL_COMP4H       = 6,  /*!< COMP4H     */
    GPIO10_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO10_BIT_MUXSEL;

#define GPIO10_ALL_MUXSEL_GPIO10       ((0x0UL) << GPIO10_ALL_MUXSEL_Pos)
#define GPIO10_ALL_MUXSEL_ADC10        ((0x1UL) << GPIO10_ALL_MUXSEL_Pos)
#define GPIO10_ALL_MUXSEL_SPI_MOSI     ((0x2UL) << GPIO10_ALL_MUXSEL_Pos)
#define GPIO10_ALL_MUXSEL_SPI_MISO     ((0x3UL) << GPIO10_ALL_MUXSEL_Pos)
#define GPIO10_ALL_MUXSEL_COMP4H       ((0x6UL) << GPIO10_ALL_MUXSEL_Pos)
#define GPIO10_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO10_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO10          IE
 *  @access     PINMUX->GPIO10.bit.IE
 *  @brief      Input enable
 */
#define GPIO10_ALL_IE_Pos (3)
#define GPIO10_ALL_IE_Msk (0x1UL << GPIO10_ALL_IE_Pos)

typedef enum
{
    GPIO10_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO10_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO10_BIT_IE;

#define GPIO10_ALL_IE_DISABLE     ((0x0UL) << GPIO10_ALL_IE_Pos)
#define GPIO10_ALL_IE_ENABLE      ((0x1UL) << GPIO10_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO10          SMT
 *  @access     PINMUX->GPIO10.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO10_ALL_SMT_Pos (4)
#define GPIO10_ALL_SMT_Msk (0x1UL << GPIO10_ALL_SMT_Pos)

typedef enum
{
    GPIO10_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO10_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO10_BIT_SMT;

#define GPIO10_ALL_SMT_NORMAL      ((0x0UL) << GPIO10_ALL_SMT_Pos)
#define GPIO10_ALL_SMT_SCHMITT     ((0x1UL) << GPIO10_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO10          DEGLITCH
 *  @access     PINMUX->GPIO10.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO10_ALL_DEGLITCH_Pos (5)
#define GPIO10_ALL_DEGLITCH_Msk (0x1UL << GPIO10_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO10_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO10_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO10_BIT_DEGLITCH;

#define GPIO10_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO10_ALL_DEGLITCH_Pos)
#define GPIO10_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO10_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO10          STRENGTH
 *  @access     PINMUX->GPIO10.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO10_ALL_STRENGTH_Pos (6)
#define GPIO10_ALL_STRENGTH_Msk (0x3UL << GPIO10_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO10_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO10_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO10_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO10_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO10_BIT_STRENGTH;

#define GPIO10_ALL_STRENGTH_5MA      ((0x0UL) << GPIO10_ALL_STRENGTH_Pos)
#define GPIO10_ALL_STRENGTH_10MA     ((0x1UL) << GPIO10_ALL_STRENGTH_Pos)
#define GPIO10_ALL_STRENGTH_15MA     ((0x2UL) << GPIO10_ALL_STRENGTH_Pos)
#define GPIO10_ALL_STRENGTH_20MA     ((0x3UL) << GPIO10_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO10          CHDFLTVAL
 *  @access     PINMUX->GPIO10.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO10_ALL_CHDFLTVAL_Pos (8)
#define GPIO10_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO10_ALL_CHDFLTVAL_Pos)

#define GPIO10_BIT_CHDFLTVAL

#define GPIO10_ALL_CHDFLTVAL_(x) ((x) << GPIO10_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO10          PD
 *  @access     PINMUX->GPIO10.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO10_ALL_PD_Pos (16)
#define GPIO10_ALL_PD_Msk (0xFFUL << GPIO10_ALL_PD_Pos)

#define GPIO10_BIT_PD

#define GPIO10_ALL_PD_(x) ((x) << GPIO10_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO10          PU
 *  @access     PINMUX->GPIO10.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO10_ALL_PU_Pos (24)
#define GPIO10_ALL_PU_Msk (0xFFUL << GPIO10_ALL_PU_Pos)

#define GPIO10_BIT_PU

#define GPIO10_ALL_PU_(x) ((x) << GPIO10_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO11          MUXSEL
 *  @access     PINMUX->GPIO11.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO11_ALL_MUXSEL_Pos (0)
#define GPIO11_ALL_MUXSEL_Msk (0x7UL << GPIO11_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO11_BIT_MUXSEL_GPIO11       = 0,  /*!< GPIO11                                 */
    GPIO11_BIT_MUXSEL_ADC11        = 1,  /*!< ADC11                                  */
    GPIO11_BIT_MUXSEL_SPI_MISO     = 2,  /*!< SPI_MISO                               */
    GPIO11_BIT_MUXSEL_SPI_MOSI     = 3,  /*!< SPI_MOSI                               */
    GPIO11_BIT_MUXSEL_DCLK         = 4,  /*!< DCLK output for monitoring             */
    GPIO11_BIT_MUXSEL_EPWRTZO      = 5,  /*!< Selectable EPWMTZ0 or EPWRTZ1 output   */
    GPIO11_BIT_MUXSEL_COMP4L       = 6,  /*!< COMP4L                                 */
    GPIO11_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO                                  */
} GPIO11_BIT_MUXSEL;

#define GPIO11_ALL_MUXSEL_GPIO11       ((0x0UL) << GPIO11_ALL_MUXSEL_Pos)
#define GPIO11_ALL_MUXSEL_ADC11        ((0x1UL) << GPIO11_ALL_MUXSEL_Pos)
#define GPIO11_ALL_MUXSEL_SPI_MISO     ((0x2UL) << GPIO11_ALL_MUXSEL_Pos)
#define GPIO11_ALL_MUXSEL_SPI_MOSI     ((0x3UL) << GPIO11_ALL_MUXSEL_Pos)
#define GPIO11_ALL_MUXSEL_DCLK         ((0x4UL) << GPIO11_ALL_MUXSEL_Pos)
#define GPIO11_ALL_MUXSEL_EPWRTZO      ((0x5UL) << GPIO11_ALL_MUXSEL_Pos)
#define GPIO11_ALL_MUXSEL_COMP4L       ((0x6UL) << GPIO11_ALL_MUXSEL_Pos)
#define GPIO11_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO11_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO11          IE
 *  @access     PINMUX->GPIO11.bit.IE
 *  @brief      Input enable
 */
#define GPIO11_ALL_IE_Pos (3)
#define GPIO11_ALL_IE_Msk (0x1UL << GPIO11_ALL_IE_Pos)

typedef enum
{
    GPIO11_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO11_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO11_BIT_IE;

#define GPIO11_ALL_IE_DISABLE     ((0x0UL) << GPIO11_ALL_IE_Pos)
#define GPIO11_ALL_IE_ENABLE      ((0x1UL) << GPIO11_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO11          SMT
 *  @access     PINMUX->GPIO11.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO11_ALL_SMT_Pos (4)
#define GPIO11_ALL_SMT_Msk (0x1UL << GPIO11_ALL_SMT_Pos)

typedef enum
{
    GPIO11_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO11_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO11_BIT_SMT;

#define GPIO11_ALL_SMT_NORMAL      ((0x0UL) << GPIO11_ALL_SMT_Pos)
#define GPIO11_ALL_SMT_SCHMITT     ((0x1UL) << GPIO11_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO11          DEGLITCH
 *  @access     PINMUX->GPIO11.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO11_ALL_DEGLITCH_Pos (5)
#define GPIO11_ALL_DEGLITCH_Msk (0x1UL << GPIO11_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO11_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO11_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO11_BIT_DEGLITCH;

#define GPIO11_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO11_ALL_DEGLITCH_Pos)
#define GPIO11_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO11_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO11          STRENGTH
 *  @access     PINMUX->GPIO11.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO11_ALL_STRENGTH_Pos (6)
#define GPIO11_ALL_STRENGTH_Msk (0x3UL << GPIO11_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO11_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO11_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO11_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO11_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO11_BIT_STRENGTH;

#define GPIO11_ALL_STRENGTH_5MA      ((0x0UL) << GPIO11_ALL_STRENGTH_Pos)
#define GPIO11_ALL_STRENGTH_10MA     ((0x1UL) << GPIO11_ALL_STRENGTH_Pos)
#define GPIO11_ALL_STRENGTH_15MA     ((0x2UL) << GPIO11_ALL_STRENGTH_Pos)
#define GPIO11_ALL_STRENGTH_20MA     ((0x3UL) << GPIO11_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO11          CHDFLTVAL
 *  @access     PINMUX->GPIO11.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO11_ALL_CHDFLTVAL_Pos (8)
#define GPIO11_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO11_ALL_CHDFLTVAL_Pos)

#define GPIO11_BIT_CHDFLTVAL

#define GPIO11_ALL_CHDFLTVAL_(x) ((x) << GPIO11_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO11          PD
 *  @access     PINMUX->GPIO11.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO11_ALL_PD_Pos (16)
#define GPIO11_ALL_PD_Msk (0xFFUL << GPIO11_ALL_PD_Pos)

#define GPIO11_BIT_PD

#define GPIO11_ALL_PD_(x) ((x) << GPIO11_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO11          PU
 *  @access     PINMUX->GPIO11.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO11_ALL_PU_Pos (24)
#define GPIO11_ALL_PU_Msk (0xFFUL << GPIO11_ALL_PU_Pos)

#define GPIO11_BIT_PU

#define GPIO11_ALL_PU_(x) ((x) << GPIO11_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO12          MUXSEL
 *  @access     PINMUX->GPIO12.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO12_ALL_MUXSEL_Pos (0)
#define GPIO12_ALL_MUXSEL_Msk (0x7UL << GPIO12_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO12_BIT_MUXSEL_GPIO12      = 0,  /*!< GPIO12    */
    GPIO12_BIT_MUXSEL_ADC12       = 1,  /*!< ADC12     */
    GPIO12_BIT_MUXSEL_I2C_SCL     = 2,  /*!< I2C_SCL   */
    GPIO12_BIT_MUXSEL_ECAPO       = 7,  /*!< ECAPO     */
} GPIO12_BIT_MUXSEL;

#define GPIO12_ALL_MUXSEL_GPIO12      ((0x0UL) << GPIO12_ALL_MUXSEL_Pos)
#define GPIO12_ALL_MUXSEL_ADC12       ((0x1UL) << GPIO12_ALL_MUXSEL_Pos)
#define GPIO12_ALL_MUXSEL_I2C_SCL     ((0x2UL) << GPIO12_ALL_MUXSEL_Pos)
#define GPIO12_ALL_MUXSEL_ECAPO       ((0x7UL) << GPIO12_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO12          IE
 *  @access     PINMUX->GPIO12.bit.IE
 *  @brief      Input enable
 */
#define GPIO12_ALL_IE_Pos (3)
#define GPIO12_ALL_IE_Msk (0x1UL << GPIO12_ALL_IE_Pos)

typedef enum
{
    GPIO12_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO12_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO12_BIT_IE;

#define GPIO12_ALL_IE_DISABLE     ((0x0UL) << GPIO12_ALL_IE_Pos)
#define GPIO12_ALL_IE_ENABLE      ((0x1UL) << GPIO12_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO12          SMT
 *  @access     PINMUX->GPIO12.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO12_ALL_SMT_Pos (4)
#define GPIO12_ALL_SMT_Msk (0x1UL << GPIO12_ALL_SMT_Pos)

typedef enum
{
    GPIO12_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO12_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO12_BIT_SMT;

#define GPIO12_ALL_SMT_NORMAL      ((0x0UL) << GPIO12_ALL_SMT_Pos)
#define GPIO12_ALL_SMT_SCHMITT     ((0x1UL) << GPIO12_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO12          DEGLITCH
 *  @access     PINMUX->GPIO12.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO12_ALL_DEGLITCH_Pos (5)
#define GPIO12_ALL_DEGLITCH_Msk (0x1UL << GPIO12_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO12_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO12_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO12_BIT_DEGLITCH;

#define GPIO12_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO12_ALL_DEGLITCH_Pos)
#define GPIO12_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO12_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO12          STRENGTH
 *  @access     PINMUX->GPIO12.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO12_ALL_STRENGTH_Pos (6)
#define GPIO12_ALL_STRENGTH_Msk (0x3UL << GPIO12_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO12_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO12_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO12_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO12_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO12_BIT_STRENGTH;

#define GPIO12_ALL_STRENGTH_5MA      ((0x0UL) << GPIO12_ALL_STRENGTH_Pos)
#define GPIO12_ALL_STRENGTH_10MA     ((0x1UL) << GPIO12_ALL_STRENGTH_Pos)
#define GPIO12_ALL_STRENGTH_15MA     ((0x2UL) << GPIO12_ALL_STRENGTH_Pos)
#define GPIO12_ALL_STRENGTH_20MA     ((0x3UL) << GPIO12_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO12          CHDFLTVAL
 *  @access     PINMUX->GPIO12.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO12_ALL_CHDFLTVAL_Pos (8)
#define GPIO12_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO12_ALL_CHDFLTVAL_Pos)

#define GPIO12_BIT_CHDFLTVAL

#define GPIO12_ALL_CHDFLTVAL_(x) ((x) << GPIO12_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO12          PD
 *  @access     PINMUX->GPIO12.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO12_ALL_PD_Pos (16)
#define GPIO12_ALL_PD_Msk (0xFFUL << GPIO12_ALL_PD_Pos)

#define GPIO12_BIT_PD

#define GPIO12_ALL_PD_(x) ((x) << GPIO12_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO12          PU
 *  @access     PINMUX->GPIO12.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO12_ALL_PU_Pos (24)
#define GPIO12_ALL_PU_Msk (0xFFUL << GPIO12_ALL_PU_Pos)

#define GPIO12_BIT_PU

#define GPIO12_ALL_PU_(x) ((x) << GPIO12_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO13          MUXSEL
 *  @access     PINMUX->GPIO13.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO13_ALL_MUXSEL_Pos (0)
#define GPIO13_ALL_MUXSEL_Msk (0x7UL << GPIO13_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO13_BIT_MUXSEL_GPIO13      = 0,  /*!< GPIO13    */
    GPIO13_BIT_MUXSEL_ADC13       = 1,  /*!< ADC13     */
    GPIO13_BIT_MUXSEL_I2C_SDA     = 2,  /*!< I2C_SDA   */
    GPIO13_BIT_MUXSEL_ECAPO       = 7,  /*!< ECAPO     */
} GPIO13_BIT_MUXSEL;

#define GPIO13_ALL_MUXSEL_GPIO13      ((0x0UL) << GPIO13_ALL_MUXSEL_Pos)
#define GPIO13_ALL_MUXSEL_ADC13       ((0x1UL) << GPIO13_ALL_MUXSEL_Pos)
#define GPIO13_ALL_MUXSEL_I2C_SDA     ((0x2UL) << GPIO13_ALL_MUXSEL_Pos)
#define GPIO13_ALL_MUXSEL_ECAPO       ((0x7UL) << GPIO13_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO13          IE
 *  @access     PINMUX->GPIO13.bit.IE
 *  @brief      Input enable
 */
#define GPIO13_ALL_IE_Pos (3)
#define GPIO13_ALL_IE_Msk (0x1UL << GPIO13_ALL_IE_Pos)

typedef enum
{
    GPIO13_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO13_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO13_BIT_IE;

#define GPIO13_ALL_IE_DISABLE     ((0x0UL) << GPIO13_ALL_IE_Pos)
#define GPIO13_ALL_IE_ENABLE      ((0x1UL) << GPIO13_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO13          SMT
 *  @access     PINMUX->GPIO13.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO13_ALL_SMT_Pos (4)
#define GPIO13_ALL_SMT_Msk (0x1UL << GPIO13_ALL_SMT_Pos)

typedef enum
{
    GPIO13_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO13_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO13_BIT_SMT;

#define GPIO13_ALL_SMT_NORMAL      ((0x0UL) << GPIO13_ALL_SMT_Pos)
#define GPIO13_ALL_SMT_SCHMITT     ((0x1UL) << GPIO13_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO13          DEGLITCH
 *  @access     PINMUX->GPIO13.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO13_ALL_DEGLITCH_Pos (5)
#define GPIO13_ALL_DEGLITCH_Msk (0x1UL << GPIO13_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO13_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO13_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO13_BIT_DEGLITCH;

#define GPIO13_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO13_ALL_DEGLITCH_Pos)
#define GPIO13_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO13_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO13          STRENGTH
 *  @access     PINMUX->GPIO13.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO13_ALL_STRENGTH_Pos (6)
#define GPIO13_ALL_STRENGTH_Msk (0x3UL << GPIO13_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO13_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO13_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO13_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO13_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO13_BIT_STRENGTH;

#define GPIO13_ALL_STRENGTH_5MA      ((0x0UL) << GPIO13_ALL_STRENGTH_Pos)
#define GPIO13_ALL_STRENGTH_10MA     ((0x1UL) << GPIO13_ALL_STRENGTH_Pos)
#define GPIO13_ALL_STRENGTH_15MA     ((0x2UL) << GPIO13_ALL_STRENGTH_Pos)
#define GPIO13_ALL_STRENGTH_20MA     ((0x3UL) << GPIO13_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO13          CHDFLTVAL
 *  @access     PINMUX->GPIO13.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO13_ALL_CHDFLTVAL_Pos (8)
#define GPIO13_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO13_ALL_CHDFLTVAL_Pos)

#define GPIO13_BIT_CHDFLTVAL

#define GPIO13_ALL_CHDFLTVAL_(x) ((x) << GPIO13_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO13          PD
 *  @access     PINMUX->GPIO13.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO13_ALL_PD_Pos (16)
#define GPIO13_ALL_PD_Msk (0xFFUL << GPIO13_ALL_PD_Pos)

#define GPIO13_BIT_PD

#define GPIO13_ALL_PD_(x) ((x) << GPIO13_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO13          PU
 *  @access     PINMUX->GPIO13.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO13_ALL_PU_Pos (24)
#define GPIO13_ALL_PU_Msk (0xFFUL << GPIO13_ALL_PU_Pos)

#define GPIO13_BIT_PU

#define GPIO13_ALL_PU_(x) ((x) << GPIO13_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO14          MUXSEL
 *  @access     PINMUX->GPIO14.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO14_ALL_MUXSEL_Pos (0)
#define GPIO14_ALL_MUXSEL_Msk (0x7UL << GPIO14_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO14_BIT_MUXSEL_GPIO14       = 0,  /*!< GPIO14     */
    GPIO14_BIT_MUXSEL_ADC14        = 1,  /*!< ADC14      */
    GPIO14_BIT_MUXSEL_UART_TXD     = 2,  /*!< UART_TXD   */
    GPIO14_BIT_MUXSEL_UART_RXD     = 3,  /*!< UART_RXD   */
    GPIO14_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO14_BIT_MUXSEL;

#define GPIO14_ALL_MUXSEL_GPIO14       ((0x0UL) << GPIO14_ALL_MUXSEL_Pos)
#define GPIO14_ALL_MUXSEL_ADC14        ((0x1UL) << GPIO14_ALL_MUXSEL_Pos)
#define GPIO14_ALL_MUXSEL_UART_TXD     ((0x2UL) << GPIO14_ALL_MUXSEL_Pos)
#define GPIO14_ALL_MUXSEL_UART_RXD     ((0x3UL) << GPIO14_ALL_MUXSEL_Pos)
#define GPIO14_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO14_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO14          IE
 *  @access     PINMUX->GPIO14.bit.IE
 *  @brief      Input enable
 */
#define GPIO14_ALL_IE_Pos (3)
#define GPIO14_ALL_IE_Msk (0x1UL << GPIO14_ALL_IE_Pos)

typedef enum
{
    GPIO14_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO14_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO14_BIT_IE;

#define GPIO14_ALL_IE_DISABLE     ((0x0UL) << GPIO14_ALL_IE_Pos)
#define GPIO14_ALL_IE_ENABLE      ((0x1UL) << GPIO14_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO14          SMT
 *  @access     PINMUX->GPIO14.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO14_ALL_SMT_Pos (4)
#define GPIO14_ALL_SMT_Msk (0x1UL << GPIO14_ALL_SMT_Pos)

typedef enum
{
    GPIO14_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO14_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO14_BIT_SMT;

#define GPIO14_ALL_SMT_NORMAL      ((0x0UL) << GPIO14_ALL_SMT_Pos)
#define GPIO14_ALL_SMT_SCHMITT     ((0x1UL) << GPIO14_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO14          DEGLITCH
 *  @access     PINMUX->GPIO14.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO14_ALL_DEGLITCH_Pos (5)
#define GPIO14_ALL_DEGLITCH_Msk (0x1UL << GPIO14_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO14_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO14_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO14_BIT_DEGLITCH;

#define GPIO14_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO14_ALL_DEGLITCH_Pos)
#define GPIO14_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO14_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO14          STRENGTH
 *  @access     PINMUX->GPIO14.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO14_ALL_STRENGTH_Pos (6)
#define GPIO14_ALL_STRENGTH_Msk (0x3UL << GPIO14_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO14_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO14_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO14_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO14_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO14_BIT_STRENGTH;

#define GPIO14_ALL_STRENGTH_5MA      ((0x0UL) << GPIO14_ALL_STRENGTH_Pos)
#define GPIO14_ALL_STRENGTH_10MA     ((0x1UL) << GPIO14_ALL_STRENGTH_Pos)
#define GPIO14_ALL_STRENGTH_15MA     ((0x2UL) << GPIO14_ALL_STRENGTH_Pos)
#define GPIO14_ALL_STRENGTH_20MA     ((0x3UL) << GPIO14_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO14          CHDFLTVAL
 *  @access     PINMUX->GPIO14.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO14_ALL_CHDFLTVAL_Pos (8)
#define GPIO14_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO14_ALL_CHDFLTVAL_Pos)

#define GPIO14_BIT_CHDFLTVAL

#define GPIO14_ALL_CHDFLTVAL_(x) ((x) << GPIO14_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO14          PD
 *  @access     PINMUX->GPIO14.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO14_ALL_PD_Pos (16)
#define GPIO14_ALL_PD_Msk (0xFFUL << GPIO14_ALL_PD_Pos)

#define GPIO14_BIT_PD

#define GPIO14_ALL_PD_(x) ((x) << GPIO14_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO14          PU
 *  @access     PINMUX->GPIO14.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO14_ALL_PU_Pos (24)
#define GPIO14_ALL_PU_Msk (0xFFUL << GPIO14_ALL_PU_Pos)

#define GPIO14_BIT_PU

#define GPIO14_ALL_PU_(x) ((x) << GPIO14_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO15          MUXSEL
 *  @access     PINMUX->GPIO15.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO15_ALL_MUXSEL_Pos (0)
#define GPIO15_ALL_MUXSEL_Msk (0x7UL << GPIO15_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO15_BIT_MUXSEL_GPIO15       = 0,  /*!< GPIO15     */
    GPIO15_BIT_MUXSEL_ADC15        = 1,  /*!< ADC15      */
    GPIO15_BIT_MUXSEL_UART_RXD     = 2,  /*!< UART_RXD   */
    GPIO15_BIT_MUXSEL_UART_TXD     = 3,  /*!< UART_TXD   */
    GPIO15_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO15_BIT_MUXSEL;

#define GPIO15_ALL_MUXSEL_GPIO15       ((0x0UL) << GPIO15_ALL_MUXSEL_Pos)
#define GPIO15_ALL_MUXSEL_ADC15        ((0x1UL) << GPIO15_ALL_MUXSEL_Pos)
#define GPIO15_ALL_MUXSEL_UART_RXD     ((0x2UL) << GPIO15_ALL_MUXSEL_Pos)
#define GPIO15_ALL_MUXSEL_UART_TXD     ((0x3UL) << GPIO15_ALL_MUXSEL_Pos)
#define GPIO15_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO15_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO15          IE
 *  @access     PINMUX->GPIO15.bit.IE
 *  @brief      Input enable
 */
#define GPIO15_ALL_IE_Pos (3)
#define GPIO15_ALL_IE_Msk (0x1UL << GPIO15_ALL_IE_Pos)

typedef enum
{
    GPIO15_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO15_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO15_BIT_IE;

#define GPIO15_ALL_IE_DISABLE     ((0x0UL) << GPIO15_ALL_IE_Pos)
#define GPIO15_ALL_IE_ENABLE      ((0x1UL) << GPIO15_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO15          SMT
 *  @access     PINMUX->GPIO15.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO15_ALL_SMT_Pos (4)
#define GPIO15_ALL_SMT_Msk (0x1UL << GPIO15_ALL_SMT_Pos)

typedef enum
{
    GPIO15_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO15_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO15_BIT_SMT;

#define GPIO15_ALL_SMT_NORMAL      ((0x0UL) << GPIO15_ALL_SMT_Pos)
#define GPIO15_ALL_SMT_SCHMITT     ((0x1UL) << GPIO15_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO15          DEGLITCH
 *  @access     PINMUX->GPIO15.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO15_ALL_DEGLITCH_Pos (5)
#define GPIO15_ALL_DEGLITCH_Msk (0x1UL << GPIO15_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO15_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO15_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO15_BIT_DEGLITCH;

#define GPIO15_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO15_ALL_DEGLITCH_Pos)
#define GPIO15_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO15_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO15          STRENGTH
 *  @access     PINMUX->GPIO15.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO15_ALL_STRENGTH_Pos (6)
#define GPIO15_ALL_STRENGTH_Msk (0x3UL << GPIO15_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO15_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO15_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO15_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO15_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO15_BIT_STRENGTH;

#define GPIO15_ALL_STRENGTH_5MA      ((0x0UL) << GPIO15_ALL_STRENGTH_Pos)
#define GPIO15_ALL_STRENGTH_10MA     ((0x1UL) << GPIO15_ALL_STRENGTH_Pos)
#define GPIO15_ALL_STRENGTH_15MA     ((0x2UL) << GPIO15_ALL_STRENGTH_Pos)
#define GPIO15_ALL_STRENGTH_20MA     ((0x3UL) << GPIO15_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO15          CHDFLTVAL
 *  @access     PINMUX->GPIO15.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO15_ALL_CHDFLTVAL_Pos (8)
#define GPIO15_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO15_ALL_CHDFLTVAL_Pos)

#define GPIO15_BIT_CHDFLTVAL

#define GPIO15_ALL_CHDFLTVAL_(x) ((x) << GPIO15_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO15          PD
 *  @access     PINMUX->GPIO15.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO15_ALL_PD_Pos (16)
#define GPIO15_ALL_PD_Msk (0xFFUL << GPIO15_ALL_PD_Pos)

#define GPIO15_BIT_PD

#define GPIO15_ALL_PD_(x) ((x) << GPIO15_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO15          PU
 *  @access     PINMUX->GPIO15.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO15_ALL_PU_Pos (24)
#define GPIO15_ALL_PU_Msk (0xFFUL << GPIO15_ALL_PU_Pos)

#define GPIO15_BIT_PU

#define GPIO15_ALL_PU_(x) ((x) << GPIO15_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO16          MUXSEL
 *  @access     PINMUX->GPIO16.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO16_ALL_MUXSEL_Pos (0)
#define GPIO16_ALL_MUXSEL_Msk (0x7UL << GPIO16_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO16_BIT_MUXSEL_GPIO16       = 0,  /*!< GPIO16     */
    GPIO16_BIT_MUXSEL_XIN          = 1,  /*!< XIN        */
    GPIO16_BIT_MUXSEL_UART_TXD     = 2,  /*!< UART_TXD   */
    GPIO16_BIT_MUXSEL_UART_RXD     = 3,  /*!< UART_RXD   */
    GPIO16_BIT_MUXSEL_PWM2A        = 4,  /*!< PWM2A      */
    GPIO16_BIT_MUXSEL_PWM5A        = 5,  /*!< PWM5A      */
    GPIO16_BIT_MUXSEL_SIO12        = 6,  /*!< SIO12      */
    GPIO16_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO16_BIT_MUXSEL;

#define GPIO16_ALL_MUXSEL_GPIO16       ((0x0UL) << GPIO16_ALL_MUXSEL_Pos)
#define GPIO16_ALL_MUXSEL_XIN          ((0x1UL) << GPIO16_ALL_MUXSEL_Pos)
#define GPIO16_ALL_MUXSEL_UART_TXD     ((0x2UL) << GPIO16_ALL_MUXSEL_Pos)
#define GPIO16_ALL_MUXSEL_UART_RXD     ((0x3UL) << GPIO16_ALL_MUXSEL_Pos)
#define GPIO16_ALL_MUXSEL_PWM2A        ((0x4UL) << GPIO16_ALL_MUXSEL_Pos)
#define GPIO16_ALL_MUXSEL_PWM5A        ((0x5UL) << GPIO16_ALL_MUXSEL_Pos)
#define GPIO16_ALL_MUXSEL_SIO12        ((0x6UL) << GPIO16_ALL_MUXSEL_Pos)
#define GPIO16_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO16_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO16          IE
 *  @access     PINMUX->GPIO16.bit.IE
 *  @brief      Input enable
 */
#define GPIO16_ALL_IE_Pos (3)
#define GPIO16_ALL_IE_Msk (0x1UL << GPIO16_ALL_IE_Pos)

typedef enum
{
    GPIO16_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO16_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO16_BIT_IE;

#define GPIO16_ALL_IE_DISABLE     ((0x0UL) << GPIO16_ALL_IE_Pos)
#define GPIO16_ALL_IE_ENABLE      ((0x1UL) << GPIO16_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO16          SMT
 *  @access     PINMUX->GPIO16.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO16_ALL_SMT_Pos (4)
#define GPIO16_ALL_SMT_Msk (0x1UL << GPIO16_ALL_SMT_Pos)

typedef enum
{
    GPIO16_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO16_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO16_BIT_SMT;

#define GPIO16_ALL_SMT_NORMAL      ((0x0UL) << GPIO16_ALL_SMT_Pos)
#define GPIO16_ALL_SMT_SCHMITT     ((0x1UL) << GPIO16_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO16          DEGLITCH
 *  @access     PINMUX->GPIO16.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO16_ALL_DEGLITCH_Pos (5)
#define GPIO16_ALL_DEGLITCH_Msk (0x1UL << GPIO16_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO16_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO16_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO16_BIT_DEGLITCH;

#define GPIO16_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO16_ALL_DEGLITCH_Pos)
#define GPIO16_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO16_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO16          STRENGTH
 *  @access     PINMUX->GPIO16.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO16_ALL_STRENGTH_Pos (6)
#define GPIO16_ALL_STRENGTH_Msk (0x3UL << GPIO16_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO16_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO16_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO16_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO16_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO16_BIT_STRENGTH;

#define GPIO16_ALL_STRENGTH_5MA      ((0x0UL) << GPIO16_ALL_STRENGTH_Pos)
#define GPIO16_ALL_STRENGTH_10MA     ((0x1UL) << GPIO16_ALL_STRENGTH_Pos)
#define GPIO16_ALL_STRENGTH_15MA     ((0x2UL) << GPIO16_ALL_STRENGTH_Pos)
#define GPIO16_ALL_STRENGTH_20MA     ((0x3UL) << GPIO16_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO16          CHDFLTVAL
 *  @access     PINMUX->GPIO16.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO16_ALL_CHDFLTVAL_Pos (8)
#define GPIO16_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO16_ALL_CHDFLTVAL_Pos)

#define GPIO16_BIT_CHDFLTVAL

#define GPIO16_ALL_CHDFLTVAL_(x) ((x) << GPIO16_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO16          PD
 *  @access     PINMUX->GPIO16.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO16_ALL_PD_Pos (16)
#define GPIO16_ALL_PD_Msk (0xFFUL << GPIO16_ALL_PD_Pos)

#define GPIO16_BIT_PD

#define GPIO16_ALL_PD_(x) ((x) << GPIO16_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO16          PU
 *  @access     PINMUX->GPIO16.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO16_ALL_PU_Pos (24)
#define GPIO16_ALL_PU_Msk (0xFFUL << GPIO16_ALL_PU_Pos)

#define GPIO16_BIT_PU

#define GPIO16_ALL_PU_(x) ((x) << GPIO16_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO17          MUXSEL
 *  @access     PINMUX->GPIO17.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO17_ALL_MUXSEL_Pos (0)
#define GPIO17_ALL_MUXSEL_Msk (0x7UL << GPIO17_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO17_BIT_MUXSEL_GPIO17       = 0,  /*!< GPIO17     */
    GPIO17_BIT_MUXSEL_XIO          = 1,  /*!< XIO        */
    GPIO17_BIT_MUXSEL_UART_RXD     = 2,  /*!< UART_RXD   */
    GPIO17_BIT_MUXSEL_UART_TXD     = 3,  /*!< UART_TXD   */
    GPIO17_BIT_MUXSEL_PWM2B        = 4,  /*!< PWM2B      */
    GPIO17_BIT_MUXSEL_PWM5B        = 5,  /*!< PWM5B      */
    GPIO17_BIT_MUXSEL_SIO13        = 6,  /*!< SIO13      */
    GPIO17_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO17_BIT_MUXSEL;

#define GPIO17_ALL_MUXSEL_GPIO17       ((0x0UL) << GPIO17_ALL_MUXSEL_Pos)
#define GPIO17_ALL_MUXSEL_XIO          ((0x1UL) << GPIO17_ALL_MUXSEL_Pos)
#define GPIO17_ALL_MUXSEL_UART_RXD     ((0x2UL) << GPIO17_ALL_MUXSEL_Pos)
#define GPIO17_ALL_MUXSEL_UART_TXD     ((0x3UL) << GPIO17_ALL_MUXSEL_Pos)
#define GPIO17_ALL_MUXSEL_PWM2B        ((0x4UL) << GPIO17_ALL_MUXSEL_Pos)
#define GPIO17_ALL_MUXSEL_PWM5B        ((0x5UL) << GPIO17_ALL_MUXSEL_Pos)
#define GPIO17_ALL_MUXSEL_SIO13        ((0x6UL) << GPIO17_ALL_MUXSEL_Pos)
#define GPIO17_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO17_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO17          IE
 *  @access     PINMUX->GPIO17.bit.IE
 *  @brief      Input enable
 */
#define GPIO17_ALL_IE_Pos (3)
#define GPIO17_ALL_IE_Msk (0x1UL << GPIO17_ALL_IE_Pos)

typedef enum
{
    GPIO17_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO17_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO17_BIT_IE;

#define GPIO17_ALL_IE_DISABLE     ((0x0UL) << GPIO17_ALL_IE_Pos)
#define GPIO17_ALL_IE_ENABLE      ((0x1UL) << GPIO17_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO17          SMT
 *  @access     PINMUX->GPIO17.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO17_ALL_SMT_Pos (4)
#define GPIO17_ALL_SMT_Msk (0x1UL << GPIO17_ALL_SMT_Pos)

typedef enum
{
    GPIO17_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO17_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO17_BIT_SMT;

#define GPIO17_ALL_SMT_NORMAL      ((0x0UL) << GPIO17_ALL_SMT_Pos)
#define GPIO17_ALL_SMT_SCHMITT     ((0x1UL) << GPIO17_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO17          DEGLITCH
 *  @access     PINMUX->GPIO17.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO17_ALL_DEGLITCH_Pos (5)
#define GPIO17_ALL_DEGLITCH_Msk (0x1UL << GPIO17_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO17_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO17_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO17_BIT_DEGLITCH;

#define GPIO17_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO17_ALL_DEGLITCH_Pos)
#define GPIO17_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO17_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO17          STRENGTH
 *  @access     PINMUX->GPIO17.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO17_ALL_STRENGTH_Pos (6)
#define GPIO17_ALL_STRENGTH_Msk (0x3UL << GPIO17_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO17_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO17_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO17_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO17_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO17_BIT_STRENGTH;

#define GPIO17_ALL_STRENGTH_5MA      ((0x0UL) << GPIO17_ALL_STRENGTH_Pos)
#define GPIO17_ALL_STRENGTH_10MA     ((0x1UL) << GPIO17_ALL_STRENGTH_Pos)
#define GPIO17_ALL_STRENGTH_15MA     ((0x2UL) << GPIO17_ALL_STRENGTH_Pos)
#define GPIO17_ALL_STRENGTH_20MA     ((0x3UL) << GPIO17_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO17          CHDFLTVAL
 *  @access     PINMUX->GPIO17.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO17_ALL_CHDFLTVAL_Pos (8)
#define GPIO17_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO17_ALL_CHDFLTVAL_Pos)

#define GPIO17_BIT_CHDFLTVAL

#define GPIO17_ALL_CHDFLTVAL_(x) ((x) << GPIO17_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO17          PD
 *  @access     PINMUX->GPIO17.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO17_ALL_PD_Pos (16)
#define GPIO17_ALL_PD_Msk (0xFFUL << GPIO17_ALL_PD_Pos)

#define GPIO17_BIT_PD

#define GPIO17_ALL_PD_(x) ((x) << GPIO17_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO17          PU
 *  @access     PINMUX->GPIO17.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO17_ALL_PU_Pos (24)
#define GPIO17_ALL_PU_Msk (0xFFUL << GPIO17_ALL_PU_Pos)

#define GPIO17_BIT_PU

#define GPIO17_ALL_PU_(x) ((x) << GPIO17_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO18          MUXSEL
 *  @access     PINMUX->GPIO18.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO18_ALL_MUXSEL_Pos (0)
#define GPIO18_ALL_MUXSEL_Msk (0x7UL << GPIO18_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO18_BIT_MUXSEL_GPIO18     = 0,  /*!< GPIO18   */
    GPIO18_BIT_MUXSEL_PWM3A      = 1,  /*!< PWM3A    */
    // GPIO18_BIT_MUXSEL_PWM3A   = 2,  /*!< PWM3A    */
    GPIO18_BIT_MUXSEL_COMP3H     = 3,  /*!< COMP3H   */
    GPIO18_BIT_MUXSEL_PWM0A      = 4,  /*!< PWM0A    */
    // GPIO18_BIT_MUXSEL_PWM0A   = 5,  /*!< PWM0A    */
    GPIO18_BIT_MUXSEL_SIO14      = 6,  /*!< SIO14    */
    GPIO18_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO18_BIT_MUXSEL;

#define GPIO18_ALL_MUXSEL_GPIO18     ((0x0UL) << GPIO18_ALL_MUXSEL_Pos)
#define GPIO18_ALL_MUXSEL_PWM3A      ((0x1UL) << GPIO18_ALL_MUXSEL_Pos)
// #define GPIO18_ALL_MUXSEL_PWM3A      ((0x2UL) << GPIO18_ALL_MUXSEL_Pos)
#define GPIO18_ALL_MUXSEL_COMP3H     ((0x3UL) << GPIO18_ALL_MUXSEL_Pos)
#define GPIO18_ALL_MUXSEL_PWM0A      ((0x4UL) << GPIO18_ALL_MUXSEL_Pos)
// #define GPIO18_ALL_MUXSEL_PWM0A      ((0x5UL) << GPIO18_ALL_MUXSEL_Pos)
#define GPIO18_ALL_MUXSEL_SIO14      ((0x6UL) << GPIO18_ALL_MUXSEL_Pos)
#define GPIO18_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO18_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO18          IE
 *  @access     PINMUX->GPIO18.bit.IE
 *  @brief      Input enable
 */
#define GPIO18_ALL_IE_Pos (3)
#define GPIO18_ALL_IE_Msk (0x1UL << GPIO18_ALL_IE_Pos)

typedef enum
{
    GPIO18_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO18_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO18_BIT_IE;

#define GPIO18_ALL_IE_DISABLE     ((0x0UL) << GPIO18_ALL_IE_Pos)
#define GPIO18_ALL_IE_ENABLE      ((0x1UL) << GPIO18_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO18          SMT
 *  @access     PINMUX->GPIO18.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO18_ALL_SMT_Pos (4)
#define GPIO18_ALL_SMT_Msk (0x1UL << GPIO18_ALL_SMT_Pos)

typedef enum
{
    GPIO18_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO18_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO18_BIT_SMT;

#define GPIO18_ALL_SMT_NORMAL      ((0x0UL) << GPIO18_ALL_SMT_Pos)
#define GPIO18_ALL_SMT_SCHMITT     ((0x1UL) << GPIO18_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO18          DEGLITCH
 *  @access     PINMUX->GPIO18.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO18_ALL_DEGLITCH_Pos (5)
#define GPIO18_ALL_DEGLITCH_Msk (0x1UL << GPIO18_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO18_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO18_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO18_BIT_DEGLITCH;

#define GPIO18_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO18_ALL_DEGLITCH_Pos)
#define GPIO18_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO18_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO18          STRENGTH
 *  @access     PINMUX->GPIO18.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO18_ALL_STRENGTH_Pos (6)
#define GPIO18_ALL_STRENGTH_Msk (0x3UL << GPIO18_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO18_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO18_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO18_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO18_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO18_BIT_STRENGTH;

#define GPIO18_ALL_STRENGTH_5MA      ((0x0UL) << GPIO18_ALL_STRENGTH_Pos)
#define GPIO18_ALL_STRENGTH_10MA     ((0x1UL) << GPIO18_ALL_STRENGTH_Pos)
#define GPIO18_ALL_STRENGTH_15MA     ((0x2UL) << GPIO18_ALL_STRENGTH_Pos)
#define GPIO18_ALL_STRENGTH_20MA     ((0x3UL) << GPIO18_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO18          CHDFLTVAL
 *  @access     PINMUX->GPIO18.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO18_ALL_CHDFLTVAL_Pos (8)
#define GPIO18_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO18_ALL_CHDFLTVAL_Pos)

#define GPIO18_BIT_CHDFLTVAL

#define GPIO18_ALL_CHDFLTVAL_(x) ((x) << GPIO18_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO18          PD
 *  @access     PINMUX->GPIO18.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO18_ALL_PD_Pos (16)
#define GPIO18_ALL_PD_Msk (0xFFUL << GPIO18_ALL_PD_Pos)

#define GPIO18_BIT_PD

#define GPIO18_ALL_PD_(x) ((x) << GPIO18_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO18          PU
 *  @access     PINMUX->GPIO18.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO18_ALL_PU_Pos (24)
#define GPIO18_ALL_PU_Msk (0xFFUL << GPIO18_ALL_PU_Pos)

#define GPIO18_BIT_PU

#define GPIO18_ALL_PU_(x) ((x) << GPIO18_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO19          MUXSEL
 *  @access     PINMUX->GPIO19.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO19_ALL_MUXSEL_Pos (0)
#define GPIO19_ALL_MUXSEL_Msk (0x7UL << GPIO19_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO19_BIT_MUXSEL_GPIO19     = 0,  /*!< GPIO19   */
    GPIO19_BIT_MUXSEL_PWM4A      = 1,  /*!< PWM4A    */
    GPIO19_BIT_MUXSEL_PWM3B      = 2,  /*!< PWM3B    */
    GPIO19_BIT_MUXSEL_COMP3L     = 3,  /*!< COMP3L   */
    GPIO19_BIT_MUXSEL_PWM1A      = 4,  /*!< PWM1A    */
    GPIO19_BIT_MUXSEL_PWM0B      = 5,  /*!< PWM0B    */
    GPIO19_BIT_MUXSEL_SIO15      = 6,  /*!< SIO15    */
    GPIO19_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO19_BIT_MUXSEL;

#define GPIO19_ALL_MUXSEL_GPIO19     ((0x0UL) << GPIO19_ALL_MUXSEL_Pos)
#define GPIO19_ALL_MUXSEL_PWM4A      ((0x1UL) << GPIO19_ALL_MUXSEL_Pos)
#define GPIO19_ALL_MUXSEL_PWM3B      ((0x2UL) << GPIO19_ALL_MUXSEL_Pos)
#define GPIO19_ALL_MUXSEL_COMP3L     ((0x3UL) << GPIO19_ALL_MUXSEL_Pos)
#define GPIO19_ALL_MUXSEL_PWM1A      ((0x4UL) << GPIO19_ALL_MUXSEL_Pos)
#define GPIO19_ALL_MUXSEL_PWM0B      ((0x5UL) << GPIO19_ALL_MUXSEL_Pos)
#define GPIO19_ALL_MUXSEL_SIO15      ((0x6UL) << GPIO19_ALL_MUXSEL_Pos)
#define GPIO19_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO19_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO19          IE
 *  @access     PINMUX->GPIO19.bit.IE
 *  @brief      Input enable
 */
#define GPIO19_ALL_IE_Pos (3)
#define GPIO19_ALL_IE_Msk (0x1UL << GPIO19_ALL_IE_Pos)

typedef enum
{
    GPIO19_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO19_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO19_BIT_IE;

#define GPIO19_ALL_IE_DISABLE     ((0x0UL) << GPIO19_ALL_IE_Pos)
#define GPIO19_ALL_IE_ENABLE      ((0x1UL) << GPIO19_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO19          SMT
 *  @access     PINMUX->GPIO19.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO19_ALL_SMT_Pos (4)
#define GPIO19_ALL_SMT_Msk (0x1UL << GPIO19_ALL_SMT_Pos)

typedef enum
{
    GPIO19_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO19_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO19_BIT_SMT;

#define GPIO19_ALL_SMT_NORMAL      ((0x0UL) << GPIO19_ALL_SMT_Pos)
#define GPIO19_ALL_SMT_SCHMITT     ((0x1UL) << GPIO19_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO19          DEGLITCH
 *  @access     PINMUX->GPIO19.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO19_ALL_DEGLITCH_Pos (5)
#define GPIO19_ALL_DEGLITCH_Msk (0x1UL << GPIO19_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO19_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO19_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO19_BIT_DEGLITCH;

#define GPIO19_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO19_ALL_DEGLITCH_Pos)
#define GPIO19_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO19_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO19          STRENGTH
 *  @access     PINMUX->GPIO19.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO19_ALL_STRENGTH_Pos (6)
#define GPIO19_ALL_STRENGTH_Msk (0x3UL << GPIO19_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO19_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO19_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO19_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO19_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO19_BIT_STRENGTH;

#define GPIO19_ALL_STRENGTH_5MA      ((0x0UL) << GPIO19_ALL_STRENGTH_Pos)
#define GPIO19_ALL_STRENGTH_10MA     ((0x1UL) << GPIO19_ALL_STRENGTH_Pos)
#define GPIO19_ALL_STRENGTH_15MA     ((0x2UL) << GPIO19_ALL_STRENGTH_Pos)
#define GPIO19_ALL_STRENGTH_20MA     ((0x3UL) << GPIO19_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO19          CHDFLTVAL
 *  @access     PINMUX->GPIO19.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO19_ALL_CHDFLTVAL_Pos (8)
#define GPIO19_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO19_ALL_CHDFLTVAL_Pos)

#define GPIO19_BIT_CHDFLTVAL

#define GPIO19_ALL_CHDFLTVAL_(x) ((x) << GPIO19_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO19          PD
 *  @access     PINMUX->GPIO19.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO19_ALL_PD_Pos (16)
#define GPIO19_ALL_PD_Msk (0xFFUL << GPIO19_ALL_PD_Pos)

#define GPIO19_BIT_PD

#define GPIO19_ALL_PD_(x) ((x) << GPIO19_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO19          PU
 *  @access     PINMUX->GPIO19.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO19_ALL_PU_Pos (24)
#define GPIO19_ALL_PU_Msk (0xFFUL << GPIO19_ALL_PU_Pos)

#define GPIO19_BIT_PU

#define GPIO19_ALL_PU_(x) ((x) << GPIO19_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO20          MUXSEL
 *  @access     PINMUX->GPIO20.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO20_ALL_MUXSEL_Pos (0)
#define GPIO20_ALL_MUXSEL_Msk (0x7UL << GPIO20_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO20_BIT_MUXSEL_GPIO20     = 0,  /*!< GPIO20   */
    GPIO20_BIT_MUXSEL_COMP4H     = 3,  /*!< COMP4H   */
    GPIO20_BIT_MUXSEL_PWM2A      = 4,  /*!< PWM2A    */
    GPIO20_BIT_MUXSEL_PWM1A      = 5,  /*!< PWM1A    */
    GPIO20_BIT_MUXSEL_SIO16      = 6,  /*!< SIO16    */
    GPIO20_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO20_BIT_MUXSEL;

#define GPIO20_ALL_MUXSEL_GPIO20     ((0x0UL) << GPIO20_ALL_MUXSEL_Pos)
#define GPIO20_ALL_MUXSEL_COMP4H     ((0x3UL) << GPIO20_ALL_MUXSEL_Pos)
#define GPIO20_ALL_MUXSEL_PWM2A      ((0x4UL) << GPIO20_ALL_MUXSEL_Pos)
#define GPIO20_ALL_MUXSEL_PWM1A      ((0x5UL) << GPIO20_ALL_MUXSEL_Pos)
#define GPIO20_ALL_MUXSEL_SIO16      ((0x6UL) << GPIO20_ALL_MUXSEL_Pos)
#define GPIO20_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO20_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO20          IE
 *  @access     PINMUX->GPIO20.bit.IE
 *  @brief      Input enable
 */
#define GPIO20_ALL_IE_Pos (3)
#define GPIO20_ALL_IE_Msk (0x1UL << GPIO20_ALL_IE_Pos)

typedef enum
{
    GPIO20_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO20_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO20_BIT_IE;

#define GPIO20_ALL_IE_DISABLE     ((0x0UL) << GPIO20_ALL_IE_Pos)
#define GPIO20_ALL_IE_ENABLE      ((0x1UL) << GPIO20_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO20          SMT
 *  @access     PINMUX->GPIO20.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO20_ALL_SMT_Pos (4)
#define GPIO20_ALL_SMT_Msk (0x1UL << GPIO20_ALL_SMT_Pos)

typedef enum
{
    GPIO20_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO20_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO20_BIT_SMT;

#define GPIO20_ALL_SMT_NORMAL      ((0x0UL) << GPIO20_ALL_SMT_Pos)
#define GPIO20_ALL_SMT_SCHMITT     ((0x1UL) << GPIO20_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO20          DEGLITCH
 *  @access     PINMUX->GPIO20.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO20_ALL_DEGLITCH_Pos (5)
#define GPIO20_ALL_DEGLITCH_Msk (0x1UL << GPIO20_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO20_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO20_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO20_BIT_DEGLITCH;

#define GPIO20_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO20_ALL_DEGLITCH_Pos)
#define GPIO20_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO20_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO20          STRENGTH
 *  @access     PINMUX->GPIO20.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO20_ALL_STRENGTH_Pos (6)
#define GPIO20_ALL_STRENGTH_Msk (0x3UL << GPIO20_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO20_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO20_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO20_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO20_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO20_BIT_STRENGTH;

#define GPIO20_ALL_STRENGTH_5MA      ((0x0UL) << GPIO20_ALL_STRENGTH_Pos)
#define GPIO20_ALL_STRENGTH_10MA     ((0x1UL) << GPIO20_ALL_STRENGTH_Pos)
#define GPIO20_ALL_STRENGTH_15MA     ((0x2UL) << GPIO20_ALL_STRENGTH_Pos)
#define GPIO20_ALL_STRENGTH_20MA     ((0x3UL) << GPIO20_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO20          CHDFLTVAL
 *  @access     PINMUX->GPIO20.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO20_ALL_CHDFLTVAL_Pos (8)
#define GPIO20_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO20_ALL_CHDFLTVAL_Pos)

#define GPIO20_BIT_CHDFLTVAL

#define GPIO20_ALL_CHDFLTVAL_(x) ((x) << GPIO20_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO20          PD
 *  @access     PINMUX->GPIO20.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO20_ALL_PD_Pos (16)
#define GPIO20_ALL_PD_Msk (0xFFUL << GPIO20_ALL_PD_Pos)

#define GPIO20_BIT_PD

#define GPIO20_ALL_PD_(x) ((x) << GPIO20_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO20          PU
 *  @access     PINMUX->GPIO20.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO20_ALL_PU_Pos (24)
#define GPIO20_ALL_PU_Msk (0xFFUL << GPIO20_ALL_PU_Pos)

#define GPIO20_BIT_PU

#define GPIO20_ALL_PU_(x) ((x) << GPIO20_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO21          MUXSEL
 *  @access     PINMUX->GPIO21.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO21_ALL_MUXSEL_Pos (0)
#define GPIO21_ALL_MUXSEL_Msk (0x7UL << GPIO21_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO21_BIT_MUXSEL_GPIO21     = 0,  /*!< GPIO21   */
    GPIO21_BIT_MUXSEL_COMP4L     = 3,  /*!< COMP4L   */
    GPIO21_BIT_MUXSEL_PWM0B      = 4,  /*!< PWM0B    */
    GPIO21_BIT_MUXSEL_PWM1B      = 5,  /*!< PWM1B    */
    GPIO21_BIT_MUXSEL_SIO17      = 6,  /*!< SIO17    */
    GPIO21_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO21_BIT_MUXSEL;

#define GPIO21_ALL_MUXSEL_GPIO21     ((0x0UL) << GPIO21_ALL_MUXSEL_Pos)
#define GPIO21_ALL_MUXSEL_COMP4L     ((0x3UL) << GPIO21_ALL_MUXSEL_Pos)
#define GPIO21_ALL_MUXSEL_PWM0B      ((0x4UL) << GPIO21_ALL_MUXSEL_Pos)
#define GPIO21_ALL_MUXSEL_PWM1B      ((0x5UL) << GPIO21_ALL_MUXSEL_Pos)
#define GPIO21_ALL_MUXSEL_SIO17      ((0x6UL) << GPIO21_ALL_MUXSEL_Pos)
#define GPIO21_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO21_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO21          IE
 *  @access     PINMUX->GPIO21.bit.IE
 *  @brief      Input enable
 */
#define GPIO21_ALL_IE_Pos (3)
#define GPIO21_ALL_IE_Msk (0x1UL << GPIO21_ALL_IE_Pos)

typedef enum
{
    GPIO21_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO21_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO21_BIT_IE;

#define GPIO21_ALL_IE_DISABLE     ((0x0UL) << GPIO21_ALL_IE_Pos)
#define GPIO21_ALL_IE_ENABLE      ((0x1UL) << GPIO21_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO21          SMT
 *  @access     PINMUX->GPIO21.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO21_ALL_SMT_Pos (4)
#define GPIO21_ALL_SMT_Msk (0x1UL << GPIO21_ALL_SMT_Pos)

typedef enum
{
    GPIO21_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO21_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO21_BIT_SMT;

#define GPIO21_ALL_SMT_NORMAL      ((0x0UL) << GPIO21_ALL_SMT_Pos)
#define GPIO21_ALL_SMT_SCHMITT     ((0x1UL) << GPIO21_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO21          DEGLITCH
 *  @access     PINMUX->GPIO21.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO21_ALL_DEGLITCH_Pos (5)
#define GPIO21_ALL_DEGLITCH_Msk (0x1UL << GPIO21_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO21_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO21_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO21_BIT_DEGLITCH;

#define GPIO21_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO21_ALL_DEGLITCH_Pos)
#define GPIO21_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO21_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO21          STRENGTH
 *  @access     PINMUX->GPIO21.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO21_ALL_STRENGTH_Pos (6)
#define GPIO21_ALL_STRENGTH_Msk (0x3UL << GPIO21_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO21_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO21_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO21_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO21_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO21_BIT_STRENGTH;

#define GPIO21_ALL_STRENGTH_5MA      ((0x0UL) << GPIO21_ALL_STRENGTH_Pos)
#define GPIO21_ALL_STRENGTH_10MA     ((0x1UL) << GPIO21_ALL_STRENGTH_Pos)
#define GPIO21_ALL_STRENGTH_15MA     ((0x2UL) << GPIO21_ALL_STRENGTH_Pos)
#define GPIO21_ALL_STRENGTH_20MA     ((0x3UL) << GPIO21_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO21          CHDFLTVAL
 *  @access     PINMUX->GPIO21.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO21_ALL_CHDFLTVAL_Pos (8)
#define GPIO21_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO21_ALL_CHDFLTVAL_Pos)

#define GPIO21_BIT_CHDFLTVAL

#define GPIO21_ALL_CHDFLTVAL_(x) ((x) << GPIO21_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO21          PD
 *  @access     PINMUX->GPIO21.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO21_ALL_PD_Pos (16)
#define GPIO21_ALL_PD_Msk (0xFFUL << GPIO21_ALL_PD_Pos)

#define GPIO21_BIT_PD

#define GPIO21_ALL_PD_(x) ((x) << GPIO21_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO21          PU
 *  @access     PINMUX->GPIO21.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO21_ALL_PU_Pos (24)
#define GPIO21_ALL_PU_Msk (0xFFUL << GPIO21_ALL_PU_Pos)

#define GPIO21_BIT_PU

#define GPIO21_ALL_PU_(x) ((x) << GPIO21_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO22          MUXSEL
 *  @access     PINMUX->GPIO22.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO22_ALL_MUXSEL_Pos (0)
#define GPIO22_ALL_MUXSEL_Msk (0x7UL << GPIO22_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO22_BIT_MUXSEL_GPIO22     = 0,  /*!< GPIO22   */
    GPIO22_BIT_MUXSEL_PWM1B      = 4,  /*!< PWM1B    */
    GPIO22_BIT_MUXSEL_PWM2A      = 5,  /*!< PWM2A    */
    GPIO22_BIT_MUXSEL_SIO0       = 6,  /*!< SIO0     */
    GPIO22_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO22_BIT_MUXSEL;

#define GPIO22_ALL_MUXSEL_GPIO22     ((0x0UL) << GPIO22_ALL_MUXSEL_Pos)
#define GPIO22_ALL_MUXSEL_PWM1B      ((0x4UL) << GPIO22_ALL_MUXSEL_Pos)
#define GPIO22_ALL_MUXSEL_PWM2A      ((0x5UL) << GPIO22_ALL_MUXSEL_Pos)
#define GPIO22_ALL_MUXSEL_SIO0       ((0x6UL) << GPIO22_ALL_MUXSEL_Pos)
#define GPIO22_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO22_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO22          IE
 *  @access     PINMUX->GPIO22.bit.IE
 *  @brief      Input enable
 */
#define GPIO22_ALL_IE_Pos (3)
#define GPIO22_ALL_IE_Msk (0x1UL << GPIO22_ALL_IE_Pos)

typedef enum
{
    GPIO22_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO22_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO22_BIT_IE;

#define GPIO22_ALL_IE_DISABLE     ((0x0UL) << GPIO22_ALL_IE_Pos)
#define GPIO22_ALL_IE_ENABLE      ((0x1UL) << GPIO22_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO22          SMT
 *  @access     PINMUX->GPIO22.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO22_ALL_SMT_Pos (4)
#define GPIO22_ALL_SMT_Msk (0x1UL << GPIO22_ALL_SMT_Pos)

typedef enum
{
    GPIO22_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO22_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO22_BIT_SMT;

#define GPIO22_ALL_SMT_NORMAL      ((0x0UL) << GPIO22_ALL_SMT_Pos)
#define GPIO22_ALL_SMT_SCHMITT     ((0x1UL) << GPIO22_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO22          DEGLITCH
 *  @access     PINMUX->GPIO22.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO22_ALL_DEGLITCH_Pos (5)
#define GPIO22_ALL_DEGLITCH_Msk (0x1UL << GPIO22_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO22_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO22_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO22_BIT_DEGLITCH;

#define GPIO22_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO22_ALL_DEGLITCH_Pos)
#define GPIO22_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO22_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO22          STRENGTH
 *  @access     PINMUX->GPIO22.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO22_ALL_STRENGTH_Pos (6)
#define GPIO22_ALL_STRENGTH_Msk (0x3UL << GPIO22_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO22_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO22_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO22_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO22_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO22_BIT_STRENGTH;

#define GPIO22_ALL_STRENGTH_5MA      ((0x0UL) << GPIO22_ALL_STRENGTH_Pos)
#define GPIO22_ALL_STRENGTH_10MA     ((0x1UL) << GPIO22_ALL_STRENGTH_Pos)
#define GPIO22_ALL_STRENGTH_15MA     ((0x2UL) << GPIO22_ALL_STRENGTH_Pos)
#define GPIO22_ALL_STRENGTH_20MA     ((0x3UL) << GPIO22_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO22          CHDFLTVAL
 *  @access     PINMUX->GPIO22.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO22_ALL_CHDFLTVAL_Pos (8)
#define GPIO22_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO22_ALL_CHDFLTVAL_Pos)

#define GPIO22_BIT_CHDFLTVAL

#define GPIO22_ALL_CHDFLTVAL_(x) ((x) << GPIO22_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO22          PD
 *  @access     PINMUX->GPIO22.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO22_ALL_PD_Pos (16)
#define GPIO22_ALL_PD_Msk (0xFFUL << GPIO22_ALL_PD_Pos)

#define GPIO22_BIT_PD

#define GPIO22_ALL_PD_(x) ((x) << GPIO22_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO22          PU
 *  @access     PINMUX->GPIO22.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO22_ALL_PU_Pos (24)
#define GPIO22_ALL_PU_Msk (0xFFUL << GPIO22_ALL_PU_Pos)

#define GPIO22_BIT_PU

#define GPIO22_ALL_PU_(x) ((x) << GPIO22_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO23          MUXSEL
 *  @access     PINMUX->GPIO23.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO23_ALL_MUXSEL_Pos (0)
#define GPIO23_ALL_MUXSEL_Msk (0x7UL << GPIO23_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO23_BIT_MUXSEL_GPIO23     = 0,  /*!< GPIO23   */
    GPIO23_BIT_MUXSEL_PWM2B      = 4,  /*!< PWM2B    */
    // GPIO23_BIT_MUXSEL_PWM2B   = 5,  /*!< PWM2B    */
    GPIO23_BIT_MUXSEL_SIO1       = 6,  /*!< SIO1     */
    GPIO23_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO23_BIT_MUXSEL;

#define GPIO23_ALL_MUXSEL_GPIO23     ((0x0UL) << GPIO23_ALL_MUXSEL_Pos)
#define GPIO23_ALL_MUXSEL_PWM2B      ((0x4UL) << GPIO23_ALL_MUXSEL_Pos)
// #define GPIO23_ALL_MUXSEL_PWM2B      ((0x5UL) << GPIO23_ALL_MUXSEL_Pos)
#define GPIO23_ALL_MUXSEL_SIO1       ((0x6UL) << GPIO23_ALL_MUXSEL_Pos)
#define GPIO23_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO23_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO23          IE
 *  @access     PINMUX->GPIO23.bit.IE
 *  @brief      Input enable
 */
#define GPIO23_ALL_IE_Pos (3)
#define GPIO23_ALL_IE_Msk (0x1UL << GPIO23_ALL_IE_Pos)

typedef enum
{
    GPIO23_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO23_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO23_BIT_IE;

#define GPIO23_ALL_IE_DISABLE     ((0x0UL) << GPIO23_ALL_IE_Pos)
#define GPIO23_ALL_IE_ENABLE      ((0x1UL) << GPIO23_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO23          SMT
 *  @access     PINMUX->GPIO23.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO23_ALL_SMT_Pos (4)
#define GPIO23_ALL_SMT_Msk (0x1UL << GPIO23_ALL_SMT_Pos)

typedef enum
{
    GPIO23_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO23_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO23_BIT_SMT;

#define GPIO23_ALL_SMT_NORMAL      ((0x0UL) << GPIO23_ALL_SMT_Pos)
#define GPIO23_ALL_SMT_SCHMITT     ((0x1UL) << GPIO23_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO23          DEGLITCH
 *  @access     PINMUX->GPIO23.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO23_ALL_DEGLITCH_Pos (5)
#define GPIO23_ALL_DEGLITCH_Msk (0x1UL << GPIO23_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO23_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO23_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO23_BIT_DEGLITCH;

#define GPIO23_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO23_ALL_DEGLITCH_Pos)
#define GPIO23_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO23_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO23          STRENGTH
 *  @access     PINMUX->GPIO23.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO23_ALL_STRENGTH_Pos (6)
#define GPIO23_ALL_STRENGTH_Msk (0x3UL << GPIO23_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO23_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO23_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO23_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO23_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO23_BIT_STRENGTH;

#define GPIO23_ALL_STRENGTH_5MA      ((0x0UL) << GPIO23_ALL_STRENGTH_Pos)
#define GPIO23_ALL_STRENGTH_10MA     ((0x1UL) << GPIO23_ALL_STRENGTH_Pos)
#define GPIO23_ALL_STRENGTH_15MA     ((0x2UL) << GPIO23_ALL_STRENGTH_Pos)
#define GPIO23_ALL_STRENGTH_20MA     ((0x3UL) << GPIO23_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO23          CHDFLTVAL
 *  @access     PINMUX->GPIO23.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO23_ALL_CHDFLTVAL_Pos (8)
#define GPIO23_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO23_ALL_CHDFLTVAL_Pos)

#define GPIO23_BIT_CHDFLTVAL

#define GPIO23_ALL_CHDFLTVAL_(x) ((x) << GPIO23_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO23          PD
 *  @access     PINMUX->GPIO23.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO23_ALL_PD_Pos (16)
#define GPIO23_ALL_PD_Msk (0xFFUL << GPIO23_ALL_PD_Pos)

#define GPIO23_BIT_PD

#define GPIO23_ALL_PD_(x) ((x) << GPIO23_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO23          PU
 *  @access     PINMUX->GPIO23.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO23_ALL_PU_Pos (24)
#define GPIO23_ALL_PU_Msk (0xFFUL << GPIO23_ALL_PU_Pos)

#define GPIO23_BIT_PU

#define GPIO23_ALL_PU_(x) ((x) << GPIO23_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO24          MUXSEL
 *  @access     PINMUX->GPIO24.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO24_ALL_MUXSEL_Pos (0)
#define GPIO24_ALL_MUXSEL_Msk (0x7UL << GPIO24_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO24_BIT_MUXSEL_GPIO24     = 0,  /*!< GPIO24   */
    GPIO24_BIT_MUXSEL_COMP0H     = 3,  /*!< COMP0H   */
    GPIO24_BIT_MUXSEL_PWM3A      = 4,  /*!< PWM3A    */
    // GPIO24_BIT_MUXSEL_PWM3A   = 5,  /*!< PWM3A    */
    GPIO24_BIT_MUXSEL_SIO2       = 6,  /*!< SIO2     */
    GPIO24_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO24_BIT_MUXSEL;

#define GPIO24_ALL_MUXSEL_GPIO24     ((0x0UL) << GPIO24_ALL_MUXSEL_Pos)
#define GPIO24_ALL_MUXSEL_COMP0H     ((0x3UL) << GPIO24_ALL_MUXSEL_Pos)
#define GPIO24_ALL_MUXSEL_PWM3A      ((0x4UL) << GPIO24_ALL_MUXSEL_Pos)
// #define GPIO24_ALL_MUXSEL_PWM3A      ((0x5UL) << GPIO24_ALL_MUXSEL_Pos)
#define GPIO24_ALL_MUXSEL_SIO2       ((0x6UL) << GPIO24_ALL_MUXSEL_Pos)
#define GPIO24_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO24_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO24          IE
 *  @access     PINMUX->GPIO24.bit.IE
 *  @brief      Input enable
 */
#define GPIO24_ALL_IE_Pos (3)
#define GPIO24_ALL_IE_Msk (0x1UL << GPIO24_ALL_IE_Pos)

typedef enum
{
    GPIO24_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO24_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO24_BIT_IE;

#define GPIO24_ALL_IE_DISABLE     ((0x0UL) << GPIO24_ALL_IE_Pos)
#define GPIO24_ALL_IE_ENABLE      ((0x1UL) << GPIO24_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO24          SMT
 *  @access     PINMUX->GPIO24.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO24_ALL_SMT_Pos (4)
#define GPIO24_ALL_SMT_Msk (0x1UL << GPIO24_ALL_SMT_Pos)

typedef enum
{
    GPIO24_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO24_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO24_BIT_SMT;

#define GPIO24_ALL_SMT_NORMAL      ((0x0UL) << GPIO24_ALL_SMT_Pos)
#define GPIO24_ALL_SMT_SCHMITT     ((0x1UL) << GPIO24_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO24          DEGLITCH
 *  @access     PINMUX->GPIO24.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO24_ALL_DEGLITCH_Pos (5)
#define GPIO24_ALL_DEGLITCH_Msk (0x1UL << GPIO24_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO24_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO24_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO24_BIT_DEGLITCH;

#define GPIO24_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO24_ALL_DEGLITCH_Pos)
#define GPIO24_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO24_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO24          STRENGTH
 *  @access     PINMUX->GPIO24.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO24_ALL_STRENGTH_Pos (6)
#define GPIO24_ALL_STRENGTH_Msk (0x3UL << GPIO24_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO24_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO24_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO24_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO24_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO24_BIT_STRENGTH;

#define GPIO24_ALL_STRENGTH_5MA      ((0x0UL) << GPIO24_ALL_STRENGTH_Pos)
#define GPIO24_ALL_STRENGTH_10MA     ((0x1UL) << GPIO24_ALL_STRENGTH_Pos)
#define GPIO24_ALL_STRENGTH_15MA     ((0x2UL) << GPIO24_ALL_STRENGTH_Pos)
#define GPIO24_ALL_STRENGTH_20MA     ((0x3UL) << GPIO24_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO24          CHDFLTVAL
 *  @access     PINMUX->GPIO24.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO24_ALL_CHDFLTVAL_Pos (8)
#define GPIO24_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO24_ALL_CHDFLTVAL_Pos)

#define GPIO24_BIT_CHDFLTVAL

#define GPIO24_ALL_CHDFLTVAL_(x) ((x) << GPIO24_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO24          PD
 *  @access     PINMUX->GPIO24.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO24_ALL_PD_Pos (16)
#define GPIO24_ALL_PD_Msk (0xFFUL << GPIO24_ALL_PD_Pos)

#define GPIO24_BIT_PD

#define GPIO24_ALL_PD_(x) ((x) << GPIO24_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO24          PU
 *  @access     PINMUX->GPIO24.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO24_ALL_PU_Pos (24)
#define GPIO24_ALL_PU_Msk (0xFFUL << GPIO24_ALL_PU_Pos)

#define GPIO24_BIT_PU

#define GPIO24_ALL_PU_(x) ((x) << GPIO24_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO25          MUXSEL
 *  @access     PINMUX->GPIO25.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO25_ALL_MUXSEL_Pos (0)
#define GPIO25_ALL_MUXSEL_Msk (0x7UL << GPIO25_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO25_BIT_MUXSEL_GPIO25     = 0,  /*!< GPIO25   */
    GPIO25_BIT_MUXSEL_COMP0L     = 3,  /*!< COMP0L   */
    GPIO25_BIT_MUXSEL_PWM4A      = 4,  /*!< PWM4A    */
    GPIO25_BIT_MUXSEL_PWM3B      = 5,  /*!< PWM3B    */
    GPIO25_BIT_MUXSEL_SIO3       = 6,  /*!< SIO3     */
    GPIO25_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO25_BIT_MUXSEL;

#define GPIO25_ALL_MUXSEL_GPIO25     ((0x0UL) << GPIO25_ALL_MUXSEL_Pos)
#define GPIO25_ALL_MUXSEL_COMP0L     ((0x3UL) << GPIO25_ALL_MUXSEL_Pos)
#define GPIO25_ALL_MUXSEL_PWM4A      ((0x4UL) << GPIO25_ALL_MUXSEL_Pos)
#define GPIO25_ALL_MUXSEL_PWM3B      ((0x5UL) << GPIO25_ALL_MUXSEL_Pos)
#define GPIO25_ALL_MUXSEL_SIO3       ((0x6UL) << GPIO25_ALL_MUXSEL_Pos)
#define GPIO25_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO25_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO25          IE
 *  @access     PINMUX->GPIO25.bit.IE
 *  @brief      Input enable
 */
#define GPIO25_ALL_IE_Pos (3)
#define GPIO25_ALL_IE_Msk (0x1UL << GPIO25_ALL_IE_Pos)

typedef enum
{
    GPIO25_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO25_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO25_BIT_IE;

#define GPIO25_ALL_IE_DISABLE     ((0x0UL) << GPIO25_ALL_IE_Pos)
#define GPIO25_ALL_IE_ENABLE      ((0x1UL) << GPIO25_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO25          SMT
 *  @access     PINMUX->GPIO25.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO25_ALL_SMT_Pos (4)
#define GPIO25_ALL_SMT_Msk (0x1UL << GPIO25_ALL_SMT_Pos)

typedef enum
{
    GPIO25_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO25_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO25_BIT_SMT;

#define GPIO25_ALL_SMT_NORMAL      ((0x0UL) << GPIO25_ALL_SMT_Pos)
#define GPIO25_ALL_SMT_SCHMITT     ((0x1UL) << GPIO25_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO25          DEGLITCH
 *  @access     PINMUX->GPIO25.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO25_ALL_DEGLITCH_Pos (5)
#define GPIO25_ALL_DEGLITCH_Msk (0x1UL << GPIO25_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO25_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO25_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO25_BIT_DEGLITCH;

#define GPIO25_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO25_ALL_DEGLITCH_Pos)
#define GPIO25_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO25_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO25          STRENGTH
 *  @access     PINMUX->GPIO25.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO25_ALL_STRENGTH_Pos (6)
#define GPIO25_ALL_STRENGTH_Msk (0x3UL << GPIO25_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO25_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO25_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO25_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO25_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO25_BIT_STRENGTH;

#define GPIO25_ALL_STRENGTH_5MA      ((0x0UL) << GPIO25_ALL_STRENGTH_Pos)
#define GPIO25_ALL_STRENGTH_10MA     ((0x1UL) << GPIO25_ALL_STRENGTH_Pos)
#define GPIO25_ALL_STRENGTH_15MA     ((0x2UL) << GPIO25_ALL_STRENGTH_Pos)
#define GPIO25_ALL_STRENGTH_20MA     ((0x3UL) << GPIO25_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO25          CHDFLTVAL
 *  @access     PINMUX->GPIO25.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO25_ALL_CHDFLTVAL_Pos (8)
#define GPIO25_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO25_ALL_CHDFLTVAL_Pos)

#define GPIO25_BIT_CHDFLTVAL

#define GPIO25_ALL_CHDFLTVAL_(x) ((x) << GPIO25_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO25          PD
 *  @access     PINMUX->GPIO25.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO25_ALL_PD_Pos (16)
#define GPIO25_ALL_PD_Msk (0xFFUL << GPIO25_ALL_PD_Pos)

#define GPIO25_BIT_PD

#define GPIO25_ALL_PD_(x) ((x) << GPIO25_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO25          PU
 *  @access     PINMUX->GPIO25.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO25_ALL_PU_Pos (24)
#define GPIO25_ALL_PU_Msk (0xFFUL << GPIO25_ALL_PU_Pos)

#define GPIO25_BIT_PU

#define GPIO25_ALL_PU_(x) ((x) << GPIO25_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO26          MUXSEL
 *  @access     PINMUX->GPIO26.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO26_ALL_MUXSEL_Pos (0)
#define GPIO26_ALL_MUXSEL_Msk (0x7UL << GPIO26_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO26_BIT_MUXSEL_GPIO26     = 0,  /*!< GPIO26   */
    GPIO26_BIT_MUXSEL_COMP1H     = 3,  /*!< COMP1H   */
    GPIO26_BIT_MUXSEL_PWM5A      = 4,  /*!< PWM5A    */
    GPIO26_BIT_MUXSEL_PWM4A      = 5,  /*!< PWM4A    */
    GPIO26_BIT_MUXSEL_SIO4       = 6,  /*!< SIO4     */
    GPIO26_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO26_BIT_MUXSEL;

#define GPIO26_ALL_MUXSEL_GPIO26     ((0x0UL) << GPIO26_ALL_MUXSEL_Pos)
#define GPIO26_ALL_MUXSEL_COMP1H     ((0x3UL) << GPIO26_ALL_MUXSEL_Pos)
#define GPIO26_ALL_MUXSEL_PWM5A      ((0x4UL) << GPIO26_ALL_MUXSEL_Pos)
#define GPIO26_ALL_MUXSEL_PWM4A      ((0x5UL) << GPIO26_ALL_MUXSEL_Pos)
#define GPIO26_ALL_MUXSEL_SIO4       ((0x6UL) << GPIO26_ALL_MUXSEL_Pos)
#define GPIO26_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO26_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO26          IE
 *  @access     PINMUX->GPIO26.bit.IE
 *  @brief      Input enable
 */
#define GPIO26_ALL_IE_Pos (3)
#define GPIO26_ALL_IE_Msk (0x1UL << GPIO26_ALL_IE_Pos)

typedef enum
{
    GPIO26_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO26_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO26_BIT_IE;

#define GPIO26_ALL_IE_DISABLE     ((0x0UL) << GPIO26_ALL_IE_Pos)
#define GPIO26_ALL_IE_ENABLE      ((0x1UL) << GPIO26_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO26          SMT
 *  @access     PINMUX->GPIO26.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO26_ALL_SMT_Pos (4)
#define GPIO26_ALL_SMT_Msk (0x1UL << GPIO26_ALL_SMT_Pos)

typedef enum
{
    GPIO26_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO26_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO26_BIT_SMT;

#define GPIO26_ALL_SMT_NORMAL      ((0x0UL) << GPIO26_ALL_SMT_Pos)
#define GPIO26_ALL_SMT_SCHMITT     ((0x1UL) << GPIO26_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO26          DEGLITCH
 *  @access     PINMUX->GPIO26.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO26_ALL_DEGLITCH_Pos (5)
#define GPIO26_ALL_DEGLITCH_Msk (0x1UL << GPIO26_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO26_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO26_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO26_BIT_DEGLITCH;

#define GPIO26_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO26_ALL_DEGLITCH_Pos)
#define GPIO26_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO26_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO26          STRENGTH
 *  @access     PINMUX->GPIO26.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO26_ALL_STRENGTH_Pos (6)
#define GPIO26_ALL_STRENGTH_Msk (0x3UL << GPIO26_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO26_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO26_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO26_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO26_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO26_BIT_STRENGTH;

#define GPIO26_ALL_STRENGTH_5MA      ((0x0UL) << GPIO26_ALL_STRENGTH_Pos)
#define GPIO26_ALL_STRENGTH_10MA     ((0x1UL) << GPIO26_ALL_STRENGTH_Pos)
#define GPIO26_ALL_STRENGTH_15MA     ((0x2UL) << GPIO26_ALL_STRENGTH_Pos)
#define GPIO26_ALL_STRENGTH_20MA     ((0x3UL) << GPIO26_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO26          CHDFLTVAL
 *  @access     PINMUX->GPIO26.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO26_ALL_CHDFLTVAL_Pos (8)
#define GPIO26_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO26_ALL_CHDFLTVAL_Pos)

#define GPIO26_BIT_CHDFLTVAL

#define GPIO26_ALL_CHDFLTVAL_(x) ((x) << GPIO26_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO26          PD
 *  @access     PINMUX->GPIO26.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO26_ALL_PD_Pos (16)
#define GPIO26_ALL_PD_Msk (0xFFUL << GPIO26_ALL_PD_Pos)

#define GPIO26_BIT_PD

#define GPIO26_ALL_PD_(x) ((x) << GPIO26_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO26          PU
 *  @access     PINMUX->GPIO26.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO26_ALL_PU_Pos (24)
#define GPIO26_ALL_PU_Msk (0xFFUL << GPIO26_ALL_PU_Pos)

#define GPIO26_BIT_PU

#define GPIO26_ALL_PU_(x) ((x) << GPIO26_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO27          MUXSEL
 *  @access     PINMUX->GPIO27.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO27_ALL_MUXSEL_Pos (0)
#define GPIO27_ALL_MUXSEL_Msk (0x7UL << GPIO27_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO27_BIT_MUXSEL_GPIO27     = 0,  /*!< GPIO27   */
    GPIO27_BIT_MUXSEL_COMP1L     = 3,  /*!< COMP1L   */
    GPIO27_BIT_MUXSEL_PWM3B      = 4,  /*!< PWM3B    */
    GPIO27_BIT_MUXSEL_PWM4B      = 5,  /*!< PWM4B    */
    GPIO27_BIT_MUXSEL_SIO5       = 6,  /*!< SIO5     */
    GPIO27_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO27_BIT_MUXSEL;

#define GPIO27_ALL_MUXSEL_GPIO27     ((0x0UL) << GPIO27_ALL_MUXSEL_Pos)
#define GPIO27_ALL_MUXSEL_COMP1L     ((0x3UL) << GPIO27_ALL_MUXSEL_Pos)
#define GPIO27_ALL_MUXSEL_PWM3B      ((0x4UL) << GPIO27_ALL_MUXSEL_Pos)
#define GPIO27_ALL_MUXSEL_PWM4B      ((0x5UL) << GPIO27_ALL_MUXSEL_Pos)
#define GPIO27_ALL_MUXSEL_SIO5       ((0x6UL) << GPIO27_ALL_MUXSEL_Pos)
#define GPIO27_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO27_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO27          IE
 *  @access     PINMUX->GPIO27.bit.IE
 *  @brief      Input enable
 */
#define GPIO27_ALL_IE_Pos (3)
#define GPIO27_ALL_IE_Msk (0x1UL << GPIO27_ALL_IE_Pos)

typedef enum
{
    GPIO27_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO27_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO27_BIT_IE;

#define GPIO27_ALL_IE_DISABLE     ((0x0UL) << GPIO27_ALL_IE_Pos)
#define GPIO27_ALL_IE_ENABLE      ((0x1UL) << GPIO27_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO27          SMT
 *  @access     PINMUX->GPIO27.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO27_ALL_SMT_Pos (4)
#define GPIO27_ALL_SMT_Msk (0x1UL << GPIO27_ALL_SMT_Pos)

typedef enum
{
    GPIO27_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO27_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO27_BIT_SMT;

#define GPIO27_ALL_SMT_NORMAL      ((0x0UL) << GPIO27_ALL_SMT_Pos)
#define GPIO27_ALL_SMT_SCHMITT     ((0x1UL) << GPIO27_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO27          DEGLITCH
 *  @access     PINMUX->GPIO27.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO27_ALL_DEGLITCH_Pos (5)
#define GPIO27_ALL_DEGLITCH_Msk (0x1UL << GPIO27_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO27_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO27_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO27_BIT_DEGLITCH;

#define GPIO27_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO27_ALL_DEGLITCH_Pos)
#define GPIO27_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO27_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO27          STRENGTH
 *  @access     PINMUX->GPIO27.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO27_ALL_STRENGTH_Pos (6)
#define GPIO27_ALL_STRENGTH_Msk (0x3UL << GPIO27_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO27_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO27_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO27_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO27_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO27_BIT_STRENGTH;

#define GPIO27_ALL_STRENGTH_5MA      ((0x0UL) << GPIO27_ALL_STRENGTH_Pos)
#define GPIO27_ALL_STRENGTH_10MA     ((0x1UL) << GPIO27_ALL_STRENGTH_Pos)
#define GPIO27_ALL_STRENGTH_15MA     ((0x2UL) << GPIO27_ALL_STRENGTH_Pos)
#define GPIO27_ALL_STRENGTH_20MA     ((0x3UL) << GPIO27_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO27          CHDFLTVAL
 *  @access     PINMUX->GPIO27.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO27_ALL_CHDFLTVAL_Pos (8)
#define GPIO27_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO27_ALL_CHDFLTVAL_Pos)

#define GPIO27_BIT_CHDFLTVAL

#define GPIO27_ALL_CHDFLTVAL_(x) ((x) << GPIO27_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO27          PD
 *  @access     PINMUX->GPIO27.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO27_ALL_PD_Pos (16)
#define GPIO27_ALL_PD_Msk (0xFFUL << GPIO27_ALL_PD_Pos)

#define GPIO27_BIT_PD

#define GPIO27_ALL_PD_(x) ((x) << GPIO27_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO27          PU
 *  @access     PINMUX->GPIO27.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO27_ALL_PU_Pos (24)
#define GPIO27_ALL_PU_Msk (0xFFUL << GPIO27_ALL_PU_Pos)

#define GPIO27_BIT_PU

#define GPIO27_ALL_PU_(x) ((x) << GPIO27_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO28          MUXSEL
 *  @access     PINMUX->GPIO28.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO28_ALL_MUXSEL_Pos (0)
#define GPIO28_ALL_MUXSEL_Msk (0x7UL << GPIO28_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO28_BIT_MUXSEL_GPIO28     = 0,  /*!< GPIO28   */
    GPIO28_BIT_MUXSEL_COMP2H     = 3,  /*!< COMP2H   */
    GPIO28_BIT_MUXSEL_PWM4B      = 4,  /*!< PWM4B    */
    GPIO28_BIT_MUXSEL_PWM5A      = 5,  /*!< PWM5A    */
    GPIO28_BIT_MUXSEL_SIO6       = 6,  /*!< SIO6     */
    GPIO28_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO28_BIT_MUXSEL;

#define GPIO28_ALL_MUXSEL_GPIO28     ((0x0UL) << GPIO28_ALL_MUXSEL_Pos)
#define GPIO28_ALL_MUXSEL_COMP2H     ((0x3UL) << GPIO28_ALL_MUXSEL_Pos)
#define GPIO28_ALL_MUXSEL_PWM4B      ((0x4UL) << GPIO28_ALL_MUXSEL_Pos)
#define GPIO28_ALL_MUXSEL_PWM5A      ((0x5UL) << GPIO28_ALL_MUXSEL_Pos)
#define GPIO28_ALL_MUXSEL_SIO6       ((0x6UL) << GPIO28_ALL_MUXSEL_Pos)
#define GPIO28_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO28_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO28          IE
 *  @access     PINMUX->GPIO28.bit.IE
 *  @brief      Input enable
 */
#define GPIO28_ALL_IE_Pos (3)
#define GPIO28_ALL_IE_Msk (0x1UL << GPIO28_ALL_IE_Pos)

typedef enum
{
    GPIO28_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO28_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO28_BIT_IE;

#define GPIO28_ALL_IE_DISABLE     ((0x0UL) << GPIO28_ALL_IE_Pos)
#define GPIO28_ALL_IE_ENABLE      ((0x1UL) << GPIO28_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO28          SMT
 *  @access     PINMUX->GPIO28.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO28_ALL_SMT_Pos (4)
#define GPIO28_ALL_SMT_Msk (0x1UL << GPIO28_ALL_SMT_Pos)

typedef enum
{
    GPIO28_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO28_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO28_BIT_SMT;

#define GPIO28_ALL_SMT_NORMAL      ((0x0UL) << GPIO28_ALL_SMT_Pos)
#define GPIO28_ALL_SMT_SCHMITT     ((0x1UL) << GPIO28_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO28          DEGLITCH
 *  @access     PINMUX->GPIO28.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO28_ALL_DEGLITCH_Pos (5)
#define GPIO28_ALL_DEGLITCH_Msk (0x1UL << GPIO28_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO28_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO28_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO28_BIT_DEGLITCH;

#define GPIO28_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO28_ALL_DEGLITCH_Pos)
#define GPIO28_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO28_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO28          STRENGTH
 *  @access     PINMUX->GPIO28.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO28_ALL_STRENGTH_Pos (6)
#define GPIO28_ALL_STRENGTH_Msk (0x3UL << GPIO28_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO28_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO28_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO28_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO28_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO28_BIT_STRENGTH;

#define GPIO28_ALL_STRENGTH_5MA      ((0x0UL) << GPIO28_ALL_STRENGTH_Pos)
#define GPIO28_ALL_STRENGTH_10MA     ((0x1UL) << GPIO28_ALL_STRENGTH_Pos)
#define GPIO28_ALL_STRENGTH_15MA     ((0x2UL) << GPIO28_ALL_STRENGTH_Pos)
#define GPIO28_ALL_STRENGTH_20MA     ((0x3UL) << GPIO28_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO28          CHDFLTVAL
 *  @access     PINMUX->GPIO28.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO28_ALL_CHDFLTVAL_Pos (8)
#define GPIO28_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO28_ALL_CHDFLTVAL_Pos)

#define GPIO28_BIT_CHDFLTVAL

#define GPIO28_ALL_CHDFLTVAL_(x) ((x) << GPIO28_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO28          PD
 *  @access     PINMUX->GPIO28.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO28_ALL_PD_Pos (16)
#define GPIO28_ALL_PD_Msk (0xFFUL << GPIO28_ALL_PD_Pos)

#define GPIO28_BIT_PD

#define GPIO28_ALL_PD_(x) ((x) << GPIO28_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO28          PU
 *  @access     PINMUX->GPIO28.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO28_ALL_PU_Pos (24)
#define GPIO28_ALL_PU_Msk (0xFFUL << GPIO28_ALL_PU_Pos)

#define GPIO28_BIT_PU

#define GPIO28_ALL_PU_(x) ((x) << GPIO28_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO29          MUXSEL
 *  @access     PINMUX->GPIO29.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO29_ALL_MUXSEL_Pos (0)
#define GPIO29_ALL_MUXSEL_Msk (0x7UL << GPIO29_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO29_BIT_MUXSEL_GPIO29     = 0,  /*!< GPIO29   */
    GPIO29_BIT_MUXSEL_COMP2L     = 3,  /*!< COMP2L   */
    GPIO29_BIT_MUXSEL_PWM5B      = 4,  /*!< PWM5B    */
    // GPIO29_BIT_MUXSEL_PWM5B   = 5,  /*!< PWM5B    */
    GPIO29_BIT_MUXSEL_SIO7       = 6,  /*!< SIO7     */
    GPIO29_BIT_MUXSEL_ECAPO      = 7,  /*!< ECAPO    */
} GPIO29_BIT_MUXSEL;

#define GPIO29_ALL_MUXSEL_GPIO29     ((0x0UL) << GPIO29_ALL_MUXSEL_Pos)
#define GPIO29_ALL_MUXSEL_COMP2L     ((0x3UL) << GPIO29_ALL_MUXSEL_Pos)
#define GPIO29_ALL_MUXSEL_PWM5B      ((0x4UL) << GPIO29_ALL_MUXSEL_Pos)
// #define GPIO29_ALL_MUXSEL_PWM5B      ((0x5UL) << GPIO29_ALL_MUXSEL_Pos)
#define GPIO29_ALL_MUXSEL_SIO7       ((0x6UL) << GPIO29_ALL_MUXSEL_Pos)
#define GPIO29_ALL_MUXSEL_ECAPO      ((0x7UL) << GPIO29_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO29          IE
 *  @access     PINMUX->GPIO29.bit.IE
 *  @brief      Input enable
 */
#define GPIO29_ALL_IE_Pos (3)
#define GPIO29_ALL_IE_Msk (0x1UL << GPIO29_ALL_IE_Pos)

typedef enum
{
    GPIO29_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO29_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO29_BIT_IE;

#define GPIO29_ALL_IE_DISABLE     ((0x0UL) << GPIO29_ALL_IE_Pos)
#define GPIO29_ALL_IE_ENABLE      ((0x1UL) << GPIO29_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO29          SMT
 *  @access     PINMUX->GPIO29.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO29_ALL_SMT_Pos (4)
#define GPIO29_ALL_SMT_Msk (0x1UL << GPIO29_ALL_SMT_Pos)

typedef enum
{
    GPIO29_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO29_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO29_BIT_SMT;

#define GPIO29_ALL_SMT_NORMAL      ((0x0UL) << GPIO29_ALL_SMT_Pos)
#define GPIO29_ALL_SMT_SCHMITT     ((0x1UL) << GPIO29_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO29          DEGLITCH
 *  @access     PINMUX->GPIO29.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO29_ALL_DEGLITCH_Pos (5)
#define GPIO29_ALL_DEGLITCH_Msk (0x1UL << GPIO29_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO29_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO29_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO29_BIT_DEGLITCH;

#define GPIO29_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO29_ALL_DEGLITCH_Pos)
#define GPIO29_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO29_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO29          STRENGTH
 *  @access     PINMUX->GPIO29.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO29_ALL_STRENGTH_Pos (6)
#define GPIO29_ALL_STRENGTH_Msk (0x3UL << GPIO29_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO29_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO29_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO29_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO29_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO29_BIT_STRENGTH;

#define GPIO29_ALL_STRENGTH_5MA      ((0x0UL) << GPIO29_ALL_STRENGTH_Pos)
#define GPIO29_ALL_STRENGTH_10MA     ((0x1UL) << GPIO29_ALL_STRENGTH_Pos)
#define GPIO29_ALL_STRENGTH_15MA     ((0x2UL) << GPIO29_ALL_STRENGTH_Pos)
#define GPIO29_ALL_STRENGTH_20MA     ((0x3UL) << GPIO29_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO29          CHDFLTVAL
 *  @access     PINMUX->GPIO29.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO29_ALL_CHDFLTVAL_Pos (8)
#define GPIO29_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO29_ALL_CHDFLTVAL_Pos)

#define GPIO29_BIT_CHDFLTVAL

#define GPIO29_ALL_CHDFLTVAL_(x) ((x) << GPIO29_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO29          PD
 *  @access     PINMUX->GPIO29.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO29_ALL_PD_Pos (16)
#define GPIO29_ALL_PD_Msk (0xFFUL << GPIO29_ALL_PD_Pos)

#define GPIO29_BIT_PD

#define GPIO29_ALL_PD_(x) ((x) << GPIO29_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO29          PU
 *  @access     PINMUX->GPIO29.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO29_ALL_PU_Pos (24)
#define GPIO29_ALL_PU_Msk (0xFFUL << GPIO29_ALL_PU_Pos)

#define GPIO29_BIT_PU

#define GPIO29_ALL_PU_(x) ((x) << GPIO29_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO30          MUXSEL
 *  @access     PINMUX->GPIO30.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO30_ALL_MUXSEL_Pos (0)
#define GPIO30_ALL_MUXSEL_Msk (0x7UL << GPIO30_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO30_BIT_MUXSEL_GPIO30       = 0,  /*!< GPIO30     */
    GPIO30_BIT_MUXSEL_SPI_SCLK     = 1,  /*!< SPI_SCLK   */
    GPIO30_BIT_MUXSEL_I2C_SCL      = 2,  /*!< I2C_SCL    */
    GPIO30_BIT_MUXSEL_COMP3H       = 3,  /*!< COMP3H     */
    GPIO30_BIT_MUXSEL_PWM3A        = 4,  /*!< PWM3A      */
    GPIO30_BIT_MUXSEL_PWM0A        = 5,  /*!< PWM0A      */
    GPIO30_BIT_MUXSEL_SIO8         = 6,  /*!< SIO8       */
    GPIO30_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO30_BIT_MUXSEL;

#define GPIO30_ALL_MUXSEL_GPIO30       ((0x0UL) << GPIO30_ALL_MUXSEL_Pos)
#define GPIO30_ALL_MUXSEL_SPI_SCLK     ((0x1UL) << GPIO30_ALL_MUXSEL_Pos)
#define GPIO30_ALL_MUXSEL_I2C_SCL      ((0x2UL) << GPIO30_ALL_MUXSEL_Pos)
#define GPIO30_ALL_MUXSEL_COMP3H       ((0x3UL) << GPIO30_ALL_MUXSEL_Pos)
#define GPIO30_ALL_MUXSEL_PWM3A        ((0x4UL) << GPIO30_ALL_MUXSEL_Pos)
#define GPIO30_ALL_MUXSEL_PWM0A        ((0x5UL) << GPIO30_ALL_MUXSEL_Pos)
#define GPIO30_ALL_MUXSEL_SIO8         ((0x6UL) << GPIO30_ALL_MUXSEL_Pos)
#define GPIO30_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO30_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO30          IE
 *  @access     PINMUX->GPIO30.bit.IE
 *  @brief      Input enable
 */
#define GPIO30_ALL_IE_Pos (3)
#define GPIO30_ALL_IE_Msk (0x1UL << GPIO30_ALL_IE_Pos)

typedef enum
{
    GPIO30_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO30_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO30_BIT_IE;

#define GPIO30_ALL_IE_DISABLE     ((0x0UL) << GPIO30_ALL_IE_Pos)
#define GPIO30_ALL_IE_ENABLE      ((0x1UL) << GPIO30_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO30          SMT
 *  @access     PINMUX->GPIO30.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO30_ALL_SMT_Pos (4)
#define GPIO30_ALL_SMT_Msk (0x1UL << GPIO30_ALL_SMT_Pos)

typedef enum
{
    GPIO30_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO30_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO30_BIT_SMT;

#define GPIO30_ALL_SMT_NORMAL      ((0x0UL) << GPIO30_ALL_SMT_Pos)
#define GPIO30_ALL_SMT_SCHMITT     ((0x1UL) << GPIO30_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO30          DEGLITCH
 *  @access     PINMUX->GPIO30.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO30_ALL_DEGLITCH_Pos (5)
#define GPIO30_ALL_DEGLITCH_Msk (0x1UL << GPIO30_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO30_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO30_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO30_BIT_DEGLITCH;

#define GPIO30_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO30_ALL_DEGLITCH_Pos)
#define GPIO30_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO30_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO30          STRENGTH
 *  @access     PINMUX->GPIO30.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO30_ALL_STRENGTH_Pos (6)
#define GPIO30_ALL_STRENGTH_Msk (0x3UL << GPIO30_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO30_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO30_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO30_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO30_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO30_BIT_STRENGTH;

#define GPIO30_ALL_STRENGTH_5MA      ((0x0UL) << GPIO30_ALL_STRENGTH_Pos)
#define GPIO30_ALL_STRENGTH_10MA     ((0x1UL) << GPIO30_ALL_STRENGTH_Pos)
#define GPIO30_ALL_STRENGTH_15MA     ((0x2UL) << GPIO30_ALL_STRENGTH_Pos)
#define GPIO30_ALL_STRENGTH_20MA     ((0x3UL) << GPIO30_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO30          CHDFLTVAL
 *  @access     PINMUX->GPIO30.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO30_ALL_CHDFLTVAL_Pos (8)
#define GPIO30_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO30_ALL_CHDFLTVAL_Pos)

#define GPIO30_BIT_CHDFLTVAL

#define GPIO30_ALL_CHDFLTVAL_(x) ((x) << GPIO30_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO30          PD
 *  @access     PINMUX->GPIO30.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO30_ALL_PD_Pos (16)
#define GPIO30_ALL_PD_Msk (0xFFUL << GPIO30_ALL_PD_Pos)

#define GPIO30_BIT_PD

#define GPIO30_ALL_PD_(x) ((x) << GPIO30_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO30          PU
 *  @access     PINMUX->GPIO30.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO30_ALL_PU_Pos (24)
#define GPIO30_ALL_PU_Msk (0xFFUL << GPIO30_ALL_PU_Pos)

#define GPIO30_BIT_PU

#define GPIO30_ALL_PU_(x) ((x) << GPIO30_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO31          MUXSEL
 *  @access     PINMUX->GPIO31.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO31_ALL_MUXSEL_Pos (0)
#define GPIO31_ALL_MUXSEL_Msk (0x7UL << GPIO31_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO31_BIT_MUXSEL_GPIO31       = 0,  /*!< GPIO31     */
    GPIO31_BIT_MUXSEL_SPI_SFRM     = 1,  /*!< SPI_SFRM   */
    GPIO31_BIT_MUXSEL_I2C_SDA      = 2,  /*!< I2C_SDA    */
    GPIO31_BIT_MUXSEL_COMP3L       = 3,  /*!< COMP3L     */
    GPIO31_BIT_MUXSEL_PWM3B        = 4,  /*!< PWM3B      */
    GPIO31_BIT_MUXSEL_PWM0B        = 5,  /*!< PWM0B      */
    GPIO31_BIT_MUXSEL_SIO9         = 6,  /*!< SIO9       */
    GPIO31_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO31_BIT_MUXSEL;

#define GPIO31_ALL_MUXSEL_GPIO31       ((0x0UL) << GPIO31_ALL_MUXSEL_Pos)
#define GPIO31_ALL_MUXSEL_SPI_SFRM     ((0x1UL) << GPIO31_ALL_MUXSEL_Pos)
#define GPIO31_ALL_MUXSEL_I2C_SDA      ((0x2UL) << GPIO31_ALL_MUXSEL_Pos)
#define GPIO31_ALL_MUXSEL_COMP3L       ((0x3UL) << GPIO31_ALL_MUXSEL_Pos)
#define GPIO31_ALL_MUXSEL_PWM3B        ((0x4UL) << GPIO31_ALL_MUXSEL_Pos)
#define GPIO31_ALL_MUXSEL_PWM0B        ((0x5UL) << GPIO31_ALL_MUXSEL_Pos)
#define GPIO31_ALL_MUXSEL_SIO9         ((0x6UL) << GPIO31_ALL_MUXSEL_Pos)
#define GPIO31_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO31_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO31          IE
 *  @access     PINMUX->GPIO31.bit.IE
 *  @brief      Input enable
 */
#define GPIO31_ALL_IE_Pos (3)
#define GPIO31_ALL_IE_Msk (0x1UL << GPIO31_ALL_IE_Pos)

typedef enum
{
    GPIO31_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO31_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO31_BIT_IE;

#define GPIO31_ALL_IE_DISABLE     ((0x0UL) << GPIO31_ALL_IE_Pos)
#define GPIO31_ALL_IE_ENABLE      ((0x1UL) << GPIO31_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO31          SMT
 *  @access     PINMUX->GPIO31.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO31_ALL_SMT_Pos (4)
#define GPIO31_ALL_SMT_Msk (0x1UL << GPIO31_ALL_SMT_Pos)

typedef enum
{
    GPIO31_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO31_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO31_BIT_SMT;

#define GPIO31_ALL_SMT_NORMAL      ((0x0UL) << GPIO31_ALL_SMT_Pos)
#define GPIO31_ALL_SMT_SCHMITT     ((0x1UL) << GPIO31_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO31          DEGLITCH
 *  @access     PINMUX->GPIO31.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO31_ALL_DEGLITCH_Pos (5)
#define GPIO31_ALL_DEGLITCH_Msk (0x1UL << GPIO31_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO31_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO31_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO31_BIT_DEGLITCH;

#define GPIO31_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO31_ALL_DEGLITCH_Pos)
#define GPIO31_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO31_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO31          STRENGTH
 *  @access     PINMUX->GPIO31.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO31_ALL_STRENGTH_Pos (6)
#define GPIO31_ALL_STRENGTH_Msk (0x3UL << GPIO31_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO31_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO31_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO31_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO31_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO31_BIT_STRENGTH;

#define GPIO31_ALL_STRENGTH_5MA      ((0x0UL) << GPIO31_ALL_STRENGTH_Pos)
#define GPIO31_ALL_STRENGTH_10MA     ((0x1UL) << GPIO31_ALL_STRENGTH_Pos)
#define GPIO31_ALL_STRENGTH_15MA     ((0x2UL) << GPIO31_ALL_STRENGTH_Pos)
#define GPIO31_ALL_STRENGTH_20MA     ((0x3UL) << GPIO31_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO31          CHDFLTVAL
 *  @access     PINMUX->GPIO31.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO31_ALL_CHDFLTVAL_Pos (8)
#define GPIO31_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO31_ALL_CHDFLTVAL_Pos)

#define GPIO31_BIT_CHDFLTVAL

#define GPIO31_ALL_CHDFLTVAL_(x) ((x) << GPIO31_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO31          PD
 *  @access     PINMUX->GPIO31.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO31_ALL_PD_Pos (16)
#define GPIO31_ALL_PD_Msk (0xFFUL << GPIO31_ALL_PD_Pos)

#define GPIO31_BIT_PD

#define GPIO31_ALL_PD_(x) ((x) << GPIO31_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO31          PU
 *  @access     PINMUX->GPIO31.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO31_ALL_PU_Pos (24)
#define GPIO31_ALL_PU_Msk (0xFFUL << GPIO31_ALL_PU_Pos)

#define GPIO31_BIT_PU

#define GPIO31_ALL_PU_(x) ((x) << GPIO31_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO32          MUXSEL
 *  @access     PINMUX->GPIO32.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO32_ALL_MUXSEL_Pos (0)
#define GPIO32_ALL_MUXSEL_Msk (0x7UL << GPIO32_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO32_BIT_MUXSEL_GPIO32       = 0,  /*!< GPIO32                          */
    GPIO32_BIT_MUXSEL_SPI_MOSI     = 1,  /*!< SPI_MOSI                        */
    GPIO32_BIT_MUXSEL_SPI_MISO     = 2,  /*!< SPI_MISO                        */
    GPIO32_BIT_MUXSEL_COMP4H       = 3,  /*!< COMP4H                          */
    GPIO32_BIT_MUXSEL_PWM4A        = 4,  /*!< PWM4A                           */
    GPIO32_BIT_MUXSEL_EPWRTZ0O     = 5,  /*!< EPWRTZ0 output for monitoring   */
    GPIO32_BIT_MUXSEL_SIO10        = 6,  /*!< SIO10                           */
    GPIO32_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO                           */
} GPIO32_BIT_MUXSEL;

#define GPIO32_ALL_MUXSEL_GPIO32       ((0x0UL) << GPIO32_ALL_MUXSEL_Pos)
#define GPIO32_ALL_MUXSEL_SPI_MOSI     ((0x1UL) << GPIO32_ALL_MUXSEL_Pos)
#define GPIO32_ALL_MUXSEL_SPI_MISO     ((0x2UL) << GPIO32_ALL_MUXSEL_Pos)
#define GPIO32_ALL_MUXSEL_COMP4H       ((0x3UL) << GPIO32_ALL_MUXSEL_Pos)
#define GPIO32_ALL_MUXSEL_PWM4A        ((0x4UL) << GPIO32_ALL_MUXSEL_Pos)
#define GPIO32_ALL_MUXSEL_EPWRTZ0O     ((0x5UL) << GPIO32_ALL_MUXSEL_Pos)
#define GPIO32_ALL_MUXSEL_SIO10        ((0x6UL) << GPIO32_ALL_MUXSEL_Pos)
#define GPIO32_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO32_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO32          IE
 *  @access     PINMUX->GPIO32.bit.IE
 *  @brief      Input enable
 */
#define GPIO32_ALL_IE_Pos (3)
#define GPIO32_ALL_IE_Msk (0x1UL << GPIO32_ALL_IE_Pos)

typedef enum
{
    GPIO32_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO32_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO32_BIT_IE;

#define GPIO32_ALL_IE_DISABLE     ((0x0UL) << GPIO32_ALL_IE_Pos)
#define GPIO32_ALL_IE_ENABLE      ((0x1UL) << GPIO32_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO32          SMT
 *  @access     PINMUX->GPIO32.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO32_ALL_SMT_Pos (4)
#define GPIO32_ALL_SMT_Msk (0x1UL << GPIO32_ALL_SMT_Pos)

typedef enum
{
    GPIO32_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO32_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO32_BIT_SMT;

#define GPIO32_ALL_SMT_NORMAL      ((0x0UL) << GPIO32_ALL_SMT_Pos)
#define GPIO32_ALL_SMT_SCHMITT     ((0x1UL) << GPIO32_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO32          DEGLITCH
 *  @access     PINMUX->GPIO32.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO32_ALL_DEGLITCH_Pos (5)
#define GPIO32_ALL_DEGLITCH_Msk (0x1UL << GPIO32_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO32_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO32_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO32_BIT_DEGLITCH;

#define GPIO32_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO32_ALL_DEGLITCH_Pos)
#define GPIO32_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO32_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO32          STRENGTH
 *  @access     PINMUX->GPIO32.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO32_ALL_STRENGTH_Pos (6)
#define GPIO32_ALL_STRENGTH_Msk (0x3UL << GPIO32_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO32_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO32_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO32_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO32_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO32_BIT_STRENGTH;

#define GPIO32_ALL_STRENGTH_5MA      ((0x0UL) << GPIO32_ALL_STRENGTH_Pos)
#define GPIO32_ALL_STRENGTH_10MA     ((0x1UL) << GPIO32_ALL_STRENGTH_Pos)
#define GPIO32_ALL_STRENGTH_15MA     ((0x2UL) << GPIO32_ALL_STRENGTH_Pos)
#define GPIO32_ALL_STRENGTH_20MA     ((0x3UL) << GPIO32_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO32          CHDFLTVAL
 *  @access     PINMUX->GPIO32.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO32_ALL_CHDFLTVAL_Pos (8)
#define GPIO32_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO32_ALL_CHDFLTVAL_Pos)

#define GPIO32_BIT_CHDFLTVAL

#define GPIO32_ALL_CHDFLTVAL_(x) ((x) << GPIO32_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO32          PD
 *  @access     PINMUX->GPIO32.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO32_ALL_PD_Pos (16)
#define GPIO32_ALL_PD_Msk (0xFFUL << GPIO32_ALL_PD_Pos)

#define GPIO32_BIT_PD

#define GPIO32_ALL_PD_(x) ((x) << GPIO32_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO32          PU
 *  @access     PINMUX->GPIO32.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO32_ALL_PU_Pos (24)
#define GPIO32_ALL_PU_Msk (0xFFUL << GPIO32_ALL_PU_Pos)

#define GPIO32_BIT_PU

#define GPIO32_ALL_PU_(x) ((x) << GPIO32_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO33          MUXSEL
 *  @access     PINMUX->GPIO33.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO33_ALL_MUXSEL_Pos (0)
#define GPIO33_ALL_MUXSEL_Msk (0x7UL << GPIO33_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO33_BIT_MUXSEL_GPIO33       = 0,  /*!< GPIO33                          */
    GPIO33_BIT_MUXSEL_SPI_MISO     = 1,  /*!< SPI_MISO                        */
    GPIO33_BIT_MUXSEL_SPI_MOSI     = 2,  /*!< SPI_MOSI                        */
    GPIO33_BIT_MUXSEL_COMP4L       = 3,  /*!< COMP4L                          */
    GPIO33_BIT_MUXSEL_PWM4B        = 4,  /*!< PWM4B                           */
    GPIO33_BIT_MUXSEL_EPWRTZ1O     = 5,  /*!< EPWRTZ1 output for monitoring   */
    GPIO33_BIT_MUXSEL_SIO11        = 6,  /*!< SIO11                           */
    GPIO33_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO                           */
} GPIO33_BIT_MUXSEL;

#define GPIO33_ALL_MUXSEL_GPIO33       ((0x0UL) << GPIO33_ALL_MUXSEL_Pos)
#define GPIO33_ALL_MUXSEL_SPI_MISO     ((0x1UL) << GPIO33_ALL_MUXSEL_Pos)
#define GPIO33_ALL_MUXSEL_SPI_MOSI     ((0x2UL) << GPIO33_ALL_MUXSEL_Pos)
#define GPIO33_ALL_MUXSEL_COMP4L       ((0x3UL) << GPIO33_ALL_MUXSEL_Pos)
#define GPIO33_ALL_MUXSEL_PWM4B        ((0x4UL) << GPIO33_ALL_MUXSEL_Pos)
#define GPIO33_ALL_MUXSEL_EPWRTZ1O     ((0x5UL) << GPIO33_ALL_MUXSEL_Pos)
#define GPIO33_ALL_MUXSEL_SIO11        ((0x6UL) << GPIO33_ALL_MUXSEL_Pos)
#define GPIO33_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO33_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO33          IE
 *  @access     PINMUX->GPIO33.bit.IE
 *  @brief      Input enable
 */
#define GPIO33_ALL_IE_Pos (3)
#define GPIO33_ALL_IE_Msk (0x1UL << GPIO33_ALL_IE_Pos)

typedef enum
{
    GPIO33_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO33_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO33_BIT_IE;

#define GPIO33_ALL_IE_DISABLE     ((0x0UL) << GPIO33_ALL_IE_Pos)
#define GPIO33_ALL_IE_ENABLE      ((0x1UL) << GPIO33_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO33          SMT
 *  @access     PINMUX->GPIO33.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO33_ALL_SMT_Pos (4)
#define GPIO33_ALL_SMT_Msk (0x1UL << GPIO33_ALL_SMT_Pos)

typedef enum
{
    GPIO33_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO33_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO33_BIT_SMT;

#define GPIO33_ALL_SMT_NORMAL      ((0x0UL) << GPIO33_ALL_SMT_Pos)
#define GPIO33_ALL_SMT_SCHMITT     ((0x1UL) << GPIO33_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO33          DEGLITCH
 *  @access     PINMUX->GPIO33.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO33_ALL_DEGLITCH_Pos (5)
#define GPIO33_ALL_DEGLITCH_Msk (0x1UL << GPIO33_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO33_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO33_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO33_BIT_DEGLITCH;

#define GPIO33_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO33_ALL_DEGLITCH_Pos)
#define GPIO33_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO33_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO33          STRENGTH
 *  @access     PINMUX->GPIO33.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO33_ALL_STRENGTH_Pos (6)
#define GPIO33_ALL_STRENGTH_Msk (0x3UL << GPIO33_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO33_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO33_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO33_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO33_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO33_BIT_STRENGTH;

#define GPIO33_ALL_STRENGTH_5MA      ((0x0UL) << GPIO33_ALL_STRENGTH_Pos)
#define GPIO33_ALL_STRENGTH_10MA     ((0x1UL) << GPIO33_ALL_STRENGTH_Pos)
#define GPIO33_ALL_STRENGTH_15MA     ((0x2UL) << GPIO33_ALL_STRENGTH_Pos)
#define GPIO33_ALL_STRENGTH_20MA     ((0x3UL) << GPIO33_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO33          CHDFLTVAL
 *  @access     PINMUX->GPIO33.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO33_ALL_CHDFLTVAL_Pos (8)
#define GPIO33_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO33_ALL_CHDFLTVAL_Pos)

#define GPIO33_BIT_CHDFLTVAL

#define GPIO33_ALL_CHDFLTVAL_(x) ((x) << GPIO33_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO33          PD
 *  @access     PINMUX->GPIO33.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO33_ALL_PD_Pos (16)
#define GPIO33_ALL_PD_Msk (0xFFUL << GPIO33_ALL_PD_Pos)

#define GPIO33_BIT_PD

#define GPIO33_ALL_PD_(x) ((x) << GPIO33_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO33          PU
 *  @access     PINMUX->GPIO33.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO33_ALL_PU_Pos (24)
#define GPIO33_ALL_PU_Msk (0xFFUL << GPIO33_ALL_PU_Pos)

#define GPIO33_BIT_PU

#define GPIO33_ALL_PU_(x) ((x) << GPIO33_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO34          MUXSEL
 *  @access     PINMUX->GPIO34.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO34_ALL_MUXSEL_Pos (0)
#define GPIO34_ALL_MUXSEL_Msk (0x7UL << GPIO34_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO34_BIT_MUXSEL_GPIO34       = 0,  /*!< GPIO34     */
    GPIO34_BIT_MUXSEL_UART_TXD     = 1,  /*!< UART_TXD   */
    GPIO34_BIT_MUXSEL_UART_RXD     = 2,  /*!< UART_RXD   */
    GPIO34_BIT_MUXSEL_I2C_SDA      = 3,  /*!< I2C_SDA    */
    GPIO34_BIT_MUXSEL_SPI_MOSI     = 4,  /*!< SPI_MISO   */
    GPIO34_BIT_MUXSEL_SPI_MISO     = 5,  /*!< SPI_MOSI   */
    GPIO34_BIT_MUXSEL_SIO12        = 6,  /*!< SIO12      */
    GPIO34_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO34_BIT_MUXSEL;

#define GPIO34_ALL_MUXSEL_GPIO34       ((0x0UL) << GPIO34_ALL_MUXSEL_Pos)
#define GPIO34_ALL_MUXSEL_UART_TXD     ((0x1UL) << GPIO34_ALL_MUXSEL_Pos)
#define GPIO34_ALL_MUXSEL_UART_RXD     ((0x2UL) << GPIO34_ALL_MUXSEL_Pos)
#define GPIO34_ALL_MUXSEL_I2C_SDA      ((0x3UL) << GPIO34_ALL_MUXSEL_Pos)
#define GPIO34_ALL_MUXSEL_SPI_MOSI     ((0x4UL) << GPIO34_ALL_MUXSEL_Pos)
#define GPIO34_ALL_MUXSEL_SPI_MISO     ((0x5UL) << GPIO34_ALL_MUXSEL_Pos)
#define GPIO34_ALL_MUXSEL_SIO12        ((0x6UL) << GPIO34_ALL_MUXSEL_Pos)
#define GPIO34_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO34_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO34          IE
 *  @access     PINMUX->GPIO34.bit.IE
 *  @brief      Input enable
 */
#define GPIO34_ALL_IE_Pos (3)
#define GPIO34_ALL_IE_Msk (0x1UL << GPIO34_ALL_IE_Pos)

typedef enum
{
    GPIO34_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO34_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO34_BIT_IE;

#define GPIO34_ALL_IE_DISABLE     ((0x0UL) << GPIO34_ALL_IE_Pos)
#define GPIO34_ALL_IE_ENABLE      ((0x1UL) << GPIO34_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO34          SMT
 *  @access     PINMUX->GPIO34.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO34_ALL_SMT_Pos (4)
#define GPIO34_ALL_SMT_Msk (0x1UL << GPIO34_ALL_SMT_Pos)

typedef enum
{
    GPIO34_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO34_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO34_BIT_SMT;

#define GPIO34_ALL_SMT_NORMAL      ((0x0UL) << GPIO34_ALL_SMT_Pos)
#define GPIO34_ALL_SMT_SCHMITT     ((0x1UL) << GPIO34_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO34          DEGLITCH
 *  @access     PINMUX->GPIO34.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO34_ALL_DEGLITCH_Pos (5)
#define GPIO34_ALL_DEGLITCH_Msk (0x1UL << GPIO34_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO34_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO34_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO34_BIT_DEGLITCH;

#define GPIO34_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO34_ALL_DEGLITCH_Pos)
#define GPIO34_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO34_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO34          STRENGTH
 *  @access     PINMUX->GPIO34.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO34_ALL_STRENGTH_Pos (6)
#define GPIO34_ALL_STRENGTH_Msk (0x3UL << GPIO34_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO34_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO34_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO34_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO34_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO34_BIT_STRENGTH;

#define GPIO34_ALL_STRENGTH_5MA      ((0x0UL) << GPIO34_ALL_STRENGTH_Pos)
#define GPIO34_ALL_STRENGTH_10MA     ((0x1UL) << GPIO34_ALL_STRENGTH_Pos)
#define GPIO34_ALL_STRENGTH_15MA     ((0x2UL) << GPIO34_ALL_STRENGTH_Pos)
#define GPIO34_ALL_STRENGTH_20MA     ((0x3UL) << GPIO34_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO34          CHDFLTVAL
 *  @access     PINMUX->GPIO34.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO34_ALL_CHDFLTVAL_Pos (8)
#define GPIO34_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO34_ALL_CHDFLTVAL_Pos)

#define GPIO34_BIT_CHDFLTVAL

#define GPIO34_ALL_CHDFLTVAL_(x) ((x) << GPIO34_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO34          PD
 *  @access     PINMUX->GPIO34.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO34_ALL_PD_Pos (16)
#define GPIO34_ALL_PD_Msk (0xFFUL << GPIO34_ALL_PD_Pos)

#define GPIO34_BIT_PD

#define GPIO34_ALL_PD_(x) ((x) << GPIO34_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO34          PU
 *  @access     PINMUX->GPIO34.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO34_ALL_PU_Pos (24)
#define GPIO34_ALL_PU_Msk (0xFFUL << GPIO34_ALL_PU_Pos)

#define GPIO34_BIT_PU

#define GPIO34_ALL_PU_(x) ((x) << GPIO34_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO35          MUXSEL
 *  @access     PINMUX->GPIO35.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO35_ALL_MUXSEL_Pos (0)
#define GPIO35_ALL_MUXSEL_Msk (0x7UL << GPIO35_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO35_BIT_MUXSEL_GPIO35       = 0,  /*!< GPIO35     */
    GPIO35_BIT_MUXSEL_UART_RXD     = 1,  /*!< UART_RXD   */
    GPIO35_BIT_MUXSEL_UART_TXD     = 2,  /*!< UART_TXD   */
    GPIO35_BIT_MUXSEL_I2C_SCL      = 3,  /*!< I2C_SCL    */
    GPIO35_BIT_MUXSEL_SPI_MISO     = 4,  /*!< SPI_MOSI   */
    GPIO35_BIT_MUXSEL_SPI_MOSI     = 5,  /*!< SPI_MISO   */
    GPIO35_BIT_MUXSEL_SIO13        = 6,  /*!< SIO13      */
    GPIO35_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO35_BIT_MUXSEL;

#define GPIO35_ALL_MUXSEL_GPIO35       ((0x0UL) << GPIO35_ALL_MUXSEL_Pos)
#define GPIO35_ALL_MUXSEL_UART_RXD     ((0x1UL) << GPIO35_ALL_MUXSEL_Pos)
#define GPIO35_ALL_MUXSEL_UART_TXD     ((0x2UL) << GPIO35_ALL_MUXSEL_Pos)
#define GPIO35_ALL_MUXSEL_I2C_SCL      ((0x3UL) << GPIO35_ALL_MUXSEL_Pos)
#define GPIO35_ALL_MUXSEL_SPI_MISO     ((0x4UL) << GPIO35_ALL_MUXSEL_Pos)
#define GPIO35_ALL_MUXSEL_SPI_MOSI     ((0x5UL) << GPIO35_ALL_MUXSEL_Pos)
#define GPIO35_ALL_MUXSEL_SIO13        ((0x6UL) << GPIO35_ALL_MUXSEL_Pos)
#define GPIO35_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO35_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO35          IE
 *  @access     PINMUX->GPIO35.bit.IE
 *  @brief      Input enable
 */
#define GPIO35_ALL_IE_Pos (3)
#define GPIO35_ALL_IE_Msk (0x1UL << GPIO35_ALL_IE_Pos)

typedef enum
{
    GPIO35_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO35_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO35_BIT_IE;

#define GPIO35_ALL_IE_DISABLE     ((0x0UL) << GPIO35_ALL_IE_Pos)
#define GPIO35_ALL_IE_ENABLE      ((0x1UL) << GPIO35_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO35          SMT
 *  @access     PINMUX->GPIO35.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO35_ALL_SMT_Pos (4)
#define GPIO35_ALL_SMT_Msk (0x1UL << GPIO35_ALL_SMT_Pos)

typedef enum
{
    GPIO35_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO35_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO35_BIT_SMT;

#define GPIO35_ALL_SMT_NORMAL      ((0x0UL) << GPIO35_ALL_SMT_Pos)
#define GPIO35_ALL_SMT_SCHMITT     ((0x1UL) << GPIO35_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO35          DEGLITCH
 *  @access     PINMUX->GPIO35.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO35_ALL_DEGLITCH_Pos (5)
#define GPIO35_ALL_DEGLITCH_Msk (0x1UL << GPIO35_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO35_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO35_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO35_BIT_DEGLITCH;

#define GPIO35_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO35_ALL_DEGLITCH_Pos)
#define GPIO35_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO35_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO35          STRENGTH
 *  @access     PINMUX->GPIO35.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO35_ALL_STRENGTH_Pos (6)
#define GPIO35_ALL_STRENGTH_Msk (0x3UL << GPIO35_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO35_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO35_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO35_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO35_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO35_BIT_STRENGTH;

#define GPIO35_ALL_STRENGTH_5MA      ((0x0UL) << GPIO35_ALL_STRENGTH_Pos)
#define GPIO35_ALL_STRENGTH_10MA     ((0x1UL) << GPIO35_ALL_STRENGTH_Pos)
#define GPIO35_ALL_STRENGTH_15MA     ((0x2UL) << GPIO35_ALL_STRENGTH_Pos)
#define GPIO35_ALL_STRENGTH_20MA     ((0x3UL) << GPIO35_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO35          CHDFLTVAL
 *  @access     PINMUX->GPIO35.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO35_ALL_CHDFLTVAL_Pos (8)
#define GPIO35_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO35_ALL_CHDFLTVAL_Pos)

#define GPIO35_BIT_CHDFLTVAL

#define GPIO35_ALL_CHDFLTVAL_(x) ((x) << GPIO35_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO35          PD
 *  @access     PINMUX->GPIO35.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO35_ALL_PD_Pos (16)
#define GPIO35_ALL_PD_Msk (0xFFUL << GPIO35_ALL_PD_Pos)

#define GPIO35_BIT_PD

#define GPIO35_ALL_PD_(x) ((x) << GPIO35_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO35          PU
 *  @access     PINMUX->GPIO35.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO35_ALL_PU_Pos (24)
#define GPIO35_ALL_PU_Msk (0xFFUL << GPIO35_ALL_PU_Pos)

#define GPIO35_BIT_PU

#define GPIO35_ALL_PU_(x) ((x) << GPIO35_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO36          MUXSEL
 *  @access     PINMUX->GPIO36.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO36_ALL_MUXSEL_Pos (0)
#define GPIO36_ALL_MUXSEL_Msk (0x7UL << GPIO36_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO36_BIT_MUXSEL_GPIO36       = 0,  /*!< GPIO36     */
    GPIO36_BIT_MUXSEL_TDO          = 1,  /*!< TDO        */
    GPIO36_BIT_MUXSEL_UART_RXD     = 2,  /*!< UART_RXD   */
    GPIO36_BIT_MUXSEL_SPI_SCLK     = 3,  /*!< SPI_SCLK   */
    GPIO36_BIT_MUXSEL_PWM5A        = 4,  /*!< PWM5A      */
    GPIO36_BIT_MUXSEL_PWM1A        = 5,  /*!< PWM1A      */
    GPIO36_BIT_MUXSEL_SIO14        = 6,  /*!< SIO14      */
    GPIO36_BIT_MUXSEL_I2C_SDA      = 7,  /*!< I2C_SDA    */
} GPIO36_BIT_MUXSEL;

#define GPIO36_ALL_MUXSEL_GPIO36       ((0x0UL) << GPIO36_ALL_MUXSEL_Pos)
#define GPIO36_ALL_MUXSEL_TDO          ((0x1UL) << GPIO36_ALL_MUXSEL_Pos)
#define GPIO36_ALL_MUXSEL_UART_RXD     ((0x2UL) << GPIO36_ALL_MUXSEL_Pos)
#define GPIO36_ALL_MUXSEL_SPI_SCLK     ((0x3UL) << GPIO36_ALL_MUXSEL_Pos)
#define GPIO36_ALL_MUXSEL_PWM5A        ((0x4UL) << GPIO36_ALL_MUXSEL_Pos)
#define GPIO36_ALL_MUXSEL_PWM1A        ((0x5UL) << GPIO36_ALL_MUXSEL_Pos)
#define GPIO36_ALL_MUXSEL_SIO14        ((0x6UL) << GPIO36_ALL_MUXSEL_Pos)
#define GPIO36_ALL_MUXSEL_I2C_SDA      ((0x7UL) << GPIO36_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO36          IE
 *  @access     PINMUX->GPIO36.bit.IE
 *  @brief      Input enable
 */
#define GPIO36_ALL_IE_Pos (3)
#define GPIO36_ALL_IE_Msk (0x1UL << GPIO36_ALL_IE_Pos)

typedef enum
{
    GPIO36_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO36_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO36_BIT_IE;

#define GPIO36_ALL_IE_DISABLE     ((0x0UL) << GPIO36_ALL_IE_Pos)
#define GPIO36_ALL_IE_ENABLE      ((0x1UL) << GPIO36_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO36          SMT
 *  @access     PINMUX->GPIO36.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO36_ALL_SMT_Pos (4)
#define GPIO36_ALL_SMT_Msk (0x1UL << GPIO36_ALL_SMT_Pos)

typedef enum
{
    GPIO36_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO36_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO36_BIT_SMT;

#define GPIO36_ALL_SMT_NORMAL      ((0x0UL) << GPIO36_ALL_SMT_Pos)
#define GPIO36_ALL_SMT_SCHMITT     ((0x1UL) << GPIO36_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO36          DEGLITCH
 *  @access     PINMUX->GPIO36.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO36_ALL_DEGLITCH_Pos (5)
#define GPIO36_ALL_DEGLITCH_Msk (0x1UL << GPIO36_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO36_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO36_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO36_BIT_DEGLITCH;

#define GPIO36_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO36_ALL_DEGLITCH_Pos)
#define GPIO36_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO36_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO36          STRENGTH
 *  @access     PINMUX->GPIO36.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO36_ALL_STRENGTH_Pos (6)
#define GPIO36_ALL_STRENGTH_Msk (0x3UL << GPIO36_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO36_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO36_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO36_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO36_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO36_BIT_STRENGTH;

#define GPIO36_ALL_STRENGTH_5MA      ((0x0UL) << GPIO36_ALL_STRENGTH_Pos)
#define GPIO36_ALL_STRENGTH_10MA     ((0x1UL) << GPIO36_ALL_STRENGTH_Pos)
#define GPIO36_ALL_STRENGTH_15MA     ((0x2UL) << GPIO36_ALL_STRENGTH_Pos)
#define GPIO36_ALL_STRENGTH_20MA     ((0x3UL) << GPIO36_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO36          CHDFLTVAL
 *  @access     PINMUX->GPIO36.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO36_ALL_CHDFLTVAL_Pos (8)
#define GPIO36_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO36_ALL_CHDFLTVAL_Pos)

#define GPIO36_BIT_CHDFLTVAL

#define GPIO36_ALL_CHDFLTVAL_(x) ((x) << GPIO36_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO36          PD
 *  @access     PINMUX->GPIO36.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO36_ALL_PD_Pos (16)
#define GPIO36_ALL_PD_Msk (0xFFUL << GPIO36_ALL_PD_Pos)

#define GPIO36_BIT_PD

#define GPIO36_ALL_PD_(x) ((x) << GPIO36_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO36          PU
 *  @access     PINMUX->GPIO36.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO36_ALL_PU_Pos (24)
#define GPIO36_ALL_PU_Msk (0xFFUL << GPIO36_ALL_PU_Pos)

#define GPIO36_BIT_PU

#define GPIO36_ALL_PU_(x) ((x) << GPIO36_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO37          MUXSEL
 *  @access     PINMUX->GPIO37.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO37_ALL_MUXSEL_Pos (0)
#define GPIO37_ALL_MUXSEL_Msk (0x7UL << GPIO37_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO37_BIT_MUXSEL_GPIO37       = 0,  /*!< GPIO37     */
    GPIO37_BIT_MUXSEL_TDI          = 1,  /*!< TDI        */
    GPIO37_BIT_MUXSEL_UART_TXD     = 2,  /*!< UART_TXD   */
    GPIO37_BIT_MUXSEL_SPI_SFRM     = 3,  /*!< SPI_SFRM   */
    GPIO37_BIT_MUXSEL_PWM5B        = 4,  /*!< PWM5B      */
    GPIO37_BIT_MUXSEL_PWM1B        = 5,  /*!< PWM1B      */
    GPIO37_BIT_MUXSEL_SIO15        = 6,  /*!< SIO15      */
    GPIO37_BIT_MUXSEL_I2C_SCL      = 7,  /*!< I2C_SCL    */
} GPIO37_BIT_MUXSEL;

#define GPIO37_ALL_MUXSEL_GPIO37       ((0x0UL) << GPIO37_ALL_MUXSEL_Pos)
#define GPIO37_ALL_MUXSEL_TDI          ((0x1UL) << GPIO37_ALL_MUXSEL_Pos)
#define GPIO37_ALL_MUXSEL_UART_TXD     ((0x2UL) << GPIO37_ALL_MUXSEL_Pos)
#define GPIO37_ALL_MUXSEL_SPI_SFRM     ((0x3UL) << GPIO37_ALL_MUXSEL_Pos)
#define GPIO37_ALL_MUXSEL_PWM5B        ((0x4UL) << GPIO37_ALL_MUXSEL_Pos)
#define GPIO37_ALL_MUXSEL_PWM1B        ((0x5UL) << GPIO37_ALL_MUXSEL_Pos)
#define GPIO37_ALL_MUXSEL_SIO15        ((0x6UL) << GPIO37_ALL_MUXSEL_Pos)
#define GPIO37_ALL_MUXSEL_I2C_SCL      ((0x7UL) << GPIO37_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO37          IE
 *  @access     PINMUX->GPIO37.bit.IE
 *  @brief      Input enable
 */
#define GPIO37_ALL_IE_Pos (3)
#define GPIO37_ALL_IE_Msk (0x1UL << GPIO37_ALL_IE_Pos)

typedef enum
{
    GPIO37_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO37_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO37_BIT_IE;

#define GPIO37_ALL_IE_DISABLE     ((0x0UL) << GPIO37_ALL_IE_Pos)
#define GPIO37_ALL_IE_ENABLE      ((0x1UL) << GPIO37_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO37          SMT
 *  @access     PINMUX->GPIO37.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO37_ALL_SMT_Pos (4)
#define GPIO37_ALL_SMT_Msk (0x1UL << GPIO37_ALL_SMT_Pos)

typedef enum
{
    GPIO37_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO37_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO37_BIT_SMT;

#define GPIO37_ALL_SMT_NORMAL      ((0x0UL) << GPIO37_ALL_SMT_Pos)
#define GPIO37_ALL_SMT_SCHMITT     ((0x1UL) << GPIO37_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO37          DEGLITCH
 *  @access     PINMUX->GPIO37.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO37_ALL_DEGLITCH_Pos (5)
#define GPIO37_ALL_DEGLITCH_Msk (0x1UL << GPIO37_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO37_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO37_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO37_BIT_DEGLITCH;

#define GPIO37_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO37_ALL_DEGLITCH_Pos)
#define GPIO37_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO37_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO37          STRENGTH
 *  @access     PINMUX->GPIO37.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO37_ALL_STRENGTH_Pos (6)
#define GPIO37_ALL_STRENGTH_Msk (0x3UL << GPIO37_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO37_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO37_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO37_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO37_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO37_BIT_STRENGTH;

#define GPIO37_ALL_STRENGTH_5MA      ((0x0UL) << GPIO37_ALL_STRENGTH_Pos)
#define GPIO37_ALL_STRENGTH_10MA     ((0x1UL) << GPIO37_ALL_STRENGTH_Pos)
#define GPIO37_ALL_STRENGTH_15MA     ((0x2UL) << GPIO37_ALL_STRENGTH_Pos)
#define GPIO37_ALL_STRENGTH_20MA     ((0x3UL) << GPIO37_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO37          CHDFLTVAL
 *  @access     PINMUX->GPIO37.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO37_ALL_CHDFLTVAL_Pos (8)
#define GPIO37_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO37_ALL_CHDFLTVAL_Pos)

#define GPIO37_BIT_CHDFLTVAL

#define GPIO37_ALL_CHDFLTVAL_(x) ((x) << GPIO37_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO37          PD
 *  @access     PINMUX->GPIO37.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO37_ALL_PD_Pos (16)
#define GPIO37_ALL_PD_Msk (0xFFUL << GPIO37_ALL_PD_Pos)

#define GPIO37_BIT_PD

#define GPIO37_ALL_PD_(x) ((x) << GPIO37_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO37          PU
 *  @access     PINMUX->GPIO37.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO37_ALL_PU_Pos (24)
#define GPIO37_ALL_PU_Msk (0xFFUL << GPIO37_ALL_PU_Pos)

#define GPIO37_BIT_PU

#define GPIO37_ALL_PU_(x) ((x) << GPIO37_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO38          MUXSEL
 *  @access     PINMUX->GPIO38.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO38_ALL_MUXSEL_Pos (0)
#define GPIO38_ALL_MUXSEL_Msk (0x7UL << GPIO38_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO38_BIT_MUXSEL_GPIO38       = 0,  /*!< GPIO38     */
    GPIO38_BIT_MUXSEL_SWD_TMS      = 1,  /*!< SWD/TMS    */
    GPIO38_BIT_MUXSEL_I2C_SDA      = 2,  /*!< I2C_SDA    */
    GPIO38_BIT_MUXSEL_SPI_MOSI     = 3,  /*!< SPI_MOSI   */
    GPIO38_BIT_MUXSEL_SPI_MISO     = 4,  /*!< SPI_MISO   */
    GPIO38_BIT_MUXSEL_PWM2A        = 5,  /*!< PWM2A      */
    GPIO38_BIT_MUXSEL_SIO16        = 6,  /*!< SIO16      */
    GPIO38_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO38_BIT_MUXSEL;

#define GPIO38_ALL_MUXSEL_GPIO38       ((0x0UL) << GPIO38_ALL_MUXSEL_Pos)
#define GPIO38_ALL_MUXSEL_SWD_TMS      ((0x1UL) << GPIO38_ALL_MUXSEL_Pos)
#define GPIO38_ALL_MUXSEL_I2C_SDA      ((0x2UL) << GPIO38_ALL_MUXSEL_Pos)
#define GPIO38_ALL_MUXSEL_SPI_MOSI     ((0x3UL) << GPIO38_ALL_MUXSEL_Pos)
#define GPIO38_ALL_MUXSEL_SPI_MISO     ((0x4UL) << GPIO38_ALL_MUXSEL_Pos)
#define GPIO38_ALL_MUXSEL_PWM2A        ((0x5UL) << GPIO38_ALL_MUXSEL_Pos)
#define GPIO38_ALL_MUXSEL_SIO16        ((0x6UL) << GPIO38_ALL_MUXSEL_Pos)
#define GPIO38_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO38_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO38          IE
 *  @access     PINMUX->GPIO38.bit.IE
 *  @brief      Input enable
 */
#define GPIO38_ALL_IE_Pos (3)
#define GPIO38_ALL_IE_Msk (0x1UL << GPIO38_ALL_IE_Pos)

typedef enum
{
    GPIO38_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO38_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO38_BIT_IE;

#define GPIO38_ALL_IE_DISABLE     ((0x0UL) << GPIO38_ALL_IE_Pos)
#define GPIO38_ALL_IE_ENABLE      ((0x1UL) << GPIO38_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO38          SMT
 *  @access     PINMUX->GPIO38.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO38_ALL_SMT_Pos (4)
#define GPIO38_ALL_SMT_Msk (0x1UL << GPIO38_ALL_SMT_Pos)

typedef enum
{
    GPIO38_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO38_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO38_BIT_SMT;

#define GPIO38_ALL_SMT_NORMAL      ((0x0UL) << GPIO38_ALL_SMT_Pos)
#define GPIO38_ALL_SMT_SCHMITT     ((0x1UL) << GPIO38_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO38          DEGLITCH
 *  @access     PINMUX->GPIO38.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO38_ALL_DEGLITCH_Pos (5)
#define GPIO38_ALL_DEGLITCH_Msk (0x1UL << GPIO38_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO38_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO38_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO38_BIT_DEGLITCH;

#define GPIO38_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO38_ALL_DEGLITCH_Pos)
#define GPIO38_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO38_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO38          STRENGTH
 *  @access     PINMUX->GPIO38.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO38_ALL_STRENGTH_Pos (6)
#define GPIO38_ALL_STRENGTH_Msk (0x3UL << GPIO38_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO38_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO38_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO38_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO38_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO38_BIT_STRENGTH;

#define GPIO38_ALL_STRENGTH_5MA      ((0x0UL) << GPIO38_ALL_STRENGTH_Pos)
#define GPIO38_ALL_STRENGTH_10MA     ((0x1UL) << GPIO38_ALL_STRENGTH_Pos)
#define GPIO38_ALL_STRENGTH_15MA     ((0x2UL) << GPIO38_ALL_STRENGTH_Pos)
#define GPIO38_ALL_STRENGTH_20MA     ((0x3UL) << GPIO38_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO38          CHDFLTVAL
 *  @access     PINMUX->GPIO38.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO38_ALL_CHDFLTVAL_Pos (8)
#define GPIO38_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO38_ALL_CHDFLTVAL_Pos)

#define GPIO38_BIT_CHDFLTVAL

#define GPIO38_ALL_CHDFLTVAL_(x) ((x) << GPIO38_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO38          PD
 *  @access     PINMUX->GPIO38.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO38_ALL_PD_Pos (16)
#define GPIO38_ALL_PD_Msk (0xFFUL << GPIO38_ALL_PD_Pos)

#define GPIO38_BIT_PD

#define GPIO38_ALL_PD_(x) ((x) << GPIO38_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO38          PU
 *  @access     PINMUX->GPIO38.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO38_ALL_PU_Pos (24)
#define GPIO38_ALL_PU_Msk (0xFFUL << GPIO38_ALL_PU_Pos)

#define GPIO38_BIT_PU

#define GPIO38_ALL_PU_(x) ((x) << GPIO38_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO39          MUXSEL
 *  @access     PINMUX->GPIO39.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO39_ALL_MUXSEL_Pos (0)
#define GPIO39_ALL_MUXSEL_Msk (0x7UL << GPIO39_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO39_BIT_MUXSEL_GPIO39       = 0,  /*!< GPIO39     */
    GPIO39_BIT_MUXSEL_SWCK_TCK     = 1,  /*!< SWCK/TCK   */
    GPIO39_BIT_MUXSEL_I2C_SCL      = 2,  /*!< I2C_SCL    */
    GPIO39_BIT_MUXSEL_SPI_MISO     = 3,  /*!< SPI_MISO   */
    GPIO39_BIT_MUXSEL_SPI_MOSI     = 4,  /*!< SPI_MOSI   */
    GPIO39_BIT_MUXSEL_PWM2B        = 5,  /*!< PWM2B      */
    GPIO39_BIT_MUXSEL_SIO17        = 6,  /*!< SIO17      */
    GPIO39_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO      */
} GPIO39_BIT_MUXSEL;

#define GPIO39_ALL_MUXSEL_GPIO39       ((0x0UL) << GPIO39_ALL_MUXSEL_Pos)
#define GPIO39_ALL_MUXSEL_SWCK_TCK     ((0x1UL) << GPIO39_ALL_MUXSEL_Pos)
#define GPIO39_ALL_MUXSEL_I2C_SCL      ((0x2UL) << GPIO39_ALL_MUXSEL_Pos)
#define GPIO39_ALL_MUXSEL_SPI_MISO     ((0x3UL) << GPIO39_ALL_MUXSEL_Pos)
#define GPIO39_ALL_MUXSEL_SPI_MOSI     ((0x4UL) << GPIO39_ALL_MUXSEL_Pos)
#define GPIO39_ALL_MUXSEL_PWM2B        ((0x5UL) << GPIO39_ALL_MUXSEL_Pos)
#define GPIO39_ALL_MUXSEL_SIO17        ((0x6UL) << GPIO39_ALL_MUXSEL_Pos)
#define GPIO39_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO39_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO39          IE
 *  @access     PINMUX->GPIO39.bit.IE
 *  @brief      Input enable
 */
#define GPIO39_ALL_IE_Pos (3)
#define GPIO39_ALL_IE_Msk (0x1UL << GPIO39_ALL_IE_Pos)

typedef enum
{
    GPIO39_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO39_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO39_BIT_IE;

#define GPIO39_ALL_IE_DISABLE     ((0x0UL) << GPIO39_ALL_IE_Pos)
#define GPIO39_ALL_IE_ENABLE      ((0x1UL) << GPIO39_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO39          SMT
 *  @access     PINMUX->GPIO39.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO39_ALL_SMT_Pos (4)
#define GPIO39_ALL_SMT_Msk (0x1UL << GPIO39_ALL_SMT_Pos)

typedef enum
{
    GPIO39_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO39_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO39_BIT_SMT;

#define GPIO39_ALL_SMT_NORMAL      ((0x0UL) << GPIO39_ALL_SMT_Pos)
#define GPIO39_ALL_SMT_SCHMITT     ((0x1UL) << GPIO39_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO39          DEGLITCH
 *  @access     PINMUX->GPIO39.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO39_ALL_DEGLITCH_Pos (5)
#define GPIO39_ALL_DEGLITCH_Msk (0x1UL << GPIO39_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO39_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO39_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO39_BIT_DEGLITCH;

#define GPIO39_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO39_ALL_DEGLITCH_Pos)
#define GPIO39_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO39_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO39          STRENGTH
 *  @access     PINMUX->GPIO39.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO39_ALL_STRENGTH_Pos (6)
#define GPIO39_ALL_STRENGTH_Msk (0x3UL << GPIO39_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO39_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO39_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO39_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO39_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO39_BIT_STRENGTH;

#define GPIO39_ALL_STRENGTH_5MA      ((0x0UL) << GPIO39_ALL_STRENGTH_Pos)
#define GPIO39_ALL_STRENGTH_10MA     ((0x1UL) << GPIO39_ALL_STRENGTH_Pos)
#define GPIO39_ALL_STRENGTH_15MA     ((0x2UL) << GPIO39_ALL_STRENGTH_Pos)
#define GPIO39_ALL_STRENGTH_20MA     ((0x3UL) << GPIO39_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO39          CHDFLTVAL
 *  @access     PINMUX->GPIO39.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO39_ALL_CHDFLTVAL_Pos (8)
#define GPIO39_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO39_ALL_CHDFLTVAL_Pos)

#define GPIO39_BIT_CHDFLTVAL

#define GPIO39_ALL_CHDFLTVAL_(x) ((x) << GPIO39_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO39          PD
 *  @access     PINMUX->GPIO39.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO39_ALL_PD_Pos (16)
#define GPIO39_ALL_PD_Msk (0xFFUL << GPIO39_ALL_PD_Pos)

#define GPIO39_BIT_PD

#define GPIO39_ALL_PD_(x) ((x) << GPIO39_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO39          PU
 *  @access     PINMUX->GPIO39.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO39_ALL_PU_Pos (24)
#define GPIO39_ALL_PU_Msk (0xFFUL << GPIO39_ALL_PU_Pos)

#define GPIO39_BIT_PU

#define GPIO39_ALL_PU_(x) ((x) << GPIO39_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO40          MUXSEL
 *  @access     PINMUX->GPIO40.bit.MUXSEL
 *  @brief      Channel select
 */
#define GPIO40_ALL_MUXSEL_Pos (0)
#define GPIO40_ALL_MUXSEL_Msk (0x7UL << GPIO40_ALL_MUXSEL_Pos)

typedef enum
{
    GPIO40_BIT_MUXSEL_GPIO40       = 0,  /*!< GPIO40                          */
    GPIO40_BIT_MUXSEL_SPI_SCLK     = 1,  /*!< SPI_SCLK                        */
    GPIO40_BIT_MUXSEL_UART_TXD     = 2,  /*!< UART_TXD                        */
    GPIO40_BIT_MUXSEL_DCLK         = 3,  /*!< DCLK output for monitoring      */
    GPIO40_BIT_MUXSEL_EPWRTZ0O     = 4,  /*!< EPWRTZ0 output for monitoring   */
    GPIO40_BIT_MUXSEL_EPWRTZ1O     = 5,  /*!< EPWRTZ1 output for monitoring   */
    GPIO40_BIT_MUXSEL_SIO0         = 6,  /*!< SIO0                            */
    GPIO40_BIT_MUXSEL_ECAPO        = 7,  /*!< ECAPO                           */
} GPIO40_BIT_MUXSEL;

#define GPIO40_ALL_MUXSEL_GPIO40       ((0x0UL) << GPIO40_ALL_MUXSEL_Pos)
#define GPIO40_ALL_MUXSEL_SPI_SCLK     ((0x1UL) << GPIO40_ALL_MUXSEL_Pos)
#define GPIO40_ALL_MUXSEL_UART_TXD     ((0x2UL) << GPIO40_ALL_MUXSEL_Pos)
#define GPIO40_ALL_MUXSEL_DCLK         ((0x3UL) << GPIO40_ALL_MUXSEL_Pos)
#define GPIO40_ALL_MUXSEL_EPWRTZ0O     ((0x4UL) << GPIO40_ALL_MUXSEL_Pos)
#define GPIO40_ALL_MUXSEL_EPWRTZ1O     ((0x5UL) << GPIO40_ALL_MUXSEL_Pos)
#define GPIO40_ALL_MUXSEL_SIO0         ((0x6UL) << GPIO40_ALL_MUXSEL_Pos)
#define GPIO40_ALL_MUXSEL_ECAPO        ((0x7UL) << GPIO40_ALL_MUXSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO40          IE
 *  @access     PINMUX->GPIO40.bit.IE
 *  @brief      Input enable
 */
#define GPIO40_ALL_IE_Pos (3)
#define GPIO40_ALL_IE_Msk (0x1UL << GPIO40_ALL_IE_Pos)

typedef enum
{
    GPIO40_BIT_IE_DISABLE     = 0,  /*!< Input is always 0   */
    GPIO40_BIT_IE_ENABLE      = 1,  /*!< Enable input        */
} GPIO40_BIT_IE;

#define GPIO40_ALL_IE_DISABLE     ((0x0UL) << GPIO40_ALL_IE_Pos)
#define GPIO40_ALL_IE_ENABLE      ((0x1UL) << GPIO40_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO40          SMT
 *  @access     PINMUX->GPIO40.bit.SMT
 *  @brief      Switch normal/schmitt input
 */
#define GPIO40_ALL_SMT_Pos (4)
#define GPIO40_ALL_SMT_Msk (0x1UL << GPIO40_ALL_SMT_Pos)

typedef enum
{
    GPIO40_BIT_SMT_NORMAL      = 0,  /*!< Normal input    */
    GPIO40_BIT_SMT_SCHMITT     = 1,  /*!< Schmitt input   */
} GPIO40_BIT_SMT;

#define GPIO40_ALL_SMT_NORMAL      ((0x0UL) << GPIO40_ALL_SMT_Pos)
#define GPIO40_ALL_SMT_SCHMITT     ((0x1UL) << GPIO40_ALL_SMT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO40          DEGLITCH
 *  @access     PINMUX->GPIO40.bit.DEGLITCH
 *  @brief      Input deglitch
 */
#define GPIO40_ALL_DEGLITCH_Pos (5)
#define GPIO40_ALL_DEGLITCH_Msk (0x1UL << GPIO40_ALL_DEGLITCH_Pos)

typedef enum
{
    GPIO40_BIT_DEGLITCH_DISABLE     = 0,  /*!< Disable input deglitch   */
    GPIO40_BIT_DEGLITCH_ENABLE      = 1,  /*!< Enable input deglitch    */
} GPIO40_BIT_DEGLITCH;

#define GPIO40_ALL_DEGLITCH_DISABLE     ((0x0UL) << GPIO40_ALL_DEGLITCH_Pos)
#define GPIO40_ALL_DEGLITCH_ENABLE      ((0x1UL) << GPIO40_ALL_DEGLITCH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO40          STRENGTH
 *  @access     PINMUX->GPIO40.bit.STRENGTH
 *  @brief      Output driving strength
 */
#define GPIO40_ALL_STRENGTH_Pos (6)
#define GPIO40_ALL_STRENGTH_Msk (0x3UL << GPIO40_ALL_STRENGTH_Pos)

typedef enum
{
    GPIO40_BIT_STRENGTH_5MA      = 0,  /*!< 5mA    */
    GPIO40_BIT_STRENGTH_10MA     = 1,  /*!< 10mA   */
    GPIO40_BIT_STRENGTH_15MA     = 2,  /*!< 15mA   */
    GPIO40_BIT_STRENGTH_20MA     = 3,  /*!< 20mA   */
} GPIO40_BIT_STRENGTH;

#define GPIO40_ALL_STRENGTH_5MA      ((0x0UL) << GPIO40_ALL_STRENGTH_Pos)
#define GPIO40_ALL_STRENGTH_10MA     ((0x1UL) << GPIO40_ALL_STRENGTH_Pos)
#define GPIO40_ALL_STRENGTH_15MA     ((0x2UL) << GPIO40_ALL_STRENGTH_Pos)
#define GPIO40_ALL_STRENGTH_20MA     ((0x3UL) << GPIO40_ALL_STRENGTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO40          CHDFLTVAL
 *  @access     PINMUX->GPIO40.bit.CHDFLTVAL
 *  @brief      Default value for each demuxed input channel
 */
#define GPIO40_ALL_CHDFLTVAL_Pos (8)
#define GPIO40_ALL_CHDFLTVAL_Msk (0xFFUL << GPIO40_ALL_CHDFLTVAL_Pos)

#define GPIO40_BIT_CHDFLTVAL

#define GPIO40_ALL_CHDFLTVAL_(x) ((x) << GPIO40_ALL_CHDFLTVAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO40          PD
 *  @access     PINMUX->GPIO40.bit.PD
 *  @brief      Pull down enable
 */
#define GPIO40_ALL_PD_Pos (16)
#define GPIO40_ALL_PD_Msk (0xFFUL << GPIO40_ALL_PD_Pos)

#define GPIO40_BIT_PD

#define GPIO40_ALL_PD_(x) ((x) << GPIO40_ALL_PD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          GPIO40          PU
 *  @access     PINMUX->GPIO40.bit.PU
 *  @brief      Pull up enable
 */
#define GPIO40_ALL_PU_Pos (24)
#define GPIO40_ALL_PU_Msk (0xFFUL << GPIO40_ALL_PU_Pos)

#define GPIO40_BIT_PU

#define GPIO40_ALL_PU_(x) ((x) << GPIO40_ALL_PU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PINMUX          PINMUXREGKEY    KEY
 *  @access     PINMUX->PINMUXREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected pinmux registers
 */
#define PINMUXREGKEY_ALL_KEY_Pos (0)
#define PINMUXREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << PINMUXREGKEY_ALL_KEY_Pos)

#define PINMUXREGKEY_BIT_KEY

#define PINMUXREGKEY_ALL_KEY_(x) ((x) << PINMUXREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     EPWR
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZFLT       EPWRTZ0
 *  @access     EPWR->EPWRTZFLT.bit.EPWRTZ0
 *  @brief      Filtered EPWRTZ0 event without latch
 */
#define EPWRTZFLT_ALL_EPWRTZ0_Pos (0)
#define EPWRTZFLT_ALL_EPWRTZ0_Msk (0x1UL << EPWRTZFLT_ALL_EPWRTZ0_Pos)

typedef enum
{
    EPWRTZFLT_BIT_EPWRTZ0_NOT_OCCUR     = 0,  /*!< EPWRTZ0 event does not happen   */
    EPWRTZFLT_BIT_EPWRTZ0_OCCUR         = 1,  /*!< EPWRTZ0 event happened          */
} EPWRTZFLT_BIT_EPWRTZ0;

#define EPWRTZFLT_ALL_EPWRTZ0_NOT_OCCUR     ((0x0UL) << EPWRTZFLT_ALL_EPWRTZ0_Pos)
#define EPWRTZFLT_ALL_EPWRTZ0_OCCUR         ((0x1UL) << EPWRTZFLT_ALL_EPWRTZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZFLT       EPWRTZ1
 *  @access     EPWR->EPWRTZFLT.bit.EPWRTZ1
 *  @brief      Filtered EPWRTZ1 event without latch
 */
#define EPWRTZFLT_ALL_EPWRTZ1_Pos (1)
#define EPWRTZFLT_ALL_EPWRTZ1_Msk (0x1UL << EPWRTZFLT_ALL_EPWRTZ1_Pos)

typedef enum
{
    EPWRTZFLT_BIT_EPWRTZ1_NOT_OCCUR     = 0,  /*!< EPWRTZ1 event does not happen   */
    EPWRTZFLT_BIT_EPWRTZ1_OCCUR         = 1,  /*!< EPWRTZ1 event happened          */
} EPWRTZFLT_BIT_EPWRTZ1;

#define EPWRTZFLT_ALL_EPWRTZ1_NOT_OCCUR     ((0x0UL) << EPWRTZFLT_ALL_EPWRTZ1_Pos)
#define EPWRTZFLT_ALL_EPWRTZ1_OCCUR         ((0x1UL) << EPWRTZFLT_ALL_EPWRTZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZSTS       EPWRTZ0
 *  @access     EPWR->EPWRTZSTS.bit.EPWRTZ0
 *  @brief      Latched EPWRTZ0 event after filtering
 */
#define EPWRTZSTS_ALL_EPWRTZ0_Pos (0)
#define EPWRTZSTS_ALL_EPWRTZ0_Msk (0x1UL << EPWRTZSTS_ALL_EPWRTZ0_Pos)

typedef enum
{
    EPWRTZSTS_BIT_EPWRTZ0_NOT_OCCUR     = 0,  /*!< EPWRTZ0 event does not happen   */
    EPWRTZSTS_BIT_EPWRTZ0_OCCUR         = 1,  /*!< EPWRTZ0 event happened          */
} EPWRTZSTS_BIT_EPWRTZ0;

#define EPWRTZSTS_ALL_EPWRTZ0_NOT_OCCUR     ((0x0UL) << EPWRTZSTS_ALL_EPWRTZ0_Pos)
#define EPWRTZSTS_ALL_EPWRTZ0_OCCUR         ((0x1UL) << EPWRTZSTS_ALL_EPWRTZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZSTS       EPWRTZ1
 *  @access     EPWR->EPWRTZSTS.bit.EPWRTZ1
 *  @brief      Latched EPWRTZ1 event after filtering
 */
#define EPWRTZSTS_ALL_EPWRTZ1_Pos (1)
#define EPWRTZSTS_ALL_EPWRTZ1_Msk (0x1UL << EPWRTZSTS_ALL_EPWRTZ1_Pos)

typedef enum
{
    EPWRTZSTS_BIT_EPWRTZ1_NOT_OCCUR     = 0,  /*!< EPWRTZ1 event does not happen   */
    EPWRTZSTS_BIT_EPWRTZ1_OCCUR         = 1,  /*!< EPWRTZ1 event happened          */
} EPWRTZSTS_BIT_EPWRTZ1;

#define EPWRTZSTS_ALL_EPWRTZ1_NOT_OCCUR     ((0x0UL) << EPWRTZSTS_ALL_EPWRTZ1_Pos)
#define EPWRTZSTS_ALL_EPWRTZ1_OCCUR         ((0x1UL) << EPWRTZSTS_ALL_EPWRTZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZCLR       EPWRTZ0
 *  @access     EPWR->EPWRTZCLR.bit.EPWRTZ0
 *  @brief      Latched EPWRTZ0 status clear
 */
#define EPWRTZCLR_ALL_EPWRTZ0_Pos (0)
#define EPWRTZCLR_ALL_EPWRTZ0_Msk (0x1UL << EPWRTZCLR_ALL_EPWRTZ0_Pos)

typedef enum
{
    EPWRTZCLR_BIT_EPWRTZ0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                        */
    EPWRTZCLR_BIT_EPWRTZ0_CLEAR         = 1,  /*!< Write a 1 clears  EPWRTZSTS[EPWRTZ0]. This bit is self-cleared.   */
} EPWRTZCLR_BIT_EPWRTZ0;

#define EPWRTZCLR_ALL_EPWRTZ0_NO_EFFECT     ((0x0UL) << EPWRTZCLR_ALL_EPWRTZ0_Pos)
#define EPWRTZCLR_ALL_EPWRTZ0_CLEAR         ((0x1UL) << EPWRTZCLR_ALL_EPWRTZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZCLR       EPWRTZ1
 *  @access     EPWR->EPWRTZCLR.bit.EPWRTZ1
 *  @brief      Latched EPWRTZ1 status clear
 */
#define EPWRTZCLR_ALL_EPWRTZ1_Pos (1)
#define EPWRTZCLR_ALL_EPWRTZ1_Msk (0x1UL << EPWRTZCLR_ALL_EPWRTZ1_Pos)

typedef enum
{
    EPWRTZCLR_BIT_EPWRTZ1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                       */
    EPWRTZCLR_BIT_EPWRTZ1_CLEAR         = 1,  /*!< Write a 1 clears EPWRTZSTS[EPWRTZ1]. This bit is self-cleared.   */
} EPWRTZCLR_BIT_EPWRTZ1;

#define EPWRTZCLR_ALL_EPWRTZ1_NO_EFFECT     ((0x0UL) << EPWRTZCLR_ALL_EPWRTZ1_Pos)
#define EPWRTZCLR_ALL_EPWRTZ1_CLEAR         ((0x1UL) << EPWRTZCLR_ALL_EPWRTZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      SEL4PWM
 *  @access     EPWR->EPWRTZ0CTL.bit.SEL4PWM
 *  @brief      Trip-zone output select for PWM
 */
#define EPWRTZ0CTL_ALL_SEL4PWM_Pos (0)
#define EPWRTZ0CTL_ALL_SEL4PWM_Msk (0x7UL << EPWRTZ0CTL_ALL_SEL4PWM_Pos)

typedef enum
{
    EPWRTZ0CTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    EPWRTZ0CTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    EPWRTZ0CTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    EPWRTZ0CTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    EPWRTZ0CTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    EPWRTZ0CTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    EPWRTZ0CTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    EPWRTZ0CTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} EPWRTZ0CTL_BIT_SEL4PWM;

#define EPWRTZ0CTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << EPWRTZ0CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ0CTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << EPWRTZ0CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ0CTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << EPWRTZ0CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ0CTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << EPWRTZ0CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ0CTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << EPWRTZ0CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ0CTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << EPWRTZ0CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ0CTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << EPWRTZ0CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ0CTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << EPWRTZ0CTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      POL4PWM
 *  @access     EPWR->EPWRTZ0CTL.bit.POL4PWM
 *  @brief      Trip-zone output polarity for PWM
 */
#define EPWRTZ0CTL_ALL_POL4PWM_Pos (3)
#define EPWRTZ0CTL_ALL_POL4PWM_Msk (0x1UL << EPWRTZ0CTL_ALL_POL4PWM_Pos)

typedef enum
{
    EPWRTZ0CTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 upon EPWRTZ0 event   */
    EPWRTZ0CTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 upon EPWRTZ0 event   */
} EPWRTZ0CTL_BIT_POL4PWM;

#define EPWRTZ0CTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << EPWRTZ0CTL_ALL_POL4PWM_Pos)
#define EPWRTZ0CTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << EPWRTZ0CTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      SEL4GPIO
 *  @access     EPWR->EPWRTZ0CTL.bit.SEL4GPIO
 *  @brief      Trip-zone output select for GPIO
 */
#define EPWRTZ0CTL_ALL_SEL4GPIO_Pos (4)
#define EPWRTZ0CTL_ALL_SEL4GPIO_Msk (0x7UL << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    EPWRTZ0CTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    EPWRTZ0CTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    EPWRTZ0CTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    EPWRTZ0CTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    EPWRTZ0CTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    EPWRTZ0CTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    EPWRTZ0CTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    EPWRTZ0CTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} EPWRTZ0CTL_BIT_SEL4GPIO;

#define EPWRTZ0CTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ0CTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ0CTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ0CTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ0CTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ0CTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ0CTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ0CTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << EPWRTZ0CTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      POL4GPIO
 *  @access     EPWR->EPWRTZ0CTL.bit.POL4GPIO
 *  @brief      Trip-zone output polarity for GPIO
 */
#define EPWRTZ0CTL_ALL_POL4GPIO_Pos (7)
#define EPWRTZ0CTL_ALL_POL4GPIO_Msk (0x1UL << EPWRTZ0CTL_ALL_POL4GPIO_Pos)

typedef enum
{
    EPWRTZ0CTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 upon EPWRTZ0 event   */
    EPWRTZ0CTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 upon EPWRTZ0 event   */
} EPWRTZ0CTL_BIT_POL4GPIO;

#define EPWRTZ0CTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << EPWRTZ0CTL_ALL_POL4GPIO_Pos)
#define EPWRTZ0CTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << EPWRTZ0CTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      IE
 *  @access     EPWR->EPWRTZ0CTL.bit.IE
 *  @brief      Trip-zone event input enable
 */
#define EPWRTZ0CTL_ALL_IE_Pos (8)
#define EPWRTZ0CTL_ALL_IE_Msk (0x1UL << EPWRTZ0CTL_ALL_IE_Pos)

typedef enum
{
    EPWRTZ0CTL_BIT_IE_DISABLE     = 0,  /*!< Disable trip-zone input   */
    EPWRTZ0CTL_BIT_IE_ENABLE      = 1,  /*!< Enable trip-zone input    */
} EPWRTZ0CTL_BIT_IE;

#define EPWRTZ0CTL_ALL_IE_DISABLE     ((0x0UL) << EPWRTZ0CTL_ALL_IE_Pos)
#define EPWRTZ0CTL_ALL_IE_ENABLE      ((0x1UL) << EPWRTZ0CTL_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      INPOL
 *  @access     EPWR->EPWRTZ0CTL.bit.INPOL
 *  @brief      Trip-zone input polarity
 */
#define EPWRTZ0CTL_ALL_INPOL_Pos (9)
#define EPWRTZ0CTL_ALL_INPOL_Msk (0x1UL << EPWRTZ0CTL_ALL_INPOL_Pos)

typedef enum
{
    EPWRTZ0CTL_BIT_INPOL_ACTIVE_LOW      = 0,  /*!< Trip-zone event happens when input is low    */
    EPWRTZ0CTL_BIT_INPOL_ACTIVE_HIGH     = 1,  /*!< Trip-zone event happens when input is high   */
} EPWRTZ0CTL_BIT_INPOL;

#define EPWRTZ0CTL_ALL_INPOL_ACTIVE_LOW      ((0x0UL) << EPWRTZ0CTL_ALL_INPOL_Pos)
#define EPWRTZ0CTL_ALL_INPOL_ACTIVE_HIGH     ((0x1UL) << EPWRTZ0CTL_ALL_INPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      SYNCCLREN
 *  @access     EPWR->EPWRTZ0CTL.bit.SYNCCLREN
 *  @brief      Enable latched EPWRTZ0 status clear by PWMSYNC
 */
#define EPWRTZ0CTL_ALL_SYNCCLREN_Pos (10)
#define EPWRTZ0CTL_ALL_SYNCCLREN_Msk (0x1UL << EPWRTZ0CTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    EPWRTZ0CTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched EPWRTZ0 status   */
    EPWRTZ0CTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched EPWRTZ0 status        */
} EPWRTZ0CTL_BIT_SYNCCLREN;

#define EPWRTZ0CTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << EPWRTZ0CTL_ALL_SYNCCLREN_Pos)
#define EPWRTZ0CTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << EPWRTZ0CTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      FLTDIV
 *  @access     EPWR->EPWRTZ0CTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define EPWRTZ0CTL_ALL_FLTDIV_Pos (11)
#define EPWRTZ0CTL_ALL_FLTDIV_Msk (0x3FFUL << EPWRTZ0CTL_ALL_FLTDIV_Pos)

#define EPWRTZ0CTL_BIT_FLTDIV

#define EPWRTZ0CTL_ALL_FLTDIV_(x) ((x) << EPWRTZ0CTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      FLTWIN
 *  @access     EPWR->EPWRTZ0CTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define EPWRTZ0CTL_ALL_FLTWIN_Pos (21)
#define EPWRTZ0CTL_ALL_FLTWIN_Msk (0x1FUL << EPWRTZ0CTL_ALL_FLTWIN_Pos)

#define EPWRTZ0CTL_BIT_FLTWIN

#define EPWRTZ0CTL_ALL_FLTWIN_(x) ((x) << EPWRTZ0CTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      FLTTH
 *  @access     EPWR->EPWRTZ0CTL.bit.FLTTH
 *  @brief      Filter's threhold is (FLTTH+1) 1's/0's for output to toggle
 */
#define EPWRTZ0CTL_ALL_FLTTH_Pos (26)
#define EPWRTZ0CTL_ALL_FLTTH_Msk (0x1FUL << EPWRTZ0CTL_ALL_FLTTH_Pos)

#define EPWRTZ0CTL_BIT_FLTTH

#define EPWRTZ0CTL_ALL_FLTTH_(x) ((x) << EPWRTZ0CTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ0CTL      FLTRST
 *  @access     EPWR->EPWRTZ0CTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define EPWRTZ0CTL_ALL_FLTRST_Pos (31)
#define EPWRTZ0CTL_ALL_FLTRST_Msk (0x1UL << EPWRTZ0CTL_ALL_FLTRST_Pos)

typedef enum
{
    EPWRTZ0CTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    EPWRTZ0CTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} EPWRTZ0CTL_BIT_FLTRST;

#define EPWRTZ0CTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << EPWRTZ0CTL_ALL_FLTRST_Pos)
#define EPWRTZ0CTL_ALL_FLTRST_RESET         ((0x1UL) << EPWRTZ0CTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      SEL4PWM
 *  @access     EPWR->EPWRTZ1CTL.bit.SEL4PWM
 *  @brief      Trip-zone output select for PWM
 */
#define EPWRTZ1CTL_ALL_SEL4PWM_Pos (0)
#define EPWRTZ1CTL_ALL_SEL4PWM_Msk (0x7UL << EPWRTZ1CTL_ALL_SEL4PWM_Pos)

typedef enum
{
    EPWRTZ1CTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    EPWRTZ1CTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    EPWRTZ1CTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    EPWRTZ1CTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    EPWRTZ1CTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    EPWRTZ1CTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    EPWRTZ1CTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    EPWRTZ1CTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} EPWRTZ1CTL_BIT_SEL4PWM;

#define EPWRTZ1CTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << EPWRTZ1CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ1CTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << EPWRTZ1CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ1CTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << EPWRTZ1CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ1CTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << EPWRTZ1CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ1CTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << EPWRTZ1CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ1CTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << EPWRTZ1CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ1CTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << EPWRTZ1CTL_ALL_SEL4PWM_Pos)
#define EPWRTZ1CTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << EPWRTZ1CTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      POL4PWM
 *  @access     EPWR->EPWRTZ1CTL.bit.POL4PWM
 *  @brief      Trip-zone output polarity for PWM
 */
#define EPWRTZ1CTL_ALL_POL4PWM_Pos (3)
#define EPWRTZ1CTL_ALL_POL4PWM_Msk (0x1UL << EPWRTZ1CTL_ALL_POL4PWM_Pos)

typedef enum
{
    EPWRTZ1CTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 upon EPWRTZ1 event   */
    EPWRTZ1CTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 upon EPWRTZ1 event   */
} EPWRTZ1CTL_BIT_POL4PWM;

#define EPWRTZ1CTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << EPWRTZ1CTL_ALL_POL4PWM_Pos)
#define EPWRTZ1CTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << EPWRTZ1CTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      SEL4GPIO
 *  @access     EPWR->EPWRTZ1CTL.bit.SEL4GPIO
 *  @brief      Trip-zone output select for GPIO
 */
#define EPWRTZ1CTL_ALL_SEL4GPIO_Pos (4)
#define EPWRTZ1CTL_ALL_SEL4GPIO_Msk (0x7UL << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    EPWRTZ1CTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    EPWRTZ1CTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    EPWRTZ1CTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    EPWRTZ1CTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    EPWRTZ1CTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    EPWRTZ1CTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    EPWRTZ1CTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    EPWRTZ1CTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} EPWRTZ1CTL_BIT_SEL4GPIO;

#define EPWRTZ1CTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ1CTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ1CTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ1CTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ1CTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ1CTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ1CTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)
#define EPWRTZ1CTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << EPWRTZ1CTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      POL4GPIO
 *  @access     EPWR->EPWRTZ1CTL.bit.POL4GPIO
 *  @brief      Trip-zone output polarity for GPIO
 */
#define EPWRTZ1CTL_ALL_POL4GPIO_Pos (7)
#define EPWRTZ1CTL_ALL_POL4GPIO_Msk (0x1UL << EPWRTZ1CTL_ALL_POL4GPIO_Pos)

typedef enum
{
    EPWRTZ1CTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 upon EPWRTZ1 event   */
    EPWRTZ1CTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 upon EPWRTZ1 event   */
} EPWRTZ1CTL_BIT_POL4GPIO;

#define EPWRTZ1CTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << EPWRTZ1CTL_ALL_POL4GPIO_Pos)
#define EPWRTZ1CTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << EPWRTZ1CTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      IE
 *  @access     EPWR->EPWRTZ1CTL.bit.IE
 *  @brief      Trip-zone event input enable
 */
#define EPWRTZ1CTL_ALL_IE_Pos (8)
#define EPWRTZ1CTL_ALL_IE_Msk (0x1UL << EPWRTZ1CTL_ALL_IE_Pos)

typedef enum
{
    EPWRTZ1CTL_BIT_IE_DISABLE     = 0,  /*!< Disable trip-zone input   */
    EPWRTZ1CTL_BIT_IE_ENABLE      = 1,  /*!< Enable trip-zone input    */
} EPWRTZ1CTL_BIT_IE;

#define EPWRTZ1CTL_ALL_IE_DISABLE     ((0x0UL) << EPWRTZ1CTL_ALL_IE_Pos)
#define EPWRTZ1CTL_ALL_IE_ENABLE      ((0x1UL) << EPWRTZ1CTL_ALL_IE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      INPOL
 *  @access     EPWR->EPWRTZ1CTL.bit.INPOL
 *  @brief      Trip-zone input polarity
 */
#define EPWRTZ1CTL_ALL_INPOL_Pos (9)
#define EPWRTZ1CTL_ALL_INPOL_Msk (0x1UL << EPWRTZ1CTL_ALL_INPOL_Pos)

typedef enum
{
    EPWRTZ1CTL_BIT_INPOL_ACTIVE_LOW      = 0,  /*!< Trip-zone event happens when input is low    */
    EPWRTZ1CTL_BIT_INPOL_ACTIVE_HIGH     = 1,  /*!< Trip-zone event happens when input is high   */
} EPWRTZ1CTL_BIT_INPOL;

#define EPWRTZ1CTL_ALL_INPOL_ACTIVE_LOW      ((0x0UL) << EPWRTZ1CTL_ALL_INPOL_Pos)
#define EPWRTZ1CTL_ALL_INPOL_ACTIVE_HIGH     ((0x1UL) << EPWRTZ1CTL_ALL_INPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      SYNCCLREN
 *  @access     EPWR->EPWRTZ1CTL.bit.SYNCCLREN
 *  @brief      Enable latched EPWRTZ1 status clear by PWMSYNC
 */
#define EPWRTZ1CTL_ALL_SYNCCLREN_Pos (10)
#define EPWRTZ1CTL_ALL_SYNCCLREN_Msk (0x1UL << EPWRTZ1CTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    EPWRTZ1CTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched EPWRTZ1 status   */
    EPWRTZ1CTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched EPWRTZ1 status        */
} EPWRTZ1CTL_BIT_SYNCCLREN;

#define EPWRTZ1CTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << EPWRTZ1CTL_ALL_SYNCCLREN_Pos)
#define EPWRTZ1CTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << EPWRTZ1CTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      FLTDIV
 *  @access     EPWR->EPWRTZ1CTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define EPWRTZ1CTL_ALL_FLTDIV_Pos (11)
#define EPWRTZ1CTL_ALL_FLTDIV_Msk (0x3FFUL << EPWRTZ1CTL_ALL_FLTDIV_Pos)

#define EPWRTZ1CTL_BIT_FLTDIV

#define EPWRTZ1CTL_ALL_FLTDIV_(x) ((x) << EPWRTZ1CTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      FLTWIN
 *  @access     EPWR->EPWRTZ1CTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define EPWRTZ1CTL_ALL_FLTWIN_Pos (21)
#define EPWRTZ1CTL_ALL_FLTWIN_Msk (0x1FUL << EPWRTZ1CTL_ALL_FLTWIN_Pos)

#define EPWRTZ1CTL_BIT_FLTWIN

#define EPWRTZ1CTL_ALL_FLTWIN_(x) ((x) << EPWRTZ1CTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      FLTTH
 *  @access     EPWR->EPWRTZ1CTL.bit.FLTTH
 *  @brief      Filter's threhold is (FLTTH+1) 1's/0's for output to toggle
 */
#define EPWRTZ1CTL_ALL_FLTTH_Pos (26)
#define EPWRTZ1CTL_ALL_FLTTH_Msk (0x1FUL << EPWRTZ1CTL_ALL_FLTTH_Pos)

#define EPWRTZ1CTL_BIT_FLTTH

#define EPWRTZ1CTL_ALL_FLTTH_(x) ((x) << EPWRTZ1CTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRTZ1CTL      FLTRST
 *  @access     EPWR->EPWRTZ1CTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define EPWRTZ1CTL_ALL_FLTRST_Pos (31)
#define EPWRTZ1CTL_ALL_FLTRST_Msk (0x1UL << EPWRTZ1CTL_ALL_FLTRST_Pos)

typedef enum
{
    EPWRTZ1CTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    EPWRTZ1CTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} EPWRTZ1CTL_BIT_FLTRST;

#define EPWRTZ1CTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << EPWRTZ1CTL_ALL_FLTRST_Pos)
#define EPWRTZ1CTL_ALL_FLTRST_RESET         ((0x1UL) << EPWRTZ1CTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRCTL         EN
 *  @access     EPWR->EPWRCTL.bit.EN
 *  @brief      Enable the ePower module
 */
#define EPWRCTL_ALL_EN_Pos (0)
#define EPWRCTL_ALL_EN_Msk (0x1UL << EPWRCTL_ALL_EN_Pos)

typedef enum
{
    EPWRCTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    EPWRCTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} EPWRCTL_BIT_EN;

#define EPWRCTL_ALL_EN_DISABLE     ((0x0UL) << EPWRCTL_ALL_EN_Pos)
#define EPWRCTL_ALL_EN_ENABLE      ((0x1UL) << EPWRCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRCTL         ENSPI
 *  @access     EPWR->EPWRCTL.bit.ENSPI
 *  @brief      Enable SPI interface with the ePower module
 */
#define EPWRCTL_ALL_ENSPI_Pos (1)
#define EPWRCTL_ALL_ENSPI_Msk (0x1UL << EPWRCTL_ALL_ENSPI_Pos)

typedef enum
{
    EPWRCTL_BIT_ENSPI_DISABLE     = 0,  /*!< Disable   */
    EPWRCTL_BIT_ENSPI_ENABLE      = 1,  /*!< Enable    */
} EPWRCTL_BIT_ENSPI;

#define EPWRCTL_ALL_ENSPI_DISABLE     ((0x0UL) << EPWRCTL_ALL_ENSPI_Pos)
#define EPWRCTL_ALL_ENSPI_ENABLE      ((0x1UL) << EPWRCTL_ALL_ENSPI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRCTL         SPIDIR
 *  @access     EPWR->EPWRCTL.bit.SPIDIR
 *  @brief      SPI TX/RX direction
 */
#define EPWRCTL_ALL_SPIDIR_Pos (2)
#define EPWRCTL_ALL_SPIDIR_Msk (0x1UL << EPWRCTL_ALL_SPIDIR_Pos)

typedef enum
{
    EPWRCTL_BIT_SPIDIR_RECEIVE_DATA     = 0,  /*!< Receive data from pre-driver module   */
    EPWRCTL_BIT_SPIDIR_SEND_DATA        = 1,  /*!< Transmit data to pre-dirver module    */
} EPWRCTL_BIT_SPIDIR;

#define EPWRCTL_ALL_SPIDIR_RECEIVE_DATA     ((0x0UL) << EPWRCTL_ALL_SPIDIR_Pos)
#define EPWRCTL_ALL_SPIDIR_SEND_DATA        ((0x1UL) << EPWRCTL_ALL_SPIDIR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRCTL         SYNCSEL0
 *  @access     EPWR->EPWRCTL.bit.SYNCSEL0
 *  @brief      Select SYNC from PWM[SYNCSEL0] to clear latched EPWRTZ0 status
 */
#define EPWRCTL_ALL_SYNCSEL0_Pos (3)
#define EPWRCTL_ALL_SYNCSEL0_Msk (0x7UL << EPWRCTL_ALL_SYNCSEL0_Pos)

#define EPWRCTL_BIT_SYNCSEL0

#define EPWRCTL_ALL_SYNCSEL0_(x) ((x) << EPWRCTL_ALL_SYNCSEL0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRCTL         SYNCSEL1
 *  @access     EPWR->EPWRCTL.bit.SYNCSEL1
 *  @brief      Select SYNC from PWM[SYNCSEL1] to clear latched EPWRTZ1 status
 */
#define EPWRCTL_ALL_SYNCSEL1_Pos (6)
#define EPWRCTL_ALL_SYNCSEL1_Msk (0x7UL << EPWRCTL_ALL_SYNCSEL1_Pos)

#define EPWRCTL_BIT_SYNCSEL1

#define EPWRCTL_ALL_SYNCSEL1_(x) ((x) << EPWRCTL_ALL_SYNCSEL1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRCTL         TZSEL4GPIO11
 *  @access     EPWR->EPWRCTL.bit.TZSEL4GPIO11
 *  @brief      Select which TZ signal is to output to GPIO11
 */
#define EPWRCTL_ALL_TZSEL4GPIO11_Pos (9)
#define EPWRCTL_ALL_TZSEL4GPIO11_Msk (0x1UL << EPWRCTL_ALL_TZSEL4GPIO11_Pos)

typedef enum
{
    EPWRCTL_BIT_TZSEL4GPIO11_EPWRTZ0     = 0,  /*!< EPWRTZ0   */
    EPWRCTL_BIT_TZSEL4GPIO11_EPWRTZ1     = 1,  /*!< EPWRTZ1   */
} EPWRCTL_BIT_TZSEL4GPIO11;

#define EPWRCTL_ALL_TZSEL4GPIO11_EPWRTZ0     ((0x0UL) << EPWRCTL_ALL_TZSEL4GPIO11_Pos)
#define EPWRCTL_ALL_TZSEL4GPIO11_EPWRTZ1     ((0x1UL) << EPWRCTL_ALL_TZSEL4GPIO11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   EPWR            EPWRREGKEY      KEY
 *  @access     EPWR->EPWRREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected registers
 */
#define EPWRREGKEY_ALL_KEY_Pos (0)
#define EPWRREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << EPWRREGKEY_ALL_KEY_Pos)

#define EPWRREGKEY_BIT_KEY

#define EPWRREGKEY_ALL_KEY_(x) ((x) << EPWRREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     ENGR
*
*
********************************************************************************/



/********************************************************************************
*
* Module Name     WDT
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTLOAD         VAL
 *  @access     WDT->WDTLOAD.bit.VAL
 *  @brief      Load value
 *              The value from which the counter is to decrease. When this register is written to,
 *              the count is immediately restarted from the new value. The minimum valid value is
 *              1.
 */
#define WDTLOAD_ALL_VAL_Pos (0)
#define WDTLOAD_ALL_VAL_Msk (0xFFFFFFFFUL << WDTLOAD_ALL_VAL_Pos)

#define WDTLOAD_BIT_VAL

#define WDTLOAD_ALL_VAL_(x) ((x) << WDTLOAD_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTCNT          VAL
 *  @access     WDT->WDTCNT.bit.VAL
 *  @brief      Current value of the decrementing counter.
 */
#define WDTCNT_ALL_VAL_Pos (0)
#define WDTCNT_ALL_VAL_Msk (0xFFFFFFFFUL << WDTCNT_ALL_VAL_Pos)

#define WDTCNT_BIT_VAL

#define WDTCNT_ALL_VAL_(x) ((x) << WDTCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTCTL          INTEN
 *  @access     WDT->WDTCTL.bit.INTEN
 *  @brief      Enable the interrupt event
 *              Reloads the counter from WDTLOAD when the interrupt upon a rising edge of this bit.
 */
#define WDTCTL_ALL_INTEN_Pos (0)
#define WDTCTL_ALL_INTEN_Msk (0x1UL << WDTCTL_ALL_INTEN_Pos)

typedef enum
{
    WDTCTL_BIT_INTEN_DISABLE     = 0,  /*!< Disable the counter and the interrupt   */
    WDTCTL_BIT_INTEN_ENABLE      = 1,  /*!< Enable the counter and the interrupt    */
} WDTCTL_BIT_INTEN;

#define WDTCTL_ALL_INTEN_DISABLE     ((0x0UL) << WDTCTL_ALL_INTEN_Pos)
#define WDTCTL_ALL_INTEN_ENABLE      ((0x1UL) << WDTCTL_ALL_INTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTCTL          RSTEN
 *  @access     WDT->WDTCTL.bit.RSTEN
 *  @brief      Enable watchdog reset output, Acts as a mask for the reset output.
 */
#define WDTCTL_ALL_RSTEN_Pos (1)
#define WDTCTL_ALL_RSTEN_Msk (0x1UL << WDTCTL_ALL_RSTEN_Pos)

typedef enum
{
    WDTCTL_BIT_RSTEN_DISABLE     = 0,  /*!< Disable the reset request   */
    WDTCTL_BIT_RSTEN_ENABLE      = 1,  /*!< Enable the reset request    */
} WDTCTL_BIT_RSTEN;

#define WDTCTL_ALL_RSTEN_DISABLE     ((0x0UL) << WDTCTL_ALL_RSTEN_Pos)
#define WDTCTL_ALL_RSTEN_ENABLE      ((0x1UL) << WDTCTL_ALL_RSTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTCTL          HALTEDRUN
 *  @access     WDT->WDTCTL.bit.HALTEDRUN
 *  @brief      Allow watchdog to run during core halted mode
 */
#define WDTCTL_ALL_HALTEDRUN_Pos (2)
#define WDTCTL_ALL_HALTEDRUN_Msk (0x1UL << WDTCTL_ALL_HALTEDRUN_Pos)

typedef enum
{
    WDTCTL_BIT_HALTEDRUN_DISABLE     = 0,  /*!< Disable watchdog when core is in halted mode   */
    WDTCTL_BIT_HALTEDRUN_ENABLE      = 1,  /*!< Enable watchdog when core is in halted mode    */
} WDTCTL_BIT_HALTEDRUN;

#define WDTCTL_ALL_HALTEDRUN_DISABLE     ((0x0UL) << WDTCTL_ALL_HALTEDRUN_Pos)
#define WDTCTL_ALL_HALTEDRUN_ENABLE      ((0x1UL) << WDTCTL_ALL_HALTEDRUN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTCTL          LOCKUPRUN
 *  @access     WDT->WDTCTL.bit.LOCKUPRUN
 *  @brief      Allow watchdog to run during core lockup mode
 */
#define WDTCTL_ALL_LOCKUPRUN_Pos (3)
#define WDTCTL_ALL_LOCKUPRUN_Msk (0x1UL << WDTCTL_ALL_LOCKUPRUN_Pos)

typedef enum
{
    WDTCTL_BIT_LOCKUPRUN_DISABLE     = 0,  /*!< Disable watchdog when core is in lockup mode   */
    WDTCTL_BIT_LOCKUPRUN_ENABLE      = 1,  /*!< Enable watchdog when core is in lockup mode    */
} WDTCTL_BIT_LOCKUPRUN;

#define WDTCTL_ALL_LOCKUPRUN_DISABLE     ((0x0UL) << WDTCTL_ALL_LOCKUPRUN_Pos)
#define WDTCTL_ALL_LOCKUPRUN_ENABLE      ((0x1UL) << WDTCTL_ALL_LOCKUPRUN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTIC           VAL
 *  @access     WDT->WDTIC.bit.VAL
 *  @brief      Interrupt clear register
 *              A write of any value to this register clears the watchdog interrupt, and reloads
 *              the counter from WDTLOAD.
 */
#define WDTIC_ALL_VAL_Pos (0)
#define WDTIC_ALL_VAL_Msk (0xFFFFFFFFUL << WDTIC_ALL_VAL_Pos)

#define WDTIC_BIT_VAL

#define WDTIC_ALL_VAL_(x) ((x) << WDTIC_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTRAWIF        RAWINT
 *  @access     WDT->WDTRAWIF.bit.RAWINT
 *  @brief      Raw interrupt status from the counter
 *              This register indicates the raw interrupt status from the counter. The value is ANDed
 *              with WDTCTL.INTEN to create the masked interrupt, which is passed to the interrupt
 *              output pin.
 */
#define WDTRAWIF_ALL_RAWINT_Pos (0)
#define WDTRAWIF_ALL_RAWINT_Msk (0x1UL << WDTRAWIF_ALL_RAWINT_Pos)

typedef enum
{
    WDTRAWIF_BIT_RAWINT_NOT_OCCUR     = 0,  /*!< Interrupt not occurred   */
    WDTRAWIF_BIT_RAWINT_OCCUR         = 1,  /*!< Interrupt occurred       */
} WDTRAWIF_BIT_RAWINT;

#define WDTRAWIF_ALL_RAWINT_NOT_OCCUR     ((0x0UL) << WDTRAWIF_ALL_RAWINT_Pos)
#define WDTRAWIF_ALL_RAWINT_OCCUR         ((0x1UL) << WDTRAWIF_ALL_RAWINT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTIF           INT
 *  @access     WDT->WDTIF.bit.INT
 *  @brief      Masked interrupt status from the counter
 *              This register indicates the masked interrupt status from the counter. This value
 *              is the logical AND of WDTRAWIF.RAWINT and WDTCTL.INTEN, and is the same value that
 *              is passed to the interrupt output pin.
 */
#define WDTIF_ALL_INT_Pos (0)
#define WDTIF_ALL_INT_Msk (0x1UL << WDTIF_ALL_INT_Pos)

typedef enum
{
    WDTIF_BIT_INT_NOT_OCCUR     = 0,  /*!< Interrupt not occurred   */
    WDTIF_BIT_INT_OCCUR         = 1,  /*!< Interrupt occurred       */
} WDTIF_BIT_INT;

#define WDTIF_ALL_INT_NOT_OCCUR     ((0x0UL) << WDTIF_ALL_INT_Pos)
#define WDTIF_ALL_INT_OCCUR         ((0x1UL) << WDTIF_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTREGKEY       LCKSTS
 *  @access     WDT->WDTREGKEY.bit.LCKSTS
 *  @brief      Register write lock status
 */
#define WDTREGKEY_ALL_LCKSTS_Pos (0)
#define WDTREGKEY_ALL_LCKSTS_Msk (0x1UL << WDTREGKEY_ALL_LCKSTS_Pos)

typedef enum
{
    WDTREGKEY_BIT_LCKSTS_UNLOCK     = 0,  /*!< Write access to all other registers is enabled (not locked)   */
    WDTREGKEY_BIT_LCKSTS_LOCK       = 1,  /*!< Write access to all other registers is disabled (locked)      */
} WDTREGKEY_BIT_LCKSTS;

#define WDTREGKEY_ALL_LCKSTS_UNLOCK     ((0x0UL) << WDTREGKEY_ALL_LCKSTS_Pos)
#define WDTREGKEY_ALL_LCKSTS_LOCK       ((0x1UL) << WDTREGKEY_ALL_LCKSTS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   WDT             WDTREGKEY       LCKCTL
 *  @access     WDT->WDTREGKEY.bit.LCKCTL
 *  @brief      Enable register writes
 *              Enable write access to all other registers by writing 0x1ACCE551.
 *              Disable write access by writing any other value.
 */
#define WDTREGKEY_ALL_LCKCTL_Pos (1)
#define WDTREGKEY_ALL_LCKCTL_Msk (0x7FFFFFFFUL << WDTREGKEY_ALL_LCKCTL_Pos)

#define WDTREGKEY_BIT_LCKCTL

#define WDTREGKEY_ALL_LCKCTL_(x) ((x) << WDTREGKEY_ALL_LCKCTL_Pos)



/********************************************************************************
*
* Module Name     GPIO
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GPLR0           VAL
 *  @access     GPIO->GPLR0.bit.VAL
 *  @brief      GPIOn pin level readback (n = 0~31)
 *              0: Pin level is low
 *              1: Pin level is high
 */
#define GPLR0_ALL_VAL_Pos (0)
#define GPLR0_ALL_VAL_Msk (0xFFFFFFFFUL << GPLR0_ALL_VAL_Pos)

#define GPLR0_BIT_VAL

#define GPLR0_ALL_VAL_(x) ((x) << GPLR0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GPLR1           VAL
 *  @access     GPIO->GPLR1.bit.VAL
 *  @brief      GPIOn pin level readback (n = 32~40)
 *              0: Pin level is low
 *              1: Pin level is high
 */
#define GPLR1_ALL_VAL_Pos (0)
#define GPLR1_ALL_VAL_Msk (0x1FFUL << GPLR1_ALL_VAL_Pos)

#define GPLR1_BIT_VAL

#define GPLR1_ALL_VAL_(x) ((x) << GPLR1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GPDR0           VAL
 *  @access     GPIO->GPDR0.bit.VAL
 *  @brief      Set GPIOn direction (n = 0~31)
 *              0: Set GPIOn as input
 *              1: Set GPIOn as output
 */
#define GPDR0_ALL_VAL_Pos (0)
#define GPDR0_ALL_VAL_Msk (0xFFFFFFFFUL << GPDR0_ALL_VAL_Pos)

#define GPDR0_BIT_VAL

#define GPDR0_ALL_VAL_(x) ((x) << GPDR0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GPDR1           VAL
 *  @access     GPIO->GPDR1.bit.VAL
 *  @brief      Set GPIOn direction (n = 32~40)
 *              0: Set GPIOn as input
 *              1: Set GPIOn as output
 */
#define GPDR1_ALL_VAL_Pos (0)
#define GPDR1_ALL_VAL_Msk (0x1FFUL << GPDR1_ALL_VAL_Pos)

#define GPDR1_BIT_VAL

#define GPDR1_ALL_VAL_(x) ((x) << GPDR1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GSLR0           VAL
 *  @access     GPIO->GSLR0.bit.VAL
 *  @brief      Set GPIOn output high (n = 0~31)
 *              0: Unaffected
 *              1: Set GPIOn output to high
 */
#define GSLR0_ALL_VAL_Pos (0)
#define GSLR0_ALL_VAL_Msk (0xFFFFFFFFUL << GSLR0_ALL_VAL_Pos)

#define GSLR0_BIT_VAL

#define GSLR0_ALL_VAL_(x) ((x) << GSLR0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GSLR1           VAL
 *  @access     GPIO->GSLR1.bit.VAL
 *  @brief      Set GPIOn output value (n = 32~40)
 *              0: Unaffected
 *              1: Set GPIOn output to high
 */
#define GSLR1_ALL_VAL_Pos (0)
#define GSLR1_ALL_VAL_Msk (0x1FFUL << GSLR1_ALL_VAL_Pos)

#define GSLR1_BIT_VAL

#define GSLR1_ALL_VAL_(x) ((x) << GSLR1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GCLR0           VAL
 *  @access     GPIO->GCLR0.bit.VAL
 *  @brief      Set GPIOn output low (n = 0~31)
 *              0: Unaffected
 *              1: Set GPIOn output to low
 */
#define GCLR0_ALL_VAL_Pos (0)
#define GCLR0_ALL_VAL_Msk (0xFFFFFFFFUL << GCLR0_ALL_VAL_Pos)

#define GCLR0_BIT_VAL

#define GCLR0_ALL_VAL_(x) ((x) << GCLR0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GCLR1           VAL
 *  @access     GPIO->GCLR1.bit.VAL
 *  @brief      Set GPIOn output low (n = 32~40)
 *              0: Unaffected
 *              1: Set GPIOn output to low
 */
#define GCLR1_ALL_VAL_Pos (0)
#define GCLR1_ALL_VAL_Msk (0x1FFUL << GCLR1_ALL_VAL_Pos)

#define GCLR1_BIT_VAL

#define GCLR1_ALL_VAL_(x) ((x) << GCLR1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GRER0           VAL
 *  @access     GPIO->GRER0.bit.VAL
 *  @brief      Enable GPIOn rising edge detect (n = 0~31)
 *              0: Disable rising edge detection on GPIOn
 *              1: Enable rising edge detection on GPIOn
 */
#define GRER0_ALL_VAL_Pos (0)
#define GRER0_ALL_VAL_Msk (0xFFFFFFFFUL << GRER0_ALL_VAL_Pos)

#define GRER0_BIT_VAL

#define GRER0_ALL_VAL_(x) ((x) << GRER0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GRER1           VAL
 *  @access     GPIO->GRER1.bit.VAL
 *  @brief      Enable GPIOn rising edge detect (n = 32~40)
 *              0: Disable rising edge detection on GPIOn
 *              1: Enable rising edge detection on GPIOn
 */
#define GRER1_ALL_VAL_Pos (0)
#define GRER1_ALL_VAL_Msk (0x1FFUL << GRER1_ALL_VAL_Pos)

#define GRER1_BIT_VAL

#define GRER1_ALL_VAL_(x) ((x) << GRER1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GFER0           VAL
 *  @access     GPIO->GFER0.bit.VAL
 *  @brief      Enable GPIOn falling edge detect (n = 0~31)
 *              0: Disable falling edge detection on GPIOn
 *              1: Enable falling edge detection on GPIOn
 */
#define GFER0_ALL_VAL_Pos (0)
#define GFER0_ALL_VAL_Msk (0xFFFFFFFFUL << GFER0_ALL_VAL_Pos)

#define GFER0_BIT_VAL

#define GFER0_ALL_VAL_(x) ((x) << GFER0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GFER1           VAL
 *  @access     GPIO->GFER1.bit.VAL
 *  @brief      Enable GPIOn falling edge detect (n = 32~40)
 *              0: Disable falling edge detection on GPIOn
 *              1: Enable falling edge detection on GPIOn
 */
#define GFER1_ALL_VAL_Pos (0)
#define GFER1_ALL_VAL_Msk (0x1FFUL << GFER1_ALL_VAL_Pos)

#define GFER1_BIT_VAL

#define GFER1_ALL_VAL_(x) ((x) << GFER1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GEDR0           VAL
 *  @access     GPIO->GEDR0.bit.VAL
 *  @brief      GPIOn edge detect status (n = 0~31)
 *              0: Read 0 indicates no detected rising or falling edge
 *              Write a 0 has no effect
 *              1: Read 1 indicates edge was detected
 *              Write 1 will clear the latched status
 */
#define GEDR0_ALL_VAL_Pos (0)
#define GEDR0_ALL_VAL_Msk (0xFFFFFFFFUL << GEDR0_ALL_VAL_Pos)

#define GEDR0_BIT_VAL

#define GEDR0_ALL_VAL_(x) ((x) << GEDR0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GEDR1           VAL
 *  @access     GPIO->GEDR1.bit.VAL
 *  @brief      GPIOn edge detect status (n = 32~40)
 *              0: Read 0 indicates no detected rising or falling edge
 *              Write a 0 has no effect
 *              1: Read 1 indicates edge was detected
 *              Write 1 will clear the latched status
 */
#define GEDR1_ALL_VAL_Pos (0)
#define GEDR1_ALL_VAL_Msk (0x1FFUL << GEDR1_ALL_VAL_Pos)

#define GEDR1_BIT_VAL

#define GEDR1_ALL_VAL_(x) ((x) << GEDR1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GSDR0           VAL
 *  @access     GPIO->GSDR0.bit.VAL
 *  @brief      Set GPDR register bit (n = 0~31)
 *              0: Unaffected
 *              1: Set GPDR bit and set GPIOn as output
 */
#define GSDR0_ALL_VAL_Pos (0)
#define GSDR0_ALL_VAL_Msk (0xFFFFFFFFUL << GSDR0_ALL_VAL_Pos)

#define GSDR0_BIT_VAL

#define GSDR0_ALL_VAL_(x) ((x) << GSDR0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GSDR1           VAL
 *  @access     GPIO->GSDR1.bit.VAL
 *  @brief      Set GPDR register bit (n = 32~40)
 *              0: Unaffected
 *              1: Set GPDR bit and set GPIOn as output
 */
#define GSDR1_ALL_VAL_Pos (0)
#define GSDR1_ALL_VAL_Msk (0x1FFUL << GSDR1_ALL_VAL_Pos)

#define GSDR1_BIT_VAL

#define GSDR1_ALL_VAL_(x) ((x) << GSDR1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GCDR0           VAL
 *  @access     GPIO->GCDR0.bit.VAL
 *  @brief      Clear GPDR register bit (n = 0~31)
 *              0: Unaffected
 *              1: Clear GPDR bit and set GPIOn as input
 */
#define GCDR0_ALL_VAL_Pos (0)
#define GCDR0_ALL_VAL_Msk (0xFFFFFFFFUL << GCDR0_ALL_VAL_Pos)

#define GCDR0_BIT_VAL

#define GCDR0_ALL_VAL_(x) ((x) << GCDR0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GCDR1           VAL
 *  @access     GPIO->GCDR1.bit.VAL
 *  @brief      Clear GPDR register bit (n = 32~40)
 *              0: Unaffected
 *              1: Clear GPDR bit and set GPIOn as input
 */
#define GCDR1_ALL_VAL_Pos (0)
#define GCDR1_ALL_VAL_Msk (0x1FFUL << GCDR1_ALL_VAL_Pos)

#define GCDR1_BIT_VAL

#define GCDR1_ALL_VAL_(x) ((x) << GCDR1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GSRER0          VAL
 *  @access     GPIO->GSRER0.bit.VAL
 *  @brief      Set GRER register bit (n = 0~31)
 *              0: Unaffected
 *              1: Set GRER bit and enable rising edge detect for GPIOn
 */
#define GSRER0_ALL_VAL_Pos (0)
#define GSRER0_ALL_VAL_Msk (0xFFFFFFFFUL << GSRER0_ALL_VAL_Pos)

#define GSRER0_BIT_VAL

#define GSRER0_ALL_VAL_(x) ((x) << GSRER0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GSRER1          VAL
 *  @access     GPIO->GSRER1.bit.VAL
 *  @brief      Set GRER register bit (n = 32~40)
 *              0: Unaffected
 *              1: Set GRER bit and enable rising edge detect for GPIOn
 */
#define GSRER1_ALL_VAL_Pos (0)
#define GSRER1_ALL_VAL_Msk (0x1FFUL << GSRER1_ALL_VAL_Pos)

#define GSRER1_BIT_VAL

#define GSRER1_ALL_VAL_(x) ((x) << GSRER1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GCRER0          VAL
 *  @access     GPIO->GCRER0.bit.VAL
 *  @brief      Clear GRER register bit (n = 0~31)
 *              0: Unaffected
 *              1: Clear GRER bit and disable rising edge detect for GPIOn
 */
#define GCRER0_ALL_VAL_Pos (0)
#define GCRER0_ALL_VAL_Msk (0xFFFFFFFFUL << GCRER0_ALL_VAL_Pos)

#define GCRER0_BIT_VAL

#define GCRER0_ALL_VAL_(x) ((x) << GCRER0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GCRER1          VAL
 *  @access     GPIO->GCRER1.bit.VAL
 *  @brief      Clear GRER register bit (n = 32~40)
 *              0: Unaffected
 *              1: Clear GRER bit and disable rising edge detect for GPIOn
 */
#define GCRER1_ALL_VAL_Pos (0)
#define GCRER1_ALL_VAL_Msk (0x1FFUL << GCRER1_ALL_VAL_Pos)

#define GCRER1_BIT_VAL

#define GCRER1_ALL_VAL_(x) ((x) << GCRER1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GSFER0          VAL
 *  @access     GPIO->GSFER0.bit.VAL
 *  @brief      Set GFER register bit (n = 0~31)
 *              0: Unaffected
 *              1: Set GFER bit and enable falling edge detect for GPIOn
 */
#define GSFER0_ALL_VAL_Pos (0)
#define GSFER0_ALL_VAL_Msk (0xFFFFFFFFUL << GSFER0_ALL_VAL_Pos)

#define GSFER0_BIT_VAL

#define GSFER0_ALL_VAL_(x) ((x) << GSFER0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GSFER1          VAL
 *  @access     GPIO->GSFER1.bit.VAL
 *  @brief      Set GFER register bit (n = 32~40)
 *              0: Unaffected
 *              1: Set GFER bit and enable falling edge detect for GPIOn
 */
#define GSFER1_ALL_VAL_Pos (0)
#define GSFER1_ALL_VAL_Msk (0x1FFUL << GSFER1_ALL_VAL_Pos)

#define GSFER1_BIT_VAL

#define GSFER1_ALL_VAL_(x) ((x) << GSFER1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GCFER0          VAL
 *  @access     GPIO->GCFER0.bit.VAL
 *  @brief      Clear GFER register bit (n = 0~31)
 *              0: Unaffected
 *              1: Clear GFER bit and disable falling edge detect for GPIOn
 */
#define GCFER0_ALL_VAL_Pos (0)
#define GCFER0_ALL_VAL_Msk (0xFFFFFFFFUL << GCFER0_ALL_VAL_Pos)

#define GCFER0_BIT_VAL

#define GCFER0_ALL_VAL_(x) ((x) << GCFER0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GCFER1          VAL
 *  @access     GPIO->GCFER1.bit.VAL
 *  @brief      Clear GFER register bit (n = 32~40)
 *              0: Unaffected
 *              1: Clear GFER bit and disable falling edge detect for GPIOn
 */
#define GCFER1_ALL_VAL_Pos (0)
#define GCFER1_ALL_VAL_Msk (0x1FFUL << GCFER1_ALL_VAL_Pos)

#define GCFER1_BIT_VAL

#define GCFER1_ALL_VAL_(x) ((x) << GCFER1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GEIE0           VAL
 *  @access     GPIO->GEIE0.bit.VAL
 *  @brief      GPIOn edge-triggered interrupt enable (n = 0~31)
 *              0: Disable GPIOn edge-triggered interrupt
 *              1: Enable GPIOn edge-triggered interrupt
 */
#define GEIE0_ALL_VAL_Pos (0)
#define GEIE0_ALL_VAL_Msk (0xFFFFFFFFUL << GEIE0_ALL_VAL_Pos)

#define GEIE0_BIT_VAL

#define GEIE0_ALL_VAL_(x) ((x) << GEIE0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GEIE1           VAL
 *  @access     GPIO->GEIE1.bit.VAL
 *  @brief      GPIOn edge-triggered interrupt enable (n = 32~40)
 *              0: Disable GPIOn edge-triggered interrupt
 *              1: Enable GPIOn edge-triggered interrupt
 */
#define GEIE1_ALL_VAL_Pos (0)
#define GEIE1_ALL_VAL_Msk (0x1FFUL << GEIE1_ALL_VAL_Pos)

#define GEIE1_BIT_VAL

#define GEIE1_ALL_VAL_(x) ((x) << GEIE1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIF0           VAL
 *  @access     GPIO->GLIF0.bit.VAL
 *  @brief      GPIOn level-triggered interrupt flag (n = 0~31)
 *              0: GPIOn level-triggered interrupt not occur
 *              1: GPIOn level-triggered interrupt occur
 */
#define GLIF0_ALL_VAL_Pos (0)
#define GLIF0_ALL_VAL_Msk (0xFFFFFFFFUL << GLIF0_ALL_VAL_Pos)

#define GLIF0_BIT_VAL

#define GLIF0_ALL_VAL_(x) ((x) << GLIF0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIF1           VAL
 *  @access     GPIO->GLIF1.bit.VAL
 *  @brief      GPIOn level-triggered interrupt flag (n = 32~40)
 *              0: GPIOn level-triggered interrupt not occur
 *              1: GPIOn level-triggered interrupt occur
 */
#define GLIF1_ALL_VAL_Pos (0)
#define GLIF1_ALL_VAL_Msk (0x1FFUL << GLIF1_ALL_VAL_Pos)

#define GLIF1_BIT_VAL

#define GLIF1_ALL_VAL_(x) ((x) << GLIF1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIE0           VAL
 *  @access     GPIO->GLIE0.bit.VAL
 *  @brief      GPIOn level-triggered interrupt enable (n = 0~31)
 *              0: Disable GPIOn level-triggered interrupt
 *              1: Enable GPIOn level-triggered interrupt
 */
#define GLIE0_ALL_VAL_Pos (0)
#define GLIE0_ALL_VAL_Msk (0xFFFFFFFFUL << GLIE0_ALL_VAL_Pos)

#define GLIE0_BIT_VAL

#define GLIE0_ALL_VAL_(x) ((x) << GLIE0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIE1           VAL
 *  @access     GPIO->GLIE1.bit.VAL
 *  @brief      GPIOn level-triggered interrupt enable (n = 32~40)
 *              0: Disable GPIOn level-triggered interrupt
 *              1: Enable GPIOn level-triggered interrupt
 */
#define GLIE1_ALL_VAL_Pos (0)
#define GLIE1_ALL_VAL_Msk (0x1FFUL << GLIE1_ALL_VAL_Pos)

#define GLIE1_BIT_VAL

#define GLIE1_ALL_VAL_(x) ((x) << GLIE1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIC0           VAL
 *  @access     GPIO->GLIC0.bit.VAL
 *  @brief      GPIOn level-triggered interrupt flag clear (n = 0~31)
 *              Write 1 will clear the level-triggered interrupt flag and write a 0 has no effect
 */
#define GLIC0_ALL_VAL_Pos (0)
#define GLIC0_ALL_VAL_Msk (0xFFFFFFFFUL << GLIC0_ALL_VAL_Pos)

#define GLIC0_BIT_VAL

#define GLIC0_ALL_VAL_(x) ((x) << GLIC0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIC1           VAL
 *  @access     GPIO->GLIC1.bit.VAL
 *  @brief      GPIOn level-triggered interrupt flag clear (n = 32~40)
 *              Write 1 will clear the level-triggered interrupt flag and write a 0 has no effect
 */
#define GLIC1_ALL_VAL_Pos (0)
#define GLIC1_ALL_VAL_Msk (0x1FFUL << GLIC1_ALL_VAL_Pos)

#define GLIC1_BIT_VAL

#define GLIC1_ALL_VAL_(x) ((x) << GLIC1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIFRC0         VAL
 *  @access     GPIO->GLIFRC0.bit.VAL
 *  @brief      GPIOn level-triggered interrupt force (n = 0~31)
 *              Write 1 will force to generate the GPIOn level-triggered interrupt and write a 0
 *              has no effect
 */
#define GLIFRC0_ALL_VAL_Pos (0)
#define GLIFRC0_ALL_VAL_Msk (0xFFFFFFFFUL << GLIFRC0_ALL_VAL_Pos)

#define GLIFRC0_BIT_VAL

#define GLIFRC0_ALL_VAL_(x) ((x) << GLIFRC0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIFRC1         VAL
 *  @access     GPIO->GLIFRC1.bit.VAL
 *  @brief      GPIOn level-triggered interrupt force (n = 32~40)
 *              Write 1 will force to generate the GPIOn level-triggered interrupt and write a 0
 *              has no effect
 */
#define GLIFRC1_ALL_VAL_Pos (0)
#define GLIFRC1_ALL_VAL_Msk (0x1FFUL << GLIFRC1_ALL_VAL_Pos)

#define GLIFRC1_BIT_VAL

#define GLIFRC1_ALL_VAL_(x) ((x) << GLIFRC1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIPOL0         VAL
 *  @access     GPIO->GLIPOL0.bit.VAL
 *  @brief      GPIOn level-triggered interrupt polarity (n = 0~31)
 *              0: Trigger interrupt when GPIOn is low
 *              1: Trigger interrupt when GPIOn is high
 */
#define GLIPOL0_ALL_VAL_Pos (0)
#define GLIPOL0_ALL_VAL_Msk (0xFFFFFFFFUL << GLIPOL0_ALL_VAL_Pos)

#define GLIPOL0_BIT_VAL

#define GLIPOL0_ALL_VAL_(x) ((x) << GLIPOL0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GLIPOL1         VAL
 *  @access     GPIO->GLIPOL1.bit.VAL
 *  @brief      GPIOn level-triggered interrupt polarity (n = 32~40)
 *              0: Trigger interrupt when GPIOn is low
 *              1: Trigger interrupt when GPIOn is high
 */
#define GLIPOL1_ALL_VAL_Pos (0)
#define GLIPOL1_ALL_VAL_Msk (0x1FFUL << GLIPOL1_ALL_VAL_Pos)

#define GLIPOL1_BIT_VAL

#define GLIPOL1_ALL_VAL_(x) ((x) << GLIPOL1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GIF             EDGE
 *  @access     GPIO->GIF.bit.EDGE
 *  @brief      GPIO edge-triggered interrupt flag
 */
#define GIF_ALL_EDGE_Pos (0)
#define GIF_ALL_EDGE_Msk (0x1UL << GIF_ALL_EDGE_Pos)

typedef enum
{
    GIF_BIT_EDGE_NOT_OCCUR     = 0,  /*!< Not Occur   */
    GIF_BIT_EDGE_OCCUR         = 1,  /*!< Occur       */
} GIF_BIT_EDGE;

#define GIF_ALL_EDGE_NOT_OCCUR     ((0x0UL) << GIF_ALL_EDGE_Pos)
#define GIF_ALL_EDGE_OCCUR         ((0x1UL) << GIF_ALL_EDGE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GIF             LEVEL
 *  @access     GPIO->GIF.bit.LEVEL
 *  @brief      GPIO level-triggered interrupt flag
 */
#define GIF_ALL_LEVEL_Pos (1)
#define GIF_ALL_LEVEL_Msk (0x1UL << GIF_ALL_LEVEL_Pos)

typedef enum
{
    GIF_BIT_LEVEL_NOT_OCCUR     = 0,  /*!< Not Occur   */
    GIF_BIT_LEVEL_OCCUR         = 1,  /*!< Occur       */
} GIF_BIT_LEVEL;

#define GIF_ALL_LEVEL_NOT_OCCUR     ((0x0UL) << GIF_ALL_LEVEL_Pos)
#define GIF_ALL_LEVEL_OCCUR         ((0x1UL) << GIF_ALL_LEVEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GIC             EDGE
 *  @access     GPIO->GIC.bit.EDGE
 *  @brief      GPIO edge-triggered interrupt flag clear
 */
#define GIC_ALL_EDGE_Pos (0)
#define GIC_ALL_EDGE_Msk (0x1UL << GIC_ALL_EDGE_Pos)

typedef enum
{
    GIC_BIT_EDGE_NO_EFFECT     = 0,  /*!< Write 0 no effect          */
    GIC_BIT_EDGE_CLEAR         = 1,  /*!< Clear the interrupt flag   */
} GIC_BIT_EDGE;

#define GIC_ALL_EDGE_NO_EFFECT     ((0x0UL) << GIC_ALL_EDGE_Pos)
#define GIC_ALL_EDGE_CLEAR         ((0x1UL) << GIC_ALL_EDGE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GIC             LEVEL
 *  @access     GPIO->GIC.bit.LEVEL
 *  @brief      GPIO level-triggered interrupt flag clear
 */
#define GIC_ALL_LEVEL_Pos (1)
#define GIC_ALL_LEVEL_Msk (0x1UL << GIC_ALL_LEVEL_Pos)

typedef enum
{
    GIC_BIT_LEVEL_NO_EFFECT     = 0,  /*!< Write 0 no effect          */
    GIC_BIT_LEVEL_CLEAR         = 1,  /*!< Clear the interrupt flag   */
} GIC_BIT_LEVEL;

#define GIC_ALL_LEVEL_NO_EFFECT     ((0x0UL) << GIC_ALL_LEVEL_Pos)
#define GIC_ALL_LEVEL_CLEAR         ((0x1UL) << GIC_ALL_LEVEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   GPIO            GPIOREGKEY      KEY
 *  @access     GPIO->GPIOREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected GPIO registers
 */
#define GPIOREGKEY_ALL_KEY_Pos (0)
#define GPIOREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << GPIOREGKEY_ALL_KEY_Pos)

#define GPIOREGKEY_BIT_KEY

#define GPIOREGKEY_ALL_KEY_(x) ((x) << GPIOREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     UART
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTRBR         VAL
 *  @access     UART->UARTRBR.bit.VAL
 *  @brief      In non-FIFO mode, this register holds the characters received by the UART Receive
 *              Shift Register. If this register is configured to use fewer than eight bits, the
 *              bits are right-justified and the most significant bits (MSB) are zeroed. Reading
 *              the register empties the register and clears the <Data Ready> field in the Line Status
 *              Register. UARTRBR latches the value of the data byte at the front of the FIFO in
 *              FIFO mode.
 */
#define UARTRBR_ALL_VAL_Pos (0)
#define UARTRBR_ALL_VAL_Msk (0xFFFFFFFFUL << UARTRBR_ALL_VAL_Pos)

#define UARTRBR_BIT_VAL

#define UARTRBR_ALL_VAL_(x) ((x) << UARTRBR_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTTHR         VAL
 *  @access     UART->UARTTHR.bit.VAL
 *  @brief      This register holds the data byte to be transmitted next in non-FIFO mode. When the
 *              Transmit Shift Register (TSR) is emptied, the contents of this register are loaded
 *              into the Transmit Shift Register and the <Transmit Data Request> field in the Line
 *              Status Register is set.
 *              A write to Transmit Holding Register puts data into the top of the FIFO in FIFO mode.
 *              The data at the front of the FIFO is loaded into the TSR when the TSR is empty.
 */
#define UARTTHR_ALL_VAL_Pos (0)
#define UARTTHR_ALL_VAL_Msk (0xFFFFFFFFUL << UARTTHR_ALL_VAL_Pos)

#define UARTTHR_BIT_VAL

#define UARTTHR_ALL_VAL_(x) ((x) << UARTTHR_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTDLL         VAL
 *  @access     UART->UARTDLL.bit.VAL
 *  @brief      Low-byte compare value to generate baud rate
 */
#define UARTDLL_ALL_VAL_Pos (0)
#define UARTDLL_ALL_VAL_Msk (0xFFUL << UARTDLL_ALL_VAL_Pos)

#define UARTDLL_BIT_VAL

#define UARTDLL_ALL_VAL_(x) ((x) << UARTDLL_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTDLH         VAL
 *  @access     UART->UARTDLH.bit.VAL
 *  @brief      High-byte compare value to generate baud rate
 */
#define UARTDLH_ALL_VAL_Pos (0)
#define UARTDLH_ALL_VAL_Msk (0xFFUL << UARTDLH_ALL_VAL_Pos)

#define UARTDLH_BIT_VAL

#define UARTDLH_ALL_VAL_(x) ((x) << UARTDLH_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIER         RAVIE
 *  @access     UART->UARTIER.bit.RAVIE
 *  @brief      Receiver Data Available Interrupt Enable (Source UARTIIR.IID)
 */
#define UARTIER_ALL_RAVIE_Pos (0)
#define UARTIER_ALL_RAVIE_Msk (0x1UL << UARTIER_ALL_RAVIE_Pos)

typedef enum
{
    UARTIER_BIT_RAVIE_RX_DATA_INT_DISABLE     = 0,  /*!< Receiver data available (trigger threshold reached) interrupt disable   */
    UARTIER_BIT_RAVIE_RX_DATA_INT_ENABLE      = 1,  /*!< Receiver data available (trigger threshold reached) interrupt enabled   */
} UARTIER_BIT_RAVIE;

#define UARTIER_ALL_RAVIE_RX_DATA_INT_DISABLE     ((0x0UL) << UARTIER_ALL_RAVIE_Pos)
#define UARTIER_ALL_RAVIE_RX_DATA_INT_ENABLE      ((0x1UL) << UARTIER_ALL_RAVIE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIER         TIE
 *  @access     UART->UARTIER.bit.TIE
 *  @brief      Transmit Data Request Interrupt Enable (Source UARTIIR.IID)
 */
#define UARTIER_ALL_TIE_Pos (1)
#define UARTIER_ALL_TIE_Msk (0x1UL << UARTIER_ALL_TIE_Pos)

typedef enum
{
    UARTIER_BIT_TIE_TX_FIFO_INT_DISABLE     = 0,  /*!< Transmit FIFO data request interrupt disabled   */
    UARTIER_BIT_TIE_TX_FIFO_INT_ENABLE      = 1,  /*!< Transmit FIFO data request interrupt enabled    */
} UARTIER_BIT_TIE;

#define UARTIER_ALL_TIE_TX_FIFO_INT_DISABLE     ((0x0UL) << UARTIER_ALL_TIE_Pos)
#define UARTIER_ALL_TIE_TX_FIFO_INT_ENABLE      ((0x1UL) << UARTIER_ALL_TIE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIER         RLSE
 *  @access     UART->UARTIER.bit.RLSE
 *  @brief      Receiver Line Status Interrupt Enable (Source UARTIIR.IID)
 */
#define UARTIER_ALL_RLSE_Pos (2)
#define UARTIER_ALL_RLSE_Msk (0x1UL << UARTIER_ALL_RLSE_Pos)

typedef enum
{
    UARTIER_BIT_RLSE_RX_LINE_INT_DISABLE     = 0,  /*!< Receiver line status interrupt disabled   */
    UARTIER_BIT_RLSE_RX_LINE_INT_ENABLE      = 1,  /*!< Receiver line status interrupt enabled    */
} UARTIER_BIT_RLSE;

#define UARTIER_ALL_RLSE_RX_LINE_INT_DISABLE     ((0x0UL) << UARTIER_ALL_RLSE_Pos)
#define UARTIER_ALL_RLSE_RX_LINE_INT_ENABLE      ((0x1UL) << UARTIER_ALL_RLSE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIER         RTOIE
 *  @access     UART->UARTIER.bit.RTOIE
 *  @brief      Receiver Time-out Interrupt Enable (Source UARTIIR.TOD)
 */
#define UARTIER_ALL_RTOIE_Pos (4)
#define UARTIER_ALL_RTOIE_Msk (0x1UL << UARTIER_ALL_RTOIE_Pos)

typedef enum
{
    UARTIER_BIT_RTOIE_RX_TIMEOUT_INT_DISABLE     = 0,  /*!< Receiver data time-out interrupt disabled   */
    UARTIER_BIT_RTOIE_RX_TIMEOUT_INT_ENABLE      = 1,  /*!< Receiver data time-out interrupt enabled    */
} UARTIER_BIT_RTOIE;

#define UARTIER_ALL_RTOIE_RX_TIMEOUT_INT_DISABLE     ((0x0UL) << UARTIER_ALL_RTOIE_Pos)
#define UARTIER_ALL_RTOIE_RX_TIMEOUT_INT_ENABLE      ((0x1UL) << UARTIER_ALL_RTOIE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIER         NRZME
 *  @access     UART->UARTIER.bit.NRZME
 *  @brief      NRZM coding enable
 *              For infrared mode, this bit is ignored and NRM coding is disabled.
 */
#define UARTIER_ALL_NRZME_Pos (5)
#define UARTIER_ALL_NRZME_Msk (0x1UL << UARTIER_ALL_NRZME_Pos)

typedef enum
{
    UARTIER_BIT_NRZME_NRZM_DISABLE      = 0,  /*!< NRZM coding disabled. General NRZ level coding is used so signal is high at 1 and  
                                                   low at 0.                                                                           */
    UARTIER_BIT_NRZME_TOGGLE_AT_ONE     = 1,  /*!< NRZM coding enabled. Signal toggles at 1 and keeps unchanged at 0                   */
} UARTIER_BIT_NRZME;

#define UARTIER_ALL_NRZME_NRZM_DISABLE      ((0x0UL) << UARTIER_ALL_NRZME_Pos)
#define UARTIER_ALL_NRZME_TOGGLE_AT_ONE     ((0x1UL) << UARTIER_ALL_NRZME_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIER         UUE
 *  @access     UART->UARTIER.bit.UUE
 *  @brief      UART Unit Enable
 */
#define UARTIER_ALL_UUE_Pos (6)
#define UARTIER_ALL_UUE_Msk (0x1UL << UARTIER_ALL_UUE_Pos)

typedef enum
{
    UARTIER_BIT_UUE_UART_DISABLE     = 0,  /*!< The unit is disabled   */
    UARTIER_BIT_UUE_UART_ENABLE      = 1,  /*!< The unit is enabled    */
} UARTIER_BIT_UUE;

#define UARTIER_ALL_UUE_UART_DISABLE     ((0x0UL) << UARTIER_ALL_UUE_Pos)
#define UARTIER_ALL_UUE_UART_ENABLE      ((0x1UL) << UARTIER_ALL_UUE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIIR         NIP
 *  @access     UART->UARTIIR.bit.NIP
 *  @brief      No Interrupt Pending
 */
#define UARTIIR_ALL_NIP_Pos (0)
#define UARTIIR_ALL_NIP_Msk (0x1UL << UARTIIR_ALL_NIP_Pos)

typedef enum
{
    UARTIIR_BIT_NIP_INT_OCCUR         = 0,  /*!< Interrupt is pending (active low)   */
    UARTIIR_BIT_NIP_INT_NOT_OCCUR     = 1,  /*!< No interrupt is pending             */
} UARTIIR_BIT_NIP;

#define UARTIIR_ALL_NIP_INT_OCCUR         ((0x0UL) << UARTIIR_ALL_NIP_Pos)
#define UARTIIR_ALL_NIP_INT_NOT_OCCUR     ((0x1UL) << UARTIIR_ALL_NIP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIIR         IID
 *  @access     UART->UARTIIR.bit.IID
 *  @brief      Interrupt Source Encoded
 */
#define UARTIIR_ALL_IID_Pos (1)
#define UARTIIR_ALL_IID_Msk (0x3UL << UARTIIR_ALL_IID_Pos)

typedef enum
{
    UARTIIR_BIT_IID_INVALID                      = 0,  /*!< Invalid option (Modem status)                                 */
    UARTIIR_BIT_IID_TX_FIFO_REQUEST_DATA_INT     = 1,  /*!< Transmit FIFO requests data                                   */
    UARTIIR_BIT_IID_RX_DATA_READY_INT            = 2,  /*!< Received data available                                       */
    UARTIIR_BIT_IID_RX_ERROR_INT                 = 3,  /*!< Receive error (Overrun, parity, framing, break, FIFO error)   */
} UARTIIR_BIT_IID;

#define UARTIIR_ALL_IID_INVALID                      ((0x0UL) << UARTIIR_ALL_IID_Pos)
#define UARTIIR_ALL_IID_TX_FIFO_REQUEST_DATA_INT     ((0x1UL) << UARTIIR_ALL_IID_Pos)
#define UARTIIR_ALL_IID_RX_DATA_READY_INT            ((0x2UL) << UARTIIR_ALL_IID_Pos)
#define UARTIIR_ALL_IID_RX_ERROR_INT                 ((0x3UL) << UARTIIR_ALL_IID_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIIR         TOD
 *  @access     UART->UARTIIR.bit.TOD
 *  @brief      Time Out Detected
 */
#define UARTIIR_ALL_TOD_Pos (3)
#define UARTIIR_ALL_TOD_Msk (0x1UL << UARTIIR_ALL_TOD_Pos)

typedef enum
{
    UARTIIR_BIT_TOD_TIMEOUT_NOT_OCCUR     = 0,  /*!< No time out interrupt is pending                 */
    UARTIIR_BIT_TOD_TIMEOUT_OCCUR         = 1,  /*!< Time out interrupt is pending (FIFO mode only)   */
} UARTIIR_BIT_TOD;

#define UARTIIR_ALL_TOD_TIMEOUT_NOT_OCCUR     ((0x0UL) << UARTIIR_ALL_TOD_Pos)
#define UARTIIR_ALL_TOD_TIMEOUT_OCCUR         ((0x1UL) << UARTIIR_ALL_TOD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIIR         ABL
 *  @access     UART->UARTIIR.bit.ABL
 *  @brief      Auto-baud Lock
 */
#define UARTIIR_ALL_ABL_Pos (4)
#define UARTIIR_ALL_ABL_Msk (0x1UL << UARTIIR_ALL_ABL_Pos)

typedef enum
{
    UARTIIR_BIT_ABL_AUTO_BAUD_NOT_LOCK     = 0,  /*!< Auto-baud circuitry has not programmed Divisor Latch registers (DLR)   */
    UARTIIR_BIT_ABL_AUTO_BAUD_LOCK         = 1,  /*!< Divisor Latch registers (DLR) programmed by auto-baud circuitry        */
} UARTIIR_BIT_ABL;

#define UARTIIR_ALL_ABL_AUTO_BAUD_NOT_LOCK     ((0x0UL) << UARTIIR_ALL_ABL_Pos)
#define UARTIIR_ALL_ABL_AUTO_BAUD_LOCK         ((0x1UL) << UARTIIR_ALL_ABL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTIIR         FIFOSTS
 *  @access     UART->UARTIIR.bit.FIFOSTS
 *  @brief      FIFO Mode Enable Status
 */
#define UARTIIR_ALL_FIFOSTS_Pos (6)
#define UARTIIR_ALL_FIFOSTS_Msk (0x3UL << UARTIIR_ALL_FIFOSTS_Pos)

typedef enum
{
    UARTIIR_BIT_FIFOSTS_NOT_FIFO_MODE     = 0,  /*!< Non-FIFO mode is selected                                                             */
    UARTIIR_BIT_FIFOSTS_FIFO_MODE         = 3,  /*!< FIFO mode is selected (<Transmit and Receive FIFO Enable> field in the FIFO Control  
                                                     Register = 1)                                                                         */
} UARTIIR_BIT_FIFOSTS;

#define UARTIIR_ALL_FIFOSTS_NOT_FIFO_MODE     ((0x0UL) << UARTIIR_ALL_FIFOSTS_Pos)
#define UARTIIR_ALL_FIFOSTS_FIFO_MODE         ((0x3UL) << UARTIIR_ALL_FIFOSTS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTFCR         TRFIFOE
 *  @access     UART->UARTFCR.bit.TRFIFOE
 *  @brief      Transmit and Receive FIFO Enable
 *              TRFIFOE enable or disables the Transmit and Receive FIFOs. When TRFIFOE is set, both
 *              FIFOs are enabled (FIFO mode). When TRFIFOE is clear, the FIFOs are both disabled
 *              (non-FIFO mode). Writing 0b0 to this bit clears all bytes in both FIFOs. When changing
 *              from FIFO mode to non-FIFO mode and vice versa, data is cleared automatically from
 *              the FIFOs. This bit must be set when other bits in this register are written or the
 *              othe					r bits are not programmed.
 */
#define UARTFCR_ALL_TRFIFOE_Pos (0)
#define UARTFCR_ALL_TRFIFOE_Msk (0x1UL << UARTFCR_ALL_TRFIFOE_Pos)

typedef enum
{
    UARTFCR_BIT_TRFIFOE_FIFO_DISABLE     = 0,  /*!< FIFOs are disabled   */
    UARTFCR_BIT_TRFIFOE_FIFO_ENABLE      = 1,  /*!< FIFOs are enabled    */
} UARTFCR_BIT_TRFIFOE;

#define UARTFCR_ALL_TRFIFOE_FIFO_DISABLE     ((0x0UL) << UARTFCR_ALL_TRFIFOE_Pos)
#define UARTFCR_ALL_TRFIFOE_FIFO_ENABLE      ((0x1UL) << UARTFCR_ALL_TRFIFOE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTFCR         CLRRF
 *  @access     UART->UARTFCR.bit.CLRRF
 *  @brief      Clear Receive FIFO
 *              When RESETRF is set, all the bytes in the Receive FIFO are cleared. The DR bit in
 *              the UARTLSR is cleared to 0. All the error bits in the FIFO and the FIFOE bit in
 *              the UARTLSR are cleared. Any error bits, OE, PE, FE or BI, that has been set in UARTLSR
 *              are still set. The Receive Shift Register is not cleared. If the UARTIIR has been
 *              set to "received data available", it is cleared.
 */
#define UARTFCR_ALL_CLRRF_Pos (1)
#define UARTFCR_ALL_CLRRF_Msk (0x1UL << UARTFCR_ALL_CLRRF_Pos)

typedef enum
{
    UARTFCR_BIT_CLRRF_NO_EFFECT         = 0,  /*!< Write a 0 has no effect and always reads back 0   */
    UARTFCR_BIT_CLRRF_CLEAR_RX_FIFO     = 1,  /*!< Write a 1 clears the receive FIFO                
                                                   This bit is self-cleared                          */
} UARTFCR_BIT_CLRRF;

#define UARTFCR_ALL_CLRRF_NO_EFFECT         ((0x0UL) << UARTFCR_ALL_CLRRF_Pos)
#define UARTFCR_ALL_CLRRF_CLEAR_RX_FIFO     ((0x1UL) << UARTFCR_ALL_CLRRF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTFCR         CLRTF
 *  @access     UART->UARTFCR.bit.CLRTF
 *  @brief      Clear Transmit FIFO
 *              When this one is set, all the bytes in the Transmit FIFO are cleared. The TDRQ bit
 *              in the LSR is set and the UARTIIR shows a transmitter requests data interrupt, if
 *              the TIE bit in the UARTIER register is set. The transmit Shift register is not cleared,
 *              and it completes the current transmission.
 */
#define UARTFCR_ALL_CLRTF_Pos (2)
#define UARTFCR_ALL_CLRTF_Msk (0x1UL << UARTFCR_ALL_CLRTF_Pos)

typedef enum
{
    UARTFCR_BIT_CLRTF_NO_EFFECT         = 0,  /*!< Write a 0 has no effect and always reads back 0   */
    UARTFCR_BIT_CLRTF_CLEAR_TX_FIFO     = 1,  /*!< Write a 1 clears the transmit FIFO               
                                                   This bit is self-cleared                          */
} UARTFCR_BIT_CLRTF;

#define UARTFCR_ALL_CLRTF_NO_EFFECT         ((0x0UL) << UARTFCR_ALL_CLRTF_Pos)
#define UARTFCR_ALL_CLRTF_CLEAR_TX_FIFO     ((0x1UL) << UARTFCR_ALL_CLRTF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTFCR         TXTH
 *  @access     UART->UARTFCR.bit.TXTH
 *  @brief      Transmitter Interrupt Trigger Level (threshold)
 */
#define UARTFCR_ALL_TXTH_Pos (3)
#define UARTFCR_ALL_TXTH_Msk (0x1UL << UARTFCR_ALL_TXTH_Pos)

typedef enum
{
    UARTFCR_BIT_TXTH_TXFIFO_HALF_EMPTY     = 0,  /*!< Interrupt request when FIFO is half empty   */
    UARTFCR_BIT_TXTH_TXFIFO_EMPTY          = 1,  /*!< Interrupt request when FIFO is empty        */
} UARTFCR_BIT_TXTH;

#define UARTFCR_ALL_TXTH_TXFIFO_HALF_EMPTY     ((0x0UL) << UARTFCR_ALL_TXTH_Pos)
#define UARTFCR_ALL_TXTH_TXFIFO_EMPTY          ((0x1UL) << UARTFCR_ALL_TXTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTFCR         BUS32
 *  @access     UART->UARTFCR.bit.BUS32
 *  @brief      32-Bit Peripheral Bus
 */
#define UARTFCR_ALL_BUS32_Pos (5)
#define UARTFCR_ALL_BUS32_Msk (0x1UL << UARTFCR_ALL_BUS32_Pos)

typedef enum
{
    UARTFCR_BIT_BUS32_8BIT      = 0,  /*!< 8-bit peripheral bus    */
    UARTFCR_BIT_BUS32_32BIT     = 1,  /*!< 32-bit peripheral bus   */
} UARTFCR_BIT_BUS32;

#define UARTFCR_ALL_BUS32_8BIT      ((0x0UL) << UARTFCR_ALL_BUS32_Pos)
#define UARTFCR_ALL_BUS32_32BIT     ((0x1UL) << UARTFCR_ALL_BUS32_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTFCR         RXTH
 *  @access     UART->UARTFCR.bit.RXTH
 *  @brief      Receive Interrupt Trigger Level (threshold)
 *              When the number of bytes in the Receive FIFO equals the interrupt trigger threshold
 *              programmed into this field and the received-data-available interrupt is enabled via
 *              the UARTIER, an interrupt is generated and appropriate bits are set in the UARTIIR.
 */
#define UARTFCR_ALL_RXTH_Pos (6)
#define UARTFCR_ALL_RXTH_Msk (0x3UL << UARTFCR_ALL_RXTH_Pos)

typedef enum
{
    UARTFCR_BIT_RXTH_RX_FIFO_THRESHOLD_1      = 0,  /*!< 1 byte or more in FIFO causes interrupt     */
    UARTFCR_BIT_RXTH_RX_FIFO_THRESHOLD_8      = 1,  /*!< 8 bytes or more in FIFO causes interrupt    */
    UARTFCR_BIT_RXTH_RX_FIFO_THRESHOLD_16     = 2,  /*!< 16 bytes or more in FIFO causes interrupt   */
    UARTFCR_BIT_RXTH_RX_FIFO_THRESHOLD_32     = 3,  /*!< 32 bytes or more in FIFO causes interrupt   */
} UARTFCR_BIT_RXTH;

#define UARTFCR_ALL_RXTH_RX_FIFO_THRESHOLD_1      ((0x0UL) << UARTFCR_ALL_RXTH_Pos)
#define UARTFCR_ALL_RXTH_RX_FIFO_THRESHOLD_8      ((0x1UL) << UARTFCR_ALL_RXTH_Pos)
#define UARTFCR_ALL_RXTH_RX_FIFO_THRESHOLD_16     ((0x2UL) << UARTFCR_ALL_RXTH_Pos)
#define UARTFCR_ALL_RXTH_RX_FIFO_THRESHOLD_32     ((0x3UL) << UARTFCR_ALL_RXTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLCR         WLS
 *  @access     UART->UARTLCR.bit.WLS
 *  @brief      Word length for each transferred character
 */
#define UARTLCR_ALL_WLS_Pos (0)
#define UARTLCR_ALL_WLS_Msk (0x3UL << UARTLCR_ALL_WLS_Pos)

typedef enum
{
    UARTLCR_BIT_WLS_5_DATA_BIT     = 0,  /*!< 5-bit character   */
    UARTLCR_BIT_WLS_6_DATA_BIT     = 1,  /*!< 6-bit character   */
    UARTLCR_BIT_WLS_7_DATA_BIT     = 2,  /*!< 7-bit character   */
    UARTLCR_BIT_WLS_8_DATA_BIT     = 3,  /*!< 8-bit character   */
} UARTLCR_BIT_WLS;

#define UARTLCR_ALL_WLS_5_DATA_BIT     ((0x0UL) << UARTLCR_ALL_WLS_Pos)
#define UARTLCR_ALL_WLS_6_DATA_BIT     ((0x1UL) << UARTLCR_ALL_WLS_Pos)
#define UARTLCR_ALL_WLS_7_DATA_BIT     ((0x2UL) << UARTLCR_ALL_WLS_Pos)
#define UARTLCR_ALL_WLS_8_DATA_BIT     ((0x3UL) << UARTLCR_ALL_WLS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLCR         STB
 *  @access     UART->UARTLCR.bit.STB
 *  @brief      Stop bits
 */
#define UARTLCR_ALL_STB_Pos (2)
#define UARTLCR_ALL_STB_Msk (0x1UL << UARTLCR_ALL_STB_Pos)

typedef enum
{
    UARTLCR_BIT_STB_1_STOP_BIT     = 0,  /*!< 1 stop bit                            */
    UARTLCR_BIT_STB_2_STOP_BIT     = 1,  /*!< 1.5 stop bits for 5-bit character    
                                              2 stop bits for 6/7/8 bit character   */
} UARTLCR_BIT_STB;

#define UARTLCR_ALL_STB_1_STOP_BIT     ((0x0UL) << UARTLCR_ALL_STB_Pos)
#define UARTLCR_ALL_STB_2_STOP_BIT     ((0x1UL) << UARTLCR_ALL_STB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLCR         PEN
 *  @access     UART->UARTLCR.bit.PEN
 *  @brief      Parity Enable
 */
#define UARTLCR_ALL_PEN_Pos (3)
#define UARTLCR_ALL_PEN_Msk (0x1UL << UARTLCR_ALL_PEN_Pos)

typedef enum
{
    UARTLCR_BIT_PEN_NO_PARITY         = 0,  /*!< No parity bit       */
    UARTLCR_BIT_PEN_PARITY_ENABLE     = 1,  /*!< Enable parity bit   */
} UARTLCR_BIT_PEN;

#define UARTLCR_ALL_PEN_NO_PARITY         ((0x0UL) << UARTLCR_ALL_PEN_Pos)
#define UARTLCR_ALL_PEN_PARITY_ENABLE     ((0x1UL) << UARTLCR_ALL_PEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLCR         EPS
 *  @access     UART->UARTLCR.bit.EPS
 *  @brief      Even Parity Select. This bit is ignored if PEN=0
 */
#define UARTLCR_ALL_EPS_Pos (4)
#define UARTLCR_ALL_EPS_Msk (0x1UL << UARTLCR_ALL_EPS_Pos)

typedef enum
{
    UARTLCR_BIT_EPS_ODD_PARITY      = 0,  /*!< Sends or checks for odd parity    */
    UARTLCR_BIT_EPS_EVEN_PARITY     = 1,  /*!< Sends or checks for even parity   */
} UARTLCR_BIT_EPS;

#define UARTLCR_ALL_EPS_ODD_PARITY      ((0x0UL) << UARTLCR_ALL_EPS_Pos)
#define UARTLCR_ALL_EPS_EVEN_PARITY     ((0x1UL) << UARTLCR_ALL_EPS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLCR         STKYP
 *  @access     UART->UARTLCR.bit.STKYP
 *  @brief      Sticky Parity. This bit is ignored if PEN=0
 */
#define UARTLCR_ALL_STKYP_Pos (5)
#define UARTLCR_ALL_STKYP_Msk (0x1UL << UARTLCR_ALL_STKYP_Pos)

typedef enum
{
    UARTLCR_BIT_STKYP_NO_EFFECT                 = 0,  /*!< No effect on parity bit                       */
    UARTLCR_BIT_STKYP_PARITY_EQU_INVERT_EPS     = 1,  /*!< Forces parity bit to be opposite of EPS bit   */
} UARTLCR_BIT_STKYP;

#define UARTLCR_ALL_STKYP_NO_EFFECT                 ((0x0UL) << UARTLCR_ALL_STKYP_Pos)
#define UARTLCR_ALL_STKYP_PARITY_EQU_INVERT_EPS     ((0x1UL) << UARTLCR_ALL_STKYP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLCR         SB
 *  @access     UART->UARTLCR.bit.SB
 *  @brief      Set Break
 *              Causes a break condition to be transmitted to the receiving UART. Acts only on the
 *              TXD pin and has no effect on the Transmit logic. In FIFO mode, wait until the transmitter
 *              is idle (UARTLSR.TXDONE=1) to set and clear SB.
 */
#define UARTLCR_ALL_SB_Pos (6)
#define UARTLCR_ALL_SB_Msk (0x1UL << UARTLCR_ALL_SB_Pos)

typedef enum
{
    UARTLCR_BIT_SB_NO_EFFECT      = 0,  /*!< No effect on TXD output          */
    UARTLCR_BIT_SB_FORCE_TX_0     = 1,  /*!< Forces TXD output to 0 (space)   */
} UARTLCR_BIT_SB;

#define UARTLCR_ALL_SB_NO_EFFECT      ((0x0UL) << UARTLCR_ALL_SB_Pos)
#define UARTLCR_ALL_SB_FORCE_TX_0     ((0x1UL) << UARTLCR_ALL_SB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLCR         DLAB
 *  @access     UART->UARTLCR.bit.DLAB
 *  @brief      Divisor Latch Access Bit
 *              Must be set to access the Divisor Latch registers of the baud-rate generator during
 *              a Read or Write operation. Must be clear to access the Receive buffer, the Transmit
 *              Holding Register, or the UARTIER.
 */
#define UARTLCR_ALL_DLAB_Pos (7)
#define UARTLCR_ALL_DLAB_Msk (0x1UL << UARTLCR_ALL_DLAB_Pos)

typedef enum
{
    UARTLCR_BIT_DLAB_DIVISOR_LOCK       = 0,  /*!< Access Transmit Holding Register, Receive Buffer Register, and Interrupt Enable Register   */
    UARTLCR_BIT_DLAB_DIVISOR_ACCESS     = 1,  /*!< Access Divisor Latch registers (UARTDLL and UARTDLH)                                       */
} UARTLCR_BIT_DLAB;

#define UARTLCR_ALL_DLAB_DIVISOR_LOCK       ((0x0UL) << UARTLCR_ALL_DLAB_Pos)
#define UARTLCR_ALL_DLAB_DIVISOR_ACCESS     ((0x1UL) << UARTLCR_ALL_DLAB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTMCR         GIE
 *  @access     UART->UARTMCR.bit.GIE
 *  @brief      Global interrupt enable
 */
#define UARTMCR_ALL_GIE_Pos (3)
#define UARTMCR_ALL_GIE_Msk (0x1UL << UARTMCR_ALL_GIE_Pos)

typedef enum
{
    UARTMCR_BIT_GIE_DISABLE     = 0,  /*!< Disable UART interrupt to CPU   */
    UARTMCR_BIT_GIE_ENABLE      = 1,  /*!< Enable UART interrupt to CPU    */
} UARTMCR_BIT_GIE;

#define UARTMCR_ALL_GIE_DISABLE     ((0x0UL) << UARTMCR_ALL_GIE_Pos)
#define UARTMCR_ALL_GIE_ENABLE      ((0x1UL) << UARTMCR_ALL_GIE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLSR         DR
 *  @access     UART->UARTLSR.bit.DR
 *  @brief      Data Ready
 *              Set when a complete incoming character has been received and transferred into the
 *              Receive Buffer Register or the FIFO. In non-FIFO mode, DR is cleared when the Receive
 *              buffer is read. In FIFO mode, DR is cleared if the FIFO is empty (last character
 *              has been read from UARTRBR) or the FIFO is reset with UARTFCR.RESETRF.
 */
#define UARTLSR_ALL_DR_Pos (0)
#define UARTLSR_ALL_DR_Msk (0x1UL << UARTLSR_ALL_DR_Pos)

typedef enum
{
    UARTLSR_BIT_DR_NO_DATA_RECEVIED     = 0,  /*!< No data has been received                  */
    UARTLSR_BIT_DR_DATA_RECEVIED        = 1,  /*!< Data is available in UARTRBR or the FIFO   */
} UARTLSR_BIT_DR;

#define UARTLSR_ALL_DR_NO_DATA_RECEVIED     ((0x0UL) << UARTLSR_ALL_DR_Pos)
#define UARTLSR_ALL_DR_DATA_RECEVIED        ((0x1UL) << UARTLSR_ALL_DR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLSR         OE
 *  @access     UART->UARTLSR.bit.OE
 *  @brief      Overrun Error
 *              In non-FIFO mode, indicates that data in Receive Buffer register was not read by
 *              the CPU before the next character was received. The new character is lost. In FIFO
 *              mode, OE indicates that all 64 bytes of the FIFO are full and the most recently received
 *              byte has been discarded. OE is set upon detection of an overrun condition and cleared
 *              when the CPU reads the UARTLSR.
 */
#define UARTLSR_ALL_OE_Pos (1)
#define UARTLSR_ALL_OE_Msk (0x1UL << UARTLSR_ALL_OE_Pos)

typedef enum
{
    UARTLSR_BIT_OE_RX_OVERRUN_NOT_OCCUR     = 0,  /*!< No data has been overrun        */
    UARTLSR_BIT_OE_RX_OVERRUN_OCCUR         = 1,  /*!< Receive data has been overrun   */
} UARTLSR_BIT_OE;

#define UARTLSR_ALL_OE_RX_OVERRUN_NOT_OCCUR     ((0x0UL) << UARTLSR_ALL_OE_Pos)
#define UARTLSR_ALL_OE_RX_OVERRUN_OCCUR         ((0x1UL) << UARTLSR_ALL_OE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLSR         PE
 *  @access     UART->UARTLSR.bit.PE
 *  @brief      Parity Error
 *              Indicates that the received data character does not have the correct even or odd
 *              parity, as selected by the even parity select bit. PE is set upon detection of a
 *              parity error and is cleared when the CPU reads the UARTLSR. In FIFO mode, PE shows
 *              a parity error for the character at the front of the FIFO, not the most recently
 *              received character.
 */
#define UARTLSR_ALL_PE_Pos (2)
#define UARTLSR_ALL_PE_Msk (0x1UL << UARTLSR_ALL_PE_Pos)

typedef enum
{
    UARTLSR_BIT_PE_PARITY_ERROR_NOT_OCCUR     = 0,  /*!< No Parity Error             */
    UARTLSR_BIT_PE_PARITY_ERROR_OCCUR         = 1,  /*!< Parity error has occurred   */
} UARTLSR_BIT_PE;

#define UARTLSR_ALL_PE_PARITY_ERROR_NOT_OCCUR     ((0x0UL) << UARTLSR_ALL_PE_Pos)
#define UARTLSR_ALL_PE_PARITY_ERROR_OCCUR         ((0x1UL) << UARTLSR_ALL_PE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLSR         FE
 *  @access     UART->UARTLSR.bit.FE
 *  @brief      Framing Error
 *              FE indicates that the received character did not have a valid stop bit. FE is set
 *              when the bit following the last data bit or parity bit is detected to be 0. FE is
 *              cleared when the CPU reads the LSR. The UART resynchronizes after a framing error.
 *              To do this, it assumes that the framing error was due to the next start bit, so it
 *              samples this start bit twice and then reads in the data. In FIFO mode, FE shows a
 *              framing error for the character at the front of the FIFO, not for the most recently
 *              received character.
 */
#define UARTLSR_ALL_FE_Pos (3)
#define UARTLSR_ALL_FE_Msk (0x1UL << UARTLSR_ALL_FE_Pos)

typedef enum
{
    UARTLSR_BIT_FE_FRAME_ERROR_NOT_OCCUR     = 0,  /*!< No Framing error                     */
    UARTLSR_BIT_FE_FRAME_ERROR_OCCUR         = 1,  /*!< Invalid stop bit has been detected   */
} UARTLSR_BIT_FE;

#define UARTLSR_ALL_FE_FRAME_ERROR_NOT_OCCUR     ((0x0UL) << UARTLSR_ALL_FE_Pos)
#define UARTLSR_ALL_FE_FRAME_ERROR_OCCUR         ((0x1UL) << UARTLSR_ALL_FE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLSR         BI
 *  @access     UART->UARTLSR.bit.BI
 *  @brief      Break Interrupt
 *              BI is set when the received data input is held low for longer than a full-word transmission
 *              time (the total time of start bit + data bits + parity bit + stop bit). BI is cleared
 *              when the CPU reads the UARTLSR. In FIFO mode, only one character equal to 0x00, is
 *              loaded into the FIFO regardless of the length of the break condition. BI shows the
 *              break condition for the character at the front of the FIFO, not the most recently
 *              received character.
 */
#define UARTLSR_ALL_BI_Pos (4)
#define UARTLSR_ALL_BI_Msk (0x1UL << UARTLSR_ALL_BI_Pos)

typedef enum
{
    UARTLSR_BIT_BI_BREAK_SIGNAL_NOT_OCCUR     = 0,  /*!< No break signal has been received   */
    UARTLSR_BIT_BI_BREAK_SIGNAL_OCCUR         = 1,  /*!< Break signal received               */
} UARTLSR_BIT_BI;

#define UARTLSR_ALL_BI_BREAK_SIGNAL_NOT_OCCUR     ((0x0UL) << UARTLSR_ALL_BI_Pos)
#define UARTLSR_ALL_BI_BREAK_SIGNAL_OCCUR         ((0x1UL) << UARTLSR_ALL_BI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLSR         TDRQ
 *  @access     UART->UARTLSR.bit.TDRQ
 *  @brief      Transmit Data Request
 *              Indicates that the UART is ready to accept a new character for transmission. In addition,
 *              this bit causes the UART to issue an interrupt to the CPU when the transmit-data
 *              request interrupt enable is set. The TDRQ bit is set when a character is transferred
 *              from the Transmit Holding Register into the Transmit Shift Register. The bit is cleared
 *              with the loading of the Transmit Holding Register. In FIFO mode, TDRQ is set when
 *              half of the characters in the FIFO have been loaded into the Shift Register or the
 *              RESETTF bit in UARTFCR has been set. It is cleared when the FIFO has more than half
 *              data. If more than 64 characters are loaded into the FIFO, the excess characters
 *              are lost.
 */
#define UARTLSR_ALL_TDRQ_Pos (5)
#define UARTLSR_ALL_TDRQ_Msk (0x1UL << UARTLSR_ALL_TDRQ_Pos)

typedef enum
{
    UARTLSR_BIT_TDRQ_TXFIFO_MORE_THAN_HALF     = 0,  /*!< There is data in the holding register or FIFO waiting to be shifted out   */
    UARTLSR_BIT_TDRQ_TXFIFO_LESS_THAN_HALF     = 1,  /*!< The transmit FIFO has half or less than half data                         */
} UARTLSR_BIT_TDRQ;

#define UARTLSR_ALL_TDRQ_TXFIFO_MORE_THAN_HALF     ((0x0UL) << UARTLSR_ALL_TDRQ_Pos)
#define UARTLSR_ALL_TDRQ_TXFIFO_LESS_THAN_HALF     ((0x1UL) << UARTLSR_ALL_TDRQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLSR         TXDONE
 *  @access     UART->UARTLSR.bit.TXDONE
 *  @brief      Transmit done
 *              Set when the Transmit Holding Register and the Transmit Shift Register are both empty.
 *              It is cleared when either the Transmit Holding Register or the Transmit Shift Register
 *              contains a data character. In FIFO mode, TXDONE is set when the Transmit FIFO and
 *              the Transmit Shift Register are both empty.
 */
#define UARTLSR_ALL_TXDONE_Pos (6)
#define UARTLSR_ALL_TXDONE_Msk (0x1UL << UARTLSR_ALL_TXDONE_Pos)

typedef enum
{
    UARTLSR_BIT_TXDONE_TRANSMIT_NOT_DONE     = 0,  /*!< There is data in the transmit shift register, the Transmit Holding Register, or the  
                                                        FIFO.                                                                                 */
    UARTLSR_BIT_TXDONE_TRANSMIT_DONE         = 1,  /*!< All the data in the transmitter has been shifted out                                  */
} UARTLSR_BIT_TXDONE;

#define UARTLSR_ALL_TXDONE_TRANSMIT_NOT_DONE     ((0x0UL) << UARTLSR_ALL_TXDONE_Pos)
#define UARTLSR_ALL_TXDONE_TRANSMIT_DONE         ((0x1UL) << UARTLSR_ALL_TXDONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTLSR         FIFOERR
 *  @access     UART->UARTLSR.bit.FIFOERR
 *  @brief      FIFO Error Status
 *              This bit is clear in non-FIFO mode. In FIFO mode, FIFOERR is set when there is at
 *              least one parity error, framing error, or break indication for any of the characters
 *              in the FIFO. The CPU read of the UARTLSR does not reset this bit. FIFOERR is reset
 *              when all errorneous characters have been read from the FIFO.
 */
#define UARTLSR_ALL_FIFOERR_Pos (7)
#define UARTLSR_ALL_FIFOERR_Msk (0x1UL << UARTLSR_ALL_FIFOERR_Pos)

typedef enum
{
    UARTLSR_BIT_FIFOERR_FIFO_ERROR_NOT_OCCUR     = 0,  /*!< No FIFO or no errors in receive FIFO                */
    UARTLSR_BIT_FIFOERR_FIFO_ERROR_OCCUR         = 1,  /*!< At least one character in receive FIFO has errors   */
} UARTLSR_BIT_FIFOERR;

#define UARTLSR_ALL_FIFOERR_FIFO_ERROR_NOT_OCCUR     ((0x0UL) << UARTLSR_ALL_FIFOERR_Pos)
#define UARTLSR_ALL_FIFOERR_FIFO_ERROR_OCCUR         ((0x1UL) << UARTLSR_ALL_FIFOERR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTISR         XMITIR
 *  @access     UART->UARTISR.bit.XMITIR
 *  @brief      Transmitter SIR Enable
 *              When XMITIR is set, the normal TXD output from the UART is processed by the lrDA
 *              encoder before it is fed to the device pin. If XMITIR is clear, all clocking to the
 *              lrDA encoder is blocked and the UART's TXD signal is connected directly to the device
 *              pin.
 */
#define UARTISR_ALL_XMITIR_Pos (0)
#define UARTISR_ALL_XMITIR_Msk (0x1UL << UARTISR_ALL_XMITIR_Pos)

typedef enum
{
    UARTISR_BIT_XMITIR_UART         = 0,  /*!< TXD signal is connected directly                            */
    UARTISR_BIT_XMITIR_INFRARED     = 1,  /*!< TXD output from the UART is processed by the lrDA encoder   */
} UARTISR_BIT_XMITIR;

#define UARTISR_ALL_XMITIR_UART         ((0x0UL) << UARTISR_ALL_XMITIR_Pos)
#define UARTISR_ALL_XMITIR_INFRARED     ((0x1UL) << UARTISR_ALL_XMITIR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTISR         RCVEIR
 *  @access     UART->UARTISR.bit.RCVEIR
 *  @brief      Receiver SIR Enable
 *              When RCVEIR is set, the signal from the RXD pin is processed by lrDA decoder before
 *              it is fed to the UART. IF RCVEIR is clear, than all clocking to the lrDA decoder
 *              is blocked and the RXD pin is fed directly to the UART.
 */
#define UARTISR_ALL_RCVEIR_Pos (1)
#define UARTISR_ALL_RCVEIR_Msk (0x1UL << UARTISR_ALL_RCVEIR_Pos)

typedef enum
{
    UARTISR_BIT_RCVEIR_UART         = 0,  /*!< Receiver is in UART mode       */
    UARTISR_BIT_RCVEIR_INFRARED     = 1,  /*!< Receiver is in infrared mode   */
} UARTISR_BIT_RCVEIR;

#define UARTISR_ALL_RCVEIR_UART         ((0x0UL) << UARTISR_ALL_RCVEIR_Pos)
#define UARTISR_ALL_RCVEIR_INFRARED     ((0x1UL) << UARTISR_ALL_RCVEIR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTISR         TXPL
 *  @access     UART->UARTISR.bit.TXPL
 *  @brief      Transmit Data Polarity
 */
#define UARTISR_ALL_TXPL_Pos (3)
#define UARTISR_ALL_TXPL_Msk (0x1UL << UARTISR_ALL_TXPL_Pos)

typedef enum
{
    UARTISR_BIT_TXPL_SEND_POSITIVE_ZERO     = 0,  /*!< SIR encoder generates a positive pulse for a data bit of zero   */
    UARTISR_BIT_TXPL_SEND_NEGATIVE_ZERO     = 1,  /*!< SIR encoder generates a negative pulse for a data bit of zero   */
} UARTISR_BIT_TXPL;

#define UARTISR_ALL_TXPL_SEND_POSITIVE_ZERO     ((0x0UL) << UARTISR_ALL_TXPL_Pos)
#define UARTISR_ALL_TXPL_SEND_NEGATIVE_ZERO     ((0x1UL) << UARTISR_ALL_TXPL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTISR         RXPL
 *  @access     UART->UARTISR.bit.RXPL
 *  @brief      Receive Data Polarity
 */
#define UARTISR_ALL_RXPL_Pos (4)
#define UARTISR_ALL_RXPL_Msk (0x1UL << UARTISR_ALL_RXPL_Pos)

typedef enum
{
    UARTISR_BIT_RXPL_REV_POSITIVE_ZERO     = 0,  /*!< SIR decoder takes positive pulses as zeros   */
    UARTISR_BIT_RXPL_REV_NEGATIVE_ZERO     = 1,  /*!< SIR decoder takes negative pulses as zeros   */
} UARTISR_BIT_RXPL;

#define UARTISR_ALL_RXPL_REV_POSITIVE_ZERO     ((0x0UL) << UARTISR_ALL_RXPL_Pos)
#define UARTISR_ALL_RXPL_REV_NEGATIVE_ZERO     ((0x1UL) << UARTISR_ALL_RXPL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTFOR         BYTECNT
 *  @access     UART->UARTFOR.bit.BYTECNT
 *  @brief      Number of bytes (0-64) remaining in the Receive FIFO
 */
#define UARTFOR_ALL_BYTECNT_Pos (0)
#define UARTFOR_ALL_BYTECNT_Msk (0x7FUL << UARTFOR_ALL_BYTECNT_Pos)

#define UARTFOR_BIT_BYTECNT

#define UARTFOR_ALL_BYTECNT_(x) ((x) << UARTFOR_ALL_BYTECNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTABR         ABE
 *  @access     UART->UARTABR.bit.ABE
 *  @brief      Auto-baud detection enable
 */
#define UARTABR_ALL_ABE_Pos (0)
#define UARTABR_ALL_ABE_Msk (0x1UL << UARTABR_ALL_ABE_Pos)

typedef enum
{
    UARTABR_BIT_ABE_DISABLE     = 0,  /*!< Auto-baud disabled   */
    UARTABR_BIT_ABE_ENABLE      = 1,  /*!< Auto-baud enabled    */
} UARTABR_BIT_ABE;

#define UARTABR_ALL_ABE_DISABLE     ((0x0UL) << UARTABR_ALL_ABE_Pos)
#define UARTABR_ALL_ABE_ENABLE      ((0x1UL) << UARTABR_ALL_ABE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTABR         ABLIE
 *  @access     UART->UARTABR.bit.ABLIE
 *  @brief      Auto-baud-lock interrupt enable
 */
#define UARTABR_ALL_ABLIE_Pos (1)
#define UARTABR_ALL_ABLIE_Msk (0x1UL << UARTABR_ALL_ABLIE_Pos)

typedef enum
{
    UARTABR_BIT_ABLIE_DISABLE     = 0,  /*!< Auto-baud-lock interrupt disabled (Source UARTIIR.ABL)   */
    UARTABR_BIT_ABLIE_ENABLE      = 1,  /*!< Auto-baud-lock interrupt enabled (Source UARTIIR.ABL)    */
} UARTABR_BIT_ABLIE;

#define UARTABR_ALL_ABLIE_DISABLE     ((0x0UL) << UARTABR_ALL_ABLIE_Pos)
#define UARTABR_ALL_ABLIE_ENABLE      ((0x1UL) << UARTABR_ALL_ABLIE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTABR         ABUP
 *  @access     UART->UARTABR.bit.ABUP
 *  @brief      Method to program Divisor Latch registers
 */
#define UARTABR_ALL_ABUP_Pos (2)
#define UARTABR_ALL_ABUP_Msk (0x1UL << UARTABR_ALL_ABUP_Pos)

typedef enum
{
    UARTABR_BIT_ABUP_SOFTWARE_PROG_DIVISOR     = 0,  /*!< Software Programs Divisor Latch registers   */
    UARTABR_BIT_ABUP_UART_PROG_DIVISOR         = 1,  /*!< UART Programs Divisor Latch registers       */
} UARTABR_BIT_ABUP;

#define UARTABR_ALL_ABUP_SOFTWARE_PROG_DIVISOR     ((0x0UL) << UARTABR_ALL_ABUP_Pos)
#define UARTABR_ALL_ABUP_UART_PROG_DIVISOR         ((0x1UL) << UARTABR_ALL_ABUP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   UART            UARTACR         CNTVAL
 *  @access     UART->UARTACR.bit.CNTVAL
 *  @brief      Number of UART clock cycles within a start-bit pulse
 */
#define UARTACR_ALL_CNTVAL_Pos (0)
#define UARTACR_ALL_CNTVAL_Msk (0xFFFFUL << UARTACR_ALL_CNTVAL_Pos)

#define UARTACR_BIT_CNTVAL

#define UARTACR_ALL_CNTVAL_(x) ((x) << UARTACR_ALL_CNTVAL_Pos)



/********************************************************************************
*
* Module Name     SSP
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL0         SIZESEL
 *  @access     SSP->SSPCTL0.bit.SIZESEL
 *  @brief      Data size select
 */
#define SSPCTL0_ALL_SIZESEL_Pos (0)
#define SSPCTL0_ALL_SIZESEL_Msk (0xFUL << SSPCTL0_ALL_SIZESEL_Pos)

typedef enum
{
    SSPCTL0_BIT_SIZESEL_FRAME_1_OR_17BIT      = 0,  /*!< 1-bit if ESIZESEL=0 and 17-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_2_OR_18BIT      = 1,  /*!< 2-bit if ESIZESEL=0 and 18-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_3_OR_19BIT      = 2,  /*!< 3-bit if ESIZESEL=0 and 19-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_4_OR_20BIT      = 3,  /*!< 4-bit if ESIZESEL=0 and 20-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_5_OR_21BIT      = 4,  /*!< 5-bit if ESIZESEL=0 and 21-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_6_OR_22BIT      = 5,  /*!< 6-bit if ESIZESEL=0 and 22-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_7_OR_23BIT      = 6,  /*!< 7-bit if ESIZESEL=0 and 23-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_8_OR_24BIT      = 7,  /*!< 8-bit if ESIZESEL=0 and 24-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_9_OR_25BIT      = 8,  /*!< 9-bit if ESIZESEL=0 and 25-bit if ESIZESEL=1    */
    SSPCTL0_BIT_SIZESEL_FRAME_10_OR_26BIT     = 9,  /*!< 10-bit if ESIZESEL=0 and 26-bit if ESIZESEL=1   */
    SSPCTL0_BIT_SIZESEL_FRAME_11_OR_27BIT     = 10,  /*!< 11-bit if ESIZESEL=0 and 27-bit if ESIZESEL=1   */
    SSPCTL0_BIT_SIZESEL_FRAME_12_OR_28BIT     = 11,  /*!< 12-bit if ESIZESEL=0 and 28-bit if ESIZESEL=1   */
    SSPCTL0_BIT_SIZESEL_FRAME_13_OR_29BIT     = 12,  /*!< 13-bit if ESIZESEL=0 and 29-bit if ESIZESEL=1   */
    SSPCTL0_BIT_SIZESEL_FRAME_14_OR_30BIT     = 13,  /*!< 14-bit if ESIZESEL=0 and 30-bit if ESIZESEL=1   */
    SSPCTL0_BIT_SIZESEL_FRAME_15_OR_31BIT     = 14,  /*!< 15-bit if ESIZESEL=0 and 31-bit if ESIZESEL=1   */
    SSPCTL0_BIT_SIZESEL_FRAME_16_OR_32BIT     = 15,  /*!< 16-bit if ESIZESEL=0 and 32-bit if ESIZESEL=1   */
} SSPCTL0_BIT_SIZESEL;

#define SSPCTL0_ALL_SIZESEL_FRAME_1_OR_17BIT      ((0x00UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_2_OR_18BIT      ((0x01UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_3_OR_19BIT      ((0x02UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_4_OR_20BIT      ((0x03UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_5_OR_21BIT      ((0x04UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_6_OR_22BIT      ((0x05UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_7_OR_23BIT      ((0x06UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_8_OR_24BIT      ((0x07UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_9_OR_25BIT      ((0x08UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_10_OR_26BIT     ((0x09UL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_11_OR_27BIT     ((0x0AUL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_12_OR_28BIT     ((0x0BUL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_13_OR_29BIT     ((0x0CUL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_14_OR_30BIT     ((0x0DUL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_15_OR_31BIT     ((0x0EUL) << SSPCTL0_ALL_SIZESEL_Pos)
#define SSPCTL0_ALL_SIZESEL_FRAME_16_OR_32BIT     ((0x0FUL) << SSPCTL0_ALL_SIZESEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL0         FRMSEL
 *  @access     SSP->SSPCTL0.bit.FRMSEL
 *  @brief      Frame Format
 */
#define SSPCTL0_ALL_FRMSEL_Pos (4)
#define SSPCTL0_ALL_FRMSEL_Msk (0x3UL << SSPCTL0_ALL_FRMSEL_Pos)

typedef enum
{
    SSPCTL0_BIT_FRMSEL_SPI_MOTOROLA     = 0,  /*!< Motorola Serial Peripheral Interface (SPI)            */
    SSPCTL0_BIT_FRMSEL_SSP_TI           = 1,  /*!< Texas Instruments Synchronous Serial Protocol (SSP)   */
    SSPCTL0_BIT_FRMSEL_PSP              = 3,  /*!< Programmable Serial Protocol (PSP)                    */
} SSPCTL0_BIT_FRMSEL;

#define SSPCTL0_ALL_FRMSEL_SPI_MOTOROLA     ((0x0UL) << SSPCTL0_ALL_FRMSEL_Pos)
#define SSPCTL0_ALL_FRMSEL_SSP_TI           ((0x1UL) << SSPCTL0_ALL_FRMSEL_Pos)
#define SSPCTL0_ALL_FRMSEL_PSP              ((0x3UL) << SSPCTL0_ALL_FRMSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL0         EN
 *  @access     SSP->SSPCTL0.bit.EN
 *  @brief      Synchronous serial port Enable
 */
#define SSPCTL0_ALL_EN_Pos (7)
#define SSPCTL0_ALL_EN_Msk (0x1UL << SSPCTL0_ALL_EN_Pos)

typedef enum
{
    SSPCTL0_BIT_EN_DISABLE     = 0,  /*!< Disable SSP   */
    SSPCTL0_BIT_EN_ENABLE      = 1,  /*!< Enable SSP    */
} SSPCTL0_BIT_EN;

#define SSPCTL0_ALL_EN_DISABLE     ((0x0UL) << SSPCTL0_ALL_EN_Pos)
#define SSPCTL0_ALL_EN_ENABLE      ((0x1UL) << SSPCTL0_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL0         ESIZESEL
 *  @access     SSP->SSPCTL0.bit.ESIZESEL
 *  @brief      Extended data size select
 */
#define SSPCTL0_ALL_ESIZESEL_Pos (20)
#define SSPCTL0_ALL_ESIZESEL_Msk (0x1UL << SSPCTL0_ALL_ESIZESEL_Pos)

typedef enum
{
    SSPCTL0_BIT_ESIZESEL_DISABLE     = 0,  /*!< A 0 is pre-appended to the SIZESEL value to set the SIZESEL range from 1 to 16 bits    */
    SSPCTL0_BIT_ESIZESEL_ENABLE      = 1,  /*!< A 1 is pre-appended to the SIZESEL value to set the SIZESEL range from 17 to 32 bits   */
} SSPCTL0_BIT_ESIZESEL;

#define SSPCTL0_ALL_ESIZESEL_DISABLE     ((0x0UL) << SSPCTL0_ALL_ESIZESEL_Pos)
#define SSPCTL0_ALL_ESIZESEL_ENABLE      ((0x1UL) << SSPCTL0_ALL_ESIZESEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL0         RFINTMSK
 *  @access     SSP->SSPCTL0.bit.RFINTMSK
 *  @brief      Receive FIFO overflow interrupt mask
 */
#define SSPCTL0_ALL_RFINTMSK_Pos (22)
#define SSPCTL0_ALL_RFINTMSK_Msk (0x1UL << SSPCTL0_ALL_RFINTMSK_Pos)

typedef enum
{
    SSPCTL0_BIT_RFINTMSK_UNMASK     = 0,  /*!< RFOVF events generate an SSP interrupt          */
    SSPCTL0_BIT_RFINTMSK_MASK       = 1,  /*!< RFOVF events do NOT generate an SSP interrupt   */
} SSPCTL0_BIT_RFINTMSK;

#define SSPCTL0_ALL_RFINTMSK_UNMASK     ((0x0UL) << SSPCTL0_ALL_RFINTMSK_Pos)
#define SSPCTL0_ALL_RFINTMSK_MASK       ((0x1UL) << SSPCTL0_ALL_RFINTMSK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL0         TFINTMSK
 *  @access     SSP->SSPCTL0.bit.TFINTMSK
 *  @brief      Transmit FIFO underflow interrupt mask
 */
#define SSPCTL0_ALL_TFINTMSK_Pos (23)
#define SSPCTL0_ALL_TFINTMSK_Msk (0x1UL << SSPCTL0_ALL_TFINTMSK_Pos)

typedef enum
{
    SSPCTL0_BIT_TFINTMSK_UNMASK     = 0,  /*!< TFUDF events generate an SSP interrupt          */
    SSPCTL0_BIT_TFINTMSK_MASK       = 1,  /*!< TFUDF events do NOT generate an SSP interrupt   */
} SSPCTL0_BIT_TFINTMSK;

#define SSPCTL0_ALL_TFINTMSK_UNMASK     ((0x0UL) << SSPCTL0_ALL_TFINTMSK_Pos)
#define SSPCTL0_ALL_TFINTMSK_MASK       ((0x1UL) << SSPCTL0_ALL_TFINTMSK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL0         FPACKEN
 *  @access     SSP->SSPCTL0.bit.FPACKEN
 *  @brief      FIFO packing enable
 */
#define SSPCTL0_ALL_FPACKEN_Pos (29)
#define SSPCTL0_ALL_FPACKEN_Msk (0x1UL << SSPCTL0_ALL_FPACKEN_Pos)

typedef enum
{
    SSPCTL0_BIT_FPACKEN_DISABLE     = 0,  /*!< Disable FIFO packing   */
    SSPCTL0_BIT_FPACKEN_ENABLE      = 1,  /*!< Enable FIFO packing    */
} SSPCTL0_BIT_FPACKEN;

#define SSPCTL0_ALL_FPACKEN_DISABLE     ((0x0UL) << SSPCTL0_ALL_FPACKEN_Pos)
#define SSPCTL0_ALL_FPACKEN_ENABLE      ((0x1UL) << SSPCTL0_ALL_FPACKEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         RFIE
 *  @access     SSP->SSPCTL1.bit.RFIE
 *  @brief      Receive FIFO interrupt enable
 */
#define SSPCTL1_ALL_RFIE_Pos (0)
#define SSPCTL1_ALL_RFIE_Msk (0x1UL << SSPCTL1_ALL_RFIE_Pos)

typedef enum
{
    SSPCTL1_BIT_RFIE_DISABLE     = 0,  /*!< Disable RXFIFO interrupt   */
    SSPCTL1_BIT_RFIE_ENABLE      = 1,  /*!< Enable RXFIFO interrupt    */
} SSPCTL1_BIT_RFIE;

#define SSPCTL1_ALL_RFIE_DISABLE     ((0x0UL) << SSPCTL1_ALL_RFIE_Pos)
#define SSPCTL1_ALL_RFIE_ENABLE      ((0x1UL) << SSPCTL1_ALL_RFIE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         TFIE
 *  @access     SSP->SSPCTL1.bit.TFIE
 *  @brief      Transmit FIFO interrupt enable
 */
#define SSPCTL1_ALL_TFIE_Pos (1)
#define SSPCTL1_ALL_TFIE_Msk (0x1UL << SSPCTL1_ALL_TFIE_Pos)

typedef enum
{
    SSPCTL1_BIT_TFIE_DISABLE     = 0,  /*!< Disable TXFIFO interrupt   */
    SSPCTL1_BIT_TFIE_ENABLE      = 1,  /*!< Enable TXFIFO interrupt    */
} SSPCTL1_BIT_TFIE;

#define SSPCTL1_ALL_TFIE_DISABLE     ((0x0UL) << SSPCTL1_ALL_TFIE_Pos)
#define SSPCTL1_ALL_TFIE_ENABLE      ((0x1UL) << SSPCTL1_ALL_TFIE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         CLKPOL
 *  @access     SSP->SSPCTL1.bit.CLKPOL
 *  @brief      Motorola SPI SSP_SCLK polarity setting
 */
#define SSPCTL1_ALL_CLKPOL_Pos (3)
#define SSPCTL1_ALL_CLKPOL_Msk (0x1UL << SSPCTL1_ALL_CLKPOL_Pos)

typedef enum
{
    SSPCTL1_BIT_CLKPOL_CLK_IDLE_LOW      = 0,  /*!< SSP_SCLK of inactive or idle state is low    */
    SSPCTL1_BIT_CLKPOL_CLK_IDLE_HIGH     = 1,  /*!< SSP_SCLK of inactive or idle state is high   */
} SSPCTL1_BIT_CLKPOL;

#define SSPCTL1_ALL_CLKPOL_CLK_IDLE_LOW      ((0x0UL) << SSPCTL1_ALL_CLKPOL_Pos)
#define SSPCTL1_ALL_CLKPOL_CLK_IDLE_HIGH     ((0x1UL) << SSPCTL1_ALL_CLKPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         CLKPHS
 *  @access     SSP->SSPCTL1.bit.CLKPHS
 *  @brief      Motorola SPI SSP_SCLK phase setting
 */
#define SSPCTL1_ALL_CLKPHS_Pos (4)
#define SSPCTL1_ALL_CLKPHS_Msk (0x1UL << SSPCTL1_ALL_CLKPHS_Pos)

typedef enum
{
    SSPCTL1_BIT_CLKPHS_SAMPLE_ON_1st_CLK_EDGE     = 0,  /*!< Start sampling data on the 1st SSP_SCLK edge after the start of a frame   */
    SSPCTL1_BIT_CLKPHS_SAMPLE_ON_2nd_CLK_EDGE     = 1,  /*!< Start sampling data on the 2nd SSP_SCLK edge after the start of a frame   */
} SSPCTL1_BIT_CLKPHS;

#define SSPCTL1_ALL_CLKPHS_SAMPLE_ON_1st_CLK_EDGE     ((0x0UL) << SSPCTL1_ALL_CLKPHS_Pos)
#define SSPCTL1_ALL_CLKPHS_SAMPLE_ON_2nd_CLK_EDGE     ((0x1UL) << SSPCTL1_ALL_CLKPHS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         TFTH
 *  @access     SSP->SSPCTL1.bit.TFTH
 *  @brief      Threshold level at which TXFIFO asserts interrupt.
 *              Level should be set to the preferred threshold value.
 */
#define SSPCTL1_ALL_TFTH_Pos (6)
#define SSPCTL1_ALL_TFTH_Msk (0xFUL << SSPCTL1_ALL_TFTH_Pos)

#define SSPCTL1_BIT_TFTH

#define SSPCTL1_ALL_TFTH_(x) ((x) << SSPCTL1_ALL_TFTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         RFTH
 *  @access     SSP->SSPCTL1.bit.RFTH
 *  @brief      Threshold level at which RXFIFO asserts interrupt.
 *              Level should be set to the preferred threshold value minus 1.
 */
#define SSPCTL1_ALL_RFTH_Pos (10)
#define SSPCTL1_ALL_RFTH_Msk (0xFUL << SSPCTL1_ALL_RFTH_Pos)

#define SSPCTL1_BIT_RFTH

#define SSPCTL1_ALL_RFTH_(x) ((x) << SSPCTL1_ALL_RFTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         FRMINV
 *  @access     SSP->SSPCTL1.bit.FRMINV
 *  @brief      Invert frame signal
 */
#define SSPCTL1_ALL_FRMINV_Pos (16)
#define SSPCTL1_ALL_FRMINV_Msk (0x1UL << SSPCTL1_ALL_FRMINV_Pos)

typedef enum
{
    SSPCTL1_BIT_FRMINV_NORMAL     = 0,  /*!< SSP_SFRM polarity is determined by the PSP polarity bits              */
    SSPCTL1_BIT_FRMINV_INVERT     = 1,  /*!< SSP_SFRM polarity is inverted to the definition by PSP polarity bit   */
} SSPCTL1_BIT_FRMINV;

#define SSPCTL1_ALL_FRMINV_NORMAL     ((0x0UL) << SSPCTL1_ALL_FRMINV_Pos)
#define SSPCTL1_ALL_FRMINV_INVERT     ((0x1UL) << SSPCTL1_ALL_FRMINV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         RXTOIE
 *  @access     SSP->SSPCTL1.bit.RXTOIE
 *  @brief      Receiver time-out interrupt enable
 */
#define SSPCTL1_ALL_RXTOIE_Pos (19)
#define SSPCTL1_ALL_RXTOIE_Msk (0x1UL << SSPCTL1_ALL_RXTOIE_Pos)

typedef enum
{
    SSPCTL1_BIT_RXTOIE_DISABLE     = 0,  /*!< Disable receiver time-out interrupt   */
    SSPCTL1_BIT_RXTOIE_ENABLE      = 1,  /*!< Enable receiver time-out interrupt    */
} SSPCTL1_BIT_RXTOIE;

#define SSPCTL1_ALL_RXTOIE_DISABLE     ((0x0UL) << SSPCTL1_ALL_RXTOIE_Pos)
#define SSPCTL1_ALL_RXTOIE_ENABLE      ((0x1UL) << SSPCTL1_ALL_RXTOIE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         TRAIL
 *  @access     SSP->SSPCTL1.bit.TRAIL
 *  @brief      Trailing byte control
 */
#define SSPCTL1_ALL_TRAIL_Pos (22)
#define SSPCTL1_ALL_TRAIL_Msk (0x1UL << SSPCTL1_ALL_TRAIL_Pos)

typedef enum
{
    SSPCTL1_BIT_TRAIL_CPU_HANDLE     = 0,  /*!< Trailing bytes are handled by CPU   */
    SSPCTL1_BIT_TRAIL_DMA_HANDLE     = 1,  /*!< Trailing bytes are handled by DMA   */
} SSPCTL1_BIT_TRAIL;

#define SSPCTL1_ALL_TRAIL_CPU_HANDLE     ((0x0UL) << SSPCTL1_ALL_TRAIL_Pos)
#define SSPCTL1_ALL_TRAIL_DMA_HANDLE     ((0x1UL) << SSPCTL1_ALL_TRAIL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         RXONLY
 *  @access     SSP->SSPCTL1.bit.RXONLY
 *  @brief      Receive-only mode
 */
#define SSPCTL1_ALL_RXONLY_Pos (23)
#define SSPCTL1_ALL_RXONLY_Msk (0x1UL << SSPCTL1_ALL_RXONLY_Pos)

typedef enum
{
    SSPCTL1_BIT_RXONLY_TXRX_MODE     = 0,  /*!< Transmit/receive mode           */
    SSPCTL1_BIT_RXONLY_RX_MODE       = 1,  /*!< Receive without transmit mode   */
} SSPCTL1_BIT_RXONLY;

#define SSPCTL1_ALL_RXONLY_TXRX_MODE     ((0x0UL) << SSPCTL1_ALL_RXONLY_Pos)
#define SSPCTL1_ALL_RXONLY_RX_MODE       ((0x1UL) << SSPCTL1_ALL_RXONLY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         FRMDIR
 *  @access     SSP->SSPCTL1.bit.FRMDIR
 *  @brief      SSP frame (SSP_SFRM) direction
 */
#define SSPCTL1_ALL_FRMDIR_Pos (24)
#define SSPCTL1_ALL_FRMDIR_Msk (0x1UL << SSPCTL1_ALL_FRMDIR_Pos)

typedef enum
{
    SSPCTL1_BIT_FRMDIR_MASTER_MODE     = 0,  /*!< Master mode, SSP port drives SSP_SFRM    */
    SSPCTL1_BIT_FRMDIR_SLAVE_MODE      = 1,  /*!< Slave mode, SSP port receives SSP_SFRM   */
} SSPCTL1_BIT_FRMDIR;

#define SSPCTL1_ALL_FRMDIR_MASTER_MODE     ((0x0UL) << SSPCTL1_ALL_FRMDIR_Pos)
#define SSPCTL1_ALL_FRMDIR_SLAVE_MODE      ((0x1UL) << SSPCTL1_ALL_FRMDIR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         CLKDIR
 *  @access     SSP->SSPCTL1.bit.CLKDIR
 *  @brief      SSP clock (SSP_SCLK) direction
 */
#define SSPCTL1_ALL_CLKDIR_Pos (25)
#define SSPCTL1_ALL_CLKDIR_Msk (0x1UL << SSPCTL1_ALL_CLKDIR_Pos)

typedef enum
{
    SSPCTL1_BIT_CLKDIR_MASTER_MODE     = 0,  /*!< Master mode, SSP port drives SSP_SCLK    */
    SSPCTL1_BIT_CLKDIR_SLAVE_MODE      = 1,  /*!< Slave mode, SSP port receives SSP_SCLK   */
} SSPCTL1_BIT_CLKDIR;

#define SSPCTL1_ALL_CLKDIR_MASTER_MODE     ((0x0UL) << SSPCTL1_ALL_CLKDIR_Pos)
#define SSPCTL1_ALL_CLKDIR_SLAVE_MODE      ((0x1UL) << SSPCTL1_ALL_CLKDIR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         SLVCLKSEL
 *  @access     SSP->SSPCTL1.bit.SLVCLKSEL
 *  @brief      Slave clock free running control
 */
#define SSPCTL1_ALL_SLVCLKSEL_Pos (28)
#define SSPCTL1_ALL_SLVCLKSEL_Msk (0x1UL << SSPCTL1_ALL_SLVCLKSEL_Pos)

typedef enum
{
    SSPCTL1_BIT_SLVCLKSEL_SLAVE_INTERNAL_SCLK     = 0,  /*!< Clock input to SSP_SCLK is not active when SSPCTL1.CLKDIR=1 (slave mode)   */
    SSPCTL1_BIT_SLVCLKSEL_SLAVE_EXTENAL_SCLK      = 1,  /*!< Clock input to SSP_SCLK is active when SSPCTL1.CLKDIR=1 (slave mode)       */
} SSPCTL1_BIT_SLVCLKSEL;

#define SSPCTL1_ALL_SLVCLKSEL_SLAVE_INTERNAL_SCLK     ((0x0UL) << SSPCTL1_ALL_SLVCLKSEL_Pos)
#define SSPCTL1_ALL_SLVCLKSEL_SLAVE_EXTENAL_SCLK      ((0x1UL) << SSPCTL1_ALL_SLVCLKSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         TXTRIEN
 *  @access     SSP->SSPCTL1.bit.TXTRIEN
 *  @brief      TXD tri-stated enable
 */
#define SSPCTL1_ALL_TXTRIEN_Pos (30)
#define SSPCTL1_ALL_TXTRIEN_Msk (0x1UL << SSPCTL1_ALL_TXTRIEN_Pos)

typedef enum
{
    SSPCTL1_BIT_TXTRIEN_TX_TRISTATE_DISABLE     = 0,  /*!< SSP_TXD output signal is not tri-stated            */
    SSPCTL1_BIT_TXTRIEN_TX_TRISTATE_ENALBLE     = 1,  /*!< SSP_TXD is tri-stated when not transmitting data   */
} SSPCTL1_BIT_TXTRIEN;

#define SSPCTL1_ALL_TXTRIEN_TX_TRISTATE_DISABLE     ((0x0UL) << SSPCTL1_ALL_TXTRIEN_Pos)
#define SSPCTL1_ALL_TXTRIEN_TX_TRISTATE_ENALBLE     ((0x1UL) << SSPCTL1_ALL_TXTRIEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPCTL1         TXTRITIME
 *  @access     SSP->SSPCTL1.bit.TXTRITIME
 *  @brief      TXD tri-stated enable on last phase
 */
#define SSPCTL1_ALL_TXTRITIME_Pos (31)
#define SSPCTL1_ALL_TXTRITIME_Msk (0x1UL << SSPCTL1_ALL_TXTRITIME_Pos)

typedef enum
{
    SSPCTL1_BIT_TXTRITIME_TX_TRISTATE_MODE_0     = 0,  /*!< SSP_TXD is tri-stated 1/2 clock cycle after the beginning of the LSB      */
    SSPCTL1_BIT_TXTRITIME_TX_TRISTATE_MODE_1     = 1,  /*!< SSP_TXD output signal is tri-stated on the clock edge that ends the LSB   */
} SSPCTL1_BIT_TXTRITIME;

#define SSPCTL1_ALL_TXTRITIME_TX_TRISTATE_MODE_0     ((0x0UL) << SSPCTL1_ALL_TXTRITIME_Pos)
#define SSPCTL1_ALL_TXTRITIME_TX_TRISTATE_MODE_1     ((0x1UL) << SSPCTL1_ALL_TXTRITIME_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          TNF
 *  @access     SSP->SSPSTS.bit.TNF
 *  @brief      Transmit FIFO not full
 */
#define SSPSTS_ALL_TNF_Pos (2)
#define SSPSTS_ALL_TNF_Msk (0x1UL << SSPSTS_ALL_TNF_Pos)

typedef enum
{
    SSPSTS_BIT_TNF_FULL         = 0,  /*!< TXFIFO is full       */
    SSPSTS_BIT_TNF_NOT_FULL     = 1,  /*!< TXFIFO is not full   */
} SSPSTS_BIT_TNF;

#define SSPSTS_ALL_TNF_FULL         ((0x0UL) << SSPSTS_ALL_TNF_Pos)
#define SSPSTS_ALL_TNF_NOT_FULL     ((0x1UL) << SSPSTS_ALL_TNF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          RNE
 *  @access     SSP->SSPSTS.bit.RNE
 *  @brief      Receive FIFO not empty
 */
#define SSPSTS_ALL_RNE_Pos (3)
#define SSPSTS_ALL_RNE_Msk (0x1UL << SSPSTS_ALL_RNE_Pos)

typedef enum
{
    SSPSTS_BIT_RNE_EMPTY         = 0,  /*!< RXFIFO is empty       */
    SSPSTS_BIT_RNE_NOT_EMPTY     = 1,  /*!< RXFIFO is not empty   */
} SSPSTS_BIT_RNE;

#define SSPSTS_ALL_RNE_EMPTY         ((0x0UL) << SSPSTS_ALL_RNE_Pos)
#define SSPSTS_ALL_RNE_NOT_EMPTY     ((0x1UL) << SSPSTS_ALL_RNE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          BUSY
 *  @access     SSP->SSPSTS.bit.BUSY
 *  @brief      SSP busy
 */
#define SSPSTS_ALL_BUSY_Pos (4)
#define SSPSTS_ALL_BUSY_Msk (0x1UL << SSPSTS_ALL_BUSY_Pos)

typedef enum
{
    SSPSTS_BIT_BUSY_PORT_IDLE     = 0,  /*!< SSP port is idle or disabled                                  */
    SSPSTS_BIT_BUSY_PORT_BUSY     = 1,  /*!< SSP port is currently transmitting or receiving framed data   */
} SSPSTS_BIT_BUSY;

#define SSPSTS_ALL_BUSY_PORT_IDLE     ((0x0UL) << SSPSTS_ALL_BUSY_Pos)
#define SSPSTS_ALL_BUSY_PORT_BUSY     ((0x1UL) << SSPSTS_ALL_BUSY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          TFS
 *  @access     SSP->SSPSTS.bit.TFS
 *  @brief      Transmit FIFO service request
 */
#define SSPSTS_ALL_TFS_Pos (5)
#define SSPSTS_ALL_TFS_Msk (0x1UL << SSPSTS_ALL_TFS_Pos)

typedef enum
{
    SSPSTS_BIT_TFS_NOT_OCCUR     = 0,  /*!< TXFIFO level exceeds the threshold (TFTH), or SSP port disabled   */
    SSPSTS_BIT_TFS_OCCUR         = 1,  /*!< TXFIFO level is at or below threshold (TFTH)                      */
} SSPSTS_BIT_TFS;

#define SSPSTS_ALL_TFS_NOT_OCCUR     ((0x0UL) << SSPSTS_ALL_TFS_Pos)
#define SSPSTS_ALL_TFS_OCCUR         ((0x1UL) << SSPSTS_ALL_TFS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          RFS
 *  @access     SSP->SSPSTS.bit.RFS
 *  @brief      Receive FIFO service request
 */
#define SSPSTS_ALL_RFS_Pos (6)
#define SSPSTS_ALL_RFS_Msk (0x1UL << SSPSTS_ALL_RFS_Pos)

typedef enum
{
    SSPSTS_BIT_RFS_NOT_OCCUR     = 0,  /*!< RXFIFO level is at or below RXFIFO threshold (RFTH + 1), or SSP port is disabled   */
    SSPSTS_BIT_RFS_OCCUR         = 1,  /*!< RXFIFO level exceeds RXFIFO threshold (RFTH + 1 )                                  */
} SSPSTS_BIT_RFS;

#define SSPSTS_ALL_RFS_NOT_OCCUR     ((0x0UL) << SSPSTS_ALL_RFS_Pos)
#define SSPSTS_ALL_RFS_OCCUR         ((0x1UL) << SSPSTS_ALL_RFS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          RFOVF
 *  @access     SSP->SSPSTS.bit.RFOVF
 *  @brief      Receive FIFO overflow
 */
#define SSPSTS_ALL_RFOVF_Pos (7)
#define SSPSTS_ALL_RFOVF_Msk (0x1UL << SSPSTS_ALL_RFOVF_Pos)

typedef enum
{
    SSPSTS_BIT_RFOVF_NOT_OCCUR       = 0,  /*!< Read a 0 indicates no receive FIFO overflow.                 
                                                Write a 0 has no effect.                                      */
    SSPSTS_BIT_RFOVF_OCCUR_CLEAR     = 1,  /*!< Read a 1 indicates data put to a full RXFIFO was attempted.  
                                                Write a 1 clears the latched flag.                            */
} SSPSTS_BIT_RFOVF;

#define SSPSTS_ALL_RFOVF_NOT_OCCUR       ((0x0UL) << SSPSTS_ALL_RFOVF_Pos)
#define SSPSTS_ALL_RFOVF_OCCUR_CLEAR     ((0x1UL) << SSPSTS_ALL_RFOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          TFLVL
 *  @access     SSP->SSPSTS.bit.TFLVL
 *  @brief      Transmit FIFO level
 *              The value is number of entries in TXFIFO.
 */
#define SSPSTS_ALL_TFLVL_Pos (8)
#define SSPSTS_ALL_TFLVL_Msk (0xFUL << SSPSTS_ALL_TFLVL_Pos)

#define SSPSTS_BIT_TFLVL

#define SSPSTS_ALL_TFLVL_(x) ((x) << SSPSTS_ALL_TFLVL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          RFLVL
 *  @access     SSP->SSPSTS.bit.RFLVL
 *  @brief      Receive FIFO level
 *              The value is number of entries minus one in RXFIFO.
 */
#define SSPSTS_ALL_RFLVL_Pos (12)
#define SSPSTS_ALL_RFLVL_Msk (0xFUL << SSPSTS_ALL_RFLVL_Pos)

#define SSPSTS_BIT_RFLVL

#define SSPSTS_ALL_RFLVL_(x) ((x) << SSPSTS_ALL_RFLVL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          RXTO
 *  @access     SSP->SSPSTS.bit.RXTO
 *  @brief      Receiver time-out
 */
#define SSPSTS_ALL_RXTO_Pos (19)
#define SSPSTS_ALL_RXTO_Msk (0x1UL << SSPSTS_ALL_RXTO_Pos)

typedef enum
{
    SSPSTS_BIT_RXTO_NOT_OCCUR       = 0,  /*!< Read a 0 indicates no time-out on receiving.  
                                               Write a 0 has no effect.                       */
    SSPSTS_BIT_RXTO_OCCUR_CLEAR     = 1,  /*!< Read a 1 indicates time-out on receiving.     
                                               Write a 1 clears the latched flag.             */
} SSPSTS_BIT_RXTO;

#define SSPSTS_ALL_RXTO_NOT_OCCUR       ((0x0UL) << SSPSTS_ALL_RXTO_Pos)
#define SSPSTS_ALL_RXTO_OCCUR_CLEAR     ((0x1UL) << SSPSTS_ALL_RXTO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          TFUDF
 *  @access     SSP->SSPSTS.bit.TFUDF
 *  @brief      Transmit FIFO underflow
 */
#define SSPSTS_ALL_TFUDF_Pos (21)
#define SSPSTS_ALL_TFUDF_Msk (0x1UL << SSPSTS_ALL_TFUDF_Pos)

typedef enum
{
    SSPSTS_BIT_TFUDF_NOT_OCCUR       = 0,  /*!< Read a 0 indicates no TXFIFO overflow                             
                                                Write a 0 has no effect                                            */
    SSPSTS_BIT_TFUDF_OCCUR_CLEAR     = 1,  /*!< Read a 1 indicates data fetch from an empty TXFIFO was attempted  
                                                Write a 1 clears the latched flag                                  */
} SSPSTS_BIT_TFUDF;

#define SSPSTS_ALL_TFUDF_NOT_OCCUR       ((0x0UL) << SSPSTS_ALL_TFUDF_Pos)
#define SSPSTS_ALL_TFUDF_OCCUR_CLEAR     ((0x1UL) << SSPSTS_ALL_TFUDF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          SLVCLKSTS
 *  @access     SSP->SSPSTS.bit.SLVCLKSTS
 *  @brief      Slave clock status
 */
#define SSPSTS_ALL_SLVCLKSTS_Pos (22)
#define SSPSTS_ALL_SLVCLKSTS_Msk (0x1UL << SSPSTS_ALL_SLVCLKSTS_Pos)

typedef enum
{
    SSPSTS_BIT_SLVCLKSTS_SLAVE_PORT_READY     = 0,  /*!< The SSP port is ready for slave clock operations                  */
    SSPSTS_BIT_SLVCLKSTS_SLAVE_PORT_BUSY      = 1,  /*!< The SSP port is currently busy synchronizing slave mode signals   */
} SSPSTS_BIT_SLVCLKSTS;

#define SSPSTS_ALL_SLVCLKSTS_SLAVE_PORT_READY     ((0x0UL) << SSPSTS_ALL_SLVCLKSTS_Pos)
#define SSPSTS_ALL_SLVCLKSTS_SLAVE_PORT_BUSY      ((0x1UL) << SSPSTS_ALL_SLVCLKSTS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          TFODDSTS
 *  @access     SSP->SSPSTS.bit.TFODDSTS
 *  @brief      TX FIFO odd sample status
 *              This bit is used only when FIFO packing is enabled
 */
#define SSPSTS_ALL_TFODDSTS_Pos (30)
#define SSPSTS_ALL_TFODDSTS_Msk (0x1UL << SSPSTS_ALL_TFODDSTS_Pos)

typedef enum
{
    SSPSTS_BIT_TFODDSTS_EVEN_SAMPLE_IN_TXFIFO     = 0,  /*!< TXFIFO entry has a even number of samples   */
    SSPSTS_BIT_TFODDSTS_ODD_SAMPLE_IN_TXFIFO      = 1,  /*!< TXFIFO entry has an odd number of samples   */
} SSPSTS_BIT_TFODDSTS;

#define SSPSTS_ALL_TFODDSTS_EVEN_SAMPLE_IN_TXFIFO     ((0x0UL) << SSPSTS_ALL_TFODDSTS_Pos)
#define SSPSTS_ALL_TFODDSTS_ODD_SAMPLE_IN_TXFIFO      ((0x1UL) << SSPSTS_ALL_TFODDSTS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPSTS          RFODDSTS
 *  @access     SSP->SSPSTS.bit.RFODDSTS
 *  @brief      RX FIFO odd sample status
 *              This bit is used only when FIFO packing is enabled
 */
#define SSPSTS_ALL_RFODDSTS_Pos (31)
#define SSPSTS_ALL_RFODDSTS_Msk (0x1UL << SSPSTS_ALL_RFODDSTS_Pos)

typedef enum
{
    SSPSTS_BIT_RFODDSTS_2_SAMPLE_IN_RXFIFO     = 0,  /*!< RXFIFO entry has 2 samples   */
    SSPSTS_BIT_RFODDSTS_1_SAMPLE_IN_RXFIFO     = 1,  /*!< RXFIFO entry has 1 sample    */
} SSPSTS_BIT_RFODDSTS;

#define SSPSTS_ALL_RFODDSTS_2_SAMPLE_IN_RXFIFO     ((0x0UL) << SSPSTS_ALL_RFODDSTS_Pos)
#define SSPSTS_ALL_RFODDSTS_1_SAMPLE_IN_RXFIFO     ((0x1UL) << SSPSTS_ALL_RFODDSTS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPFRC          TFREQ
 *  @access     SSP->SSPFRC.bit.TFREQ
 *  @brief      Force TXFIFO service request (Non-maskable)
 */
#define SSPFRC_ALL_TFREQ_Pos (5)
#define SSPFRC_ALL_TFREQ_Msk (0x1UL << SSPFRC_ALL_TFREQ_Pos)

typedef enum
{
    SSPFRC_BIT_TFREQ_RELEASE_FORCE     = 0,  /*!< Write a 0 release the force                          */
    SSPFRC_BIT_TFREQ_FORCE             = 1,  /*!< Write a 1 force a TXFIFO service request interrupt  
                                                  This bit needs to be cleared manually                */
} SSPFRC_BIT_TFREQ;

#define SSPFRC_ALL_TFREQ_RELEASE_FORCE     ((0x0UL) << SSPFRC_ALL_TFREQ_Pos)
#define SSPFRC_ALL_TFREQ_FORCE             ((0x1UL) << SSPFRC_ALL_TFREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPFRC          RFREQ
 *  @access     SSP->SSPFRC.bit.RFREQ
 *  @brief      Force RXFIFO service request (Non-maskable)
 */
#define SSPFRC_ALL_RFREQ_Pos (6)
#define SSPFRC_ALL_RFREQ_Msk (0x1UL << SSPFRC_ALL_RFREQ_Pos)

typedef enum
{
    SSPFRC_BIT_RFREQ_RELEASE_FORCE     = 0,  /*!< Write a 0 release the force                          */
    SSPFRC_BIT_RFREQ_FORCE             = 1,  /*!< Write a 1 force a RXFIFO service request interrupt  
                                                  This bit needs to be cleared manually                */
} SSPFRC_BIT_RFREQ;

#define SSPFRC_ALL_RFREQ_RELEASE_FORCE     ((0x0UL) << SSPFRC_ALL_RFREQ_Pos)
#define SSPFRC_ALL_RFREQ_FORCE             ((0x1UL) << SSPFRC_ALL_RFREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPFRC          RFOVF
 *  @access     SSP->SSPFRC.bit.RFOVF
 *  @brief      Force RXFIFO overrun (Non-maskable)
 */
#define SSPFRC_ALL_RFOVF_Pos (7)
#define SSPFRC_ALL_RFOVF_Msk (0x1UL << SSPFRC_ALL_RFOVF_Pos)

typedef enum
{
    SSPFRC_BIT_RFOVF_RELEASE_FORCE     = 0,  /*!< Write a 0 release the force                  */
    SSPFRC_BIT_RFOVF_FORCE             = 1,  /*!< Write a 1 force a RXFIFO overrun interrupt  
                                                  This bit needs to be cleared manually        */
} SSPFRC_BIT_RFOVF;

#define SSPFRC_ALL_RFOVF_RELEASE_FORCE     ((0x0UL) << SSPFRC_ALL_RFOVF_Pos)
#define SSPFRC_ALL_RFOVF_FORCE             ((0x1UL) << SSPFRC_ALL_RFOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPDATA         VAL
 *  @access     SSP->SSPDATA.bit.VAL
 *  @brief      Data to be written to the TXFIFO or read from the RXFIFO
 */
#define SSPDATA_ALL_VAL_Pos (0)
#define SSPDATA_ALL_VAL_Msk (0xFFFFFFFFUL << SSPDATA_ALL_VAL_Pos)

#define SSPDATA_BIT_VAL

#define SSPDATA_ALL_VAL_(x) ((x) << SSPDATA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SSP             SSPTO           VAL
 *  @access     SSP->SSPTO.bit.VAL
 *  @brief      Timeout interval defined as 2^VAL-1.
 */
#define SSPTO_ALL_VAL_Pos (0)
#define SSPTO_ALL_VAL_Msk (0xFFFFFFUL << SSPTO_ALL_VAL_Pos)

#define SSPTO_BIT_VAL

#define SSPTO_ALL_VAL_(x) ((x) << SSPTO_ALL_VAL_Pos)



/********************************************************************************
*
* Module Name     I2C
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CCTL          MASTER
 *  @access     I2C->I2CCTL.bit.MASTER
 *  @brief      Enable I2C master
 *              The bit should be the same as SLVDIS
 */
#define I2CCTL_ALL_MASTER_Pos (0)
#define I2CCTL_ALL_MASTER_Msk (0x1UL << I2CCTL_ALL_MASTER_Pos)

typedef enum
{
    I2CCTL_BIT_MASTER_DISABLE     = 0,  /*!< Disable I2C master   */
    I2CCTL_BIT_MASTER_ENABLE      = 1,  /*!< Enable I2C master    */
} I2CCTL_BIT_MASTER;

#define I2CCTL_ALL_MASTER_DISABLE     ((0x0UL) << I2CCTL_ALL_MASTER_Pos)
#define I2CCTL_ALL_MASTER_ENABLE      ((0x1UL) << I2CCTL_ALL_MASTER_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CCTL          SPEED
 *  @access     I2C->I2CCTL.bit.SPEED
 *  @brief      Speed in master mode
 */
#define I2CCTL_ALL_SPEED_Pos (1)
#define I2CCTL_ALL_SPEED_Msk (0x3UL << I2CCTL_ALL_SPEED_Pos)

typedef enum
{
    I2CCTL_BIT_SPEED_100K_BPS      = 1,  /*!< Standard mode (100 kbit/s)     */
    I2CCTL_BIT_SPEED_400K_BPS      = 2,  /*!< Fast mode (400 kbit/s)         */
    I2CCTL_BIT_SPEED_3400K_BPS     = 3,  /*!< High speed mode (3.4 Mbit/s)   */
} I2CCTL_BIT_SPEED;

#define I2CCTL_ALL_SPEED_100K_BPS      ((0x1UL) << I2CCTL_ALL_SPEED_Pos)
#define I2CCTL_ALL_SPEED_400K_BPS      ((0x2UL) << I2CCTL_ALL_SPEED_Pos)
#define I2CCTL_ALL_SPEED_3400K_BPS     ((0x3UL) << I2CCTL_ALL_SPEED_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CCTL          SLVADDR10B
 *  @access     I2C->I2CCTL.bit.SLVADDR10B
 *  @brief      Addressing mode in slave mode
 */
#define I2CCTL_ALL_SLVADDR10B_Pos (3)
#define I2CCTL_ALL_SLVADDR10B_Msk (0x1UL << I2CCTL_ALL_SLVADDR10B_Pos)

typedef enum
{
    I2CCTL_BIT_SLVADDR10B_7BIT_ADDR      = 0,  /*!< 7-bit addressing                                                                    
                                                    The I2C ignores transactions that involve 10-bit addressing; for 7-bit addressing,  
                                                    only the lower 7 bits of the I2CSLVADDR register are compared.                       */
    I2CCTL_BIT_SLVADDR10B_10BIT_ADDR     = 1,  /*!< 10-bit addressing                                                                   
                                                    The I2C responds to only 10-bit addressing transfers that match the full 10 bits    
                                                    of the I2CSLVADDR register.                                                          */
} I2CCTL_BIT_SLVADDR10B;

#define I2CCTL_ALL_SLVADDR10B_7BIT_ADDR      ((0x0UL) << I2CCTL_ALL_SLVADDR10B_Pos)
#define I2CCTL_ALL_SLVADDR10B_10BIT_ADDR     ((0x1UL) << I2CCTL_ALL_SLVADDR10B_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CCTL          ADDRSTS
 *  @access     I2C->I2CCTL.bit.ADDRSTS
 *  @brief      Read-only copy of I2CMASTERADDR[12]
 */
#define I2CCTL_ALL_ADDRSTS_Pos (4)
#define I2CCTL_ALL_ADDRSTS_Msk (0x1UL << I2CCTL_ALL_ADDRSTS_Pos)

typedef enum
{
    I2CCTL_BIT_ADDRSTS_7BIT_ADDR      = 0,  /*!< 7-bit addressing    */
    I2CCTL_BIT_ADDRSTS_10BIT_ADDR     = 1,  /*!< 10-bit addressing   */
} I2CCTL_BIT_ADDRSTS;

#define I2CCTL_ALL_ADDRSTS_7BIT_ADDR      ((0x0UL) << I2CCTL_ALL_ADDRSTS_Pos)
#define I2CCTL_ALL_ADDRSTS_10BIT_ADDR     ((0x1UL) << I2CCTL_ALL_ADDRSTS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CCTL          RESTARTEN
 *  @access     I2C->I2CCTL.bit.RESTARTEN
 *  @brief      Determines whether RESTART conditions may be sent when acting as a master. Some older
 *              slaves do not support handling RESTART conditions; however, RESTART conditions are
 *              used in several I2C operations.
 *              When RESTART is disabled, the master is prohibited from performing the following
 *              functions:
 *              - Change direction within a transfer (split)
 *              - Send a START BYTE
 *              - High-speed mode operation
 *              - Combined format transfers in 7-bit addressing modes
 *              - Read operation with a 10-bit address
 *              - Send multiple bytes per transfer By replacing RESTART condition followed by a STOP
 *              and a subsequent START condition, split operations are broken down into multiple
 *              I2C transfers. If the above operations are performed, it will result in setting bit
 *              6 (TXABRT) of the I2CRAWIF register.
 */
#define I2CCTL_ALL_RESTARTEN_Pos (5)
#define I2CCTL_ALL_RESTARTEN_Msk (0x1UL << I2CCTL_ALL_RESTARTEN_Pos)

typedef enum
{
    I2CCTL_BIT_RESTARTEN_DISABLE     = 0,  /*!< Disable   */
    I2CCTL_BIT_RESTARTEN_ENABLE      = 1,  /*!< Enable    */
} I2CCTL_BIT_RESTARTEN;

#define I2CCTL_ALL_RESTARTEN_DISABLE     ((0x0UL) << I2CCTL_ALL_RESTARTEN_Pos)
#define I2CCTL_ALL_RESTARTEN_ENABLE      ((0x1UL) << I2CCTL_ALL_RESTARTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CCTL          SLVDIS
 *  @access     I2C->I2CCTL.bit.SLVDIS
 *  @brief      Disable I2C slave
 *              This bit should be the same as MASTER
 */
#define I2CCTL_ALL_SLVDIS_Pos (6)
#define I2CCTL_ALL_SLVDIS_Msk (0x1UL << I2CCTL_ALL_SLVDIS_Pos)

typedef enum
{
    I2CCTL_BIT_SLVDIS_SLAVE_ENABLE      = 0,  /*!< Enable I2C slave    */
    I2CCTL_BIT_SLVDIS_SLAVE_DISABLE     = 1,  /*!< Dsiable I2C slave   */
} I2CCTL_BIT_SLVDIS;

#define I2CCTL_ALL_SLVDIS_SLAVE_ENABLE      ((0x0UL) << I2CCTL_ALL_SLVDIS_Pos)
#define I2CCTL_ALL_SLVDIS_SLAVE_DISABLE     ((0x1UL) << I2CCTL_ALL_SLVDIS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CMASTERADDR   TARADDR
 *  @access     I2C->I2CMASTERADDR.bit.TARADDR
 *  @brief      Target address for any master transaction.
 *              These bits are ignored for issuing a General Call.
 *              To generate a START BYTE, the CPU needs to write only once into these bits.
 *              It should not be the same as I2CSLVADDR.
 */
#define I2CMASTERADDR_ALL_TARADDR_Pos (0)
#define I2CMASTERADDR_ALL_TARADDR_Msk (0x3FFUL << I2CMASTERADDR_ALL_TARADDR_Pos)

#define I2CMASTERADDR_BIT_TARADDR

#define I2CMASTERADDR_ALL_TARADDR_(x) ((x) << I2CMASTERADDR_ALL_TARADDR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CMASTERADDR   GCORSTART
 *  @access     I2C->I2CMASTERADDR.bit.GCORSTART
 *  @brief      Special command select
 */
#define I2CMASTERADDR_ALL_GCORSTART_Pos (10)
#define I2CMASTERADDR_ALL_GCORSTART_Msk (0x1UL << I2CMASTERADDR_ALL_GCORSTART_Pos)

typedef enum
{
    I2CMASTERADDR_BIT_GCORSTART_GENERAL_CALL     = 0,  /*!< General Call                                                                       
                                                            After issuing a General Call, only writes may be performed. Attempting to issue a  
                                                            read command results in setting bit 6 (TXABRT) of the I2CRAWIF register. The I2C   
                                                            remains in General Call mode until the SPECIAL bit is cleared                       */
    I2CMASTERADDR_BIT_GCORSTART_START            = 1,  /*!< Start Byte                                                                          */
} I2CMASTERADDR_BIT_GCORSTART;

#define I2CMASTERADDR_ALL_GCORSTART_GENERAL_CALL     ((0x0UL) << I2CMASTERADDR_ALL_GCORSTART_Pos)
#define I2CMASTERADDR_ALL_GCORSTART_START            ((0x1UL) << I2CMASTERADDR_ALL_GCORSTART_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CMASTERADDR   SPECIAL
 *  @access     I2C->I2CMASTERADDR.bit.SPECIAL
 *  @brief      Special command enable
 */
#define I2CMASTERADDR_ALL_SPECIAL_Pos (11)
#define I2CMASTERADDR_ALL_SPECIAL_Msk (0x1UL << I2CMASTERADDR_ALL_SPECIAL_Pos)

typedef enum
{
    I2CMASTERADDR_BIT_SPECIAL_DISABLE     = 0,  /*!< Disable special command and ignore GCORSTART bit       */
    I2CMASTERADDR_BIT_SPECIAL_ENABLE      = 1,  /*!< Enable special command as specified in GCORSTART bit   */
} I2CMASTERADDR_BIT_SPECIAL;

#define I2CMASTERADDR_ALL_SPECIAL_DISABLE     ((0x0UL) << I2CMASTERADDR_ALL_SPECIAL_Pos)
#define I2CMASTERADDR_ALL_SPECIAL_ENABLE      ((0x1UL) << I2CMASTERADDR_ALL_SPECIAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CMASTERADDR   MASTERADDR10B
 *  @access     I2C->I2CMASTERADDR.bit.MASTERADDR10B
 *  @brief      Addressing mode in master mode
 */
#define I2CMASTERADDR_ALL_MASTERADDR10B_Pos (12)
#define I2CMASTERADDR_ALL_MASTERADDR10B_Msk (0x1UL << I2CMASTERADDR_ALL_MASTERADDR10B_Pos)

typedef enum
{
    I2CMASTERADDR_BIT_MASTERADDR10B_7BIT_ADDR      = 0,  /*!< 7-bit addressing    */
    I2CMASTERADDR_BIT_MASTERADDR10B_10BIT_ADDR     = 1,  /*!< 10-bit addressing   */
} I2CMASTERADDR_BIT_MASTERADDR10B;

#define I2CMASTERADDR_ALL_MASTERADDR10B_7BIT_ADDR      ((0x0UL) << I2CMASTERADDR_ALL_MASTERADDR10B_Pos)
#define I2CMASTERADDR_ALL_MASTERADDR10B_10BIT_ADDR     ((0x1UL) << I2CMASTERADDR_ALL_MASTERADDR10B_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSLVADDR      VAL
 *  @access     I2C->I2CSLVADDR.bit.VAL
 *  @brief      Slave address when I2C acts as a slave
 *              This register can be written only when the I2C interface is disabled (I2CENABLE=0).
 *              Writes at other times have no effect.
 *              Note: The default values cannot be any of the reserved address locations: that is,
 *              0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed
 *              if you program the I2CSLVADDR or I2CMASTERADDR to a reserved value.
 */
#define I2CSLVADDR_ALL_VAL_Pos (0)
#define I2CSLVADDR_ALL_VAL_Msk (0x3FFUL << I2CSLVADDR_ALL_VAL_Pos)

#define I2CSLVADDR_BIT_VAL

#define I2CSLVADDR_ALL_VAL_(x) ((x) << I2CSLVADDR_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CHSMADDR      VAL
 *  @access     I2C->I2CHSMADDR.bit.VAL
 *  @brief      The 3LSBs of the 8-bit high-speed mode master code in format of (0x00001xxx)
 *              This register can be written only when the I2C interface is disabled (I2CENABLE=0)
 *              Writes at other times have no effect.
 */
#define I2CHSMADDR_ALL_VAL_Pos (0)
#define I2CHSMADDR_ALL_VAL_Msk (0x7UL << I2CHSMADDR_ALL_VAL_Pos)

#define I2CHSMADDR_BIT_VAL

#define I2CHSMADDR_ALL_VAL_(x) ((x) << I2CHSMADDR_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CDATACMD      DATA
 *  @access     I2C->I2CDATACMD.bit.DATA
 *  @brief      Data transmitted or received on the I2C bus.
 *              A write to the register sets the data to be transmitted.
 *              A read to the register gets the received data.
 */
#define I2CDATACMD_ALL_DATA_Pos (0)
#define I2CDATACMD_ALL_DATA_Msk (0xFFUL << I2CDATACMD_ALL_DATA_Pos)

#define I2CDATACMD_BIT_DATA

#define I2CDATACMD_ALL_DATA_(x) ((x) << I2CDATACMD_ALL_DATA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CDATACMD      CMD
 *  @access     I2C->I2CDATACMD.bit.CMD
 *  @brief      Read or write control
 */
#define I2CDATACMD_ALL_CMD_Pos (8)
#define I2CDATACMD_ALL_CMD_Msk (0x1UL << I2CDATACMD_ALL_CMD_Pos)

typedef enum
{
    I2CDATACMD_BIT_CMD_WRITE     = 0,  /*!< Write   */
    I2CDATACMD_BIT_CMD_READ      = 1,  /*!< Read    */
} I2CDATACMD_BIT_CMD;

#define I2CDATACMD_ALL_CMD_WRITE     ((0x0UL) << I2CDATACMD_ALL_CMD_Pos)
#define I2CDATACMD_ALL_CMD_READ      ((0x1UL) << I2CDATACMD_ALL_CMD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSSHCNT       VAL
 *  @access     I2C->I2CSSHCNT.bit.VAL
 *  @brief      Duration for SCL high in standard speed mode.
 *              i.e. SCL is high for I2CSSHCNT clock cycles
 *              The minimum valid value is 6. Write a value below 6 will be reset as 6 by the hardware.
 *              Register can be written only when I2CENABLE=0. Writes at other times have no effect.
 */
#define I2CSSHCNT_ALL_VAL_Pos (0)
#define I2CSSHCNT_ALL_VAL_Msk (0xFFFFUL << I2CSSHCNT_ALL_VAL_Pos)

#define I2CSSHCNT_BIT_VAL

#define I2CSSHCNT_ALL_VAL_(x) ((x) << I2CSSHCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSSLCNT       VAL
 *  @access     I2C->I2CSSLCNT.bit.VAL
 *  @brief      Duration for SCL low in standard speed mode.
 *              i.e. SCL is low for I2CSSLCNT clock cycles
 *              The minimum valid value is 8. Write a value below 8 will be reset as 8 by the hardware.
 *              Register can be written only when I2CENABLE=0. Writes at other times have no effect.
 */
#define I2CSSLCNT_ALL_VAL_Pos (0)
#define I2CSSLCNT_ALL_VAL_Msk (0xFFFFUL << I2CSSLCNT_ALL_VAL_Pos)

#define I2CSSLCNT_BIT_VAL

#define I2CSSLCNT_ALL_VAL_(x) ((x) << I2CSSLCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CFSHCNT       VAL
 *  @access     I2C->I2CFSHCNT.bit.VAL
 *  @brief      Duration for SCL high in fast speed mode.
 *              i.e. SCL is high for I2CFSHCNT clock cycles
 *              The minimum valid value is 6. Write a value below 6 will be reset as 6 by the hardware.
 *              Register can be written only when I2CENABLE=0. Writes at other times have no effect.
 */
#define I2CFSHCNT_ALL_VAL_Pos (0)
#define I2CFSHCNT_ALL_VAL_Msk (0xFFFFUL << I2CFSHCNT_ALL_VAL_Pos)

#define I2CFSHCNT_BIT_VAL

#define I2CFSHCNT_ALL_VAL_(x) ((x) << I2CFSHCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CFSLCNT       VAL
 *  @access     I2C->I2CFSLCNT.bit.VAL
 *  @brief      Duration for SCL low in fast speed mode.
 *              i.e. SCL is low for I2CFSLCNT clock cycles
 *              The minimum valid value is 8. Write a value below 8 will be reset as 8 by the hardware.
 *              Register can be written only when I2CENABLE=0. Writes at other times have no effect.
 */
#define I2CFSLCNT_ALL_VAL_Pos (0)
#define I2CFSLCNT_ALL_VAL_Msk (0xFFFFUL << I2CFSLCNT_ALL_VAL_Pos)

#define I2CFSLCNT_BIT_VAL

#define I2CFSLCNT_ALL_VAL_(x) ((x) << I2CFSLCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CHSHCNT       VAL
 *  @access     I2C->I2CHSHCNT.bit.VAL
 *  @brief      Duration for SCL high in high speed mode.
 *              i.e. SCL is high for I2CHSHCNT clock cycles
 *              The minimum valid value is 6. Write a value below 6 will be reset as 6 by the hardware.
 *              Register can be written only when I2CENABLE=0. Writes at other times have no effect.
 */
#define I2CHSHCNT_ALL_VAL_Pos (0)
#define I2CHSHCNT_ALL_VAL_Msk (0xFFFFUL << I2CHSHCNT_ALL_VAL_Pos)

#define I2CHSHCNT_BIT_VAL

#define I2CHSHCNT_ALL_VAL_(x) ((x) << I2CHSHCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CHSLCNT       VAL
 *  @access     I2C->I2CHSLCNT.bit.VAL
 *  @brief      Duration for SCL low in high speed mode.
 *              i.e. SCL is low for I2CHSLCNT clock cycles
 *              The minimum valid value is 8. Write a value below 8 will be reset as 8 by the hardware.
 *              Register can be written only when I2CENABLE=0. Writes at other times have no effect.
 */
#define I2CHSLCNT_ALL_VAL_Pos (0)
#define I2CHSLCNT_ALL_VAL_Msk (0xFFFFUL << I2CHSLCNT_ALL_VAL_Pos)

#define I2CHSLCNT_BIT_VAL

#define I2CHSLCNT_ALL_VAL_(x) ((x) << I2CHSLCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           RXUDF
 *  @access     I2C->I2CIF.bit.RXUDF
 *  @brief      Flag to indicate the processor attempts to read the receive buffer via I2CDATACMD
 *              register when it is empty
 */
#define I2CIF_ALL_RXUDF_Pos (0)
#define I2CIF_ALL_RXUDF_Msk (0x1UL << I2CIF_ALL_RXUDF_Pos)

typedef enum
{
    I2CIF_BIT_RXUDF_NOT_OCCUR     = 0,  /*!< Receive buffer does not underflow   */
    I2CIF_BIT_RXUDF_OCCUR         = 1,  /*!< Receive buffer underflows           */
} I2CIF_BIT_RXUDF;

#define I2CIF_ALL_RXUDF_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_RXUDF_Pos)
#define I2CIF_ALL_RXUDF_OCCUR         ((0x1UL) << I2CIF_ALL_RXUDF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           RXOVF
 *  @access     I2C->I2CIF.bit.RXOVF
 *  @brief      Flag to indicate the receive buffer is completely filled to 16 and an additional
 *              byte is received from an external I2C device. The I2C acknowledges this, but any
 *              data bytes received after the FIFO is full are lost.
 */
#define I2CIF_ALL_RXOVF_Pos (1)
#define I2CIF_ALL_RXOVF_Msk (0x1UL << I2CIF_ALL_RXOVF_Pos)

typedef enum
{
    I2CIF_BIT_RXOVF_NOT_OCCUR     = 0,  /*!< Receive buffer does not overflow   */
    I2CIF_BIT_RXOVF_OCCUR         = 1,  /*!< Receive buffer overflows           */
} I2CIF_BIT_RXOVF;

#define I2CIF_ALL_RXOVF_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_RXOVF_Pos)
#define I2CIF_ALL_RXOVF_OCCUR         ((0x1UL) << I2CIF_ALL_RXOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           RXDAV
 *  @access     I2C->I2CIF.bit.RXDAV
 *  @brief      Flag to indicate the receive buffer reaches or goes above the threshold in the I2CRXTH
 *              register so data is available to read
 */
#define I2CIF_ALL_RXDAV_Pos (2)
#define I2CIF_ALL_RXDAV_Msk (0x1UL << I2CIF_ALL_RXDAV_Pos)

typedef enum
{
    I2CIF_BIT_RXDAV_NOT_OCCUR     = 0,  /*!< Receive buffer is below threshold              */
    I2CIF_BIT_RXDAV_OCCUR         = 1,  /*!< Receive buffer is at or above the threshold   
                                             Self-cleared when level goes below threshold   */
} I2CIF_BIT_RXDAV;

#define I2CIF_ALL_RXDAV_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_RXDAV_Pos)
#define I2CIF_ALL_RXDAV_OCCUR         ((0x1UL) << I2CIF_ALL_RXDAV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           TXOVF
 *  @access     I2C->I2CIF.bit.TXOVF
 *  @brief      Flag to indicate an attempt to write I2CDATACMD register when transmit buffer is
 *              fill to 15
 */
#define I2CIF_ALL_TXOVF_Pos (3)
#define I2CIF_ALL_TXOVF_Msk (0x1UL << I2CIF_ALL_TXOVF_Pos)

typedef enum
{
    I2CIF_BIT_TXOVF_NOT_OCCUR     = 0,  /*!< Transmit buffer does not overflow   */
    I2CIF_BIT_TXOVF_OCCUR         = 1,  /*!< Transmit buffer overflows           */
} I2CIF_BIT_TXOVF;

#define I2CIF_ALL_TXOVF_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_TXOVF_Pos)
#define I2CIF_ALL_TXOVF_OCCUR         ((0x1UL) << I2CIF_ALL_TXOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           TXDREQ
 *  @access     I2C->I2CIF.bit.TXDREQ
 *  @brief      Flag to indicate the transmit buffer is at or below the threshold value set in the
 *              I2CTXTH register so requets more data
 */
#define I2CIF_ALL_TXDREQ_Pos (4)
#define I2CIF_ALL_TXDREQ_Msk (0x1UL << I2CIF_ALL_TXDREQ_Pos)

typedef enum
{
    I2CIF_BIT_TXDREQ_NOT_OCCUR     = 0,  /*!< Transmit buffer is above threshold             */
    I2CIF_BIT_TXDREQ_OCCUR         = 1,  /*!< Transmit buffer is at or below the threshold  
                                              Self-cleared when level goes above threshold   */
} I2CIF_BIT_TXDREQ;

#define I2CIF_ALL_TXDREQ_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_TXDREQ_Pos)
#define I2CIF_ALL_TXDREQ_OCCUR         ((0x1UL) << I2CIF_ALL_TXDREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           RDREQ
 *  @access     I2C->I2CIF.bit.RDREQ
 *  @brief      Latched external master read request flag when the I2C is acting as a slave
 */
#define I2CIF_ALL_RDREQ_Pos (5)
#define I2CIF_ALL_RDREQ_Msk (0x1UL << I2CIF_ALL_RDREQ_Pos)

typedef enum
{
    I2CIF_BIT_RDREQ_NOT_OCCUR     = 0,  /*!< No read request is received from another master                                     */
    I2CIF_BIT_RDREQ_OCCUR         = 1,  /*!< Read request was received from another master.                                     
                                             The processor must respond to this interrupt and then write the requested data to  
                                             the I2CDATACMD register.                                                            */
} I2CIF_BIT_RDREQ;

#define I2CIF_ALL_RDREQ_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_RDREQ_Pos)
#define I2CIF_ALL_RDREQ_OCCUR         ((0x1UL) << I2CIF_ALL_RDREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           TXABRT
 *  @access     I2C->I2CIF.bit.TXABRT
 *  @brief      Latched transmission abort flag
 */
#define I2CIF_ALL_TXABRT_Pos (6)
#define I2CIF_ALL_TXABRT_Msk (0x1UL << I2CIF_ALL_TXABRT_Pos)

typedef enum
{
    I2CIF_BIT_TXABRT_NOT_OCCUR     = 0,  /*!< No transmission abortion occurred                                                            */
    I2CIF_BIT_TXABRT_OCCUR         = 1,  /*!< Transimission aborted and TX FIFO remains in flushed state until the register I2CTXABRTCLR  
                                              is read                                                                                      */
} I2CIF_BIT_TXABRT;

#define I2CIF_ALL_TXABRT_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_TXABRT_Pos)
#define I2CIF_ALL_TXABRT_OCCUR         ((0x1UL) << I2CIF_ALL_TXABRT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           RXDONE
 *  @access     I2C->I2CIF.bit.RXDONE
 *  @brief      Flag to indicate external master receive is done when I2C acts as a slave transmitter
 */
#define I2CIF_ALL_RXDONE_Pos (7)
#define I2CIF_ALL_RXDONE_Msk (0x1UL << I2CIF_ALL_RXDONE_Pos)

typedef enum
{
    I2CIF_BIT_RXDONE_NOT_OCCUR     = 0,  /*!< Slave transmission is acknowledged by the other master, which continues data receiving.   */
    I2CIF_BIT_RXDONE_OCCUR         = 1,  /*!< Slave transmission is not acknowledge by the other master, which finishes the data       
                                              receiving                                                                                 */
} I2CIF_BIT_RXDONE;

#define I2CIF_ALL_RXDONE_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_RXDONE_Pos)
#define I2CIF_ALL_RXDONE_OCCUR         ((0x1UL) << I2CIF_ALL_RXDONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           ACT
 *  @access     I2C->I2CIF.bit.ACT
 *  @brief      Latched I2C activity status flag
 */
#define I2CIF_ALL_ACT_Pos (8)
#define I2CIF_ALL_ACT_Msk (0x1UL << I2CIF_ALL_ACT_Pos)

typedef enum
{
    I2CIF_BIT_ACT_NOT_OCCUR     = 0,  /*!< There is no activity detected on I2C interface   */
    I2CIF_BIT_ACT_OCCUR         = 1,  /*!< Activity has been detected on I2C interface      */
} I2CIF_BIT_ACT;

#define I2CIF_ALL_ACT_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_ACT_Pos)
#define I2CIF_ALL_ACT_OCCUR         ((0x1UL) << I2CIF_ALL_ACT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           STOPDET
 *  @access     I2C->I2CIF.bit.STOPDET
 *  @brief      STOP condition flag
 */
#define I2CIF_ALL_STOPDET_Pos (9)
#define I2CIF_ALL_STOPDET_Msk (0x1UL << I2CIF_ALL_STOPDET_Pos)

typedef enum
{
    I2CIF_BIT_STOPDET_NOT_OCCUR     = 0,  /*!< Condition is not detected   */
    I2CIF_BIT_STOPDET_OCCUR         = 1,  /*!< Condition is detected       */
} I2CIF_BIT_STOPDET;

#define I2CIF_ALL_STOPDET_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_STOPDET_Pos)
#define I2CIF_ALL_STOPDET_OCCUR         ((0x1UL) << I2CIF_ALL_STOPDET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           STARTDET
 *  @access     I2C->I2CIF.bit.STARTDET
 *  @brief      START or RESTART condition flag
 */
#define I2CIF_ALL_STARTDET_Pos (10)
#define I2CIF_ALL_STARTDET_Msk (0x1UL << I2CIF_ALL_STARTDET_Pos)

typedef enum
{
    I2CIF_BIT_STARTDET_NOT_OCCUR     = 0,  /*!< Condition is not detected   */
    I2CIF_BIT_STARTDET_OCCUR         = 1,  /*!< Condition is detected       */
} I2CIF_BIT_STARTDET;

#define I2CIF_ALL_STARTDET_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_STARTDET_Pos)
#define I2CIF_ALL_STARTDET_OCCUR         ((0x1UL) << I2CIF_ALL_STARTDET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIF           GENCALL
 *  @access     I2C->I2CIF.bit.GENCALL
 *  @brief      General Call address received and acknowledged flag
 */
#define I2CIF_ALL_GENCALL_Pos (11)
#define I2CIF_ALL_GENCALL_Msk (0x1UL << I2CIF_ALL_GENCALL_Pos)

typedef enum
{
    I2CIF_BIT_GENCALL_NOT_OCCUR     = 0,  /*!< Not occur   */
    I2CIF_BIT_GENCALL_OCCUR         = 1,  /*!< Occurred    */
} I2CIF_BIT_GENCALL;

#define I2CIF_ALL_GENCALL_NOT_OCCUR     ((0x0UL) << I2CIF_ALL_GENCALL_Pos)
#define I2CIF_ALL_GENCALL_OCCUR         ((0x1UL) << I2CIF_ALL_GENCALL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           RXUDF
 *  @access     I2C->I2CIE.bit.RXUDF
 *  @brief      Enable/disable RXUDF interrupt
 */
#define I2CIE_ALL_RXUDF_Pos (0)
#define I2CIE_ALL_RXUDF_Msk (0x1UL << I2CIE_ALL_RXUDF_Pos)

typedef enum
{
    I2CIE_BIT_RXUDF_DISABLE     = 0,  /*!< Disable RXUDF interrupt   */
    I2CIE_BIT_RXUDF_ENABLE      = 1,  /*!< Enable RXUDF interrupt    */
} I2CIE_BIT_RXUDF;

#define I2CIE_ALL_RXUDF_DISABLE     ((0x0UL) << I2CIE_ALL_RXUDF_Pos)
#define I2CIE_ALL_RXUDF_ENABLE      ((0x1UL) << I2CIE_ALL_RXUDF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           RXOVF
 *  @access     I2C->I2CIE.bit.RXOVF
 *  @brief      Enable/disable RXOVF interrupt
 */
#define I2CIE_ALL_RXOVF_Pos (1)
#define I2CIE_ALL_RXOVF_Msk (0x1UL << I2CIE_ALL_RXOVF_Pos)

typedef enum
{
    I2CIE_BIT_RXOVF_DISABLE     = 0,  /*!< Disable RXOVF interrupt   */
    I2CIE_BIT_RXOVF_ENABLE      = 1,  /*!< Enable RXOVF interrupt    */
} I2CIE_BIT_RXOVF;

#define I2CIE_ALL_RXOVF_DISABLE     ((0x0UL) << I2CIE_ALL_RXOVF_Pos)
#define I2CIE_ALL_RXOVF_ENABLE      ((0x1UL) << I2CIE_ALL_RXOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           RXDAV
 *  @access     I2C->I2CIE.bit.RXDAV
 *  @brief      Enable/disable RXDAV interrupt
 */
#define I2CIE_ALL_RXDAV_Pos (2)
#define I2CIE_ALL_RXDAV_Msk (0x1UL << I2CIE_ALL_RXDAV_Pos)

typedef enum
{
    I2CIE_BIT_RXDAV_DISABLE     = 0,  /*!< Disable RXDAV interrupt   */
    I2CIE_BIT_RXDAV_ENABLE      = 1,  /*!< Enable RXDAV interrupt    */
} I2CIE_BIT_RXDAV;

#define I2CIE_ALL_RXDAV_DISABLE     ((0x0UL) << I2CIE_ALL_RXDAV_Pos)
#define I2CIE_ALL_RXDAV_ENABLE      ((0x1UL) << I2CIE_ALL_RXDAV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           TXOVF
 *  @access     I2C->I2CIE.bit.TXOVF
 *  @brief      Enable/disable TXOVF interrupt
 */
#define I2CIE_ALL_TXOVF_Pos (3)
#define I2CIE_ALL_TXOVF_Msk (0x1UL << I2CIE_ALL_TXOVF_Pos)

typedef enum
{
    I2CIE_BIT_TXOVF_DISABLE     = 0,  /*!< Disable TXOVF interrupt   */
    I2CIE_BIT_TXOVF_ENABLE      = 1,  /*!< Enable TXOVF interrupt    */
} I2CIE_BIT_TXOVF;

#define I2CIE_ALL_TXOVF_DISABLE     ((0x0UL) << I2CIE_ALL_TXOVF_Pos)
#define I2CIE_ALL_TXOVF_ENABLE      ((0x1UL) << I2CIE_ALL_TXOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           TXDREQ
 *  @access     I2C->I2CIE.bit.TXDREQ
 *  @brief      Enable/disable TXDREQ interrupt
 */
#define I2CIE_ALL_TXDREQ_Pos (4)
#define I2CIE_ALL_TXDREQ_Msk (0x1UL << I2CIE_ALL_TXDREQ_Pos)

typedef enum
{
    I2CIE_BIT_TXDREQ_DISABLE     = 0,  /*!< Disable TXDREQ interrupt   */
    I2CIE_BIT_TXDREQ_ENABLE      = 1,  /*!< Enable TXDREQ interrupt    */
} I2CIE_BIT_TXDREQ;

#define I2CIE_ALL_TXDREQ_DISABLE     ((0x0UL) << I2CIE_ALL_TXDREQ_Pos)
#define I2CIE_ALL_TXDREQ_ENABLE      ((0x1UL) << I2CIE_ALL_TXDREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           RDREQ
 *  @access     I2C->I2CIE.bit.RDREQ
 *  @brief      Enable/disable RDREQ interrupt
 */
#define I2CIE_ALL_RDREQ_Pos (5)
#define I2CIE_ALL_RDREQ_Msk (0x1UL << I2CIE_ALL_RDREQ_Pos)

typedef enum
{
    I2CIE_BIT_RDREQ_DISABLE     = 0,  /*!< Disable RDREQ interrupt   */
    I2CIE_BIT_RDREQ_ENABLE      = 1,  /*!< Enable RDREQ interrupt    */
} I2CIE_BIT_RDREQ;

#define I2CIE_ALL_RDREQ_DISABLE     ((0x0UL) << I2CIE_ALL_RDREQ_Pos)
#define I2CIE_ALL_RDREQ_ENABLE      ((0x1UL) << I2CIE_ALL_RDREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           TXABRT
 *  @access     I2C->I2CIE.bit.TXABRT
 *  @brief      Enable/disable TXABRT interrupt
 */
#define I2CIE_ALL_TXABRT_Pos (6)
#define I2CIE_ALL_TXABRT_Msk (0x1UL << I2CIE_ALL_TXABRT_Pos)

typedef enum
{
    I2CIE_BIT_TXABRT_DISABLE     = 0,  /*!< Disable TXABRT interrupt   */
    I2CIE_BIT_TXABRT_ENABLE      = 1,  /*!< Enable TXABRT interrupt    */
} I2CIE_BIT_TXABRT;

#define I2CIE_ALL_TXABRT_DISABLE     ((0x0UL) << I2CIE_ALL_TXABRT_Pos)
#define I2CIE_ALL_TXABRT_ENABLE      ((0x1UL) << I2CIE_ALL_TXABRT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           RXDONE
 *  @access     I2C->I2CIE.bit.RXDONE
 *  @brief      Enable/disable RXDONE interrupt
 */
#define I2CIE_ALL_RXDONE_Pos (7)
#define I2CIE_ALL_RXDONE_Msk (0x1UL << I2CIE_ALL_RXDONE_Pos)

typedef enum
{
    I2CIE_BIT_RXDONE_DISABLE     = 0,  /*!< Disable RXDONE interrupt   */
    I2CIE_BIT_RXDONE_ENABLE      = 1,  /*!< Enable RXDONE interrupt    */
} I2CIE_BIT_RXDONE;

#define I2CIE_ALL_RXDONE_DISABLE     ((0x0UL) << I2CIE_ALL_RXDONE_Pos)
#define I2CIE_ALL_RXDONE_ENABLE      ((0x1UL) << I2CIE_ALL_RXDONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           ACT
 *  @access     I2C->I2CIE.bit.ACT
 *  @brief      Enable/disable ACTIVITY interrupt
 */
#define I2CIE_ALL_ACT_Pos (8)
#define I2CIE_ALL_ACT_Msk (0x1UL << I2CIE_ALL_ACT_Pos)

typedef enum
{
    I2CIE_BIT_ACT_DISABLE     = 0,  /*!< Disable ACTIVITY interrupt   */
    I2CIE_BIT_ACT_ENABLE      = 1,  /*!< Enable ACTIVITY interrupt    */
} I2CIE_BIT_ACT;

#define I2CIE_ALL_ACT_DISABLE     ((0x0UL) << I2CIE_ALL_ACT_Pos)
#define I2CIE_ALL_ACT_ENABLE      ((0x1UL) << I2CIE_ALL_ACT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           STOPDET
 *  @access     I2C->I2CIE.bit.STOPDET
 *  @brief      Enable/disable STOPDET interrupt
 */
#define I2CIE_ALL_STOPDET_Pos (9)
#define I2CIE_ALL_STOPDET_Msk (0x1UL << I2CIE_ALL_STOPDET_Pos)

typedef enum
{
    I2CIE_BIT_STOPDET_DISABLE     = 0,  /*!< Disable STOPDET interrupt   */
    I2CIE_BIT_STOPDET_ENABLE      = 1,  /*!< Enable STOPDET interrupt    */
} I2CIE_BIT_STOPDET;

#define I2CIE_ALL_STOPDET_DISABLE     ((0x0UL) << I2CIE_ALL_STOPDET_Pos)
#define I2CIE_ALL_STOPDET_ENABLE      ((0x1UL) << I2CIE_ALL_STOPDET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           STARTDET
 *  @access     I2C->I2CIE.bit.STARTDET
 *  @brief      Enable/disable STARTDET interrupt
 */
#define I2CIE_ALL_STARTDET_Pos (10)
#define I2CIE_ALL_STARTDET_Msk (0x1UL << I2CIE_ALL_STARTDET_Pos)

typedef enum
{
    I2CIE_BIT_STARTDET_DISABLE     = 0,  /*!< Disable STARTDET interrupt   */
    I2CIE_BIT_STARTDET_ENABLE      = 1,  /*!< Enable STARTDET interrupt    */
} I2CIE_BIT_STARTDET;

#define I2CIE_ALL_STARTDET_DISABLE     ((0x0UL) << I2CIE_ALL_STARTDET_Pos)
#define I2CIE_ALL_STARTDET_ENABLE      ((0x1UL) << I2CIE_ALL_STARTDET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CIE           GENCALL
 *  @access     I2C->I2CIE.bit.GENCALL
 *  @brief      Enable/disable GENCALL interrupt
 */
#define I2CIE_ALL_GENCALL_Pos (11)
#define I2CIE_ALL_GENCALL_Msk (0x1UL << I2CIE_ALL_GENCALL_Pos)

typedef enum
{
    I2CIE_BIT_GENCALL_DISABLE     = 0,  /*!< Disable GENCALL interrupt   */
    I2CIE_BIT_GENCALL_ENABLE      = 1,  /*!< Enable GENCALL interrupt    */
} I2CIE_BIT_GENCALL;

#define I2CIE_ALL_GENCALL_DISABLE     ((0x0UL) << I2CIE_ALL_GENCALL_Pos)
#define I2CIE_ALL_GENCALL_ENABLE      ((0x1UL) << I2CIE_ALL_GENCALL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        RXUDF
 *  @access     I2C->I2CRAWIF.bit.RXUDF
 *  @brief      Flag to indicate the processor attempts to read the receive buffer via I2CDATACMD
 *              register when it is empty
 */
#define I2CRAWIF_ALL_RXUDF_Pos (0)
#define I2CRAWIF_ALL_RXUDF_Msk (0x1UL << I2CRAWIF_ALL_RXUDF_Pos)

typedef enum
{
    I2CRAWIF_BIT_RXUDF_NOT_OCCUR     = 0,  /*!< Receive buffer does not underflow   */
    I2CRAWIF_BIT_RXUDF_OCCUR         = 1,  /*!< Receive buffer underflows           */
} I2CRAWIF_BIT_RXUDF;

#define I2CRAWIF_ALL_RXUDF_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_RXUDF_Pos)
#define I2CRAWIF_ALL_RXUDF_OCCUR         ((0x1UL) << I2CRAWIF_ALL_RXUDF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        RXOVF
 *  @access     I2C->I2CRAWIF.bit.RXOVF
 *  @brief      Flag to indicate the receive buffer is completely filled to 16 and an additional
 *              byte is received from an external I2C device. The I2C acknowledges this, but any
 *              data bytes received after the FIFO is full are lost.
 */
#define I2CRAWIF_ALL_RXOVF_Pos (1)
#define I2CRAWIF_ALL_RXOVF_Msk (0x1UL << I2CRAWIF_ALL_RXOVF_Pos)

typedef enum
{
    I2CRAWIF_BIT_RXOVF_NOT_OCCUR     = 0,  /*!< Receive buffer does not overflow   */
    I2CRAWIF_BIT_RXOVF_OCCUR         = 1,  /*!< Receive buffer overflows           */
} I2CRAWIF_BIT_RXOVF;

#define I2CRAWIF_ALL_RXOVF_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_RXOVF_Pos)
#define I2CRAWIF_ALL_RXOVF_OCCUR         ((0x1UL) << I2CRAWIF_ALL_RXOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        RXDAV
 *  @access     I2C->I2CRAWIF.bit.RXDAV
 *  @brief      Flag to indicate the receive buffer reaches or goes above the threshold in the I2CRXTH
 *              register so data is available to read
 */
#define I2CRAWIF_ALL_RXDAV_Pos (2)
#define I2CRAWIF_ALL_RXDAV_Msk (0x1UL << I2CRAWIF_ALL_RXDAV_Pos)

typedef enum
{
    I2CRAWIF_BIT_RXDAV_NOT_OCCUR     = 0,  /*!< Receive buffer is below threshold              */
    I2CRAWIF_BIT_RXDAV_OCCUR         = 1,  /*!< Receive buffer is at or above the threshold   
                                                Self-cleared when level goes below threshold   */
} I2CRAWIF_BIT_RXDAV;

#define I2CRAWIF_ALL_RXDAV_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_RXDAV_Pos)
#define I2CRAWIF_ALL_RXDAV_OCCUR         ((0x1UL) << I2CRAWIF_ALL_RXDAV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        TXOVF
 *  @access     I2C->I2CRAWIF.bit.TXOVF
 *  @brief      Flag to indicate an attempt to write I2CDATACMD register when transmit buffer is
 *              fill to 15
 */
#define I2CRAWIF_ALL_TXOVF_Pos (3)
#define I2CRAWIF_ALL_TXOVF_Msk (0x1UL << I2CRAWIF_ALL_TXOVF_Pos)

typedef enum
{
    I2CRAWIF_BIT_TXOVF_NOT_OCCUR     = 0,  /*!< Transmit buffer does not overflow   */
    I2CRAWIF_BIT_TXOVF_OCCUR         = 1,  /*!< Transmit buffer overflows           */
} I2CRAWIF_BIT_TXOVF;

#define I2CRAWIF_ALL_TXOVF_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_TXOVF_Pos)
#define I2CRAWIF_ALL_TXOVF_OCCUR         ((0x1UL) << I2CRAWIF_ALL_TXOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        TXDREQ
 *  @access     I2C->I2CRAWIF.bit.TXDREQ
 *  @brief      Flag to indicate the transmit buffer is at or below the threshold value set in the
 *              I2CTXTH register so requets more data
 */
#define I2CRAWIF_ALL_TXDREQ_Pos (4)
#define I2CRAWIF_ALL_TXDREQ_Msk (0x1UL << I2CRAWIF_ALL_TXDREQ_Pos)

typedef enum
{
    I2CRAWIF_BIT_TXDREQ_NOT_OCCUR     = 0,  /*!< Transmit buffer is above threshold             */
    I2CRAWIF_BIT_TXDREQ_OCCUR         = 1,  /*!< Transmit buffer is at or below the threshold  
                                                 Self-cleared when level goes above threshold   */
} I2CRAWIF_BIT_TXDREQ;

#define I2CRAWIF_ALL_TXDREQ_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_TXDREQ_Pos)
#define I2CRAWIF_ALL_TXDREQ_OCCUR         ((0x1UL) << I2CRAWIF_ALL_TXDREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        RDREQ
 *  @access     I2C->I2CRAWIF.bit.RDREQ
 *  @brief      Latched external master read request flag when the I2C is acting as a slave
 */
#define I2CRAWIF_ALL_RDREQ_Pos (5)
#define I2CRAWIF_ALL_RDREQ_Msk (0x1UL << I2CRAWIF_ALL_RDREQ_Pos)

typedef enum
{
    I2CRAWIF_BIT_RDREQ_NOT_OCCUR     = 0,  /*!< No read request is received from another master                                     */
    I2CRAWIF_BIT_RDREQ_OCCUR         = 1,  /*!< Read request was received from another master.                                     
                                                The processor must respond to this interrupt and then write the requested data to  
                                                the I2CDATACMD register.                                                            */
} I2CRAWIF_BIT_RDREQ;

#define I2CRAWIF_ALL_RDREQ_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_RDREQ_Pos)
#define I2CRAWIF_ALL_RDREQ_OCCUR         ((0x1UL) << I2CRAWIF_ALL_RDREQ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        TXABRT
 *  @access     I2C->I2CRAWIF.bit.TXABRT
 *  @brief      Latched transmission abort flag
 */
#define I2CRAWIF_ALL_TXABRT_Pos (6)
#define I2CRAWIF_ALL_TXABRT_Msk (0x1UL << I2CRAWIF_ALL_TXABRT_Pos)

typedef enum
{
    I2CRAWIF_BIT_TXABRT_NOT_OCCUR     = 0,  /*!< No transmission abortion occurred                                                            */
    I2CRAWIF_BIT_TXABRT_OCCUR         = 1,  /*!< Transimission aborted and TX FIFO remains in flushed state until the register I2CTXABRTCLR  
                                                 is read                                                                                      */
} I2CRAWIF_BIT_TXABRT;

#define I2CRAWIF_ALL_TXABRT_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_TXABRT_Pos)
#define I2CRAWIF_ALL_TXABRT_OCCUR         ((0x1UL) << I2CRAWIF_ALL_TXABRT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        RXDONE
 *  @access     I2C->I2CRAWIF.bit.RXDONE
 *  @brief      Flag to indicate external master receive is done when I2C acts as a slave transmitter
 */
#define I2CRAWIF_ALL_RXDONE_Pos (7)
#define I2CRAWIF_ALL_RXDONE_Msk (0x1UL << I2CRAWIF_ALL_RXDONE_Pos)

typedef enum
{
    I2CRAWIF_BIT_RXDONE_NOT_OCCUR     = 0,  /*!< Slave transmission is acknowledged by the other master, which continues data receiving.   */
    I2CRAWIF_BIT_RXDONE_OCCUR         = 1,  /*!< Slave transmission is not acknowledge by the other master, which finishes the data       
                                                 receiving                                                                                 */
} I2CRAWIF_BIT_RXDONE;

#define I2CRAWIF_ALL_RXDONE_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_RXDONE_Pos)
#define I2CRAWIF_ALL_RXDONE_OCCUR         ((0x1UL) << I2CRAWIF_ALL_RXDONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        ACT
 *  @access     I2C->I2CRAWIF.bit.ACT
 *  @brief      Latched I2C activity status flag
 */
#define I2CRAWIF_ALL_ACT_Pos (8)
#define I2CRAWIF_ALL_ACT_Msk (0x1UL << I2CRAWIF_ALL_ACT_Pos)

typedef enum
{
    I2CRAWIF_BIT_ACT_NOT_OCCUR     = 0,  /*!< There is no activity detected on I2C interface   */
    I2CRAWIF_BIT_ACT_OCCUR         = 1,  /*!< Activity has been detected on I2C interface      */
} I2CRAWIF_BIT_ACT;

#define I2CRAWIF_ALL_ACT_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_ACT_Pos)
#define I2CRAWIF_ALL_ACT_OCCUR         ((0x1UL) << I2CRAWIF_ALL_ACT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        STOPDET
 *  @access     I2C->I2CRAWIF.bit.STOPDET
 *  @brief      STOP condition flag
 */
#define I2CRAWIF_ALL_STOPDET_Pos (9)
#define I2CRAWIF_ALL_STOPDET_Msk (0x1UL << I2CRAWIF_ALL_STOPDET_Pos)

typedef enum
{
    I2CRAWIF_BIT_STOPDET_NOT_OCCUR     = 0,  /*!< Condition is not detected   */
    I2CRAWIF_BIT_STOPDET_OCCUR         = 1,  /*!< Condition is detected       */
} I2CRAWIF_BIT_STOPDET;

#define I2CRAWIF_ALL_STOPDET_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_STOPDET_Pos)
#define I2CRAWIF_ALL_STOPDET_OCCUR         ((0x1UL) << I2CRAWIF_ALL_STOPDET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        STARTDET
 *  @access     I2C->I2CRAWIF.bit.STARTDET
 *  @brief      START or RESTART condition flag
 */
#define I2CRAWIF_ALL_STARTDET_Pos (10)
#define I2CRAWIF_ALL_STARTDET_Msk (0x1UL << I2CRAWIF_ALL_STARTDET_Pos)

typedef enum
{
    I2CRAWIF_BIT_STARTDET_NOT_OCCUR     = 0,  /*!< Condition is not detected   */
    I2CRAWIF_BIT_STARTDET_OCCUR         = 1,  /*!< Condition is detected       */
} I2CRAWIF_BIT_STARTDET;

#define I2CRAWIF_ALL_STARTDET_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_STARTDET_Pos)
#define I2CRAWIF_ALL_STARTDET_OCCUR         ((0x1UL) << I2CRAWIF_ALL_STARTDET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRAWIF        GENCALL
 *  @access     I2C->I2CRAWIF.bit.GENCALL
 *  @brief      General Call address received and acknowledged flag
 */
#define I2CRAWIF_ALL_GENCALL_Pos (11)
#define I2CRAWIF_ALL_GENCALL_Msk (0x1UL << I2CRAWIF_ALL_GENCALL_Pos)

typedef enum
{
    I2CRAWIF_BIT_GENCALL_NOT_OCCUR     = 0,  /*!< Not occur   */
    I2CRAWIF_BIT_GENCALL_OCCUR         = 1,  /*!< Occurred    */
} I2CRAWIF_BIT_GENCALL;

#define I2CRAWIF_ALL_GENCALL_NOT_OCCUR     ((0x0UL) << I2CRAWIF_ALL_GENCALL_Pos)
#define I2CRAWIF_ALL_GENCALL_OCCUR         ((0x1UL) << I2CRAWIF_ALL_GENCALL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRXTH         VAL
 *  @access     I2C->I2CRXTH.bit.VAL
 *  @brief      Receive FIFO threshold level to trigger the RXDAV interrupt
 */
#define I2CRXTH_ALL_VAL_Pos (0)
#define I2CRXTH_ALL_VAL_Msk (0xFUL << I2CRXTH_ALL_VAL_Pos)

#define I2CRXTH_BIT_VAL

#define I2CRXTH_ALL_VAL_(x) ((x) << I2CRXTH_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRXTH         KEY
 *  @access     I2C->I2CRXTH.bit.KEY
 *  @brief      Must write 0x0 to this field when write to low LSBs, else LSBs is always 0xF.
 *              Always readback 0
 */
#define I2CRXTH_ALL_KEY_Pos (4)
#define I2CRXTH_ALL_KEY_Msk (0xFUL << I2CRXTH_ALL_KEY_Pos)

#define I2CRXTH_BIT_KEY

#define I2CRXTH_ALL_KEY_(x) ((x) << I2CRXTH_ALL_KEY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXTH         VAL
 *  @access     I2C->I2CTXTH.bit.VAL
 *  @brief      Transmit FIFO threshold level to trigger the TXDREQ interrupt
 */
#define I2CTXTH_ALL_VAL_Pos (0)
#define I2CTXTH_ALL_VAL_Msk (0xFUL << I2CTXTH_ALL_VAL_Pos)

#define I2CTXTH_BIT_VAL

#define I2CTXTH_ALL_VAL_(x) ((x) << I2CTXTH_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXTH         KEY
 *  @access     I2C->I2CTXTH.bit.KEY
 *  @brief      Must write 0x0 to this field when write to low LSBs, else LSBs is always 0xF.
 *              Always readback 0
 */
#define I2CTXTH_ALL_KEY_Pos (4)
#define I2CTXTH_ALL_KEY_Msk (0xFUL << I2CTXTH_ALL_KEY_Pos)

#define I2CTXTH_BIT_KEY

#define I2CTXTH_ALL_KEY_(x) ((x) << I2CTXTH_ALL_KEY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CINTCLR       CLR
 *  @access     I2C->I2CINTCLR.bit.CLR
 *  @brief      Read this register to clear the combined interrupt, all individual interrupts, and
 *              the I2CTXABRTSRC register. This bit does not clear hardware clearable interrupts
 *              but software clearable interrupts.
 *              Refer to I2CTXABRTSRC.STARTNORESTART for an exception to clear I2CTXABRTSRC register.
 */
#define I2CINTCLR_ALL_CLR_Pos (0)
#define I2CINTCLR_ALL_CLR_Msk (0x1UL << I2CINTCLR_ALL_CLR_Pos)

typedef enum
{
    I2CINTCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CINTCLR_BIT_CLR;

#define I2CINTCLR_ALL_CLR_0     ((0x0UL) << I2CINTCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRXUDFCLR     CLR
 *  @access     I2C->I2CRXUDFCLR.bit.CLR
 *  @brief      Read this register to clear the RXUDF flag
 */
#define I2CRXUDFCLR_ALL_CLR_Pos (0)
#define I2CRXUDFCLR_ALL_CLR_Msk (0x1UL << I2CRXUDFCLR_ALL_CLR_Pos)

typedef enum
{
    I2CRXUDFCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CRXUDFCLR_BIT_CLR;

#define I2CRXUDFCLR_ALL_CLR_0     ((0x0UL) << I2CRXUDFCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRXOVFCLR     CLR
 *  @access     I2C->I2CRXOVFCLR.bit.CLR
 *  @brief      Read this register to clear the RXOVF flag
 */
#define I2CRXOVFCLR_ALL_CLR_Pos (0)
#define I2CRXOVFCLR_ALL_CLR_Msk (0x1UL << I2CRXOVFCLR_ALL_CLR_Pos)

typedef enum
{
    I2CRXOVFCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CRXOVFCLR_BIT_CLR;

#define I2CRXOVFCLR_ALL_CLR_0     ((0x0UL) << I2CRXOVFCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXOVFCLR     CLR
 *  @access     I2C->I2CTXOVFCLR.bit.CLR
 *  @brief      Read this register to clear the TXOVF flag
 */
#define I2CTXOVFCLR_ALL_CLR_Pos (0)
#define I2CTXOVFCLR_ALL_CLR_Msk (0x1UL << I2CTXOVFCLR_ALL_CLR_Pos)

typedef enum
{
    I2CTXOVFCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CTXOVFCLR_BIT_CLR;

#define I2CTXOVFCLR_ALL_CLR_0     ((0x0UL) << I2CTXOVFCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRDREQCLR     CLR
 *  @access     I2C->I2CRDREQCLR.bit.CLR
 *  @brief      Read this register to clear the RDREQ flag
 */
#define I2CRDREQCLR_ALL_CLR_Pos (0)
#define I2CRDREQCLR_ALL_CLR_Msk (0x1UL << I2CRDREQCLR_ALL_CLR_Pos)

typedef enum
{
    I2CRDREQCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CRDREQCLR_BIT_CLR;

#define I2CRDREQCLR_ALL_CLR_0     ((0x0UL) << I2CRDREQCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTCLR    CLR
 *  @access     I2C->I2CTXABRTCLR.bit.CLR
 *  @brief      Read this register to clear the TXABRT flag and the I2CTXABRTSRC register. This also
 *              releases the TX FIFO from the flushed/reset state, allowing more writes to the TX
 *              FIFO.
 *              Refer to I2CTXABRTSRC.STARTNORESTART for an exception to clear I2CTXABRTSRC register.
 */
#define I2CTXABRTCLR_ALL_CLR_Pos (0)
#define I2CTXABRTCLR_ALL_CLR_Msk (0x1UL << I2CTXABRTCLR_ALL_CLR_Pos)

typedef enum
{
    I2CTXABRTCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CTXABRTCLR_BIT_CLR;

#define I2CTXABRTCLR_ALL_CLR_0     ((0x0UL) << I2CTXABRTCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRXDONECLR    CLR
 *  @access     I2C->I2CRXDONECLR.bit.CLR
 *  @brief      Read this register to clear the RXDONE flag
 */
#define I2CRXDONECLR_ALL_CLR_Pos (0)
#define I2CRXDONECLR_ALL_CLR_Msk (0x1UL << I2CRXDONECLR_ALL_CLR_Pos)

typedef enum
{
    I2CRXDONECLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CRXDONECLR_BIT_CLR;

#define I2CRXDONECLR_ALL_CLR_0     ((0x0UL) << I2CRXDONECLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CACTCLR       CLR
 *  @access     I2C->I2CACTCLR.bit.CLR
 *  @brief      Reading this register clears the ACT flag if the I2C is not active anymore. If the
 *              I2C module is still active on the bus, the ACTIVITY flag continues to be set.
 *              It is automatically cleared by hardware if the module is disabled and there is no
 *              further activity on the bus.
 */
#define I2CACTCLR_ALL_CLR_Pos (0)
#define I2CACTCLR_ALL_CLR_Msk (0x1UL << I2CACTCLR_ALL_CLR_Pos)

typedef enum
{
    I2CACTCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CACTCLR_BIT_CLR;

#define I2CACTCLR_ALL_CLR_0     ((0x0UL) << I2CACTCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTOPDETCLR   CLR
 *  @access     I2C->I2CSTOPDETCLR.bit.CLR
 *  @brief      Read this register to clear the STOPDET flag
 */
#define I2CSTOPDETCLR_ALL_CLR_Pos (0)
#define I2CSTOPDETCLR_ALL_CLR_Msk (0x1UL << I2CSTOPDETCLR_ALL_CLR_Pos)

typedef enum
{
    I2CSTOPDETCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CSTOPDETCLR_BIT_CLR;

#define I2CSTOPDETCLR_ALL_CLR_0     ((0x0UL) << I2CSTOPDETCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTARTDETCLR  CLR
 *  @access     I2C->I2CSTARTDETCLR.bit.CLR
 *  @brief      Read this register to clear the STARTDET flag
 */
#define I2CSTARTDETCLR_ALL_CLR_Pos (0)
#define I2CSTARTDETCLR_ALL_CLR_Msk (0x1UL << I2CSTARTDETCLR_ALL_CLR_Pos)

typedef enum
{
    I2CSTARTDETCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CSTARTDETCLR_BIT_CLR;

#define I2CSTARTDETCLR_ALL_CLR_0     ((0x0UL) << I2CSTARTDETCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CGENCALLCLR   CLR
 *  @access     I2C->I2CGENCALLCLR.bit.CLR
 *  @brief      Read this register to clear the GENCALL flag
 */
#define I2CGENCALLCLR_ALL_CLR_Pos (0)
#define I2CGENCALLCLR_ALL_CLR_Msk (0x1UL << I2CGENCALLCLR_ALL_CLR_Pos)

typedef enum
{
    I2CGENCALLCLR_BIT_CLR_0     = 0,  /*!< Read to clear   */
} I2CGENCALLCLR_BIT_CLR;

#define I2CGENCALLCLR_ALL_CLR_0     ((0x0UL) << I2CGENCALLCLR_ALL_CLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CENABLE       EN
 *  @access     I2C->I2CENABLE.bit.EN
 *  @brief      Controls whether the I2C is enabled.
 *              There are two CLK_I2C delay when enable or disable the I2C.
 *              When I2C is disabled, the following occurs:
 *              - The TX FIFO and RX FIFO get flushed.
 *              - Status bits in the I2CIF register are still active until I2C goes into IDLE state.
 *              - If the module is transmitting, it stops as well as deletes the contents of the
 *              transmit buffer after the current transfer is complete.
 *              - If the module is receiving, the I2C stops the current transfer at the end of the
 *              current byte and does not acknowledge the transfer.
 */
#define I2CENABLE_ALL_EN_Pos (0)
#define I2CENABLE_ALL_EN_Msk (0x1UL << I2CENABLE_ALL_EN_Pos)

typedef enum
{
    I2CENABLE_BIT_EN_DISABLE     = 0,  /*!< Disable I2C (Hold FIFOs in an erased state). Software can disable I2C while it is   
                                            active. However, it is important that care be taken to ensure that i2c is disabled  
                                            properly.                                                                            */
    I2CENABLE_BIT_EN_ENABLE      = 1,  /*!< Enable I2C                                                                           */
} I2CENABLE_BIT_EN;

#define I2CENABLE_ALL_EN_DISABLE     ((0x0UL) << I2CENABLE_ALL_EN_Pos)
#define I2CENABLE_ALL_EN_ENABLE      ((0x1UL) << I2CENABLE_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTS          ACT
 *  @access     I2C->I2CSTS.bit.ACT
 *  @brief      I2C activity status (Logic OR of SACT and MACT)
 */
#define I2CSTS_ALL_ACT_Pos (0)
#define I2CSTS_ALL_ACT_Msk (0x1UL << I2CSTS_ALL_ACT_Pos)

typedef enum
{
    I2CSTS_BIT_ACT_IDLE       = 0,  /*!< Both master and slave FSM are in idle state   */
    I2CSTS_BIT_ACT_ACTIVE     = 1,  /*!< Either master or slave FSM is active          */
} I2CSTS_BIT_ACT;

#define I2CSTS_ALL_ACT_IDLE       ((0x0UL) << I2CSTS_ALL_ACT_Pos)
#define I2CSTS_ALL_ACT_ACTIVE     ((0x1UL) << I2CSTS_ALL_ACT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTS          TFNF
 *  @access     I2C->I2CSTS.bit.TFNF
 *  @brief      Transmit FIFO not full
 */
#define I2CSTS_ALL_TFNF_Pos (1)
#define I2CSTS_ALL_TFNF_Msk (0x1UL << I2CSTS_ALL_TFNF_Pos)

typedef enum
{
    I2CSTS_BIT_TFNF_FULL         = 0,  /*!< Transmit FIFO is full                    */
    I2CSTS_BIT_TFNF_NOT_FULL     = 1,  /*!< Transmit FIFO contains empty locations   */
} I2CSTS_BIT_TFNF;

#define I2CSTS_ALL_TFNF_FULL         ((0x0UL) << I2CSTS_ALL_TFNF_Pos)
#define I2CSTS_ALL_TFNF_NOT_FULL     ((0x1UL) << I2CSTS_ALL_TFNF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTS          TFE
 *  @access     I2C->I2CSTS.bit.TFE
 *  @brief      Transmit FIFO completely empty
 */
#define I2CSTS_ALL_TFE_Pos (2)
#define I2CSTS_ALL_TFE_Msk (0x1UL << I2CSTS_ALL_TFE_Pos)

typedef enum
{
    I2CSTS_BIT_TFE_NOT_EMPTY     = 0,  /*!< Transmit FIFO contains one or more entries   */
    I2CSTS_BIT_TFE_EMPTY         = 1,  /*!< Transmit FIFO is empty                       */
} I2CSTS_BIT_TFE;

#define I2CSTS_ALL_TFE_NOT_EMPTY     ((0x0UL) << I2CSTS_ALL_TFE_Pos)
#define I2CSTS_ALL_TFE_EMPTY         ((0x1UL) << I2CSTS_ALL_TFE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTS          RFNE
 *  @access     I2C->I2CSTS.bit.RFNE
 *  @brief      Receive FIFO not empty
 */
#define I2CSTS_ALL_RFNE_Pos (3)
#define I2CSTS_ALL_RFNE_Msk (0x1UL << I2CSTS_ALL_RFNE_Pos)

typedef enum
{
    I2CSTS_BIT_RFNE_EMPTY         = 0,  /*!< Receive FIFO is empty                       */
    I2CSTS_BIT_RFNE_NOT_EMPTY     = 1,  /*!< Receive FIFO contains one or more entries   */
} I2CSTS_BIT_RFNE;

#define I2CSTS_ALL_RFNE_EMPTY         ((0x0UL) << I2CSTS_ALL_RFNE_Pos)
#define I2CSTS_ALL_RFNE_NOT_EMPTY     ((0x1UL) << I2CSTS_ALL_RFNE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTS          RFF
 *  @access     I2C->I2CSTS.bit.RFF
 *  @brief      Receive FIFO completely full
 */
#define I2CSTS_ALL_RFF_Pos (4)
#define I2CSTS_ALL_RFF_Msk (0x1UL << I2CSTS_ALL_RFF_Pos)

typedef enum
{
    I2CSTS_BIT_RFF_NOT_FULL     = 0,  /*!< Receive FIFO contains empty location   */
    I2CSTS_BIT_RFF_FULL         = 1,  /*!< Receive FIFO is completely full        */
} I2CSTS_BIT_RFF;

#define I2CSTS_ALL_RFF_NOT_FULL     ((0x0UL) << I2CSTS_ALL_RFF_Pos)
#define I2CSTS_ALL_RFF_FULL         ((0x1UL) << I2CSTS_ALL_RFF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTS          MACT
 *  @access     I2C->I2CSTS.bit.MACT
 *  @brief      Master FSM activity status
 */
#define I2CSTS_ALL_MACT_Pos (5)
#define I2CSTS_ALL_MACT_Msk (0x1UL << I2CSTS_ALL_MACT_Pos)

typedef enum
{
    I2CSTS_BIT_MACT_IDLE       = 0,  /*!< Master FSM is in IDLE state (Inactive)     */
    I2CSTS_BIT_MACT_ACTIVE     = 1,  /*!< Master FSM is not in IDLE state (Active)   */
} I2CSTS_BIT_MACT;

#define I2CSTS_ALL_MACT_IDLE       ((0x0UL) << I2CSTS_ALL_MACT_Pos)
#define I2CSTS_ALL_MACT_ACTIVE     ((0x1UL) << I2CSTS_ALL_MACT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSTS          SACT
 *  @access     I2C->I2CSTS.bit.SACT
 *  @brief      Slave FSM (Finite State Machine) activity status
 */
#define I2CSTS_ALL_SACT_Pos (6)
#define I2CSTS_ALL_SACT_Msk (0x1UL << I2CSTS_ALL_SACT_Pos)

typedef enum
{
    I2CSTS_BIT_SACT_IDLE       = 0,  /*!< Slave FSM is in IDLE state (Inactive)     */
    I2CSTS_BIT_SACT_ACTIVE     = 1,  /*!< Slave FSM is not in IDLE state (Active)   */
} I2CSTS_BIT_SACT;

#define I2CSTS_ALL_SACT_IDLE       ((0x0UL) << I2CSTS_ALL_SACT_Pos)
#define I2CSTS_ALL_SACT_ACTIVE     ((0x1UL) << I2CSTS_ALL_SACT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTFLVL        VAL
 *  @access     I2C->I2CTFLVL.bit.VAL
 *  @brief      Number of valid data entries in the transmit FIFO.
 */
#define I2CTFLVL_ALL_VAL_Pos (0)
#define I2CTFLVL_ALL_VAL_Msk (0x1FUL << I2CTFLVL_ALL_VAL_Pos)

#define I2CTFLVL_BIT_VAL

#define I2CTFLVL_ALL_VAL_(x) ((x) << I2CTFLVL_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CRFLVL        VAL
 *  @access     I2C->I2CRFLVL.bit.VAL
 *  @brief      Number of valid data entries in the receive FIFO.
 */
#define I2CRFLVL_ALL_VAL_Pos (0)
#define I2CRFLVL_ALL_VAL_Msk (0x1FUL << I2CRFLVL_ALL_VAL_Pos)

#define I2CRFLVL_BIT_VAL

#define I2CRFLVL_ALL_VAL_(x) ((x) << I2CRFLVL_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSDAHOLD      VAL
 *  @access     I2C->I2CSDAHOLD.bit.VAL
 *  @brief      Configure SDA hold time as VAL CLK_I2C cycles
 *              i.e. If the required hold delay is 1000ns, then for an CLK_I2C frequency of 10 MHz,
 *              this register is recommended to be programmed as 11.
 *              This register can be written only when I2CENABLE=0. Writes at other times have no
 *              effect.
 */
#define I2CSDAHOLD_ALL_VAL_Pos (0)
#define I2CSDAHOLD_ALL_VAL_Msk (0xFFFFUL << I2CSDAHOLD_ALL_VAL_Pos)

#define I2CSDAHOLD_BIT_VAL

#define I2CSDAHOLD_ALL_VAL_(x) ((x) << I2CSDAHOLD_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    ADDR7BNACK
 *  @access     I2C->I2CTXABRTSRC.bit.ADDR7BNACK
 *  @brief      Role of I2C: Master transmitter/receiver
 *              This bit is set when master is in 7-bit addressing mode and the address sent was
 *              not acknowledged by any slave.
 */
#define I2CTXABRTSRC_ALL_ADDR7BNACK_Pos (0)
#define I2CTXABRTSRC_ALL_ADDR7BNACK_Msk (0x1UL << I2CTXABRTSRC_ALL_ADDR7BNACK_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_ADDR7BNACK_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_ADDR7BNACK_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_ADDR7BNACK;

#define I2CTXABRTSRC_ALL_ADDR7BNACK_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_ADDR7BNACK_Pos)
#define I2CTXABRTSRC_ALL_ADDR7BNACK_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_ADDR7BNACK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    ADDR10B1NACK
 *  @access     I2C->I2CTXABRTSRC.bit.ADDR10B1NACK
 *  @brief      Role of I2C: Master transmitter/receiver
 *              This bit is set when master is in 10-bit address mode and the first 10-bit address
 *              byte was not acknowledged by any slave.
 */
#define I2CTXABRTSRC_ALL_ADDR10B1NACK_Pos (1)
#define I2CTXABRTSRC_ALL_ADDR10B1NACK_Msk (0x1UL << I2CTXABRTSRC_ALL_ADDR10B1NACK_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_ADDR10B1NACK_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_ADDR10B1NACK_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_ADDR10B1NACK;

#define I2CTXABRTSRC_ALL_ADDR10B1NACK_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_ADDR10B1NACK_Pos)
#define I2CTXABRTSRC_ALL_ADDR10B1NACK_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_ADDR10B1NACK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    ADDR10B2NACK
 *  @access     I2C->I2CTXABRTSRC.bit.ADDR10B2NACK
 *  @brief      Role of I2C: Master transmitter/receiver
 *              This bit is set when master is in 10-bit address mode and the second address byte
 *              of the 10-bit address was not acknowledged by any slave.
 */
#define I2CTXABRTSRC_ALL_ADDR10B2NACK_Pos (2)
#define I2CTXABRTSRC_ALL_ADDR10B2NACK_Msk (0x1UL << I2CTXABRTSRC_ALL_ADDR10B2NACK_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_ADDR10B2NACK_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_ADDR10B2NACK_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_ADDR10B2NACK;

#define I2CTXABRTSRC_ALL_ADDR10B2NACK_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_ADDR10B2NACK_Pos)
#define I2CTXABRTSRC_ALL_ADDR10B2NACK_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_ADDR10B2NACK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    TXDATANACK
 *  @access     I2C->I2CTXABRTSRC.bit.TXDATANACK
 *  @brief      Role of I2C: Master transmitter
 *              This bit is set when master has received an acknowledgement for the address, but
 *              when it sent data byte(s) following the address, it did not receive an acknowledge
 *              from the remote slave(s).
 */
#define I2CTXABRTSRC_ALL_TXDATANACK_Pos (3)
#define I2CTXABRTSRC_ALL_TXDATANACK_Msk (0x1UL << I2CTXABRTSRC_ALL_TXDATANACK_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_TXDATANACK_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_TXDATANACK_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_TXDATANACK;

#define I2CTXABRTSRC_ALL_TXDATANACK_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_TXDATANACK_Pos)
#define I2CTXABRTSRC_ALL_TXDATANACK_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_TXDATANACK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    GCNACK
 *  @access     I2C->I2CTXABRTSRC.bit.GCNACK
 *  @brief      Role of I2C: Master transmitter
 *              This bit is set when master sent a General Call and no slave on the bus acknowledged
 *              the General Call.
 */
#define I2CTXABRTSRC_ALL_GCNACK_Pos (4)
#define I2CTXABRTSRC_ALL_GCNACK_Msk (0x1UL << I2CTXABRTSRC_ALL_GCNACK_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_GCNACK_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_GCNACK_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_GCNACK;

#define I2CTXABRTSRC_ALL_GCNACK_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_GCNACK_Pos)
#define I2CTXABRTSRC_ALL_GCNACK_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_GCNACK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    GCREAD
 *  @access     I2C->I2CTXABRTSRC.bit.GCREAD
 *  @brief      Role of I2C: Master transmitter
 *              This bit is set when master sent a General Call but the user programmed the byte
 *              following the General Call to be a read from the bus (I2CDATACMD.CMD=1).
 */
#define I2CTXABRTSRC_ALL_GCREAD_Pos (5)
#define I2CTXABRTSRC_ALL_GCREAD_Msk (0x1UL << I2CTXABRTSRC_ALL_GCREAD_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_GCREAD_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_GCREAD_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_GCREAD;

#define I2CTXABRTSRC_ALL_GCREAD_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_GCREAD_Pos)
#define I2CTXABRTSRC_ALL_GCREAD_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_GCREAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    HSACKDET
 *  @access     I2C->I2CTXABRTSRC.bit.HSACKDET
 *  @brief      Role of I2C: Master transmitter/receiver
 *              This bit is set when master is in high speed mode and the high speed master code
 *              was acknowledged (wrong behavior).
 */
#define I2CTXABRTSRC_ALL_HSACKDET_Pos (6)
#define I2CTXABRTSRC_ALL_HSACKDET_Msk (0x1UL << I2CTXABRTSRC_ALL_HSACKDET_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_HSACKDET_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_HSACKDET_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_HSACKDET;

#define I2CTXABRTSRC_ALL_HSACKDET_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_HSACKDET_Pos)
#define I2CTXABRTSRC_ALL_HSACKDET_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_HSACKDET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    STARTACKDET
 *  @access     I2C->I2CTXABRTSRC.bit.STARTACKDET
 *  @brief      Role of I2C: Master transmitter/receiver
 *              This bit is set when master has sent a START Byte and the START Byte was acknowledged
 *              (wrong behavior).
 */
#define I2CTXABRTSRC_ALL_STARTACKDET_Pos (7)
#define I2CTXABRTSRC_ALL_STARTACKDET_Msk (0x1UL << I2CTXABRTSRC_ALL_STARTACKDET_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_STARTACKDET_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_STARTACKDET_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_STARTACKDET;

#define I2CTXABRTSRC_ALL_STARTACKDET_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_STARTACKDET_Pos)
#define I2CTXABRTSRC_ALL_STARTACKDET_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_STARTACKDET_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    HSNORESTART
 *  @access     I2C->I2CTXABRTSRC.bit.HSNORESTART
 *  @brief      Role of I2C: Master transmitter/receiver
 *              This bit is set when the restart is disabled (I2CCTL.RESTARTEN=0) and the user is
 *              trying to use the master to transfer data in high speed mode.
 */
#define I2CTXABRTSRC_ALL_HSNORESTART_Pos (8)
#define I2CTXABRTSRC_ALL_HSNORESTART_Msk (0x1UL << I2CTXABRTSRC_ALL_HSNORESTART_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_HSNORESTART_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_HSNORESTART_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_HSNORESTART;

#define I2CTXABRTSRC_ALL_HSNORESTART_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_HSNORESTART_Pos)
#define I2CTXABRTSRC_ALL_HSNORESTART_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_HSNORESTART_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    STARTNORESTART
 *  @access     I2C->I2CTXABRTSRC.bit.STARTNORESTART
 *  @brief      Role of I2C: Master transmitter/receiver
 *              This bit is set when the restart is disabled (I2CCTL.RESTARTEN=0) and the user is
 *              trying to send a START Byte.
 *              Follow configurations below to avoid this error
 *              (1) I2CCTL.RESTARTEN=1
 *              (2) I2CMASTERADDR.SPECIAL=0 or I2CMASTERADDR.GCORSTART=0
 *              Otherwise, this bit is set again at next clock after it is cleared by reading from
 *              I2CTXABRTCLR register.
 */
#define I2CTXABRTSRC_ALL_STARTNORESTART_Pos (9)
#define I2CTXABRTSRC_ALL_STARTNORESTART_Msk (0x1UL << I2CTXABRTSRC_ALL_STARTNORESTART_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_STARTNORESTART_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_STARTNORESTART_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_STARTNORESTART;

#define I2CTXABRTSRC_ALL_STARTNORESTART_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_STARTNORESTART_Pos)
#define I2CTXABRTSRC_ALL_STARTNORESTART_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_STARTNORESTART_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    RD10BNORESTART
 *  @access     I2C->I2CTXABRTSRC.bit.RD10BNORESTART
 *  @brief      Role of I2C: Master receiver
 *              This bit is set when the restart is disabled (I2CCTL.RESTARTEN=0) and the master
 *              sends a read command in 10-bit addressing mode.
 */
#define I2CTXABRTSRC_ALL_RD10BNORESTART_Pos (10)
#define I2CTXABRTSRC_ALL_RD10BNORESTART_Msk (0x1UL << I2CTXABRTSRC_ALL_RD10BNORESTART_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_RD10BNORESTART_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_RD10BNORESTART_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_RD10BNORESTART;

#define I2CTXABRTSRC_ALL_RD10BNORESTART_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_RD10BNORESTART_Pos)
#define I2CTXABRTSRC_ALL_RD10BNORESTART_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_RD10BNORESTART_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    MASTERDIS
 *  @access     I2C->I2CTXABRTSRC.bit.MASTERDIS
 *  @brief      Role of I2C: Master transmitter/receiver
 *              This bit is set when user tries to initiate a master operation with the master mode
 *              is disabled.
 */
#define I2CTXABRTSRC_ALL_MASTERDIS_Pos (11)
#define I2CTXABRTSRC_ALL_MASTERDIS_Msk (0x1UL << I2CTXABRTSRC_ALL_MASTERDIS_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_MASTERDIS_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_MASTERDIS_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_MASTERDIS;

#define I2CTXABRTSRC_ALL_MASTERDIS_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_MASTERDIS_Pos)
#define I2CTXABRTSRC_ALL_MASTERDIS_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_MASTERDIS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    MARBLOST
 *  @access     I2C->I2CTXABRTSRC.bit.MARBLOST
 *  @brief      Role of I2C: Master/slave transmitter
 *              This bit is set when master has lost arbitration, or if I2CTXABRTSRC.SARBLOST is
 *              also set, then the slave transmitter has lost arbitration.
 */
#define I2CTXABRTSRC_ALL_MARBLOST_Pos (12)
#define I2CTXABRTSRC_ALL_MARBLOST_Msk (0x1UL << I2CTXABRTSRC_ALL_MARBLOST_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_MARBLOST_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_MARBLOST_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_MARBLOST;

#define I2CTXABRTSRC_ALL_MARBLOST_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_MARBLOST_Pos)
#define I2CTXABRTSRC_ALL_MARBLOST_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_MARBLOST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    SLVFLUSHTF
 *  @access     I2C->I2CTXABRTSRC.bit.SLVFLUSHTF
 *  @brief      Role of I2C: Slave transmitter
 *              This bis is set when slave has received a read command and some data exists in the
 *              TX FIFO so the slave issues a TXABRT interrupt to flush old data in TX FIFO.
 */
#define I2CTXABRTSRC_ALL_SLVFLUSHTF_Pos (13)
#define I2CTXABRTSRC_ALL_SLVFLUSHTF_Msk (0x1UL << I2CTXABRTSRC_ALL_SLVFLUSHTF_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_SLVFLUSHTF_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_SLVFLUSHTF_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_SLVFLUSHTF;

#define I2CTXABRTSRC_ALL_SLVFLUSHTF_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_SLVFLUSHTF_Pos)
#define I2CTXABRTSRC_ALL_SLVFLUSHTF_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_SLVFLUSHTF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    SARBLOST
 *  @access     I2C->I2CTXABRTSRC.bit.SARBLOST
 *  @brief      Role of I2C: Slave transmitter
 *              This bit is set when slave lost the bus while transmitting data to a remote master.
 *              I2CTXABRTSRC.MARBLOST is set at the same time.
 *              Note: Even though the slave never 'owns' the bus, something could go wrong on the
 *              bus. This is a failsafe check. For instance, during a data transmission at the low-to-high
 *              transition of SCL, if what is on the data bus is not what is supposed to be transmitted,
 *              then I2C no longer own the bus.
 */
#define I2CTXABRTSRC_ALL_SARBLOST_Pos (14)
#define I2CTXABRTSRC_ALL_SARBLOST_Msk (0x1UL << I2CTXABRTSRC_ALL_SARBLOST_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_SARBLOST_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_SARBLOST_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_SARBLOST;

#define I2CTXABRTSRC_ALL_SARBLOST_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_SARBLOST_Pos)
#define I2CTXABRTSRC_ALL_SARBLOST_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_SARBLOST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CTXABRTSRC    SLVRDINTX
 *  @access     I2C->I2CTXABRTSRC.bit.SLVRDINTX
 *  @brief      Role of I2C: Slave transmitter
 *              This bit is set when the processor side responds to a slave mode request for data
 *              to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of I2CDATACMD
 *              register.
 */
#define I2CTXABRTSRC_ALL_SLVRDINTX_Pos (15)
#define I2CTXABRTSRC_ALL_SLVRDINTX_Msk (0x1UL << I2CTXABRTSRC_ALL_SLVRDINTX_Pos)

typedef enum
{
    I2CTXABRTSRC_BIT_SLVRDINTX_NOT_OCCUR     = 0,  /*!<    */
    I2CTXABRTSRC_BIT_SLVRDINTX_OCCUR         = 1,  /*!<    */
} I2CTXABRTSRC_BIT_SLVRDINTX;

#define I2CTXABRTSRC_ALL_SLVRDINTX_NOT_OCCUR     ((0x0UL) << I2CTXABRTSRC_ALL_SLVRDINTX_Pos)
#define I2CTXABRTSRC_ALL_SLVRDINTX_OCCUR         ((0x1UL) << I2CTXABRTSRC_ALL_SLVRDINTX_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CSDASETUP     VAL
 *  @access     I2C->I2CSDASETUP.bit.VAL
 *  @brief      Configure SDA setup time as VAL CLK_I2C cycles
 *              i.e. If the required setup delay is 1000ns, then for an CLK_I2C frequency of 10 MHz,
 *              this register is recommended to be programmed as 11.
 */
#define I2CSDASETUP_ALL_VAL_Pos (0)
#define I2CSDASETUP_ALL_VAL_Msk (0xFFUL << I2CSDASETUP_ALL_VAL_Pos)

#define I2CSDASETUP_BIT_VAL

#define I2CSDASETUP_ALL_VAL_(x) ((x) << I2CSDASETUP_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CACKGC        ACKGC
 *  @access     I2C->I2CACKGC.bit.ACKGC
 *  @brief      Respond upon General Call
 */
#define I2CACKGC_ALL_ACKGC_Pos (0)
#define I2CACKGC_ALL_ACKGC_Msk (0x1UL << I2CACKGC_ALL_ACKGC_Pos)

typedef enum
{
    I2CACKGC_BIT_ACKGC_DISABLE     = 0,  /*!< Responds General Call with an NACK   */
    I2CACKGC_BIT_ACKGC_ENABLE      = 1,  /*!< Responds General Call with an ACK    */
} I2CACKGC_BIT_ACKGC;

#define I2CACKGC_ALL_ACKGC_DISABLE     ((0x0UL) << I2CACKGC_ALL_ACKGC_Pos)
#define I2CACKGC_ALL_ACKGC_ENABLE      ((0x1UL) << I2CACKGC_ALL_ACKGC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CENSTS        EN
 *  @access     I2C->I2CENSTS.bit.EN
 *  @brief      I2C enabled status
 */
#define I2CENSTS_ALL_EN_Pos (0)
#define I2CENSTS_ALL_EN_Msk (0x1UL << I2CENSTS_ALL_EN_Pos)

typedef enum
{
    I2CENSTS_BIT_EN_DISABLE     = 0,  /*!< I2C is deemed completely inactive                   
                                           SLVRDLOST and SLVDISONBUSY bits can be read safely   */
    I2CENSTS_BIT_EN_ENABLE      = 1,  /*!< I2C is deemed to be in an enabled state              */
} I2CENSTS_BIT_EN;

#define I2CENSTS_ALL_EN_DISABLE     ((0x0UL) << I2CENSTS_ALL_EN_Pos)
#define I2CENSTS_ALL_EN_ENABLE      ((0x1UL) << I2CENSTS_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CENSTS        SLVDISONBUSY
 *  @access     I2C->I2CENSTS.bit.SLVDISONBUSY
 *  @brief      Slave disabled while it is busy
 */
#define I2CENSTS_ALL_SLVDISONBUSY_Pos (1)
#define I2CENSTS_ALL_SLVDISONBUSY_Msk (0x1UL << I2CENSTS_ALL_SLVDISONBUSY_Pos)

typedef enum
{
    I2CENSTS_BIT_SLVDISONBUSY_NOT_OCCUR     = 0,  /*!< I2CENABLE is stable during slave operation                                         */
    I2CENSTS_BIT_SLVDISONBUSY_OCCUR         = 1,  /*!< I2CENABLE is changed from 1 to 0 when I2C slave is receiving from a remote mater  
                                                       on                                                                                
                                                       (a) The address byte of the slave transmitter                                     
                                                       (b) The address and data bytes of the slave receiver                               */
} I2CENSTS_BIT_SLVDISONBUSY;

#define I2CENSTS_ALL_SLVDISONBUSY_NOT_OCCUR     ((0x0UL) << I2CENSTS_ALL_SLVDISONBUSY_Pos)
#define I2CENSTS_ALL_SLVDISONBUSY_OCCUR         ((0x1UL) << I2CENSTS_ALL_SLVDISONBUSY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CENSTS        SLVRDLOST
 *  @access     I2C->I2CENSTS.bit.SLVRDLOST
 *  @brief      Slave received data lost upon disable I2C
 */
#define I2CENSTS_ALL_SLVRDLOST_Pos (2)
#define I2CENSTS_ALL_SLVRDLOST_Msk (0x1UL << I2CENSTS_ALL_SLVRDLOST_Pos)

typedef enum
{
    I2CENSTS_BIT_SLVRDLOST_NOT_OCCUR     = 0,  /*!< Slave receiver operation is done before I2CENABLE is changed from 1 to 0           */
    I2CENSTS_BIT_SLVRDLOST_OCCUR         = 1,  /*!< Slave receiver operation is aborted with at least one data byte received from an  
                                                    I2C transfer when I2CENABLE is changed from 1 to 0                                 */
} I2CENSTS_BIT_SLVRDLOST;

#define I2CENSTS_ALL_SLVRDLOST_NOT_OCCUR     ((0x0UL) << I2CENSTS_ALL_SLVRDLOST_Pos)
#define I2CENSTS_ALL_SLVRDLOST_OCCUR         ((0x1UL) << I2CENSTS_ALL_SLVRDLOST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CFSSPKLEN     VAL
 *  @access     I2C->I2CFSSPKLEN.bit.VAL
 *  @brief      Duration in fast speed mode of the longest spike in the SCL or SDA lines that are
 *              filtered out by the spike suppression logic.
 *              The minimum value is 1 and write a 0 will be reset as 1 by the hardware.
 *              This register can be written only when I2CENABLE=0. Writes at other times have no
 *              effect.
 */
#define I2CFSSPKLEN_ALL_VAL_Pos (0)
#define I2CFSSPKLEN_ALL_VAL_Msk (0xFFUL << I2CFSSPKLEN_ALL_VAL_Pos)

#define I2CFSSPKLEN_BIT_VAL

#define I2CFSSPKLEN_ALL_VAL_(x) ((x) << I2CFSSPKLEN_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   I2C             I2CHSSPKLEN     VAL
 *  @access     I2C->I2CHSSPKLEN.bit.VAL
 *  @brief      Duration in high speed mode of the longest spike in the SCL or SDA lines that are
 *              filtered out by the spike suppression logic.
 *              The minimum value is 1 and write a 0 will be reset as 1 by the hardware.
 *              This register can be written only when I2CENABLE=0. Writes at other times have no
 *              effect.
 */
#define I2CHSSPKLEN_ALL_VAL_Pos (0)
#define I2CHSSPKLEN_ALL_VAL_Msk (0xFFUL << I2CHSSPKLEN_ALL_VAL_Pos)

#define I2CHSSPKLEN_BIT_VAL

#define I2CHSSPKLEN_ALL_VAL_(x) ((x) << I2CHSSPKLEN_ALL_VAL_Pos)



/********************************************************************************
*
* Module Name     TIMER
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRCTL          EN
 *  @access     TIMER->TMRCTL.bit.EN
 *  @brief      Timer enable
 */
#define TMRCTL_ALL_EN_Pos (0)
#define TMRCTL_ALL_EN_Msk (0x1UL << TMRCTL_ALL_EN_Pos)

typedef enum
{
    TMRCTL_BIT_EN_DISABLE     = 0,  /*!< Disable Timer   */
    TMRCTL_BIT_EN_ENABLE      = 1,  /*!< Enable Timer    */
} TMRCTL_BIT_EN;

#define TMRCTL_ALL_EN_DISABLE     ((0x0UL) << TMRCTL_ALL_EN_Pos)
#define TMRCTL_ALL_EN_ENABLE      ((0x1UL) << TMRCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRCTL          ADCSOCEN
 *  @access     TIMER->TMRCTL.bit.ADCSOCEN
 *  @brief      ADCSOC generation enable
 */
#define TMRCTL_ALL_ADCSOCEN_Pos (2)
#define TMRCTL_ALL_ADCSOCEN_Msk (0x1UL << TMRCTL_ALL_ADCSOCEN_Pos)

typedef enum
{
    TMRCTL_BIT_ADCSOCEN_DISABLE     = 0,  /*!< Do not generate ADCSOC                             */
    TMRCTL_BIT_ADCSOCEN_ENABLE      = 1,  /*!< Generate ADCSOC whenever TMRCNT counts down to 0   */
} TMRCTL_BIT_ADCSOCEN;

#define TMRCTL_ALL_ADCSOCEN_DISABLE     ((0x0UL) << TMRCTL_ALL_ADCSOCEN_Pos)
#define TMRCTL_ALL_ADCSOCEN_ENABLE      ((0x1UL) << TMRCTL_ALL_ADCSOCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRCTL          PWMSYNCEN
 *  @access     TIMER->TMRCTL.bit.PWMSYNCEN
 *  @brief      PWMSYNC generation enable
 */
#define TMRCTL_ALL_PWMSYNCEN_Pos (3)
#define TMRCTL_ALL_PWMSYNCEN_Msk (0x1UL << TMRCTL_ALL_PWMSYNCEN_Pos)

typedef enum
{
    TMRCTL_BIT_PWMSYNCEN_DISABLE     = 0,  /*!< Do not generate PWMSYNC                             */
    TMRCTL_BIT_PWMSYNCEN_ENABLE      = 1,  /*!< Generate PWMSYNC whenever TMRCNT counts down to 0   */
} TMRCTL_BIT_PWMSYNCEN;

#define TMRCTL_ALL_PWMSYNCEN_DISABLE     ((0x0UL) << TMRCTL_ALL_PWMSYNCEN_Pos)
#define TMRCTL_ALL_PWMSYNCEN_ENABLE      ((0x1UL) << TMRCTL_ALL_PWMSYNCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRCTL          EXTINMODE
 *  @access     TIMER->TMRCTL.bit.EXTINMODE
 *  @brief      External input mode
 */
#define TMRCTL_ALL_EXTINMODE_Pos (4)
#define TMRCTL_ALL_EXTINMODE_Msk (0x3UL << TMRCTL_ALL_EXTINMODE_Pos)

typedef enum
{
    TMRCTL_BIT_EXTINMODE_DISABLE     = 0,  /*!< Disable external input                */
    TMRCTL_BIT_EXTINMODE_EXTCLK      = 2,  /*!< Take external input as timer clock    */
    TMRCTL_BIT_EXTINMODE_EXTEN       = 3,  /*!< Take external input as timer enable   */
} TMRCTL_BIT_EXTINMODE;

#define TMRCTL_ALL_EXTINMODE_DISABLE     ((0x0UL) << TMRCTL_ALL_EXTINMODE_Pos)
#define TMRCTL_ALL_EXTINMODE_EXTCLK      ((0x2UL) << TMRCTL_ALL_EXTINMODE_Pos)
#define TMRCTL_ALL_EXTINMODE_EXTEN       ((0x3UL) << TMRCTL_ALL_EXTINMODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRCTL          EXTPOL
 *  @access     TIMER->TMRCTL.bit.EXTPOL
 *  @brief      External input polarity
 */
#define TMRCTL_ALL_EXTPOL_Pos (6)
#define TMRCTL_ALL_EXTPOL_Msk (0x1UL << TMRCTL_ALL_EXTPOL_Pos)

typedef enum
{
    TMRCTL_BIT_EXTPOL_ACTIVE_LOW      = 0,  /*!< Active low    */
    TMRCTL_BIT_EXTPOL_ACTIVE_HIGH     = 1,  /*!< Active high   */
} TMRCTL_BIT_EXTPOL;

#define TMRCTL_ALL_EXTPOL_ACTIVE_LOW      ((0x0UL) << TMRCTL_ALL_EXTPOL_Pos)
#define TMRCTL_ALL_EXTPOL_ACTIVE_HIGH     ((0x1UL) << TMRCTL_ALL_EXTPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRCTL          EXTSEL
 *  @access     TIMER->TMRCTL.bit.EXTSEL
 *  @brief      External input source select (GPIO number)
 */
#define TMRCTL_ALL_EXTSEL_Pos (7)
#define TMRCTL_ALL_EXTSEL_Msk (0x3FUL << TMRCTL_ALL_EXTSEL_Pos)

#define TMRCTL_BIT_EXTSEL

#define TMRCTL_ALL_EXTSEL_(x) ((x) << TMRCTL_ALL_EXTSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRCNT          VAL
 *  @access     TIMER->TMRCNT.bit.VAL
 *  @brief      Current value of timer counter.
 */
#define TMRCNT_ALL_VAL_Pos (0)
#define TMRCNT_ALL_VAL_Msk (0xFFFFFFFFUL << TMRCNT_ALL_VAL_Pos)

#define TMRCNT_BIT_VAL

#define TMRCNT_ALL_VAL_(x) ((x) << TMRCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRRELOAD       VAL
 *  @access     TIMER->TMRRELOAD.bit.VAL
 *  @brief      Reload value, A Write to this registers sets the current value.
 */
#define TMRRELOAD_ALL_VAL_Pos (0)
#define TMRRELOAD_ALL_VAL_Msk (0xFFFFFFFFUL << TMRRELOAD_ALL_VAL_Pos)

#define TMRRELOAD_BIT_VAL

#define TMRRELOAD_ALL_VAL_(x) ((x) << TMRRELOAD_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRIF           INT
 *  @access     TIMER->TMRIF.bit.INT
 *  @brief      Timer interrupt
 */
#define TMRIF_ALL_INT_Pos (0)
#define TMRIF_ALL_INT_Msk (0x1UL << TMRIF_ALL_INT_Pos)

typedef enum
{
    TMRIF_BIT_INT_NOT_OCCUR     = 0,  /*!< Interrupt not occurred                                          */
    TMRIF_BIT_INT_OCCUR         = 1,  /*!< Interrupt occurred and issued to CPU                           
                                           No further interrupt will be issued until the flag is cleared   */
} TMRIF_BIT_INT;

#define TMRIF_ALL_INT_NOT_OCCUR     ((0x0UL) << TMRIF_ALL_INT_Pos)
#define TMRIF_ALL_INT_OCCUR         ((0x1UL) << TMRIF_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRRAWIF        INT
 *  @access     TIMER->TMRRAWIF.bit.INT
 *  @brief      Timer raw interrupt status. This bit is set whenever TMRCNT counts down to 0 and
 *              cleared only by writing a 1 to TMRIC
 */
#define TMRRAWIF_ALL_INT_Pos (0)
#define TMRRAWIF_ALL_INT_Msk (0x1UL << TMRRAWIF_ALL_INT_Pos)

typedef enum
{
    TMRRAWIF_BIT_INT_NOT_OCCUR     = 0,  /*!< Interrupt not occurred   */
    TMRRAWIF_BIT_INT_OCCUR         = 1,  /*!< Interrupt occurred       */
} TMRRAWIF_BIT_INT;

#define TMRRAWIF_ALL_INT_NOT_OCCUR     ((0x0UL) << TMRRAWIF_ALL_INT_Pos)
#define TMRRAWIF_ALL_INT_OCCUR         ((0x1UL) << TMRRAWIF_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRIE           INT
 *  @access     TIMER->TMRIE.bit.INT
 *  @brief      Timer interrupt enable. This bit does not affect TMRRAWIF and PWMSYNC/ADCSOC generation
 */
#define TMRIE_ALL_INT_Pos (0)
#define TMRIE_ALL_INT_Msk (0x1UL << TMRIE_ALL_INT_Pos)

typedef enum
{
    TMRIE_BIT_INT_DISABLE     = 0,  /*!< Do not issue interrupt to CPU         */
    TMRIE_BIT_INT_ENABLE      = 1,  /*!< Issue interrupt whenever TMRRAWIF=1   */
} TMRIE_BIT_INT;

#define TMRIE_ALL_INT_DISABLE     ((0x0UL) << TMRIE_ALL_INT_Pos)
#define TMRIE_ALL_INT_ENABLE      ((0x1UL) << TMRIE_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRIFRC         INT
 *  @access     TIMER->TMRIFRC.bit.INT
 *  @brief      Timer interrupt software force
 */
#define TMRIFRC_ALL_INT_Pos (0)
#define TMRIFRC_ALL_INT_Msk (0x1UL << TMRIFRC_ALL_INT_Pos)

typedef enum
{
    TMRIFRC_BIT_INT_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.            
                                             Always reads back a 0.                 */
    TMRIFRC_BIT_INT_FORCE         = 1,  /*!< Writing a 1 forces the TMRRAWIF flag  
                                             This bit is self-cleared to 0.         */
} TMRIFRC_BIT_INT;

#define TMRIFRC_ALL_INT_NO_EFFECT     ((0x0UL) << TMRIFRC_ALL_INT_Pos)
#define TMRIFRC_ALL_INT_FORCE         ((0x1UL) << TMRIFRC_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   TIMER           TMRIC           INT
 *  @access     TIMER->TMRIC.bit.INT
 *  @brief      Timer interrupt clear
 */
#define TMRIC_ALL_INT_Pos (0)
#define TMRIC_ALL_INT_Msk (0x1UL << TMRIC_ALL_INT_Pos)

typedef enum
{
    TMRIC_BIT_INT_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.                  
                                           Always reads back a 0.                       */
    TMRIC_BIT_INT_CLEAR         = 1,  /*!< Writing a 1 clears the TMRRAWIF/TMRIF flag  
                                           This bit is self-cleared to 0.               */
} TMRIC_BIT_INT;

#define TMRIC_ALL_INT_NO_EFFECT     ((0x0UL) << TMRIC_ALL_INT_Pos)
#define TMRIC_ALL_INT_CLEAR         ((0x1UL) << TMRIC_ALL_INT_Pos)



/********************************************************************************
*
* Module Name     CRC
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCIF           DONE
 *  @access     CRC->CRCIF.bit.DONE
 *  @brief      CRC calculation done interrupt status after mask
 */
#define CRCIF_ALL_DONE_Pos (0)
#define CRCIF_ALL_DONE_Msk (0x1UL << CRCIF_ALL_DONE_Pos)

typedef enum
{
    CRCIF_BIT_DONE_NOT_OCCUR     = 0,  /*!< Interrupt is not occurred   */
    CRCIF_BIT_DONE_OCCUR         = 1,  /*!< Interrupt is occurred       */
} CRCIF_BIT_DONE;

#define CRCIF_ALL_DONE_NOT_OCCUR     ((0x0UL) << CRCIF_ALL_DONE_Pos)
#define CRCIF_ALL_DONE_OCCUR         ((0x1UL) << CRCIF_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCRAWIF        DONE
 *  @access     CRC->CRCRAWIF.bit.DONE
 *  @brief      CRC calculation done interrupt raw status regardless of mask
 */
#define CRCRAWIF_ALL_DONE_Pos (0)
#define CRCRAWIF_ALL_DONE_Msk (0x1UL << CRCRAWIF_ALL_DONE_Pos)

typedef enum
{
    CRCRAWIF_BIT_DONE_NOT_OCCUR     = 0,  /*!< Interrupt is not occurred   */
    CRCRAWIF_BIT_DONE_OCCUR         = 1,  /*!< Interrupt is occurred       */
} CRCRAWIF_BIT_DONE;

#define CRCRAWIF_ALL_DONE_NOT_OCCUR     ((0x0UL) << CRCRAWIF_ALL_DONE_Pos)
#define CRCRAWIF_ALL_DONE_OCCUR         ((0x1UL) << CRCRAWIF_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCIC           DONE
 *  @access     CRC->CRCIC.bit.DONE
 *  @brief      Clearance of CRCIF[0] and CRCRAWIF[0]
 */
#define CRCIC_ALL_DONE_Pos (0)
#define CRCIC_ALL_DONE_Msk (0x1UL << CRCIC_ALL_DONE_Pos)

typedef enum
{
    CRCIC_BIT_DONE_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.       */
    CRCIC_BIT_DONE_CLEAR         = 1,  /*!< Write a 1 clears both CRCIF[0] and CRCRAWIF[0].  
                                            This bit is self-cleared to 0                     */
} CRCIC_BIT_DONE;

#define CRCIC_ALL_DONE_NO_EFFECT     ((0x0UL) << CRCIC_ALL_DONE_Pos)
#define CRCIC_ALL_DONE_CLEAR         ((0x1UL) << CRCIC_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCIE           DONE
 *  @access     CRC->CRCIE.bit.DONE
 *  @brief      Enable interrupt triggered by CRCRWIF[0]
 */
#define CRCIE_ALL_DONE_Pos (0)
#define CRCIE_ALL_DONE_Msk (0x1UL << CRCIE_ALL_DONE_Pos)

typedef enum
{
    CRCIE_BIT_DONE_DISABLE     = 0,  /*!< Disable generation of IRQ and corresponding CRCIF[0]   */
    CRCIE_BIT_DONE_ENABLE      = 1,  /*!< Enable generation of IRQ and corresponding CRCIF[0]    */
} CRCIE_BIT_DONE;

#define CRCIE_ALL_DONE_DISABLE     ((0x0UL) << CRCIE_ALL_DONE_Pos)
#define CRCIE_ALL_DONE_ENABLE      ((0x1UL) << CRCIE_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCCTL          EN
 *  @access     CRC->CRCCTL.bit.EN
 *  @brief      CRC calculate enable
 */
#define CRCCTL_ALL_EN_Pos (0)
#define CRCCTL_ALL_EN_Msk (0x1UL << CRCCTL_ALL_EN_Pos)

typedef enum
{
    CRCCTL_BIT_EN_DISABLE     = 0,  /*!< Disable CRC calculation                                                                    */
    CRCCTL_BIT_EN_ENABLE      = 1,  /*!< Enable CRC calculation, it is automatically cleared when the CRC calculation is finished   */
} CRCCTL_BIT_EN;

#define CRCCTL_ALL_EN_DISABLE     ((0x0UL) << CRCCTL_ALL_EN_Pos)
#define CRCCTL_ALL_EN_ENABLE      ((0x1UL) << CRCCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCCTL          MODE
 *  @access     CRC->CRCCTL.bit.MODE
 *  @brief      CRC mode select
 */
#define CRCCTL_ALL_MODE_Pos (1)
#define CRCCTL_ALL_MODE_Msk (0x7UL << CRCCTL_ALL_MODE_Pos)

typedef enum
{
    CRCCTL_BIT_MODE_16_CCITT       = 0,  /*!< x^16+x^12+x^5+1 (CRC-16-CCITT, CRC-CCITT)                                            */
    CRCCTL_BIT_MODE_16_IBM         = 1,  /*!< x^16+x^15+x^2+1 (CRC-16, CRC-16-IBM, CRC-16-ANSI)                                    */
    CRCCTL_BIT_MODE_16_T10_DIF     = 2,  /*!< x^16+x^15+x^11+x^9+x^8+x^7+x^5+x^4+x^2+x+1 (CRC-16-T10-DIF)                          */
    CRCCTL_BIT_MODE_IEEE802_3      = 3,  /*!< x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1 (CRC-32-IEEE802.3)   */
    CRCCTL_BIT_MODE_16_DNP         = 4,  /*!< x^16+x^13+x^12+x^11+x^10+x^8+x^6+x^5+x^2+1(CRC-16-DNP)                               */
} CRCCTL_BIT_MODE;

#define CRCCTL_ALL_MODE_16_CCITT       ((0x0UL) << CRCCTL_ALL_MODE_Pos)
#define CRCCTL_ALL_MODE_16_IBM         ((0x1UL) << CRCCTL_ALL_MODE_Pos)
#define CRCCTL_ALL_MODE_16_T10_DIF     ((0x2UL) << CRCCTL_ALL_MODE_Pos)
#define CRCCTL_ALL_MODE_IEEE802_3      ((0x3UL) << CRCCTL_ALL_MODE_Pos)
#define CRCCTL_ALL_MODE_16_DNP         ((0x4UL) << CRCCTL_ALL_MODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCSTRLEN       VAL
 *  @access     CRC->CRCSTRLEN.bit.VAL
 *  @brief      Input stream length minus 1(in unit of byte)
 */
#define CRCSTRLEN_ALL_VAL_Pos (0)
#define CRCSTRLEN_ALL_VAL_Msk (0xFFFFFFFFUL << CRCSTRLEN_ALL_VAL_Pos)

#define CRCSTRLEN_BIT_VAL

#define CRCSTRLEN_ALL_VAL_(x) ((x) << CRCSTRLEN_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCSTRIN        VAL
 *  @access     CRC->CRCSTRIN.bit.VAL
 *  @brief      Stream Input data register
 */
#define CRCSTRIN_ALL_VAL_Pos (0)
#define CRCSTRIN_ALL_VAL_Msk (0xFFFFFFFFUL << CRCSTRIN_ALL_VAL_Pos)

#define CRCSTRIN_BIT_VAL

#define CRCSTRIN_ALL_VAL_(x) ((x) << CRCSTRIN_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   CRC             CRCRESULT       VAL
 *  @access     CRC->CRCRESULT.bit.VAL
 *  @brief      CRC calculation result
 */
#define CRCRESULT_ALL_VAL_Pos (0)
#define CRCRESULT_ALL_VAL_Msk (0xFFFFFFFFUL << CRCRESULT_ALL_VAL_Pos)

#define CRCRESULT_BIT_VAL

#define CRCRESULT_ALL_VAL_(x) ((x) << CRCRESULT_ALL_VAL_Pos)



/********************************************************************************
*
* Module Name     AES
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         START
 *  @access     AES->AESCTL0.bit.START
 *  @brief      Start AES
 */
#define AESCTL0_ALL_START_Pos (0)
#define AESCTL0_ALL_START_Msk (0x1UL << AESCTL0_ALL_START_Pos)

typedef enum
{
    AESCTL0_BIT_START_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.   */
    AESCTL0_BIT_START_AES_START     = 1,  /*!< Write a 1 starts AES operation               
                                               This bit is self-cleared to 0                 */
} AESCTL0_BIT_START;

#define AESCTL0_ALL_START_NO_EFFECT     ((0x0UL) << AESCTL0_ALL_START_Pos)
#define AESCTL0_ALL_START_AES_START     ((0x1UL) << AESCTL0_ALL_START_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         IFIFOCLR
 *  @access     AES->AESCTL0.bit.IFIFOCLR
 *  @brief      Clear input FIFO
 */
#define AESCTL0_ALL_IFIFOCLR_Pos (2)
#define AESCTL0_ALL_IFIFOCLR_Msk (0x1UL << AESCTL0_ALL_IFIFOCLR_Pos)

typedef enum
{
    AESCTL0_BIT_IFIFOCLR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.   */
    AESCTL0_BIT_IFIFOCLR_CLEAR         = 1,  /*!< Write a 1 clears the input FIFO              
                                                  This bit is self-cleared to 0                 */
} AESCTL0_BIT_IFIFOCLR;

#define AESCTL0_ALL_IFIFOCLR_NO_EFFECT     ((0x0UL) << AESCTL0_ALL_IFIFOCLR_Pos)
#define AESCTL0_ALL_IFIFOCLR_CLEAR         ((0x1UL) << AESCTL0_ALL_IFIFOCLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         OFIFOCLR
 *  @access     AES->AESCTL0.bit.OFIFOCLR
 *  @brief      Clear output FIFO
 */
#define AESCTL0_ALL_OFIFOCLR_Pos (3)
#define AESCTL0_ALL_OFIFOCLR_Msk (0x1UL << AESCTL0_ALL_OFIFOCLR_Pos)

typedef enum
{
    AESCTL0_BIT_OFIFOCLR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.   */
    AESCTL0_BIT_OFIFOCLR_CLEAR         = 1,  /*!< Write a 1 clears the output FIFO             
                                                  This bit is self-cleared to 0                 */
} AESCTL0_BIT_OFIFOCLR;

#define AESCTL0_ALL_OFIFOCLR_NO_EFFECT     ((0x0UL) << AESCTL0_ALL_OFIFOCLR_Pos)
#define AESCTL0_ALL_OFIFOCLR_CLEAR         ((0x1UL) << AESCTL0_ALL_OFIFOCLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         OUTMSG
 *  @access     AES->AESCTL0.bit.OUTMSG
 *  @brief      Output stream to output FIFO
 */
#define AESCTL0_ALL_OUTMSG_Pos (4)
#define AESCTL0_ALL_OUTMSG_Msk (0x1UL << AESCTL0_ALL_OUTMSG_Pos)

typedef enum
{
    AESCTL0_BIT_OUTMSG_DISABLE     = 0,  /*!< Block output stream from output FIFO   */
    AESCTL0_BIT_OUTMSG_ENABLE      = 1,  /*!< Forward output stream to output FIFO   */
} AESCTL0_BIT_OUTMSG;

#define AESCTL0_ALL_OUTMSG_DISABLE     ((0x0UL) << AESCTL0_ALL_OUTMSG_Pos)
#define AESCTL0_ALL_OUTMSG_ENABLE      ((0x1UL) << AESCTL0_ALL_OUTMSG_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         OUTHDR
 *  @access     AES->AESCTL0.bit.OUTHDR
 *  @brief      Output B0 and l(a) in CCM* mode
 */
#define AESCTL0_ALL_OUTHDR_Pos (5)
#define AESCTL0_ALL_OUTHDR_Msk (0x1UL << AESCTL0_ALL_OUTHDR_Pos)

typedef enum
{
    AESCTL0_BIT_OUTHDR_DISABLE     = 0,  /*!< Don't output B0 and l(a) at the beginning of output stream   */
    AESCTL0_BIT_OUTHDR_ENABLE      = 1,  /*!< Output B0 and l(a) at the beginning of output stream         */
} AESCTL0_BIT_OUTHDR;

#define AESCTL0_ALL_OUTHDR_DISABLE     ((0x0UL) << AESCTL0_ALL_OUTHDR_Pos)
#define AESCTL0_ALL_OUTHDR_ENABLE      ((0x1UL) << AESCTL0_ALL_OUTHDR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         KEYSIZE
 *  @access     AES->AESCTL0.bit.KEYSIZE
 *  @brief      Key size parameter
 */
#define AESCTL0_ALL_KEYSIZE_Pos (10)
#define AESCTL0_ALL_KEYSIZE_Msk (0x3UL << AESCTL0_ALL_KEYSIZE_Pos)

typedef enum
{
    AESCTL0_BIT_KEYSIZE_16BYTE     = 0,  /*!< 16 bytes   */
    AESCTL0_BIT_KEYSIZE_32BYTE     = 1,  /*!< 32 bytes   */
    AESCTL0_BIT_KEYSIZE_24BYTE     = 2,  /*!< 24 bytes   */
} AESCTL0_BIT_KEYSIZE;

#define AESCTL0_ALL_KEYSIZE_16BYTE     ((0x0UL) << AESCTL0_ALL_KEYSIZE_Pos)
#define AESCTL0_ALL_KEYSIZE_32BYTE     ((0x1UL) << AESCTL0_ALL_KEYSIZE_Pos)
#define AESCTL0_ALL_KEYSIZE_24BYTE     ((0x2UL) << AESCTL0_ALL_KEYSIZE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         MICLEN
 *  @access     AES->AESCTL0.bit.MICLEN
 *  @brief      Length of MIC field
 */
#define AESCTL0_ALL_MICLEN_Pos (12)
#define AESCTL0_ALL_MICLEN_Msk (0x3UL << AESCTL0_ALL_MICLEN_Pos)

typedef enum
{
    AESCTL0_BIT_MICLEN_0BYTE      = 0,  /*!< 0 bytes    */
    AESCTL0_BIT_MICLEN_4BYTE      = 1,  /*!< 4 bytes    */
    AESCTL0_BIT_MICLEN_8BYTE      = 2,  /*!< 8 bytes    */
    AESCTL0_BIT_MICLEN_16BYTE     = 3,  /*!< 16 bytes   */
} AESCTL0_BIT_MICLEN;

#define AESCTL0_ALL_MICLEN_0BYTE      ((0x0UL) << AESCTL0_ALL_MICLEN_Pos)
#define AESCTL0_ALL_MICLEN_4BYTE      ((0x1UL) << AESCTL0_ALL_MICLEN_Pos)
#define AESCTL0_ALL_MICLEN_8BYTE      ((0x2UL) << AESCTL0_ALL_MICLEN_Pos)
#define AESCTL0_ALL_MICLEN_16BYTE     ((0x3UL) << AESCTL0_ALL_MICLEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         OUTMIC
 *  @access     AES->AESCTL0.bit.OUTMIC
 *  @brief      Append MIC/HASH at the end of output stream in CCM* mode encryption/MMO mode.
 */
#define AESCTL0_ALL_OUTMIC_Pos (14)
#define AESCTL0_ALL_OUTMIC_Msk (0x1UL << AESCTL0_ALL_OUTMIC_Pos)

typedef enum
{
    AESCTL0_BIT_OUTMIC_DISABLE     = 0,  /*!< Not append MIC/HASH at the end of output stream in CCM* mode encryption or MMO mode   */
    AESCTL0_BIT_OUTMIC_ENABLE      = 1,  /*!< Append MIC/HASH at the end of output stream in CCM* mode encryption or MMO mode       */
} AESCTL0_BIT_OUTMIC;

#define AESCTL0_ALL_OUTMIC_DISABLE     ((0x0UL) << AESCTL0_ALL_OUTMIC_Pos)
#define AESCTL0_ALL_OUTMIC_ENABLE      ((0x1UL) << AESCTL0_ALL_OUTMIC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         DECRYPTEN
 *  @access     AES->AESCTL0.bit.DECRYPTEN
 *  @brief      Decrypt operation. Ignored in MMO and BYPASS Mode.
 */
#define AESCTL0_ALL_DECRYPTEN_Pos (15)
#define AESCTL0_ALL_DECRYPTEN_Msk (0x1UL << AESCTL0_ALL_DECRYPTEN_Pos)

typedef enum
{
    AESCTL0_BIT_DECRYPTEN_ENCRYPT     = 0,  /*!< Encryption   */
    AESCTL0_BIT_DECRYPTEN_DECRYPT     = 1,  /*!< Decryption   */
} AESCTL0_BIT_DECRYPTEN;

#define AESCTL0_ALL_DECRYPTEN_ENCRYPT     ((0x0UL) << AESCTL0_ALL_DECRYPTEN_Pos)
#define AESCTL0_ALL_DECRYPTEN_DECRYPT     ((0x1UL) << AESCTL0_ALL_DECRYPTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         MODE
 *  @access     AES->AESCTL0.bit.MODE
 *  @brief      AES running mode
 */
#define AESCTL0_ALL_MODE_Pos (16)
#define AESCTL0_ALL_MODE_Msk (0x7UL << AESCTL0_ALL_MODE_Pos)

typedef enum
{
    AESCTL0_BIT_MODE_ECB        = 0,  /*!< ECB      */
    AESCTL0_BIT_MODE_CBC        = 1,  /*!< CBC      */
    AESCTL0_BIT_MODE_CTR        = 2,  /*!< CTR      */
    AESCTL0_BIT_MODE_CCM        = 5,  /*!< CCM*     */
    AESCTL0_BIT_MODE_MMO        = 6,  /*!< MMO      */
    AESCTL0_BIT_MODE_BYPASS     = 7,  /*!< BYPASS   */
} AESCTL0_BIT_MODE;

#define AESCTL0_ALL_MODE_ECB        ((0x0UL) << AESCTL0_ALL_MODE_Pos)
#define AESCTL0_ALL_MODE_CBC        ((0x1UL) << AESCTL0_ALL_MODE_Pos)
#define AESCTL0_ALL_MODE_CTR        ((0x2UL) << AESCTL0_ALL_MODE_Pos)
#define AESCTL0_ALL_MODE_CCM        ((0x5UL) << AESCTL0_ALL_MODE_Pos)
#define AESCTL0_ALL_MODE_MMO        ((0x6UL) << AESCTL0_ALL_MODE_Pos)
#define AESCTL0_ALL_MODE_BYPASS     ((0x7UL) << AESCTL0_ALL_MODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESCTL0         CTRMOD
 *  @access     AES->AESCTL0.bit.CTRMOD
 *  @brief      CTR mode's counter modular
 *              modular=2^128:[7'h0-7'hF]
 *              modular=2^ctr_mod: others
 */
#define AESCTL0_ALL_CTRMOD_Pos (19)
#define AESCTL0_ALL_CTRMOD_Msk (0x7FUL << AESCTL0_ALL_CTRMOD_Pos)

#define AESCTL0_BIT_CTRMOD

#define AESCTL0_ALL_CTRMOD_(x) ((x) << AESCTL0_ALL_CTRMOD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTS          DONE
 *  @access     AES->AESSTS.bit.DONE
 *  @brief      AES operation done
 */
#define AESSTS_ALL_DONE_Pos (0)
#define AESSTS_ALL_DONE_Msk (0x1UL << AESSTS_ALL_DONE_Pos)

typedef enum
{
    AESSTS_BIT_DONE_OPERATION_NOT_DONE     = 0,  /*!< AES operation has not done yet   */
    AESSTS_BIT_DONE_OPERATION_DONE         = 1,  /*!< AES operation done               */
} AESSTS_BIT_DONE;

#define AESSTS_ALL_DONE_OPERATION_NOT_DONE     ((0x0UL) << AESSTS_ALL_DONE_Pos)
#define AESSTS_ALL_DONE_OPERATION_DONE         ((0x1UL) << AESSTS_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTS          IFIFOFULL
 *  @access     AES->AESSTS.bit.IFIFOFULL
 *  @brief      Input FIFO full
 */
#define AESSTS_ALL_IFIFOFULL_Pos (4)
#define AESSTS_ALL_IFIFOFULL_Msk (0x1UL << AESSTS_ALL_IFIFOFULL_Pos)

typedef enum
{
    AESSTS_BIT_IFIFOFULL_NOT_FULL     = 0,  /*!< Input FIFO is not full   */
    AESSTS_BIT_IFIFOFULL_FULL         = 1,  /*!< Input FIFO is full       */
} AESSTS_BIT_IFIFOFULL;

#define AESSTS_ALL_IFIFOFULL_NOT_FULL     ((0x0UL) << AESSTS_ALL_IFIFOFULL_Pos)
#define AESSTS_ALL_IFIFOFULL_FULL         ((0x1UL) << AESSTS_ALL_IFIFOFULL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTS          OFIFORDY
 *  @access     AES->AESSTS.bit.OFIFORDY
 *  @brief      Output FIFO is ready to read
 */
#define AESSTS_ALL_OFIFORDY_Pos (6)
#define AESSTS_ALL_OFIFORDY_Msk (0x1UL << AESSTS_ALL_OFIFORDY_Pos)

typedef enum
{
    AESSTS_BIT_OFIFORDY_NOT_READY     = 0,  /*!< Output FIFO is not ready to read   */
    AESSTS_BIT_OFIFORDY_READY         = 1,  /*!< Output FIFO is ready to read       */
} AESSTS_BIT_OFIFORDY;

#define AESSTS_ALL_OFIFORDY_NOT_READY     ((0x0UL) << AESSTS_ALL_OFIFORDY_Pos)
#define AESSTS_ALL_OFIFORDY_READY         ((0x1UL) << AESSTS_ALL_OFIFORDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTS          OFIFOEMPTY
 *  @access     AES->AESSTS.bit.OFIFOEMPTY
 *  @brief      Output FIFO empty
 */
#define AESSTS_ALL_OFIFOEMPTY_Pos (7)
#define AESSTS_ALL_OFIFOEMPTY_Msk (0x1UL << AESSTS_ALL_OFIFOEMPTY_Pos)

typedef enum
{
    AESSTS_BIT_OFIFOEMPTY_NOT_EMPTY     = 0,  /*!< Output FIFO is not empty   */
    AESSTS_BIT_OFIFOEMPTY_EMPTY         = 1,  /*!< Output FIFO is empty       */
} AESSTS_BIT_OFIFOEMPTY;

#define AESSTS_ALL_OFIFOEMPTY_NOT_EMPTY     ((0x0UL) << AESSTS_ALL_OFIFOEMPTY_Pos)
#define AESSTS_ALL_OFIFOEMPTY_EMPTY         ((0x1UL) << AESSTS_ALL_OFIFOEMPTY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTS          ERRCODE
 *  @access     AES->AESSTS.bit.ERRCODE
 *  @brief      AES operation error status
 */
#define AESSTS_ALL_ERRCODE_Pos (11)
#define AESSTS_ALL_ERRCODE_Msk (0x7UL << AESSTS_ALL_ERRCODE_Pos)

typedef enum
{
    AESSTS_BIT_ERRCODE_NO_ERROR     = 0,  /*!< No operation error                                                                  */
    AESSTS_BIT_ERRCODE_1            = 1,  /*!< Input stream size less than 16 byte in ECB, CBC and CTR mode                        */
    AESSTS_BIT_ERRCODE_2            = 2,  /*!< Data is not multiple of 16 bytes in ECB mode or Data is more than 2^13-1 bytes in  
                                               MMO mode                                                                            */
    AESSTS_BIT_ERRCODE_3            = 3,  /*!< Data is not multiple of 16 bytes and less than 16 bytes in ECB mode                 */
    AESSTS_BIT_ERRCODE_4            = 4,  /*!< MIC Mismatch during CCM* Decryption                                                 */
} AESSTS_BIT_ERRCODE;

#define AESSTS_ALL_ERRCODE_NO_ERROR     ((0x0UL) << AESSTS_ALL_ERRCODE_Pos)
#define AESSTS_ALL_ERRCODE_1            ((0x1UL) << AESSTS_ALL_ERRCODE_Pos)
#define AESSTS_ALL_ERRCODE_2            ((0x2UL) << AESSTS_ALL_ERRCODE_Pos)
#define AESSTS_ALL_ERRCODE_3            ((0x3UL) << AESSTS_ALL_ERRCODE_Pos)
#define AESSTS_ALL_ERRCODE_4            ((0x4UL) << AESSTS_ALL_ERRCODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTS          IFIFODEPTH
 *  @access     AES->AESSTS.bit.IFIFODEPTH
 *  @brief      The input FIFO depth
 */
#define AESSTS_ALL_IFIFODEPTH_Pos (14)
#define AESSTS_ALL_IFIFODEPTH_Msk (0x7UL << AESSTS_ALL_IFIFODEPTH_Pos)

#define AESSTS_BIT_IFIFODEPTH

#define AESSTS_ALL_IFIFODEPTH_(x) ((x) << AESSTS_ALL_IFIFODEPTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTS          OFIFODEPTH
 *  @access     AES->AESSTS.bit.OFIFODEPTH
 *  @brief      The output FIFO depth
 */
#define AESSTS_ALL_OFIFODEPTH_Pos (17)
#define AESSTS_ALL_OFIFODEPTH_Msk (0x7UL << AESSTS_ALL_OFIFODEPTH_Pos)

#define AESSTS_BIT_OFIFODEPTH

#define AESSTS_ALL_OFIFODEPTH_(x) ((x) << AESSTS_ALL_OFIFODEPTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESASTRLEN      VAL
 *  @access     AES->AESASTRLEN.bit.VAL
 *  @brief      Size of associate string
 */
#define AESASTRLEN_ALL_VAL_Pos (0)
#define AESASTRLEN_ALL_VAL_Msk (0xFFFFFFFFUL << AESASTRLEN_ALL_VAL_Pos)

#define AESASTRLEN_BIT_VAL

#define AESASTRLEN_ALL_VAL_(x) ((x) << AESASTRLEN_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESMSTRLEN      VAL
 *  @access     AES->AESMSTRLEN.bit.VAL
 *  @brief      Size of message string
 */
#define AESMSTRLEN_ALL_VAL_Pos (0)
#define AESMSTRLEN_ALL_VAL_Msk (0xFFFFFFFFUL << AESMSTRLEN_ALL_VAL_Pos)

#define AESMSTRLEN_BIT_VAL

#define AESMSTRLEN_ALL_VAL_(x) ((x) << AESMSTRLEN_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTRIN        VAL
 *  @access     AES->AESSTRIN.bit.VAL
 *  @brief      input message word
 */
#define AESSTRIN_ALL_VAL_Pos (0)
#define AESSTRIN_ALL_VAL_Msk (0xFFFFFFFFUL << AESSTRIN_ALL_VAL_Pos)

#define AESSTRIN_BIT_VAL

#define AESSTRIN_ALL_VAL_(x) ((x) << AESSTRIN_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIV0          VAL
 *  @access     AES->AESIV0.bit.VAL
 *  @brief      Byte 0-3 of initial vector
 */
#define AESIV0_ALL_VAL_Pos (0)
#define AESIV0_ALL_VAL_Msk (0xFFFFFFFFUL << AESIV0_ALL_VAL_Pos)

#define AESIV0_BIT_VAL

#define AESIV0_ALL_VAL_(x) ((x) << AESIV0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIV1          VAL
 *  @access     AES->AESIV1.bit.VAL
 *  @brief      Byte 4-7 of initial vector
 */
#define AESIV1_ALL_VAL_Pos (0)
#define AESIV1_ALL_VAL_Msk (0xFFFFFFFFUL << AESIV1_ALL_VAL_Pos)

#define AESIV1_BIT_VAL

#define AESIV1_ALL_VAL_(x) ((x) << AESIV1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIV2          VAL
 *  @access     AES->AESIV2.bit.VAL
 *  @brief      Byte 8-11 of initial vector
 */
#define AESIV2_ALL_VAL_Pos (0)
#define AESIV2_ALL_VAL_Msk (0xFFFFFFFFUL << AESIV2_ALL_VAL_Pos)

#define AESIV2_BIT_VAL

#define AESIV2_ALL_VAL_(x) ((x) << AESIV2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIV3          VAL
 *  @access     AES->AESIV3.bit.VAL
 *  @brief      Byte 12-15 of initial vector
 */
#define AESIV3_ALL_VAL_Pos (0)
#define AESIV3_ALL_VAL_Msk (0xFFFFFFFFUL << AESIV3_ALL_VAL_Pos)

#define AESIV3_BIT_VAL

#define AESIV3_ALL_VAL_(x) ((x) << AESIV3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESKEY0         VAL
 *  @access     AES->AESKEY0.bit.VAL
 *  @brief      Byte 0-3 of key
 */
#define AESKEY0_ALL_VAL_Pos (0)
#define AESKEY0_ALL_VAL_Msk (0xFFFFFFFFUL << AESKEY0_ALL_VAL_Pos)

#define AESKEY0_BIT_VAL

#define AESKEY0_ALL_VAL_(x) ((x) << AESKEY0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESKEY1         VAL
 *  @access     AES->AESKEY1.bit.VAL
 *  @brief      Byte 4-7 of key
 */
#define AESKEY1_ALL_VAL_Pos (0)
#define AESKEY1_ALL_VAL_Msk (0xFFFFFFFFUL << AESKEY1_ALL_VAL_Pos)

#define AESKEY1_BIT_VAL

#define AESKEY1_ALL_VAL_(x) ((x) << AESKEY1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESKEY2         VAL
 *  @access     AES->AESKEY2.bit.VAL
 *  @brief      Byte 8-11 of key
 */
#define AESKEY2_ALL_VAL_Pos (0)
#define AESKEY2_ALL_VAL_Msk (0xFFFFFFFFUL << AESKEY2_ALL_VAL_Pos)

#define AESKEY2_BIT_VAL

#define AESKEY2_ALL_VAL_(x) ((x) << AESKEY2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESKEY3         VAL
 *  @access     AES->AESKEY3.bit.VAL
 *  @brief      Byte 12-15 of key
 */
#define AESKEY3_ALL_VAL_Pos (0)
#define AESKEY3_ALL_VAL_Msk (0xFFFFFFFFUL << AESKEY3_ALL_VAL_Pos)

#define AESKEY3_BIT_VAL

#define AESKEY3_ALL_VAL_(x) ((x) << AESKEY3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESKEY4         VAL
 *  @access     AES->AESKEY4.bit.VAL
 *  @brief      Byte of 16-19 of key
 */
#define AESKEY4_ALL_VAL_Pos (0)
#define AESKEY4_ALL_VAL_Msk (0xFFFFFFFFUL << AESKEY4_ALL_VAL_Pos)

#define AESKEY4_BIT_VAL

#define AESKEY4_ALL_VAL_(x) ((x) << AESKEY4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESKEY5         VAL
 *  @access     AES->AESKEY5.bit.VAL
 *  @brief      Byte 20-23 of key
 */
#define AESKEY5_ALL_VAL_Pos (0)
#define AESKEY5_ALL_VAL_Msk (0xFFFFFFFFUL << AESKEY5_ALL_VAL_Pos)

#define AESKEY5_BIT_VAL

#define AESKEY5_ALL_VAL_(x) ((x) << AESKEY5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESKEY6         VAL
 *  @access     AES->AESKEY6.bit.VAL
 *  @brief      Byte 24-27 of key
 */
#define AESKEY6_ALL_VAL_Pos (0)
#define AESKEY6_ALL_VAL_Msk (0xFFFFFFFFUL << AESKEY6_ALL_VAL_Pos)

#define AESKEY6_BIT_VAL

#define AESKEY6_ALL_VAL_(x) ((x) << AESKEY6_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESKEY7         VAL
 *  @access     AES->AESKEY7.bit.VAL
 *  @brief      Byte 28-31 of key
 */
#define AESKEY7_ALL_VAL_Pos (0)
#define AESKEY7_ALL_VAL_Msk (0xFFFFFFFFUL << AESKEY7_ALL_VAL_Pos)

#define AESKEY7_BIT_VAL

#define AESKEY7_ALL_VAL_(x) ((x) << AESKEY7_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESSTROUT       VAL
 *  @access     AES->AESSTROUT.bit.VAL
 *  @brief      Output message word
 */
#define AESSTROUT_ALL_VAL_Pos (0)
#define AESSTROUT_ALL_VAL_Msk (0xFFFFFFFFUL << AESSTROUT_ALL_VAL_Pos)

#define AESSTROUT_BIT_VAL

#define AESSTROUT_ALL_VAL_(x) ((x) << AESSTROUT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESOV0          VAL
 *  @access     AES->AESOV0.bit.VAL
 *  @brief      Byte 0-3 of output vector
 */
#define AESOV0_ALL_VAL_Pos (0)
#define AESOV0_ALL_VAL_Msk (0xFFFFFFFFUL << AESOV0_ALL_VAL_Pos)

#define AESOV0_BIT_VAL

#define AESOV0_ALL_VAL_(x) ((x) << AESOV0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESOV1          VAL
 *  @access     AES->AESOV1.bit.VAL
 *  @brief      Byte 4-7 of output vector
 */
#define AESOV1_ALL_VAL_Pos (0)
#define AESOV1_ALL_VAL_Msk (0xFFFFFFFFUL << AESOV1_ALL_VAL_Pos)

#define AESOV1_BIT_VAL

#define AESOV1_ALL_VAL_(x) ((x) << AESOV1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESOV2          VAL
 *  @access     AES->AESOV2.bit.VAL
 *  @brief      Byte 8-11 of output vector
 */
#define AESOV2_ALL_VAL_Pos (0)
#define AESOV2_ALL_VAL_Msk (0xFFFFFFFFUL << AESOV2_ALL_VAL_Pos)

#define AESOV2_BIT_VAL

#define AESOV2_ALL_VAL_(x) ((x) << AESOV2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESOV3          VAL
 *  @access     AES->AESOV3.bit.VAL
 *  @brief      Byte 12-15 of output vector
 */
#define AESOV3_ALL_VAL_Pos (0)
#define AESOV3_ALL_VAL_Msk (0xFFFFFFFFUL << AESOV3_ALL_VAL_Pos)

#define AESOV3_BIT_VAL

#define AESOV3_ALL_VAL_(x) ((x) << AESOV3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIF           DONE
 *  @access     AES->AESIF.bit.DONE
 *  @brief      Status of AES operation done interrupt
 */
#define AESIF_ALL_DONE_Pos (0)
#define AESIF_ALL_DONE_Msk (0x1UL << AESIF_ALL_DONE_Pos)

typedef enum
{
    AESIF_BIT_DONE_NOT_OCCUR     = 0,  /*!< AES operation done interrupt not occurred   */
    AESIF_BIT_DONE_OCCUR         = 1,  /*!< AES operation done interrupt occurred       */
} AESIF_BIT_DONE;

#define AESIF_ALL_DONE_NOT_OCCUR     ((0x0UL) << AESIF_ALL_DONE_Pos)
#define AESIF_ALL_DONE_OCCUR         ((0x1UL) << AESIF_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIF           IFIFOFULL
 *  @access     AES->AESIF.bit.IFIFOFULL
 *  @brief      Status of AES input FIFO full interrupt
 */
#define AESIF_ALL_IFIFOFULL_Pos (1)
#define AESIF_ALL_IFIFOFULL_Msk (0x1UL << AESIF_ALL_IFIFOFULL_Pos)

typedef enum
{
    AESIF_BIT_IFIFOFULL_NOT_OCCUR     = 0,  /*!< AES input FIFO full interrupt not occurred   */
    AESIF_BIT_IFIFOFULL_OCCUR         = 1,  /*!< AES input FIFO full interrupt occurred       */
} AESIF_BIT_IFIFOFULL;

#define AESIF_ALL_IFIFOFULL_NOT_OCCUR     ((0x0UL) << AESIF_ALL_IFIFOFULL_Pos)
#define AESIF_ALL_IFIFOFULL_OCCUR         ((0x1UL) << AESIF_ALL_IFIFOFULL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIF           OFIFOEMPTY
 *  @access     AES->AESIF.bit.OFIFOEMPTY
 *  @brief      Status of AES output FIFO empty interrupt
 */
#define AESIF_ALL_OFIFOEMPTY_Pos (2)
#define AESIF_ALL_OFIFOEMPTY_Msk (0x1UL << AESIF_ALL_OFIFOEMPTY_Pos)

typedef enum
{
    AESIF_BIT_OFIFOEMPTY_NOT_OCCUR     = 0,  /*!< AES output FIFO empty interrupt not occurred   */
    AESIF_BIT_OFIFOEMPTY_OCCUR         = 1,  /*!< AES output FIFO empty interrupt occurred       */
} AESIF_BIT_OFIFOEMPTY;

#define AESIF_ALL_OFIFOEMPTY_NOT_OCCUR     ((0x0UL) << AESIF_ALL_OFIFOEMPTY_Pos)
#define AESIF_ALL_OFIFOEMPTY_OCCUR         ((0x1UL) << AESIF_ALL_OFIFOEMPTY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIE           DONE
 *  @access     AES->AESIE.bit.DONE
 *  @brief      Enable of AES operation done interrupt
 */
#define AESIE_ALL_DONE_Pos (0)
#define AESIE_ALL_DONE_Msk (0x1UL << AESIE_ALL_DONE_Pos)

typedef enum
{
    AESIE_BIT_DONE_DISABLE     = 0,  /*!< Disable AES operation done interrupt   */
    AESIE_BIT_DONE_ENABLE      = 1,  /*!< Enable AES operation done interrupt    */
} AESIE_BIT_DONE;

#define AESIE_ALL_DONE_DISABLE     ((0x0UL) << AESIE_ALL_DONE_Pos)
#define AESIE_ALL_DONE_ENABLE      ((0x1UL) << AESIE_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIE           IFIFOFULL
 *  @access     AES->AESIE.bit.IFIFOFULL
 *  @brief      Enable of AES input FIFO full interrupt
 */
#define AESIE_ALL_IFIFOFULL_Pos (1)
#define AESIE_ALL_IFIFOFULL_Msk (0x1UL << AESIE_ALL_IFIFOFULL_Pos)

typedef enum
{
    AESIE_BIT_IFIFOFULL_DISABLE     = 0,  /*!< Disable AES input FIFO full interrupt   */
    AESIE_BIT_IFIFOFULL_ENABLE      = 1,  /*!< Enable AES input FIFO full interrupt    */
} AESIE_BIT_IFIFOFULL;

#define AESIE_ALL_IFIFOFULL_DISABLE     ((0x0UL) << AESIE_ALL_IFIFOFULL_Pos)
#define AESIE_ALL_IFIFOFULL_ENABLE      ((0x1UL) << AESIE_ALL_IFIFOFULL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIE           OFIFOEMPTY
 *  @access     AES->AESIE.bit.OFIFOEMPTY
 *  @brief      Enable AES output FIFO empty interrupt
 */
#define AESIE_ALL_OFIFOEMPTY_Pos (2)
#define AESIE_ALL_OFIFOEMPTY_Msk (0x1UL << AESIE_ALL_OFIFOEMPTY_Pos)

typedef enum
{
    AESIE_BIT_OFIFOEMPTY_DISABLE     = 0,  /*!< Disable AES output FIFO empty interrupt   */
    AESIE_BIT_OFIFOEMPTY_ENABLE      = 1,  /*!< Enable AES output FIFO empty interrupt    */
} AESIE_BIT_OFIFOEMPTY;

#define AESIE_ALL_OFIFOEMPTY_DISABLE     ((0x0UL) << AESIE_ALL_OFIFOEMPTY_Pos)
#define AESIE_ALL_OFIFOEMPTY_ENABLE      ((0x1UL) << AESIE_ALL_OFIFOEMPTY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESRAWIF        DONE
 *  @access     AES->AESRAWIF.bit.DONE
 *  @brief      AES operation done interrupt raw status regardless of mask
 */
#define AESRAWIF_ALL_DONE_Pos (0)
#define AESRAWIF_ALL_DONE_Msk (0x1UL << AESRAWIF_ALL_DONE_Pos)

typedef enum
{
    AESRAWIF_BIT_DONE_NOT_OCCUR     = 0,  /*!< AES operation done interrupt not occurred   */
    AESRAWIF_BIT_DONE_OCCUR         = 1,  /*!< AES operation done interrupt occurred       */
} AESRAWIF_BIT_DONE;

#define AESRAWIF_ALL_DONE_NOT_OCCUR     ((0x0UL) << AESRAWIF_ALL_DONE_Pos)
#define AESRAWIF_ALL_DONE_OCCUR         ((0x1UL) << AESRAWIF_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESRAWIF        IFIFOFULL
 *  @access     AES->AESRAWIF.bit.IFIFOFULL
 *  @brief      AES input FIFO full interrupt raw status regardless of mask
 */
#define AESRAWIF_ALL_IFIFOFULL_Pos (1)
#define AESRAWIF_ALL_IFIFOFULL_Msk (0x1UL << AESRAWIF_ALL_IFIFOFULL_Pos)

typedef enum
{
    AESRAWIF_BIT_IFIFOFULL_NOT_OCCUR     = 0,  /*!< AES no input FIFO full interrupt not occurred   */
    AESRAWIF_BIT_IFIFOFULL_OCCUR         = 1,  /*!< AES no input FIFO full interrupt occurred       */
} AESRAWIF_BIT_IFIFOFULL;

#define AESRAWIF_ALL_IFIFOFULL_NOT_OCCUR     ((0x0UL) << AESRAWIF_ALL_IFIFOFULL_Pos)
#define AESRAWIF_ALL_IFIFOFULL_OCCUR         ((0x1UL) << AESRAWIF_ALL_IFIFOFULL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESRAWIF        OFIFOEMPTY
 *  @access     AES->AESRAWIF.bit.OFIFOEMPTY
 *  @brief      AES output FIFO empty interrupt raw status regardless of mask
 */
#define AESRAWIF_ALL_OFIFOEMPTY_Pos (2)
#define AESRAWIF_ALL_OFIFOEMPTY_Msk (0x1UL << AESRAWIF_ALL_OFIFOEMPTY_Pos)

typedef enum
{
    AESRAWIF_BIT_OFIFOEMPTY_NOT_OCCUR     = 0,  /*!< AES output FIFO empty interrupt not occurred   */
    AESRAWIF_BIT_OFIFOEMPTY_OCCUR         = 1,  /*!< AES output FIFO empty interrupt                */
} AESRAWIF_BIT_OFIFOEMPTY;

#define AESRAWIF_ALL_OFIFOEMPTY_NOT_OCCUR     ((0x0UL) << AESRAWIF_ALL_OFIFOEMPTY_Pos)
#define AESRAWIF_ALL_OFIFOEMPTY_OCCUR         ((0x1UL) << AESRAWIF_ALL_OFIFOEMPTY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIC           DONE
 *  @access     AES->AESIC.bit.DONE
 *  @brief      Clearance of AES operation done interrupt status and raw status
 */
#define AESIC_ALL_DONE_Pos (0)
#define AESIC_ALL_DONE_Msk (0x1UL << AESIC_ALL_DONE_Pos)

typedef enum
{
    AESIC_BIT_DONE_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.                                */
    AESIC_BIT_DONE_CLEAR         = 1,  /*!< Write a 1 clears both AES operation done interrupt status and raw status  
                                            This bit is self-cleared to 0                                              */
} AESIC_BIT_DONE;

#define AESIC_ALL_DONE_NO_EFFECT     ((0x0UL) << AESIC_ALL_DONE_Pos)
#define AESIC_ALL_DONE_CLEAR         ((0x1UL) << AESIC_ALL_DONE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIC           IFIFOFULL
 *  @access     AES->AESIC.bit.IFIFOFULL
 *  @brief      Clearance of AES input FIFO full interrupt status and raw status
 */
#define AESIC_ALL_IFIFOFULL_Pos (1)
#define AESIC_ALL_IFIFOFULL_Msk (0x1UL << AESIC_ALL_IFIFOFULL_Pos)

typedef enum
{
    AESIC_BIT_IFIFOFULL_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.                                 */
    AESIC_BIT_IFIFOFULL_CLEAR         = 1,  /*!< Write a 1 clears both AES input FIFO full interrupt status and raw status  
                                                 This bit is self-cleared to 0                                               */
} AESIC_BIT_IFIFOFULL;

#define AESIC_ALL_IFIFOFULL_NO_EFFECT     ((0x0UL) << AESIC_ALL_IFIFOFULL_Pos)
#define AESIC_ALL_IFIFOFULL_CLEAR         ((0x1UL) << AESIC_ALL_IFIFOFULL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   AES             AESIC           OFIFOEMPTY
 *  @access     AES->AESIC.bit.OFIFOEMPTY
 *  @brief      clearance of AES output FIFO empty interrupt status and raw status
 */
#define AESIC_ALL_OFIFOEMPTY_Pos (2)
#define AESIC_ALL_OFIFOEMPTY_Msk (0x1UL << AESIC_ALL_OFIFOEMPTY_Pos)

typedef enum
{
    AESIC_BIT_OFIFOEMPTY_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.                                   */
    AESIC_BIT_OFIFOEMPTY_CLEAR         = 1,  /*!< Write a 1 clears both AES output FIFO empty interrupt status and raw status  
                                                  This bit is self-cleared to 0                                                 */
} AESIC_BIT_OFIFOEMPTY;

#define AESIC_ALL_OFIFOEMPTY_NO_EFFECT     ((0x0UL) << AESIC_ALL_OFIFOEMPTY_Pos)
#define AESIC_ALL_OFIFOEMPTY_CLEAR         ((0x1UL) << AESIC_ALL_OFIFOEMPTY_Pos)



/********************************************************************************
*
* Module Name     FLASH
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHCTL        COMMAND
 *  @access     FLASH->FLASHCTL.bit.COMMAND
 *  @brief      Flash command
 */
#define FLASHCTL_ALL_COMMAND_Pos (0)
#define FLASHCTL_ALL_COMMAND_Msk (0xFUL << FLASHCTL_ALL_COMMAND_Pos)

typedef enum
{
    FLASHCTL_BIT_COMMAND_POWER_UP        = 0,  /*!< Power up                     */
    FLASHCTL_BIT_COMMAND_READ            = 1,  /*!< Read                         */
    FLASHCTL_BIT_COMMAND_VREAD0          = 2,  /*!< Verify read 0                */
    FLASHCTL_BIT_COMMAND_VREAD1          = 3,  /*!< Verify read 1                */
    FLASHCTL_BIT_COMMAND_PROG_WD_PRE     = 4,  /*!< Prepare Program word         */
    FLASHCTL_BIT_COMMAND_PROG_WD_NOM     = 5,  /*!< Program word                 */
    FLASHCTL_BIT_COMMAND_PROG_PG_PRE     = 6,  /*!< Prepare Program page words   */
    FLASHCTL_BIT_COMMAND_PROG_PG_NOM     = 7,  /*!< Program page words           */
    FLASHCTL_BIT_COMMAND_ERASE_SEC       = 8,  /*!< Erase sector                 */
    FLASHCTL_BIT_COMMAND_ERASE_BLOCK     = 9,  /*!< Erase block                  */
    FLASHCTL_BIT_COMMAND_ERASE_CHIP      = 10,  /*!< Erase chip                   */
    FLASHCTL_BIT_COMMAND_RECALL_READ     = 13,  /*!< Recall read                  */
    FLASHCTL_BIT_COMMAND_SET_CONFIG      = 14,  /*!< Set configuration            */
    FLASHCTL_BIT_COMMAND_POWER_DOWN      = 15,  /*!< Powe down                    */
} FLASHCTL_BIT_COMMAND;

#define FLASHCTL_ALL_COMMAND_POWER_UP        ((0x00UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_READ            ((0x01UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_VREAD0          ((0x02UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_VREAD1          ((0x03UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_PROG_WD_PRE     ((0x04UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_PROG_WD_NOM     ((0x05UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_PROG_PG_PRE     ((0x06UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_PROG_PG_NOM     ((0x07UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_ERASE_SEC       ((0x08UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_ERASE_BLOCK     ((0x09UL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_ERASE_CHIP      ((0x0AUL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_RECALL_READ     ((0x0DUL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_SET_CONFIG      ((0x0EUL) << FLASHCTL_ALL_COMMAND_Pos)
#define FLASHCTL_ALL_COMMAND_POWER_DOWN      ((0x0FUL) << FLASHCTL_ALL_COMMAND_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHCTL        DATAACCEPT
 *  @access     FLASH->FLASHCTL.bit.DATAACCEPT
 *  @brief      FLASHDIN cannot be changed when this bit is 0
 */
#define FLASHCTL_ALL_DATAACCEPT_Pos (4)
#define FLASHCTL_ALL_DATAACCEPT_Msk (0x1UL << FLASHCTL_ALL_DATAACCEPT_Pos)

#define FLASHCTL_BIT_DATAACCEPT

#define FLASHCTL_ALL_DATAACCEPT_(x) ((x) << FLASHCTL_ALL_DATAACCEPT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHCTL        EXECUTION
 *  @access     FLASH->FLASHCTL.bit.EXECUTION
 *  @brief      Command is in execution
 */
#define FLASHCTL_ALL_EXECUTION_Pos (5)
#define FLASHCTL_ALL_EXECUTION_Msk (0x1UL << FLASHCTL_ALL_EXECUTION_Pos)

#define FLASHCTL_BIT_EXECUTION

#define FLASHCTL_ALL_EXECUTION_(x) ((x) << FLASHCTL_ALL_EXECUTION_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHCTL        XIPEN
 *  @access     FLASH->FLASHCTL.bit.XIPEN
 *  @brief      XIP module enable
 */
#define FLASHCTL_ALL_XIPEN_Pos (6)
#define FLASHCTL_ALL_XIPEN_Msk (0x1UL << FLASHCTL_ALL_XIPEN_Pos)

typedef enum
{
    FLASHCTL_BIT_XIPEN_DISABLE     = 0,  /*!< Disable XIP module   */
    FLASHCTL_BIT_XIPEN_ENABLE      = 1,  /*!< Enable XIP module    */
} FLASHCTL_BIT_XIPEN;

#define FLASHCTL_ALL_XIPEN_DISABLE     ((0x0UL) << FLASHCTL_ALL_XIPEN_Pos)
#define FLASHCTL_ALL_XIPEN_ENABLE      ((0x1UL) << FLASHCTL_ALL_XIPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHADDR       VAL
 *  @access     FLASH->FLASHADDR.bit.VAL
 *  @brief      Flash address
 */
#define FLASHADDR_ALL_VAL_Pos (0)
#define FLASHADDR_ALL_VAL_Msk (0xFFFFFFFFUL << FLASHADDR_ALL_VAL_Pos)

#define FLASHADDR_BIT_VAL

#define FLASHADDR_ALL_VAL_(x) ((x) << FLASHADDR_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHDIN        FLASHDIN
 *  @access     FLASH->FLASHDIN.bit.FLASHDIN
 *  @brief      Flash input data
 */
#define FLASHDIN_ALL_FLASHDIN_Pos (0)
#define FLASHDIN_ALL_FLASHDIN_Msk (0xFFFFFFFFUL << FLASHDIN_ALL_FLASHDIN_Pos)

#define FLASHDIN_BIT_FLASHDIN

#define FLASHDIN_ALL_FLASHDIN_(x) ((x) << FLASHDIN_ALL_FLASHDIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHDOUT       FLASHDOUT
 *  @access     FLASH->FLASHDOUT.bit.FLASHDOUT
 *  @brief      Flash output data
 */
#define FLASHDOUT_ALL_FLASHDOUT_Pos (0)
#define FLASHDOUT_ALL_FLASHDOUT_Msk (0xFFFFFFFFUL << FLASHDOUT_ALL_FLASHDOUT_Pos)

#define FLASHDOUT_BIT_FLASHDOUT

#define FLASHDOUT_ALL_FLASHDOUT_(x) ((x) << FLASHDOUT_ALL_FLASHDOUT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING0    TAEPH
 *  @access     FLASH->FLASHTIMING0.bit.TAEPH
 *  @brief      
 */
#define FLASHTIMING0_ALL_TAEPH_Pos (0)
#define FLASHTIMING0_ALL_TAEPH_Msk (0x3FUL << FLASHTIMING0_ALL_TAEPH_Pos)

#define FLASHTIMING0_BIT_TAEPH

#define FLASHTIMING0_ALL_TAEPH_(x) ((x) << FLASHTIMING0_ALL_TAEPH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING0    TAA
 *  @access     FLASH->FLASHTIMING0.bit.TAA
 *  @brief      
 */
#define FLASHTIMING0_ALL_TAA_Pos (6)
#define FLASHTIMING0_ALL_TAA_Msk (0x3FUL << FLASHTIMING0_ALL_TAA_Pos)

#define FLASHTIMING0_BIT_TAA

#define FLASHTIMING0_ALL_TAA_(x) ((x) << FLASHTIMING0_ALL_TAA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING0    TAS
 *  @access     FLASH->FLASHTIMING0.bit.TAS
 *  @brief      
 */
#define FLASHTIMING0_ALL_TAS_Pos (12)
#define FLASHTIMING0_ALL_TAS_Msk (0x3FUL << FLASHTIMING0_ALL_TAS_Pos)

#define FLASHTIMING0_BIT_TAS

#define FLASHTIMING0_ALL_TAS_(x) ((x) << FLASHTIMING0_ALL_TAS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING0    TNVSSEC
 *  @access     FLASH->FLASHTIMING0.bit.TNVSSEC
 *  @brief      
 */
#define FLASHTIMING0_ALL_TNVSSEC_Pos (18)
#define FLASHTIMING0_ALL_TNVSSEC_Msk (0x3FUL << FLASHTIMING0_ALL_TNVSSEC_Pos)

#define FLASHTIMING0_BIT_TNVSSEC

#define FLASHTIMING0_ALL_TNVSSEC_(x) ((x) << FLASHTIMING0_ALL_TNVSSEC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING0    TNVSCHIP
 *  @access     FLASH->FLASHTIMING0.bit.TNVSCHIP
 *  @brief      
 */
#define FLASHTIMING0_ALL_TNVSCHIP_Pos (24)
#define FLASHTIMING0_ALL_TNVSCHIP_Msk (0x3FUL << FLASHTIMING0_ALL_TNVSCHIP_Pos)

#define FLASHTIMING0_BIT_TNVSCHIP

#define FLASHTIMING0_ALL_TNVSCHIP_(x) ((x) << FLASHTIMING0_ALL_TNVSCHIP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING1    TSSE
 *  @access     FLASH->FLASHTIMING1.bit.TSSE
 *  @brief      Sector erase
 */
#define FLASHTIMING1_ALL_TSSE_Pos (0)
#define FLASHTIMING1_ALL_TSSE_Msk (0x3FUL << FLASHTIMING1_ALL_TSSE_Pos)

#define FLASHTIMING1_BIT_TSSE

#define FLASHTIMING1_ALL_TSSE_(x) ((x) << FLASHTIMING1_ALL_TSSE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING1    TSBE
 *  @access     FLASH->FLASHTIMING1.bit.TSBE
 *  @brief      Block erase
 */
#define FLASHTIMING1_ALL_TSBE_Pos (6)
#define FLASHTIMING1_ALL_TSBE_Msk (0x3FUL << FLASHTIMING1_ALL_TSBE_Pos)

#define FLASHTIMING1_BIT_TSBE

#define FLASHTIMING1_ALL_TSBE_(x) ((x) << FLASHTIMING1_ALL_TSBE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING1    TUS
 *  @access     FLASH->FLASHTIMING1.bit.TUS
 *  @brief      
 */
#define FLASHTIMING1_ALL_TUS_Pos (12)
#define FLASHTIMING1_ALL_TUS_Msk (0x1FFUL << FLASHTIMING1_ALL_TUS_Pos)

#define FLASHTIMING1_BIT_TUS

#define FLASHTIMING1_ALL_TUS_(x) ((x) << FLASHTIMING1_ALL_TUS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING1    TMS
 *  @access     FLASH->FLASHTIMING1.bit.TMS
 *  @brief      
 */
#define FLASHTIMING1_ALL_TMS_Pos (21)
#define FLASHTIMING1_ALL_TMS_Msk (0x7FFUL << FLASHTIMING1_ALL_TMS_Pos)

#define FLASHTIMING1_BIT_TMS

#define FLASHTIMING1_ALL_TMS_(x) ((x) << FLASHTIMING1_ALL_TMS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING2    TSCE
 *  @access     FLASH->FLASHTIMING2.bit.TSCE
 *  @brief      
 */
#define FLASHTIMING2_ALL_TSCE_Pos (0)
#define FLASHTIMING2_ALL_TSCE_Msk (0x3FUL << FLASHTIMING2_ALL_TSCE_Pos)

#define FLASHTIMING2_BIT_TSCE

#define FLASHTIMING2_ALL_TSCE_(x) ((x) << FLASHTIMING2_ALL_TSCE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING2    TPGS
 *  @access     FLASH->FLASHTIMING2.bit.TPGS
 *  @brief      
 */
#define FLASHTIMING2_ALL_TPGS_Pos (6)
#define FLASHTIMING2_ALL_TPGS_Msk (0x3FUL << FLASHTIMING2_ALL_TPGS_Pos)

#define FLASHTIMING2_BIT_TPGS

#define FLASHTIMING2_ALL_TPGS_(x) ((x) << FLASHTIMING2_ALL_TPGS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING2    TPROG
 *  @access     FLASH->FLASHTIMING2.bit.TPROG
 *  @brief      
 */
#define FLASHTIMING2_ALL_TPROG_Pos (12)
#define FLASHTIMING2_ALL_TPROG_Msk (0x3FUL << FLASHTIMING2_ALL_TPROG_Pos)

#define FLASHTIMING2_BIT_TPROG

#define FLASHTIMING2_ALL_TPROG_(x) ((x) << FLASHTIMING2_ALL_TPROG_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING2    TPGH
 *  @access     FLASH->FLASHTIMING2.bit.TPGH
 *  @brief      
 */
#define FLASHTIMING2_ALL_TPGH_Pos (18)
#define FLASHTIMING2_ALL_TPGH_Msk (0x3FUL << FLASHTIMING2_ALL_TPGH_Pos)

#define FLASHTIMING2_BIT_TPGH

#define FLASHTIMING2_ALL_TPGH_(x) ((x) << FLASHTIMING2_ALL_TPGH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING2    TRCVPROG
 *  @access     FLASH->FLASHTIMING2.bit.TRCVPROG
 *  @brief      
 */
#define FLASHTIMING2_ALL_TRCVPROG_Pos (24)
#define FLASHTIMING2_ALL_TRCVPROG_Msk (0x3FUL << FLASHTIMING2_ALL_TRCVPROG_Pos)

#define FLASHTIMING2_BIT_TRCVPROG

#define FLASHTIMING2_ALL_TRCVPROG_(x) ((x) << FLASHTIMING2_ALL_TRCVPROG_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING3    TPREPROG
 *  @access     FLASH->FLASHTIMING3.bit.TPREPROG
 *  @brief      
 */
#define FLASHTIMING3_ALL_TPREPROG_Pos (0)
#define FLASHTIMING3_ALL_TPREPROG_Msk (0x3FUL << FLASHTIMING3_ALL_TPREPROG_Pos)

#define FLASHTIMING3_BIT_TPREPROG

#define FLASHTIMING3_ALL_TPREPROG_(x) ((x) << FLASHTIMING3_ALL_TPREPROG_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING3    TAPS
 *  @access     FLASH->FLASHTIMING3.bit.TAPS
 *  @brief      
 */
#define FLASHTIMING3_ALL_TAPS_Pos (6)
#define FLASHTIMING3_ALL_TAPS_Msk (0x3FUL << FLASHTIMING3_ALL_TAPS_Pos)

#define FLASHTIMING3_BIT_TAPS

#define FLASHTIMING3_ALL_TAPS_(x) ((x) << FLASHTIMING3_ALL_TAPS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING3    TAAR
 *  @access     FLASH->FLASHTIMING3.bit.TAAR
 *  @brief      
 */
#define FLASHTIMING3_ALL_TAAR_Pos (12)
#define FLASHTIMING3_ALL_TAAR_Msk (0x3FUL << FLASHTIMING3_ALL_TAAR_Pos)

#define FLASHTIMING3_BIT_TAAR

#define FLASHTIMING3_ALL_TAAR_(x) ((x) << FLASHTIMING3_ALL_TAAR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING3    TCFS
 *  @access     FLASH->FLASHTIMING3.bit.TCFS
 *  @brief      
 */
#define FLASHTIMING3_ALL_TCFS_Pos (18)
#define FLASHTIMING3_ALL_TCFS_Msk (0x3FUL << FLASHTIMING3_ALL_TCFS_Pos)

#define FLASHTIMING3_BIT_TCFS

#define FLASHTIMING3_ALL_TCFS_(x) ((x) << FLASHTIMING3_ALL_TCFS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING3    TCONFEN
 *  @access     FLASH->FLASHTIMING3.bit.TCONFEN
 *  @brief      
 */
#define FLASHTIMING3_ALL_TCONFEN_Pos (24)
#define FLASHTIMING3_ALL_TCONFEN_Msk (0x3FUL << FLASHTIMING3_ALL_TCONFEN_Pos)

#define FLASHTIMING3_BIT_TCONFEN

#define FLASHTIMING3_ALL_TCONFEN_(x) ((x) << FLASHTIMING3_ALL_TCONFEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING4    TDS
 *  @access     FLASH->FLASHTIMING4.bit.TDS
 *  @brief      
 */
#define FLASHTIMING4_ALL_TDS_Pos (0)
#define FLASHTIMING4_ALL_TDS_Msk (0x3FUL << FLASHTIMING4_ALL_TDS_Pos)

#define FLASHTIMING4_BIT_TDS

#define FLASHTIMING4_ALL_TDS_(x) ((x) << FLASHTIMING4_ALL_TDS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING4    TRW
 *  @access     FLASH->FLASHTIMING4.bit.TRW
 *  @brief      
 */
#define FLASHTIMING4_ALL_TRW_Pos (6)
#define FLASHTIMING4_ALL_TRW_Msk (0x3FUL << FLASHTIMING4_ALL_TRW_Pos)

#define FLASHTIMING4_BIT_TRW

#define FLASHTIMING4_ALL_TRW_(x) ((x) << FLASHTIMING4_ALL_TRW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING4    TCFH
 *  @access     FLASH->FLASHTIMING4.bit.TCFH
 *  @brief      
 */
#define FLASHTIMING4_ALL_TCFH_Pos (12)
#define FLASHTIMING4_ALL_TCFH_Msk (0x3FUL << FLASHTIMING4_ALL_TCFH_Pos)

#define FLASHTIMING4_BIT_TCFH

#define FLASHTIMING4_ALL_TCFH_(x) ((x) << FLASHTIMING4_ALL_TCFH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING4    TCFL
 *  @access     FLASH->FLASHTIMING4.bit.TCFL
 *  @brief      
 */
#define FLASHTIMING4_ALL_TCFL_Pos (18)
#define FLASHTIMING4_ALL_TCFL_Msk (0x3FUL << FLASHTIMING4_ALL_TCFL_Pos)

#define FLASHTIMING4_BIT_TCFL

#define FLASHTIMING4_ALL_TCFL_(x) ((x) << FLASHTIMING4_ALL_TCFL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING4    TRCVERASE
 *  @access     FLASH->FLASHTIMING4.bit.TRCVERASE
 *  @brief      
 */
#define FLASHTIMING4_ALL_TRCVERASE_Pos (24)
#define FLASHTIMING4_ALL_TRCVERASE_Msk (0x7FUL << FLASHTIMING4_ALL_TRCVERASE_Pos)

#define FLASHTIMING4_BIT_TRCVERASE

#define FLASHTIMING4_ALL_TRCVERASE_(x) ((x) << FLASHTIMING4_ALL_TRCVERASE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING5    TAAVR
 *  @access     FLASH->FLASHTIMING5.bit.TAAVR
 *  @brief      
 */
#define FLASHTIMING5_ALL_TAAVR_Pos (0)
#define FLASHTIMING5_ALL_TAAVR_Msk (0x3FUL << FLASHTIMING5_ALL_TAAVR_Pos)

#define FLASHTIMING5_BIT_TAAVR

#define FLASHTIMING5_ALL_TAAVR_(x) ((x) << FLASHTIMING5_ALL_TAAVR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING5    TRSRECALL
 *  @access     FLASH->FLASHTIMING5.bit.TRSRECALL
 *  @brief      
 */
#define FLASHTIMING5_ALL_TRSRECALL_Pos (6)
#define FLASHTIMING5_ALL_TRSRECALL_Msk (0x3FUL << FLASHTIMING5_ALL_TRSRECALL_Pos)

#define FLASHTIMING5_BIT_TRSRECALL

#define FLASHTIMING5_ALL_TRSRECALL_(x) ((x) << FLASHTIMING5_ALL_TRSRECALL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHTIMING5    TRSVREAD
 *  @access     FLASH->FLASHTIMING5.bit.TRSVREAD
 *  @brief      
 */
#define FLASHTIMING5_ALL_TRSVREAD_Pos (12)
#define FLASHTIMING5_ALL_TRSVREAD_Msk (0x3FUL << FLASHTIMING5_ALL_TRSVREAD_Pos)

#define FLASHTIMING5_BIT_TRSVREAD

#define FLASHTIMING5_ALL_TRSVREAD_(x) ((x) << FLASHTIMING5_ALL_TRSVREAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT0
 *  @access     FLASH->FLASHWP0.bit.UNIT0
 *  @brief      Write protection for flash unit 0
 */
#define FLASHWP0_ALL_UNIT0_Pos (0)
#define FLASHWP0_ALL_UNIT0_Msk (0x1UL << FLASHWP0_ALL_UNIT0_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT0_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT0_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT0;

#define FLASHWP0_ALL_UNIT0_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT0_Pos)
#define FLASHWP0_ALL_UNIT0_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT1
 *  @access     FLASH->FLASHWP0.bit.UNIT1
 *  @brief      Write protection for flash unit 1
 */
#define FLASHWP0_ALL_UNIT1_Pos (1)
#define FLASHWP0_ALL_UNIT1_Msk (0x1UL << FLASHWP0_ALL_UNIT1_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT1_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT1_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT1;

#define FLASHWP0_ALL_UNIT1_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT1_Pos)
#define FLASHWP0_ALL_UNIT1_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT2
 *  @access     FLASH->FLASHWP0.bit.UNIT2
 *  @brief      Write protection for flash unit 2
 */
#define FLASHWP0_ALL_UNIT2_Pos (2)
#define FLASHWP0_ALL_UNIT2_Msk (0x1UL << FLASHWP0_ALL_UNIT2_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT2_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT2_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT2;

#define FLASHWP0_ALL_UNIT2_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT2_Pos)
#define FLASHWP0_ALL_UNIT2_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT3
 *  @access     FLASH->FLASHWP0.bit.UNIT3
 *  @brief      Write protection for flash unit 3
 */
#define FLASHWP0_ALL_UNIT3_Pos (3)
#define FLASHWP0_ALL_UNIT3_Msk (0x1UL << FLASHWP0_ALL_UNIT3_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT3_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT3_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT3;

#define FLASHWP0_ALL_UNIT3_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT3_Pos)
#define FLASHWP0_ALL_UNIT3_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT4
 *  @access     FLASH->FLASHWP0.bit.UNIT4
 *  @brief      Write protection for flash unit 4
 */
#define FLASHWP0_ALL_UNIT4_Pos (4)
#define FLASHWP0_ALL_UNIT4_Msk (0x1UL << FLASHWP0_ALL_UNIT4_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT4_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT4_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT4;

#define FLASHWP0_ALL_UNIT4_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT4_Pos)
#define FLASHWP0_ALL_UNIT4_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT5
 *  @access     FLASH->FLASHWP0.bit.UNIT5
 *  @brief      Write protection for flash unit 5
 */
#define FLASHWP0_ALL_UNIT5_Pos (5)
#define FLASHWP0_ALL_UNIT5_Msk (0x1UL << FLASHWP0_ALL_UNIT5_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT5_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT5_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT5;

#define FLASHWP0_ALL_UNIT5_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT5_Pos)
#define FLASHWP0_ALL_UNIT5_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT6
 *  @access     FLASH->FLASHWP0.bit.UNIT6
 *  @brief      Write protection for flash unit 6
 */
#define FLASHWP0_ALL_UNIT6_Pos (6)
#define FLASHWP0_ALL_UNIT6_Msk (0x1UL << FLASHWP0_ALL_UNIT6_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT6_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT6_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT6;

#define FLASHWP0_ALL_UNIT6_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT6_Pos)
#define FLASHWP0_ALL_UNIT6_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT7
 *  @access     FLASH->FLASHWP0.bit.UNIT7
 *  @brief      Write protection for flash unit 7
 */
#define FLASHWP0_ALL_UNIT7_Pos (7)
#define FLASHWP0_ALL_UNIT7_Msk (0x1UL << FLASHWP0_ALL_UNIT7_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT7_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT7_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT7;

#define FLASHWP0_ALL_UNIT7_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT7_Pos)
#define FLASHWP0_ALL_UNIT7_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT8
 *  @access     FLASH->FLASHWP0.bit.UNIT8
 *  @brief      Write protection for flash unit 8
 */
#define FLASHWP0_ALL_UNIT8_Pos (8)
#define FLASHWP0_ALL_UNIT8_Msk (0x1UL << FLASHWP0_ALL_UNIT8_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT8_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT8_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT8;

#define FLASHWP0_ALL_UNIT8_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT8_Pos)
#define FLASHWP0_ALL_UNIT8_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT9
 *  @access     FLASH->FLASHWP0.bit.UNIT9
 *  @brief      Write protection for flash unit 9
 */
#define FLASHWP0_ALL_UNIT9_Pos (9)
#define FLASHWP0_ALL_UNIT9_Msk (0x1UL << FLASHWP0_ALL_UNIT9_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT9_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT9_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT9;

#define FLASHWP0_ALL_UNIT9_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT9_Pos)
#define FLASHWP0_ALL_UNIT9_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT10
 *  @access     FLASH->FLASHWP0.bit.UNIT10
 *  @brief      Write protection for flash unit 10
 */
#define FLASHWP0_ALL_UNIT10_Pos (10)
#define FLASHWP0_ALL_UNIT10_Msk (0x1UL << FLASHWP0_ALL_UNIT10_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT10_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT10_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT10;

#define FLASHWP0_ALL_UNIT10_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT10_Pos)
#define FLASHWP0_ALL_UNIT10_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT11
 *  @access     FLASH->FLASHWP0.bit.UNIT11
 *  @brief      Write protection for flash unit 11
 */
#define FLASHWP0_ALL_UNIT11_Pos (11)
#define FLASHWP0_ALL_UNIT11_Msk (0x1UL << FLASHWP0_ALL_UNIT11_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT11_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT11_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT11;

#define FLASHWP0_ALL_UNIT11_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT11_Pos)
#define FLASHWP0_ALL_UNIT11_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT12
 *  @access     FLASH->FLASHWP0.bit.UNIT12
 *  @brief      Write protection for flash unit 12
 */
#define FLASHWP0_ALL_UNIT12_Pos (12)
#define FLASHWP0_ALL_UNIT12_Msk (0x1UL << FLASHWP0_ALL_UNIT12_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT12_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT12_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT12;

#define FLASHWP0_ALL_UNIT12_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT12_Pos)
#define FLASHWP0_ALL_UNIT12_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT13
 *  @access     FLASH->FLASHWP0.bit.UNIT13
 *  @brief      Write protection for flash unit 13
 */
#define FLASHWP0_ALL_UNIT13_Pos (13)
#define FLASHWP0_ALL_UNIT13_Msk (0x1UL << FLASHWP0_ALL_UNIT13_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT13_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT13_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT13;

#define FLASHWP0_ALL_UNIT13_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT13_Pos)
#define FLASHWP0_ALL_UNIT13_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT14
 *  @access     FLASH->FLASHWP0.bit.UNIT14
 *  @brief      Write protection for flash unit 14
 */
#define FLASHWP0_ALL_UNIT14_Pos (14)
#define FLASHWP0_ALL_UNIT14_Msk (0x1UL << FLASHWP0_ALL_UNIT14_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT14_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT14_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT14;

#define FLASHWP0_ALL_UNIT14_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT14_Pos)
#define FLASHWP0_ALL_UNIT14_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT15
 *  @access     FLASH->FLASHWP0.bit.UNIT15
 *  @brief      Write protection for flash unit 15
 */
#define FLASHWP0_ALL_UNIT15_Pos (15)
#define FLASHWP0_ALL_UNIT15_Msk (0x1UL << FLASHWP0_ALL_UNIT15_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT15_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT15_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT15;

#define FLASHWP0_ALL_UNIT15_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT15_Pos)
#define FLASHWP0_ALL_UNIT15_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT16
 *  @access     FLASH->FLASHWP0.bit.UNIT16
 *  @brief      Write protection for flash unit 16
 */
#define FLASHWP0_ALL_UNIT16_Pos (16)
#define FLASHWP0_ALL_UNIT16_Msk (0x1UL << FLASHWP0_ALL_UNIT16_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT16_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT16_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT16;

#define FLASHWP0_ALL_UNIT16_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT16_Pos)
#define FLASHWP0_ALL_UNIT16_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT16_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT17
 *  @access     FLASH->FLASHWP0.bit.UNIT17
 *  @brief      Write protection for flash unit 17
 */
#define FLASHWP0_ALL_UNIT17_Pos (17)
#define FLASHWP0_ALL_UNIT17_Msk (0x1UL << FLASHWP0_ALL_UNIT17_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT17_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT17_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT17;

#define FLASHWP0_ALL_UNIT17_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT17_Pos)
#define FLASHWP0_ALL_UNIT17_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT17_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT18
 *  @access     FLASH->FLASHWP0.bit.UNIT18
 *  @brief      Write protection for flash unit 18
 */
#define FLASHWP0_ALL_UNIT18_Pos (18)
#define FLASHWP0_ALL_UNIT18_Msk (0x1UL << FLASHWP0_ALL_UNIT18_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT18_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT18_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT18;

#define FLASHWP0_ALL_UNIT18_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT18_Pos)
#define FLASHWP0_ALL_UNIT18_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT18_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT19
 *  @access     FLASH->FLASHWP0.bit.UNIT19
 *  @brief      Write protection for flash unit 19
 */
#define FLASHWP0_ALL_UNIT19_Pos (19)
#define FLASHWP0_ALL_UNIT19_Msk (0x1UL << FLASHWP0_ALL_UNIT19_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT19_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT19_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT19;

#define FLASHWP0_ALL_UNIT19_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT19_Pos)
#define FLASHWP0_ALL_UNIT19_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT19_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT20
 *  @access     FLASH->FLASHWP0.bit.UNIT20
 *  @brief      Write protection for flash unit 20
 */
#define FLASHWP0_ALL_UNIT20_Pos (20)
#define FLASHWP0_ALL_UNIT20_Msk (0x1UL << FLASHWP0_ALL_UNIT20_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT20_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT20_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT20;

#define FLASHWP0_ALL_UNIT20_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT20_Pos)
#define FLASHWP0_ALL_UNIT20_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT20_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT21
 *  @access     FLASH->FLASHWP0.bit.UNIT21
 *  @brief      Write protection for flash unit 21
 */
#define FLASHWP0_ALL_UNIT21_Pos (21)
#define FLASHWP0_ALL_UNIT21_Msk (0x1UL << FLASHWP0_ALL_UNIT21_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT21_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT21_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT21;

#define FLASHWP0_ALL_UNIT21_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT21_Pos)
#define FLASHWP0_ALL_UNIT21_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT21_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT22
 *  @access     FLASH->FLASHWP0.bit.UNIT22
 *  @brief      Write protection for flash unit 22
 */
#define FLASHWP0_ALL_UNIT22_Pos (22)
#define FLASHWP0_ALL_UNIT22_Msk (0x1UL << FLASHWP0_ALL_UNIT22_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT22_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT22_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT22;

#define FLASHWP0_ALL_UNIT22_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT22_Pos)
#define FLASHWP0_ALL_UNIT22_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT22_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT23
 *  @access     FLASH->FLASHWP0.bit.UNIT23
 *  @brief      Write protection for flash unit 23
 */
#define FLASHWP0_ALL_UNIT23_Pos (23)
#define FLASHWP0_ALL_UNIT23_Msk (0x1UL << FLASHWP0_ALL_UNIT23_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT23_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT23_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT23;

#define FLASHWP0_ALL_UNIT23_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT23_Pos)
#define FLASHWP0_ALL_UNIT23_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT23_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT24
 *  @access     FLASH->FLASHWP0.bit.UNIT24
 *  @brief      Write protection for flash unit 24
 */
#define FLASHWP0_ALL_UNIT24_Pos (24)
#define FLASHWP0_ALL_UNIT24_Msk (0x1UL << FLASHWP0_ALL_UNIT24_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT24_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT24_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT24;

#define FLASHWP0_ALL_UNIT24_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT24_Pos)
#define FLASHWP0_ALL_UNIT24_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT24_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT25
 *  @access     FLASH->FLASHWP0.bit.UNIT25
 *  @brief      Write protection for flash unit 25
 */
#define FLASHWP0_ALL_UNIT25_Pos (25)
#define FLASHWP0_ALL_UNIT25_Msk (0x1UL << FLASHWP0_ALL_UNIT25_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT25_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT25_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT25;

#define FLASHWP0_ALL_UNIT25_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT25_Pos)
#define FLASHWP0_ALL_UNIT25_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT25_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT26
 *  @access     FLASH->FLASHWP0.bit.UNIT26
 *  @brief      Write protection for flash unit 26
 */
#define FLASHWP0_ALL_UNIT26_Pos (26)
#define FLASHWP0_ALL_UNIT26_Msk (0x1UL << FLASHWP0_ALL_UNIT26_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT26_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT26_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT26;

#define FLASHWP0_ALL_UNIT26_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT26_Pos)
#define FLASHWP0_ALL_UNIT26_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT26_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT27
 *  @access     FLASH->FLASHWP0.bit.UNIT27
 *  @brief      Write protection for flash unit 27
 */
#define FLASHWP0_ALL_UNIT27_Pos (27)
#define FLASHWP0_ALL_UNIT27_Msk (0x1UL << FLASHWP0_ALL_UNIT27_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT27_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT27_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT27;

#define FLASHWP0_ALL_UNIT27_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT27_Pos)
#define FLASHWP0_ALL_UNIT27_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT27_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT28
 *  @access     FLASH->FLASHWP0.bit.UNIT28
 *  @brief      Write protection for flash unit 28
 */
#define FLASHWP0_ALL_UNIT28_Pos (28)
#define FLASHWP0_ALL_UNIT28_Msk (0x1UL << FLASHWP0_ALL_UNIT28_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT28_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT28_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT28;

#define FLASHWP0_ALL_UNIT28_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT28_Pos)
#define FLASHWP0_ALL_UNIT28_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT28_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT29
 *  @access     FLASH->FLASHWP0.bit.UNIT29
 *  @brief      Write protection for flash unit 29
 */
#define FLASHWP0_ALL_UNIT29_Pos (29)
#define FLASHWP0_ALL_UNIT29_Msk (0x1UL << FLASHWP0_ALL_UNIT29_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT29_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT29_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT29;

#define FLASHWP0_ALL_UNIT29_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT29_Pos)
#define FLASHWP0_ALL_UNIT29_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT29_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT30
 *  @access     FLASH->FLASHWP0.bit.UNIT30
 *  @brief      Write protection for flash unit 30
 */
#define FLASHWP0_ALL_UNIT30_Pos (30)
#define FLASHWP0_ALL_UNIT30_Msk (0x1UL << FLASHWP0_ALL_UNIT30_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT30_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT30_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT30;

#define FLASHWP0_ALL_UNIT30_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT30_Pos)
#define FLASHWP0_ALL_UNIT30_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT30_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP0        UNIT31
 *  @access     FLASH->FLASHWP0.bit.UNIT31
 *  @brief      Write protection for flash unit 31
 */
#define FLASHWP0_ALL_UNIT31_Pos (31)
#define FLASHWP0_ALL_UNIT31_Msk (0x1UL << FLASHWP0_ALL_UNIT31_Pos)

typedef enum
{
    FLASHWP0_BIT_UNIT31_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP0_BIT_UNIT31_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP0_BIT_UNIT31;

#define FLASHWP0_ALL_UNIT31_UNPROTECT     ((0x0UL) << FLASHWP0_ALL_UNIT31_Pos)
#define FLASHWP0_ALL_UNIT31_PROTECT       ((0x1UL) << FLASHWP0_ALL_UNIT31_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT32
 *  @access     FLASH->FLASHWP1.bit.UNIT32
 *  @brief      Write protection for flash unit 32
 */
#define FLASHWP1_ALL_UNIT32_Pos (0)
#define FLASHWP1_ALL_UNIT32_Msk (0x1UL << FLASHWP1_ALL_UNIT32_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT32_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT32_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT32;

#define FLASHWP1_ALL_UNIT32_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT32_Pos)
#define FLASHWP1_ALL_UNIT32_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT32_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT33
 *  @access     FLASH->FLASHWP1.bit.UNIT33
 *  @brief      Write protection for flash unit 33
 */
#define FLASHWP1_ALL_UNIT33_Pos (1)
#define FLASHWP1_ALL_UNIT33_Msk (0x1UL << FLASHWP1_ALL_UNIT33_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT33_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT33_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT33;

#define FLASHWP1_ALL_UNIT33_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT33_Pos)
#define FLASHWP1_ALL_UNIT33_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT33_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT34
 *  @access     FLASH->FLASHWP1.bit.UNIT34
 *  @brief      Write protection for flash unit 34
 */
#define FLASHWP1_ALL_UNIT34_Pos (2)
#define FLASHWP1_ALL_UNIT34_Msk (0x1UL << FLASHWP1_ALL_UNIT34_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT34_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT34_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT34;

#define FLASHWP1_ALL_UNIT34_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT34_Pos)
#define FLASHWP1_ALL_UNIT34_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT34_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT35
 *  @access     FLASH->FLASHWP1.bit.UNIT35
 *  @brief      Write protection for flash unit 35
 */
#define FLASHWP1_ALL_UNIT35_Pos (3)
#define FLASHWP1_ALL_UNIT35_Msk (0x1UL << FLASHWP1_ALL_UNIT35_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT35_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT35_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT35;

#define FLASHWP1_ALL_UNIT35_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT35_Pos)
#define FLASHWP1_ALL_UNIT35_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT35_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT36
 *  @access     FLASH->FLASHWP1.bit.UNIT36
 *  @brief      Write protection for flash unit 36
 */
#define FLASHWP1_ALL_UNIT36_Pos (4)
#define FLASHWP1_ALL_UNIT36_Msk (0x1UL << FLASHWP1_ALL_UNIT36_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT36_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT36_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT36;

#define FLASHWP1_ALL_UNIT36_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT36_Pos)
#define FLASHWP1_ALL_UNIT36_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT36_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT37
 *  @access     FLASH->FLASHWP1.bit.UNIT37
 *  @brief      Write protection for flash unit 37
 */
#define FLASHWP1_ALL_UNIT37_Pos (5)
#define FLASHWP1_ALL_UNIT37_Msk (0x1UL << FLASHWP1_ALL_UNIT37_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT37_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT37_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT37;

#define FLASHWP1_ALL_UNIT37_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT37_Pos)
#define FLASHWP1_ALL_UNIT37_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT37_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT38
 *  @access     FLASH->FLASHWP1.bit.UNIT38
 *  @brief      Write protection for flash unit 38
 */
#define FLASHWP1_ALL_UNIT38_Pos (6)
#define FLASHWP1_ALL_UNIT38_Msk (0x1UL << FLASHWP1_ALL_UNIT38_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT38_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT38_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT38;

#define FLASHWP1_ALL_UNIT38_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT38_Pos)
#define FLASHWP1_ALL_UNIT38_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT38_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT39
 *  @access     FLASH->FLASHWP1.bit.UNIT39
 *  @brief      Write protection for flash unit 39
 */
#define FLASHWP1_ALL_UNIT39_Pos (7)
#define FLASHWP1_ALL_UNIT39_Msk (0x1UL << FLASHWP1_ALL_UNIT39_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT39_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT39_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT39;

#define FLASHWP1_ALL_UNIT39_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT39_Pos)
#define FLASHWP1_ALL_UNIT39_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT39_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT40
 *  @access     FLASH->FLASHWP1.bit.UNIT40
 *  @brief      Write protection for flash unit 40
 */
#define FLASHWP1_ALL_UNIT40_Pos (8)
#define FLASHWP1_ALL_UNIT40_Msk (0x1UL << FLASHWP1_ALL_UNIT40_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT40_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT40_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT40;

#define FLASHWP1_ALL_UNIT40_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT40_Pos)
#define FLASHWP1_ALL_UNIT40_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT40_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT41
 *  @access     FLASH->FLASHWP1.bit.UNIT41
 *  @brief      Write protection for flash unit 41
 */
#define FLASHWP1_ALL_UNIT41_Pos (9)
#define FLASHWP1_ALL_UNIT41_Msk (0x1UL << FLASHWP1_ALL_UNIT41_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT41_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT41_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT41;

#define FLASHWP1_ALL_UNIT41_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT41_Pos)
#define FLASHWP1_ALL_UNIT41_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT41_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT42
 *  @access     FLASH->FLASHWP1.bit.UNIT42
 *  @brief      Write protection for flash unit 42
 */
#define FLASHWP1_ALL_UNIT42_Pos (10)
#define FLASHWP1_ALL_UNIT42_Msk (0x1UL << FLASHWP1_ALL_UNIT42_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT42_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT42_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT42;

#define FLASHWP1_ALL_UNIT42_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT42_Pos)
#define FLASHWP1_ALL_UNIT42_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT42_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT43
 *  @access     FLASH->FLASHWP1.bit.UNIT43
 *  @brief      Write protection for flash unit 43
 */
#define FLASHWP1_ALL_UNIT43_Pos (11)
#define FLASHWP1_ALL_UNIT43_Msk (0x1UL << FLASHWP1_ALL_UNIT43_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT43_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT43_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT43;

#define FLASHWP1_ALL_UNIT43_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT43_Pos)
#define FLASHWP1_ALL_UNIT43_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT43_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT44
 *  @access     FLASH->FLASHWP1.bit.UNIT44
 *  @brief      Write protection for flash unit 44
 */
#define FLASHWP1_ALL_UNIT44_Pos (12)
#define FLASHWP1_ALL_UNIT44_Msk (0x1UL << FLASHWP1_ALL_UNIT44_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT44_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT44_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT44;

#define FLASHWP1_ALL_UNIT44_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT44_Pos)
#define FLASHWP1_ALL_UNIT44_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT44_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT45
 *  @access     FLASH->FLASHWP1.bit.UNIT45
 *  @brief      Write protection for flash unit 45
 */
#define FLASHWP1_ALL_UNIT45_Pos (13)
#define FLASHWP1_ALL_UNIT45_Msk (0x1UL << FLASHWP1_ALL_UNIT45_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT45_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT45_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT45;

#define FLASHWP1_ALL_UNIT45_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT45_Pos)
#define FLASHWP1_ALL_UNIT45_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT45_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT46
 *  @access     FLASH->FLASHWP1.bit.UNIT46
 *  @brief      Write protection for flash unit 46
 */
#define FLASHWP1_ALL_UNIT46_Pos (14)
#define FLASHWP1_ALL_UNIT46_Msk (0x1UL << FLASHWP1_ALL_UNIT46_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT46_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT46_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT46;

#define FLASHWP1_ALL_UNIT46_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT46_Pos)
#define FLASHWP1_ALL_UNIT46_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT46_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT47
 *  @access     FLASH->FLASHWP1.bit.UNIT47
 *  @brief      Write protection for flash unit 47
 */
#define FLASHWP1_ALL_UNIT47_Pos (15)
#define FLASHWP1_ALL_UNIT47_Msk (0x1UL << FLASHWP1_ALL_UNIT47_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT47_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT47_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT47;

#define FLASHWP1_ALL_UNIT47_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT47_Pos)
#define FLASHWP1_ALL_UNIT47_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT47_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT48
 *  @access     FLASH->FLASHWP1.bit.UNIT48
 *  @brief      Write protection for flash unit 48
 */
#define FLASHWP1_ALL_UNIT48_Pos (16)
#define FLASHWP1_ALL_UNIT48_Msk (0x1UL << FLASHWP1_ALL_UNIT48_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT48_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT48_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT48;

#define FLASHWP1_ALL_UNIT48_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT48_Pos)
#define FLASHWP1_ALL_UNIT48_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT48_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT49
 *  @access     FLASH->FLASHWP1.bit.UNIT49
 *  @brief      Write protection for flash unit 49
 */
#define FLASHWP1_ALL_UNIT49_Pos (17)
#define FLASHWP1_ALL_UNIT49_Msk (0x1UL << FLASHWP1_ALL_UNIT49_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT49_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT49_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT49;

#define FLASHWP1_ALL_UNIT49_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT49_Pos)
#define FLASHWP1_ALL_UNIT49_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT49_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT50
 *  @access     FLASH->FLASHWP1.bit.UNIT50
 *  @brief      Write protection for flash unit 50
 */
#define FLASHWP1_ALL_UNIT50_Pos (18)
#define FLASHWP1_ALL_UNIT50_Msk (0x1UL << FLASHWP1_ALL_UNIT50_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT50_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT50_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT50;

#define FLASHWP1_ALL_UNIT50_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT50_Pos)
#define FLASHWP1_ALL_UNIT50_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT50_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT51
 *  @access     FLASH->FLASHWP1.bit.UNIT51
 *  @brief      Write protection for flash unit 51
 */
#define FLASHWP1_ALL_UNIT51_Pos (19)
#define FLASHWP1_ALL_UNIT51_Msk (0x1UL << FLASHWP1_ALL_UNIT51_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT51_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT51_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT51;

#define FLASHWP1_ALL_UNIT51_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT51_Pos)
#define FLASHWP1_ALL_UNIT51_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT51_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT52
 *  @access     FLASH->FLASHWP1.bit.UNIT52
 *  @brief      Write protection for flash unit 52
 */
#define FLASHWP1_ALL_UNIT52_Pos (20)
#define FLASHWP1_ALL_UNIT52_Msk (0x1UL << FLASHWP1_ALL_UNIT52_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT52_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT52_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT52;

#define FLASHWP1_ALL_UNIT52_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT52_Pos)
#define FLASHWP1_ALL_UNIT52_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT52_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT53
 *  @access     FLASH->FLASHWP1.bit.UNIT53
 *  @brief      Write protection for flash unit 53
 */
#define FLASHWP1_ALL_UNIT53_Pos (21)
#define FLASHWP1_ALL_UNIT53_Msk (0x1UL << FLASHWP1_ALL_UNIT53_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT53_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT53_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT53;

#define FLASHWP1_ALL_UNIT53_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT53_Pos)
#define FLASHWP1_ALL_UNIT53_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT53_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT54
 *  @access     FLASH->FLASHWP1.bit.UNIT54
 *  @brief      Write protection for flash unit 54
 */
#define FLASHWP1_ALL_UNIT54_Pos (22)
#define FLASHWP1_ALL_UNIT54_Msk (0x1UL << FLASHWP1_ALL_UNIT54_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT54_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT54_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT54;

#define FLASHWP1_ALL_UNIT54_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT54_Pos)
#define FLASHWP1_ALL_UNIT54_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT54_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT55
 *  @access     FLASH->FLASHWP1.bit.UNIT55
 *  @brief      Write protection for flash unit 55
 */
#define FLASHWP1_ALL_UNIT55_Pos (23)
#define FLASHWP1_ALL_UNIT55_Msk (0x1UL << FLASHWP1_ALL_UNIT55_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT55_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT55_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT55;

#define FLASHWP1_ALL_UNIT55_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT55_Pos)
#define FLASHWP1_ALL_UNIT55_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT55_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT56
 *  @access     FLASH->FLASHWP1.bit.UNIT56
 *  @brief      Write protection for flash unit 56
 */
#define FLASHWP1_ALL_UNIT56_Pos (24)
#define FLASHWP1_ALL_UNIT56_Msk (0x1UL << FLASHWP1_ALL_UNIT56_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT56_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT56_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT56;

#define FLASHWP1_ALL_UNIT56_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT56_Pos)
#define FLASHWP1_ALL_UNIT56_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT56_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT57
 *  @access     FLASH->FLASHWP1.bit.UNIT57
 *  @brief      Write protection for flash unit 57
 */
#define FLASHWP1_ALL_UNIT57_Pos (25)
#define FLASHWP1_ALL_UNIT57_Msk (0x1UL << FLASHWP1_ALL_UNIT57_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT57_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT57_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT57;

#define FLASHWP1_ALL_UNIT57_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT57_Pos)
#define FLASHWP1_ALL_UNIT57_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT57_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT58
 *  @access     FLASH->FLASHWP1.bit.UNIT58
 *  @brief      Write protection for flash unit 58
 */
#define FLASHWP1_ALL_UNIT58_Pos (26)
#define FLASHWP1_ALL_UNIT58_Msk (0x1UL << FLASHWP1_ALL_UNIT58_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT58_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT58_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT58;

#define FLASHWP1_ALL_UNIT58_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT58_Pos)
#define FLASHWP1_ALL_UNIT58_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT58_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT59
 *  @access     FLASH->FLASHWP1.bit.UNIT59
 *  @brief      Write protection for flash unit 59
 */
#define FLASHWP1_ALL_UNIT59_Pos (27)
#define FLASHWP1_ALL_UNIT59_Msk (0x1UL << FLASHWP1_ALL_UNIT59_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT59_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT59_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT59;

#define FLASHWP1_ALL_UNIT59_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT59_Pos)
#define FLASHWP1_ALL_UNIT59_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT59_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT60
 *  @access     FLASH->FLASHWP1.bit.UNIT60
 *  @brief      Write protection for flash unit 60
 */
#define FLASHWP1_ALL_UNIT60_Pos (28)
#define FLASHWP1_ALL_UNIT60_Msk (0x1UL << FLASHWP1_ALL_UNIT60_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT60_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT60_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT60;

#define FLASHWP1_ALL_UNIT60_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT60_Pos)
#define FLASHWP1_ALL_UNIT60_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT60_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT61
 *  @access     FLASH->FLASHWP1.bit.UNIT61
 *  @brief      Write protection for flash unit 61
 */
#define FLASHWP1_ALL_UNIT61_Pos (29)
#define FLASHWP1_ALL_UNIT61_Msk (0x1UL << FLASHWP1_ALL_UNIT61_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT61_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT61_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT61;

#define FLASHWP1_ALL_UNIT61_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT61_Pos)
#define FLASHWP1_ALL_UNIT61_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT61_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT62
 *  @access     FLASH->FLASHWP1.bit.UNIT62
 *  @brief      Write protection for flash unit 62
 */
#define FLASHWP1_ALL_UNIT62_Pos (30)
#define FLASHWP1_ALL_UNIT62_Msk (0x1UL << FLASHWP1_ALL_UNIT62_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT62_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT62_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT62;

#define FLASHWP1_ALL_UNIT62_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT62_Pos)
#define FLASHWP1_ALL_UNIT62_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT62_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP1        UNIT63
 *  @access     FLASH->FLASHWP1.bit.UNIT63
 *  @brief      Write protection for flash unit 63
 */
#define FLASHWP1_ALL_UNIT63_Pos (31)
#define FLASHWP1_ALL_UNIT63_Msk (0x1UL << FLASHWP1_ALL_UNIT63_Pos)

typedef enum
{
    FLASHWP1_BIT_UNIT63_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP1_BIT_UNIT63_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP1_BIT_UNIT63;

#define FLASHWP1_ALL_UNIT63_UNPROTECT     ((0x0UL) << FLASHWP1_ALL_UNIT63_Pos)
#define FLASHWP1_ALL_UNIT63_PROTECT       ((0x1UL) << FLASHWP1_ALL_UNIT63_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT64
 *  @access     FLASH->FLASHWP2.bit.UNIT64
 *  @brief      Write protection for flash unit 64
 */
#define FLASHWP2_ALL_UNIT64_Pos (0)
#define FLASHWP2_ALL_UNIT64_Msk (0x1UL << FLASHWP2_ALL_UNIT64_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT64_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT64_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT64;

#define FLASHWP2_ALL_UNIT64_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT64_Pos)
#define FLASHWP2_ALL_UNIT64_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT64_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT65
 *  @access     FLASH->FLASHWP2.bit.UNIT65
 *  @brief      Write protection for flash unit 65
 */
#define FLASHWP2_ALL_UNIT65_Pos (1)
#define FLASHWP2_ALL_UNIT65_Msk (0x1UL << FLASHWP2_ALL_UNIT65_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT65_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT65_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT65;

#define FLASHWP2_ALL_UNIT65_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT65_Pos)
#define FLASHWP2_ALL_UNIT65_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT65_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT66
 *  @access     FLASH->FLASHWP2.bit.UNIT66
 *  @brief      Write protection for flash unit 66
 */
#define FLASHWP2_ALL_UNIT66_Pos (2)
#define FLASHWP2_ALL_UNIT66_Msk (0x1UL << FLASHWP2_ALL_UNIT66_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT66_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT66_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT66;

#define FLASHWP2_ALL_UNIT66_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT66_Pos)
#define FLASHWP2_ALL_UNIT66_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT66_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT67
 *  @access     FLASH->FLASHWP2.bit.UNIT67
 *  @brief      Write protection for flash unit 67
 */
#define FLASHWP2_ALL_UNIT67_Pos (3)
#define FLASHWP2_ALL_UNIT67_Msk (0x1UL << FLASHWP2_ALL_UNIT67_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT67_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT67_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT67;

#define FLASHWP2_ALL_UNIT67_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT67_Pos)
#define FLASHWP2_ALL_UNIT67_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT67_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT68
 *  @access     FLASH->FLASHWP2.bit.UNIT68
 *  @brief      Write protection for flash unit 68
 */
#define FLASHWP2_ALL_UNIT68_Pos (4)
#define FLASHWP2_ALL_UNIT68_Msk (0x1UL << FLASHWP2_ALL_UNIT68_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT68_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT68_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT68;

#define FLASHWP2_ALL_UNIT68_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT68_Pos)
#define FLASHWP2_ALL_UNIT68_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT68_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT69
 *  @access     FLASH->FLASHWP2.bit.UNIT69
 *  @brief      Write protection for flash unit 69
 */
#define FLASHWP2_ALL_UNIT69_Pos (5)
#define FLASHWP2_ALL_UNIT69_Msk (0x1UL << FLASHWP2_ALL_UNIT69_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT69_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT69_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT69;

#define FLASHWP2_ALL_UNIT69_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT69_Pos)
#define FLASHWP2_ALL_UNIT69_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT69_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT70
 *  @access     FLASH->FLASHWP2.bit.UNIT70
 *  @brief      Write protection for flash unit 70
 */
#define FLASHWP2_ALL_UNIT70_Pos (6)
#define FLASHWP2_ALL_UNIT70_Msk (0x1UL << FLASHWP2_ALL_UNIT70_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT70_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT70_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT70;

#define FLASHWP2_ALL_UNIT70_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT70_Pos)
#define FLASHWP2_ALL_UNIT70_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT70_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT71
 *  @access     FLASH->FLASHWP2.bit.UNIT71
 *  @brief      Write protection for flash unit 71
 */
#define FLASHWP2_ALL_UNIT71_Pos (7)
#define FLASHWP2_ALL_UNIT71_Msk (0x1UL << FLASHWP2_ALL_UNIT71_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT71_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT71_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT71;

#define FLASHWP2_ALL_UNIT71_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT71_Pos)
#define FLASHWP2_ALL_UNIT71_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT71_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT72
 *  @access     FLASH->FLASHWP2.bit.UNIT72
 *  @brief      Write protection for flash unit 72
 */
#define FLASHWP2_ALL_UNIT72_Pos (8)
#define FLASHWP2_ALL_UNIT72_Msk (0x1UL << FLASHWP2_ALL_UNIT72_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT72_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT72_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT72;

#define FLASHWP2_ALL_UNIT72_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT72_Pos)
#define FLASHWP2_ALL_UNIT72_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT72_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT73
 *  @access     FLASH->FLASHWP2.bit.UNIT73
 *  @brief      Write protection for flash unit 73
 */
#define FLASHWP2_ALL_UNIT73_Pos (9)
#define FLASHWP2_ALL_UNIT73_Msk (0x1UL << FLASHWP2_ALL_UNIT73_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT73_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT73_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT73;

#define FLASHWP2_ALL_UNIT73_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT73_Pos)
#define FLASHWP2_ALL_UNIT73_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT73_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT74
 *  @access     FLASH->FLASHWP2.bit.UNIT74
 *  @brief      Write protection for flash unit 74
 */
#define FLASHWP2_ALL_UNIT74_Pos (10)
#define FLASHWP2_ALL_UNIT74_Msk (0x1UL << FLASHWP2_ALL_UNIT74_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT74_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT74_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT74;

#define FLASHWP2_ALL_UNIT74_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT74_Pos)
#define FLASHWP2_ALL_UNIT74_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT74_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT75
 *  @access     FLASH->FLASHWP2.bit.UNIT75
 *  @brief      Write protection for flash unit 75
 */
#define FLASHWP2_ALL_UNIT75_Pos (11)
#define FLASHWP2_ALL_UNIT75_Msk (0x1UL << FLASHWP2_ALL_UNIT75_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT75_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT75_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT75;

#define FLASHWP2_ALL_UNIT75_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT75_Pos)
#define FLASHWP2_ALL_UNIT75_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT75_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT76
 *  @access     FLASH->FLASHWP2.bit.UNIT76
 *  @brief      Write protection for flash unit 76
 */
#define FLASHWP2_ALL_UNIT76_Pos (12)
#define FLASHWP2_ALL_UNIT76_Msk (0x1UL << FLASHWP2_ALL_UNIT76_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT76_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT76_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT76;

#define FLASHWP2_ALL_UNIT76_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT76_Pos)
#define FLASHWP2_ALL_UNIT76_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT76_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT77
 *  @access     FLASH->FLASHWP2.bit.UNIT77
 *  @brief      Write protection for flash unit 77
 */
#define FLASHWP2_ALL_UNIT77_Pos (13)
#define FLASHWP2_ALL_UNIT77_Msk (0x1UL << FLASHWP2_ALL_UNIT77_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT77_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT77_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT77;

#define FLASHWP2_ALL_UNIT77_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT77_Pos)
#define FLASHWP2_ALL_UNIT77_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT77_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT78
 *  @access     FLASH->FLASHWP2.bit.UNIT78
 *  @brief      Write protection for flash unit 78
 */
#define FLASHWP2_ALL_UNIT78_Pos (14)
#define FLASHWP2_ALL_UNIT78_Msk (0x1UL << FLASHWP2_ALL_UNIT78_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT78_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT78_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT78;

#define FLASHWP2_ALL_UNIT78_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT78_Pos)
#define FLASHWP2_ALL_UNIT78_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT78_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT79
 *  @access     FLASH->FLASHWP2.bit.UNIT79
 *  @brief      Write protection for flash unit 79
 */
#define FLASHWP2_ALL_UNIT79_Pos (15)
#define FLASHWP2_ALL_UNIT79_Msk (0x1UL << FLASHWP2_ALL_UNIT79_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT79_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT79_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT79;

#define FLASHWP2_ALL_UNIT79_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT79_Pos)
#define FLASHWP2_ALL_UNIT79_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT79_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT80
 *  @access     FLASH->FLASHWP2.bit.UNIT80
 *  @brief      Write protection for flash unit 80
 */
#define FLASHWP2_ALL_UNIT80_Pos (16)
#define FLASHWP2_ALL_UNIT80_Msk (0x1UL << FLASHWP2_ALL_UNIT80_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT80_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT80_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT80;

#define FLASHWP2_ALL_UNIT80_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT80_Pos)
#define FLASHWP2_ALL_UNIT80_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT80_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT81
 *  @access     FLASH->FLASHWP2.bit.UNIT81
 *  @brief      Write protection for flash unit 81
 */
#define FLASHWP2_ALL_UNIT81_Pos (17)
#define FLASHWP2_ALL_UNIT81_Msk (0x1UL << FLASHWP2_ALL_UNIT81_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT81_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT81_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT81;

#define FLASHWP2_ALL_UNIT81_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT81_Pos)
#define FLASHWP2_ALL_UNIT81_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT81_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT82
 *  @access     FLASH->FLASHWP2.bit.UNIT82
 *  @brief      Write protection for flash unit 82
 */
#define FLASHWP2_ALL_UNIT82_Pos (18)
#define FLASHWP2_ALL_UNIT82_Msk (0x1UL << FLASHWP2_ALL_UNIT82_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT82_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT82_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT82;

#define FLASHWP2_ALL_UNIT82_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT82_Pos)
#define FLASHWP2_ALL_UNIT82_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT82_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT83
 *  @access     FLASH->FLASHWP2.bit.UNIT83
 *  @brief      Write protection for flash unit 83
 */
#define FLASHWP2_ALL_UNIT83_Pos (19)
#define FLASHWP2_ALL_UNIT83_Msk (0x1UL << FLASHWP2_ALL_UNIT83_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT83_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT83_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT83;

#define FLASHWP2_ALL_UNIT83_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT83_Pos)
#define FLASHWP2_ALL_UNIT83_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT83_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT84
 *  @access     FLASH->FLASHWP2.bit.UNIT84
 *  @brief      Write protection for flash unit 84
 */
#define FLASHWP2_ALL_UNIT84_Pos (20)
#define FLASHWP2_ALL_UNIT84_Msk (0x1UL << FLASHWP2_ALL_UNIT84_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT84_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT84_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT84;

#define FLASHWP2_ALL_UNIT84_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT84_Pos)
#define FLASHWP2_ALL_UNIT84_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT84_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT85
 *  @access     FLASH->FLASHWP2.bit.UNIT85
 *  @brief      Write protection for flash unit 85
 */
#define FLASHWP2_ALL_UNIT85_Pos (21)
#define FLASHWP2_ALL_UNIT85_Msk (0x1UL << FLASHWP2_ALL_UNIT85_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT85_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT85_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT85;

#define FLASHWP2_ALL_UNIT85_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT85_Pos)
#define FLASHWP2_ALL_UNIT85_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT85_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT86
 *  @access     FLASH->FLASHWP2.bit.UNIT86
 *  @brief      Write protection for flash unit 86
 */
#define FLASHWP2_ALL_UNIT86_Pos (22)
#define FLASHWP2_ALL_UNIT86_Msk (0x1UL << FLASHWP2_ALL_UNIT86_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT86_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT86_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT86;

#define FLASHWP2_ALL_UNIT86_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT86_Pos)
#define FLASHWP2_ALL_UNIT86_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT86_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT87
 *  @access     FLASH->FLASHWP2.bit.UNIT87
 *  @brief      Write protection for flash unit 87
 */
#define FLASHWP2_ALL_UNIT87_Pos (23)
#define FLASHWP2_ALL_UNIT87_Msk (0x1UL << FLASHWP2_ALL_UNIT87_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT87_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT87_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT87;

#define FLASHWP2_ALL_UNIT87_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT87_Pos)
#define FLASHWP2_ALL_UNIT87_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT87_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT88
 *  @access     FLASH->FLASHWP2.bit.UNIT88
 *  @brief      Write protection for flash unit 88
 */
#define FLASHWP2_ALL_UNIT88_Pos (24)
#define FLASHWP2_ALL_UNIT88_Msk (0x1UL << FLASHWP2_ALL_UNIT88_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT88_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT88_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT88;

#define FLASHWP2_ALL_UNIT88_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT88_Pos)
#define FLASHWP2_ALL_UNIT88_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT88_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT89
 *  @access     FLASH->FLASHWP2.bit.UNIT89
 *  @brief      Write protection for flash unit 89
 */
#define FLASHWP2_ALL_UNIT89_Pos (25)
#define FLASHWP2_ALL_UNIT89_Msk (0x1UL << FLASHWP2_ALL_UNIT89_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT89_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT89_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT89;

#define FLASHWP2_ALL_UNIT89_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT89_Pos)
#define FLASHWP2_ALL_UNIT89_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT89_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT90
 *  @access     FLASH->FLASHWP2.bit.UNIT90
 *  @brief      Write protection for flash unit 90
 */
#define FLASHWP2_ALL_UNIT90_Pos (26)
#define FLASHWP2_ALL_UNIT90_Msk (0x1UL << FLASHWP2_ALL_UNIT90_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT90_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT90_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT90;

#define FLASHWP2_ALL_UNIT90_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT90_Pos)
#define FLASHWP2_ALL_UNIT90_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT90_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT91
 *  @access     FLASH->FLASHWP2.bit.UNIT91
 *  @brief      Write protection for flash unit 91
 */
#define FLASHWP2_ALL_UNIT91_Pos (27)
#define FLASHWP2_ALL_UNIT91_Msk (0x1UL << FLASHWP2_ALL_UNIT91_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT91_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT91_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT91;

#define FLASHWP2_ALL_UNIT91_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT91_Pos)
#define FLASHWP2_ALL_UNIT91_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT91_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT92
 *  @access     FLASH->FLASHWP2.bit.UNIT92
 *  @brief      Write protection for flash unit 92
 */
#define FLASHWP2_ALL_UNIT92_Pos (28)
#define FLASHWP2_ALL_UNIT92_Msk (0x1UL << FLASHWP2_ALL_UNIT92_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT92_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT92_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT92;

#define FLASHWP2_ALL_UNIT92_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT92_Pos)
#define FLASHWP2_ALL_UNIT92_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT92_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT93
 *  @access     FLASH->FLASHWP2.bit.UNIT93
 *  @brief      Write protection for flash unit 93
 */
#define FLASHWP2_ALL_UNIT93_Pos (29)
#define FLASHWP2_ALL_UNIT93_Msk (0x1UL << FLASHWP2_ALL_UNIT93_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT93_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT93_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT93;

#define FLASHWP2_ALL_UNIT93_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT93_Pos)
#define FLASHWP2_ALL_UNIT93_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT93_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT94
 *  @access     FLASH->FLASHWP2.bit.UNIT94
 *  @brief      Write protection for flash unit 94
 */
#define FLASHWP2_ALL_UNIT94_Pos (30)
#define FLASHWP2_ALL_UNIT94_Msk (0x1UL << FLASHWP2_ALL_UNIT94_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT94_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT94_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT94;

#define FLASHWP2_ALL_UNIT94_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT94_Pos)
#define FLASHWP2_ALL_UNIT94_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT94_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP2        UNIT95
 *  @access     FLASH->FLASHWP2.bit.UNIT95
 *  @brief      Write protection for flash unit 95
 */
#define FLASHWP2_ALL_UNIT95_Pos (31)
#define FLASHWP2_ALL_UNIT95_Msk (0x1UL << FLASHWP2_ALL_UNIT95_Pos)

typedef enum
{
    FLASHWP2_BIT_UNIT95_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP2_BIT_UNIT95_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP2_BIT_UNIT95;

#define FLASHWP2_ALL_UNIT95_UNPROTECT     ((0x0UL) << FLASHWP2_ALL_UNIT95_Pos)
#define FLASHWP2_ALL_UNIT95_PROTECT       ((0x1UL) << FLASHWP2_ALL_UNIT95_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT96
 *  @access     FLASH->FLASHWP3.bit.UNIT96
 *  @brief      Write protection for flash unit 96
 */
#define FLASHWP3_ALL_UNIT96_Pos (0)
#define FLASHWP3_ALL_UNIT96_Msk (0x1UL << FLASHWP3_ALL_UNIT96_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT96_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT96_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT96;

#define FLASHWP3_ALL_UNIT96_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT96_Pos)
#define FLASHWP3_ALL_UNIT96_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT96_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT97
 *  @access     FLASH->FLASHWP3.bit.UNIT97
 *  @brief      Write protection for flash unit 97
 */
#define FLASHWP3_ALL_UNIT97_Pos (1)
#define FLASHWP3_ALL_UNIT97_Msk (0x1UL << FLASHWP3_ALL_UNIT97_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT97_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT97_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT97;

#define FLASHWP3_ALL_UNIT97_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT97_Pos)
#define FLASHWP3_ALL_UNIT97_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT97_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT98
 *  @access     FLASH->FLASHWP3.bit.UNIT98
 *  @brief      Write protection for flash unit 98
 */
#define FLASHWP3_ALL_UNIT98_Pos (2)
#define FLASHWP3_ALL_UNIT98_Msk (0x1UL << FLASHWP3_ALL_UNIT98_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT98_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT98_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT98;

#define FLASHWP3_ALL_UNIT98_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT98_Pos)
#define FLASHWP3_ALL_UNIT98_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT98_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT99
 *  @access     FLASH->FLASHWP3.bit.UNIT99
 *  @brief      Write protection for flash unit 99
 */
#define FLASHWP3_ALL_UNIT99_Pos (3)
#define FLASHWP3_ALL_UNIT99_Msk (0x1UL << FLASHWP3_ALL_UNIT99_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT99_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT99_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT99;

#define FLASHWP3_ALL_UNIT99_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT99_Pos)
#define FLASHWP3_ALL_UNIT99_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT99_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT100
 *  @access     FLASH->FLASHWP3.bit.UNIT100
 *  @brief      Write protection for flash unit 100
 */
#define FLASHWP3_ALL_UNIT100_Pos (4)
#define FLASHWP3_ALL_UNIT100_Msk (0x1UL << FLASHWP3_ALL_UNIT100_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT100_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT100_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT100;

#define FLASHWP3_ALL_UNIT100_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT100_Pos)
#define FLASHWP3_ALL_UNIT100_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT100_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT101
 *  @access     FLASH->FLASHWP3.bit.UNIT101
 *  @brief      Write protection for flash unit 101
 */
#define FLASHWP3_ALL_UNIT101_Pos (5)
#define FLASHWP3_ALL_UNIT101_Msk (0x1UL << FLASHWP3_ALL_UNIT101_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT101_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT101_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT101;

#define FLASHWP3_ALL_UNIT101_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT101_Pos)
#define FLASHWP3_ALL_UNIT101_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT101_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT102
 *  @access     FLASH->FLASHWP3.bit.UNIT102
 *  @brief      Write protection for flash unit 102
 */
#define FLASHWP3_ALL_UNIT102_Pos (6)
#define FLASHWP3_ALL_UNIT102_Msk (0x1UL << FLASHWP3_ALL_UNIT102_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT102_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT102_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT102;

#define FLASHWP3_ALL_UNIT102_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT102_Pos)
#define FLASHWP3_ALL_UNIT102_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT102_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT103
 *  @access     FLASH->FLASHWP3.bit.UNIT103
 *  @brief      Write protection for flash unit 103
 */
#define FLASHWP3_ALL_UNIT103_Pos (7)
#define FLASHWP3_ALL_UNIT103_Msk (0x1UL << FLASHWP3_ALL_UNIT103_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT103_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT103_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT103;

#define FLASHWP3_ALL_UNIT103_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT103_Pos)
#define FLASHWP3_ALL_UNIT103_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT103_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT104
 *  @access     FLASH->FLASHWP3.bit.UNIT104
 *  @brief      Write protection for flash unit 104
 */
#define FLASHWP3_ALL_UNIT104_Pos (8)
#define FLASHWP3_ALL_UNIT104_Msk (0x1UL << FLASHWP3_ALL_UNIT104_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT104_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT104_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT104;

#define FLASHWP3_ALL_UNIT104_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT104_Pos)
#define FLASHWP3_ALL_UNIT104_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT104_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT105
 *  @access     FLASH->FLASHWP3.bit.UNIT105
 *  @brief      Write protection for flash unit 105
 */
#define FLASHWP3_ALL_UNIT105_Pos (9)
#define FLASHWP3_ALL_UNIT105_Msk (0x1UL << FLASHWP3_ALL_UNIT105_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT105_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT105_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT105;

#define FLASHWP3_ALL_UNIT105_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT105_Pos)
#define FLASHWP3_ALL_UNIT105_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT105_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT106
 *  @access     FLASH->FLASHWP3.bit.UNIT106
 *  @brief      Write protection for flash unit 106
 */
#define FLASHWP3_ALL_UNIT106_Pos (10)
#define FLASHWP3_ALL_UNIT106_Msk (0x1UL << FLASHWP3_ALL_UNIT106_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT106_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT106_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT106;

#define FLASHWP3_ALL_UNIT106_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT106_Pos)
#define FLASHWP3_ALL_UNIT106_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT106_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT107
 *  @access     FLASH->FLASHWP3.bit.UNIT107
 *  @brief      Write protection for flash unit 107
 */
#define FLASHWP3_ALL_UNIT107_Pos (11)
#define FLASHWP3_ALL_UNIT107_Msk (0x1UL << FLASHWP3_ALL_UNIT107_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT107_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT107_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT107;

#define FLASHWP3_ALL_UNIT107_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT107_Pos)
#define FLASHWP3_ALL_UNIT107_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT107_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT108
 *  @access     FLASH->FLASHWP3.bit.UNIT108
 *  @brief      Write protection for flash unit 108
 */
#define FLASHWP3_ALL_UNIT108_Pos (12)
#define FLASHWP3_ALL_UNIT108_Msk (0x1UL << FLASHWP3_ALL_UNIT108_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT108_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT108_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT108;

#define FLASHWP3_ALL_UNIT108_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT108_Pos)
#define FLASHWP3_ALL_UNIT108_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT108_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT109
 *  @access     FLASH->FLASHWP3.bit.UNIT109
 *  @brief      Write protection for flash unit 109
 */
#define FLASHWP3_ALL_UNIT109_Pos (13)
#define FLASHWP3_ALL_UNIT109_Msk (0x1UL << FLASHWP3_ALL_UNIT109_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT109_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT109_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT109;

#define FLASHWP3_ALL_UNIT109_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT109_Pos)
#define FLASHWP3_ALL_UNIT109_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT109_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT110
 *  @access     FLASH->FLASHWP3.bit.UNIT110
 *  @brief      Write protection for flash unit 110
 */
#define FLASHWP3_ALL_UNIT110_Pos (14)
#define FLASHWP3_ALL_UNIT110_Msk (0x1UL << FLASHWP3_ALL_UNIT110_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT110_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT110_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT110;

#define FLASHWP3_ALL_UNIT110_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT110_Pos)
#define FLASHWP3_ALL_UNIT110_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT110_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT111
 *  @access     FLASH->FLASHWP3.bit.UNIT111
 *  @brief      Write protection for flash unit 111
 */
#define FLASHWP3_ALL_UNIT111_Pos (15)
#define FLASHWP3_ALL_UNIT111_Msk (0x1UL << FLASHWP3_ALL_UNIT111_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT111_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT111_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT111;

#define FLASHWP3_ALL_UNIT111_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT111_Pos)
#define FLASHWP3_ALL_UNIT111_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT111_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT112
 *  @access     FLASH->FLASHWP3.bit.UNIT112
 *  @brief      Write protection for flash unit 112
 */
#define FLASHWP3_ALL_UNIT112_Pos (16)
#define FLASHWP3_ALL_UNIT112_Msk (0x1UL << FLASHWP3_ALL_UNIT112_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT112_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT112_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT112;

#define FLASHWP3_ALL_UNIT112_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT112_Pos)
#define FLASHWP3_ALL_UNIT112_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT112_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT113
 *  @access     FLASH->FLASHWP3.bit.UNIT113
 *  @brief      Write protection for flash unit 113
 */
#define FLASHWP3_ALL_UNIT113_Pos (17)
#define FLASHWP3_ALL_UNIT113_Msk (0x1UL << FLASHWP3_ALL_UNIT113_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT113_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT113_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT113;

#define FLASHWP3_ALL_UNIT113_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT113_Pos)
#define FLASHWP3_ALL_UNIT113_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT113_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT114
 *  @access     FLASH->FLASHWP3.bit.UNIT114
 *  @brief      Write protection for flash unit 114
 */
#define FLASHWP3_ALL_UNIT114_Pos (18)
#define FLASHWP3_ALL_UNIT114_Msk (0x1UL << FLASHWP3_ALL_UNIT114_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT114_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT114_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT114;

#define FLASHWP3_ALL_UNIT114_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT114_Pos)
#define FLASHWP3_ALL_UNIT114_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT114_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT115
 *  @access     FLASH->FLASHWP3.bit.UNIT115
 *  @brief      Write protection for flash unit 115
 */
#define FLASHWP3_ALL_UNIT115_Pos (19)
#define FLASHWP3_ALL_UNIT115_Msk (0x1UL << FLASHWP3_ALL_UNIT115_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT115_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT115_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT115;

#define FLASHWP3_ALL_UNIT115_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT115_Pos)
#define FLASHWP3_ALL_UNIT115_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT115_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT116
 *  @access     FLASH->FLASHWP3.bit.UNIT116
 *  @brief      Write protection for flash unit 116
 */
#define FLASHWP3_ALL_UNIT116_Pos (20)
#define FLASHWP3_ALL_UNIT116_Msk (0x1UL << FLASHWP3_ALL_UNIT116_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT116_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT116_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT116;

#define FLASHWP3_ALL_UNIT116_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT116_Pos)
#define FLASHWP3_ALL_UNIT116_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT116_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT117
 *  @access     FLASH->FLASHWP3.bit.UNIT117
 *  @brief      Write protection for flash unit 117
 */
#define FLASHWP3_ALL_UNIT117_Pos (21)
#define FLASHWP3_ALL_UNIT117_Msk (0x1UL << FLASHWP3_ALL_UNIT117_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT117_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT117_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT117;

#define FLASHWP3_ALL_UNIT117_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT117_Pos)
#define FLASHWP3_ALL_UNIT117_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT117_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT118
 *  @access     FLASH->FLASHWP3.bit.UNIT118
 *  @brief      Write protection for flash unit 118
 */
#define FLASHWP3_ALL_UNIT118_Pos (22)
#define FLASHWP3_ALL_UNIT118_Msk (0x1UL << FLASHWP3_ALL_UNIT118_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT118_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT118_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT118;

#define FLASHWP3_ALL_UNIT118_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT118_Pos)
#define FLASHWP3_ALL_UNIT118_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT118_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT119
 *  @access     FLASH->FLASHWP3.bit.UNIT119
 *  @brief      Write protection for flash unit 119
 */
#define FLASHWP3_ALL_UNIT119_Pos (23)
#define FLASHWP3_ALL_UNIT119_Msk (0x1UL << FLASHWP3_ALL_UNIT119_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT119_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT119_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT119;

#define FLASHWP3_ALL_UNIT119_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT119_Pos)
#define FLASHWP3_ALL_UNIT119_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT119_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT120
 *  @access     FLASH->FLASHWP3.bit.UNIT120
 *  @brief      Write protection for flash unit 120
 */
#define FLASHWP3_ALL_UNIT120_Pos (24)
#define FLASHWP3_ALL_UNIT120_Msk (0x1UL << FLASHWP3_ALL_UNIT120_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT120_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT120_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT120;

#define FLASHWP3_ALL_UNIT120_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT120_Pos)
#define FLASHWP3_ALL_UNIT120_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT120_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT121
 *  @access     FLASH->FLASHWP3.bit.UNIT121
 *  @brief      Write protection for flash unit 121
 */
#define FLASHWP3_ALL_UNIT121_Pos (25)
#define FLASHWP3_ALL_UNIT121_Msk (0x1UL << FLASHWP3_ALL_UNIT121_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT121_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT121_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT121;

#define FLASHWP3_ALL_UNIT121_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT121_Pos)
#define FLASHWP3_ALL_UNIT121_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT121_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT122
 *  @access     FLASH->FLASHWP3.bit.UNIT122
 *  @brief      Write protection for flash unit 122
 */
#define FLASHWP3_ALL_UNIT122_Pos (26)
#define FLASHWP3_ALL_UNIT122_Msk (0x1UL << FLASHWP3_ALL_UNIT122_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT122_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT122_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT122;

#define FLASHWP3_ALL_UNIT122_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT122_Pos)
#define FLASHWP3_ALL_UNIT122_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT122_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT123
 *  @access     FLASH->FLASHWP3.bit.UNIT123
 *  @brief      Write protection for flash unit 123
 */
#define FLASHWP3_ALL_UNIT123_Pos (27)
#define FLASHWP3_ALL_UNIT123_Msk (0x1UL << FLASHWP3_ALL_UNIT123_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT123_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT123_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT123;

#define FLASHWP3_ALL_UNIT123_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT123_Pos)
#define FLASHWP3_ALL_UNIT123_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT123_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT124
 *  @access     FLASH->FLASHWP3.bit.UNIT124
 *  @brief      Write protection for flash unit 124
 */
#define FLASHWP3_ALL_UNIT124_Pos (28)
#define FLASHWP3_ALL_UNIT124_Msk (0x1UL << FLASHWP3_ALL_UNIT124_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT124_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT124_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT124;

#define FLASHWP3_ALL_UNIT124_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT124_Pos)
#define FLASHWP3_ALL_UNIT124_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT124_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT125
 *  @access     FLASH->FLASHWP3.bit.UNIT125
 *  @brief      Write protection for flash unit 125
 */
#define FLASHWP3_ALL_UNIT125_Pos (29)
#define FLASHWP3_ALL_UNIT125_Msk (0x1UL << FLASHWP3_ALL_UNIT125_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT125_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT125_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT125;

#define FLASHWP3_ALL_UNIT125_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT125_Pos)
#define FLASHWP3_ALL_UNIT125_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT125_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT126
 *  @access     FLASH->FLASHWP3.bit.UNIT126
 *  @brief      Write protection for flash unit 126
 */
#define FLASHWP3_ALL_UNIT126_Pos (30)
#define FLASHWP3_ALL_UNIT126_Msk (0x1UL << FLASHWP3_ALL_UNIT126_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT126_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT126_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT126;

#define FLASHWP3_ALL_UNIT126_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT126_Pos)
#define FLASHWP3_ALL_UNIT126_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT126_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHWP3        UNIT127
 *  @access     FLASH->FLASHWP3.bit.UNIT127
 *  @brief      Write protection for flash unit 127
 */
#define FLASHWP3_ALL_UNIT127_Pos (31)
#define FLASHWP3_ALL_UNIT127_Msk (0x1UL << FLASHWP3_ALL_UNIT127_Pos)

typedef enum
{
    FLASHWP3_BIT_UNIT127_UNPROTECT     = 0,  /*!< Can be programed or erased             */
    FLASHWP3_BIT_UNIT127_PROTECT       = 1,  /*!< Cannot be programed or sector erased   */
} FLASHWP3_BIT_UNIT127;

#define FLASHWP3_ALL_UNIT127_UNPROTECT     ((0x0UL) << FLASHWP3_ALL_UNIT127_Pos)
#define FLASHWP3_ALL_UNIT127_PROTECT       ((0x1UL) << FLASHWP3_ALL_UNIT127_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   FLASH           FLASHREGKEY     KEY
 *  @access     FLASH->FLASHREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected flash registers
 */
#define FLASHREGKEY_ALL_KEY_Pos (0)
#define FLASHREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << FLASHREGKEY_ALL_KEY_Pos)

#define FLASHREGKEY_BIT_KEY

#define FLASHREGKEY_ALL_KEY_(x) ((x) << FLASHREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     PGA
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         EN
 *  @access     PGA->PGA0CTL.bit.EN
 *  @brief      PGA0 enable
 */
#define PGA0CTL_ALL_EN_Pos (0)
#define PGA0CTL_ALL_EN_Msk (0x1UL << PGA0CTL_ALL_EN_Pos)

typedef enum
{
    PGA0CTL_BIT_EN_DISABLE     = 0,  /*!< Disable PGA0   */
    PGA0CTL_BIT_EN_ENABLE      = 1,  /*!< Enable PGA0    */
} PGA0CTL_BIT_EN;

#define PGA0CTL_ALL_EN_DISABLE     ((0x0UL) << PGA0CTL_ALL_EN_Pos)
#define PGA0CTL_ALL_EN_ENABLE      ((0x1UL) << PGA0CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         MODE
 *  @access     PGA->PGA0CTL.bit.MODE
 *  @brief      PGA0 mode
 */
#define PGA0CTL_ALL_MODE_Pos (1)
#define PGA0CTL_ALL_MODE_Msk (0x3UL << PGA0CTL_ALL_MODE_Pos)

typedef enum
{
    PGA0CTL_BIT_MODE_DIFF                = 0,  /*!< Differential mode                           */
    PGA0CTL_BIT_MODE_SINGLE_POSITIVE     = 1,  /*!< Single-ended mode with positive path only   */
    PGA0CTL_BIT_MODE_SINGLE_NEGATIVE     = 2,  /*!< Single-ended mode with negative path only   */
    PGA0CTL_BIT_MODE_SINGLE_BOTH         = 3,  /*!< Single-ended mode with both paths           */
} PGA0CTL_BIT_MODE;

#define PGA0CTL_ALL_MODE_DIFF                ((0x0UL) << PGA0CTL_ALL_MODE_Pos)
#define PGA0CTL_ALL_MODE_SINGLE_POSITIVE     ((0x1UL) << PGA0CTL_ALL_MODE_Pos)
#define PGA0CTL_ALL_MODE_SINGLE_NEGATIVE     ((0x2UL) << PGA0CTL_ALL_MODE_Pos)
#define PGA0CTL_ALL_MODE_SINGLE_BOTH         ((0x3UL) << PGA0CTL_ALL_MODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         CMSEL
 *  @access     PGA->PGA0CTL.bit.CMSEL
 *  @brief      PGA0 output common voltage selection for differential mode
 */
#define PGA0CTL_ALL_CMSEL_Pos (3)
#define PGA0CTL_ALL_CMSEL_Msk (0x1UL << PGA0CTL_ALL_CMSEL_Pos)

typedef enum
{
    PGA0CTL_BIT_CMSEL_NEGATIVE_AS_COMMON     = 0,  /*!< Select negative input voltage as output common voltage   */
    PGA0CTL_BIT_CMSEL_POSITIVE_AS_COMMON     = 1,  /*!< Select positive input voltage as output common voltage   */
} PGA0CTL_BIT_CMSEL;

#define PGA0CTL_ALL_CMSEL_NEGATIVE_AS_COMMON     ((0x0UL) << PGA0CTL_ALL_CMSEL_Pos)
#define PGA0CTL_ALL_CMSEL_POSITIVE_AS_COMMON     ((0x1UL) << PGA0CTL_ALL_CMSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         INSELP
 *  @access     PGA->PGA0CTL.bit.INSELP
 *  @brief      PGA0 positive input select
 */
#define PGA0CTL_ALL_INSELP_Pos (4)
#define PGA0CTL_ALL_INSELP_Msk (0x7UL << PGA0CTL_ALL_INSELP_Pos)

typedef enum
{
    PGA0CTL_BIT_INSELP_GND       = 0,  /*!< Analog ground             */
    PGA0CTL_BIT_INSELP_DAC1      = 1,  /*!< DAC1 for common input     */
    PGA0CTL_BIT_INSELP_DAC2      = 2,  /*!< DAC2 output               */
    PGA0CTL_BIT_INSELP_ADC0      = 3,  /*!< ADC0 input from GPIO0     */
    PGA0CTL_BIT_INSELP_ADC6      = 4,  /*!< ADC6 input from GPIO6     */
    PGA0CTL_BIT_INSELP_ADC8      = 5,  /*!< ADC8 input from GPIO8     */
    PGA0CTL_BIT_INSELP_ADC10     = 6,  /*!< ADC10 input from GPIO10   */
    PGA0CTL_BIT_INSELP_ADC4      = 7,  /*!< ADC4 input from GPIO4     */
} PGA0CTL_BIT_INSELP;

#define PGA0CTL_ALL_INSELP_GND       ((0x0UL) << PGA0CTL_ALL_INSELP_Pos)
#define PGA0CTL_ALL_INSELP_DAC1      ((0x1UL) << PGA0CTL_ALL_INSELP_Pos)
#define PGA0CTL_ALL_INSELP_DAC2      ((0x2UL) << PGA0CTL_ALL_INSELP_Pos)
#define PGA0CTL_ALL_INSELP_ADC0      ((0x3UL) << PGA0CTL_ALL_INSELP_Pos)
#define PGA0CTL_ALL_INSELP_ADC6      ((0x4UL) << PGA0CTL_ALL_INSELP_Pos)
#define PGA0CTL_ALL_INSELP_ADC8      ((0x5UL) << PGA0CTL_ALL_INSELP_Pos)
#define PGA0CTL_ALL_INSELP_ADC10     ((0x6UL) << PGA0CTL_ALL_INSELP_Pos)
#define PGA0CTL_ALL_INSELP_ADC4      ((0x7UL) << PGA0CTL_ALL_INSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         INSELN
 *  @access     PGA->PGA0CTL.bit.INSELN
 *  @brief      PGA0 negative input select
 */
#define PGA0CTL_ALL_INSELN_Pos (7)
#define PGA0CTL_ALL_INSELN_Msk (0x7UL << PGA0CTL_ALL_INSELN_Pos)

typedef enum
{
    PGA0CTL_BIT_INSELN_GND      = 0,  /*!< Analog ground           */
    PGA0CTL_BIT_INSELN_DAC1     = 1,  /*!< DAC1 for common input   */
    PGA0CTL_BIT_INSELN_DAC3     = 2,  /*!< DAC3 output             */
    PGA0CTL_BIT_INSELN_ADC1     = 3,  /*!< ADC1 input from GPIO1   */
    PGA0CTL_BIT_INSELN_ADC7     = 4,  /*!< ADC7 input from GPIO7   */
    PGA0CTL_BIT_INSELN_ADC9     = 5,  /*!< ADC9 input from GPIO9   */
    PGA0CTL_BIT_INSELN_ADC5     = 6,  /*!< ADC5 input from GPIO5   */
    PGA0CTL_BIT_INSELN_ADC3     = 7,  /*!< ADC3 input from GPIO3   */
} PGA0CTL_BIT_INSELN;

#define PGA0CTL_ALL_INSELN_GND      ((0x0UL) << PGA0CTL_ALL_INSELN_Pos)
#define PGA0CTL_ALL_INSELN_DAC1     ((0x1UL) << PGA0CTL_ALL_INSELN_Pos)
#define PGA0CTL_ALL_INSELN_DAC3     ((0x2UL) << PGA0CTL_ALL_INSELN_Pos)
#define PGA0CTL_ALL_INSELN_ADC1     ((0x3UL) << PGA0CTL_ALL_INSELN_Pos)
#define PGA0CTL_ALL_INSELN_ADC7     ((0x4UL) << PGA0CTL_ALL_INSELN_Pos)
#define PGA0CTL_ALL_INSELN_ADC9     ((0x5UL) << PGA0CTL_ALL_INSELN_Pos)
#define PGA0CTL_ALL_INSELN_ADC5     ((0x6UL) << PGA0CTL_ALL_INSELN_Pos)
#define PGA0CTL_ALL_INSELN_ADC3     ((0x7UL) << PGA0CTL_ALL_INSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         GAINP
 *  @access     PGA->PGA0CTL.bit.GAINP
 *  @brief      PGA0 positive path gain
 */
#define PGA0CTL_ALL_GAINP_Pos (10)
#define PGA0CTL_ALL_GAINP_Msk (0x7UL << PGA0CTL_ALL_GAINP_Pos)

typedef enum
{
    PGA0CTL_BIT_GAINP_SINGLE_1X_DIFF_2X       = 0,  /*!< 1x for single-ended mode and 2x for differential mode     */
    PGA0CTL_BIT_GAINP_SINGLE_2X_DIFF_4X       = 1,  /*!< 2x for single-ended mode and 4x for differential mode     */
    PGA0CTL_BIT_GAINP_SINGLE_4X_DIFF_8X       = 2,  /*!< 4x for single-ended mode and 8x for differential mode     */
    PGA0CTL_BIT_GAINP_SINGLE_8X_DIFF_16X      = 3,  /*!< 8x for single-ended mode and 16x for differential mode    */
    PGA0CTL_BIT_GAINP_SINGLE_12X_DIFF_24X     = 4,  /*!< 12x for single-ended mode and 24x for differential mode   */
    PGA0CTL_BIT_GAINP_SINGLE_16X_DIFF_32X     = 5,  /*!< 16x for single-ended mode and 32x for differential mode   */
    PGA0CTL_BIT_GAINP_SINGLE_24X_DIFF_48X     = 6,  /*!< 24x for single-ended mode and 48x for differential mode   */
    PGA0CTL_BIT_GAINP_SINGLE_32X_DIFF_64X     = 7,  /*!< 32x for single-ended mode and 64x for differential mode   */
} PGA0CTL_BIT_GAINP;

#define PGA0CTL_ALL_GAINP_SINGLE_1X_DIFF_2X       ((0x0UL) << PGA0CTL_ALL_GAINP_Pos)
#define PGA0CTL_ALL_GAINP_SINGLE_2X_DIFF_4X       ((0x1UL) << PGA0CTL_ALL_GAINP_Pos)
#define PGA0CTL_ALL_GAINP_SINGLE_4X_DIFF_8X       ((0x2UL) << PGA0CTL_ALL_GAINP_Pos)
#define PGA0CTL_ALL_GAINP_SINGLE_8X_DIFF_16X      ((0x3UL) << PGA0CTL_ALL_GAINP_Pos)
#define PGA0CTL_ALL_GAINP_SINGLE_12X_DIFF_24X     ((0x4UL) << PGA0CTL_ALL_GAINP_Pos)
#define PGA0CTL_ALL_GAINP_SINGLE_16X_DIFF_32X     ((0x5UL) << PGA0CTL_ALL_GAINP_Pos)
#define PGA0CTL_ALL_GAINP_SINGLE_24X_DIFF_48X     ((0x6UL) << PGA0CTL_ALL_GAINP_Pos)
#define PGA0CTL_ALL_GAINP_SINGLE_32X_DIFF_64X     ((0x7UL) << PGA0CTL_ALL_GAINP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         GAINN
 *  @access     PGA->PGA0CTL.bit.GAINN
 *  @brief      PGA0 negative path gain
 */
#define PGA0CTL_ALL_GAINN_Pos (13)
#define PGA0CTL_ALL_GAINN_Msk (0x7UL << PGA0CTL_ALL_GAINN_Pos)

typedef enum
{
    PGA0CTL_BIT_GAINN_SINGLE_1X_DIFF_2X       = 0,  /*!< 1x for single-ended mode and 2x for differential mode     */
    PGA0CTL_BIT_GAINN_SINGLE_2X_DIFF_4X       = 1,  /*!< 2x for single-ended mode and 4x for differential mode     */
    PGA0CTL_BIT_GAINN_SINGLE_4X_DIFF_8X       = 2,  /*!< 4x for single-ended mode and 8x for differential mode     */
    PGA0CTL_BIT_GAINN_SINGLE_8X_DIFF_16X      = 3,  /*!< 8x for single-ended mode and 16x for differential mode    */
    PGA0CTL_BIT_GAINN_SINGLE_12X_DIFF_24X     = 4,  /*!< 12x for single-ended mode and 24x for differential mode   */
    PGA0CTL_BIT_GAINN_SINGLE_16X_DIFF_32X     = 5,  /*!< 16x for single-ended mode and 32x for differential mode   */
    PGA0CTL_BIT_GAINN_SINGLE_24X_DIFF_48X     = 6,  /*!< 24x for single-ended mode and 48x for differential mode   */
    PGA0CTL_BIT_GAINN_SINGLE_32X_DIFF_64X     = 7,  /*!< 32x for single-ended mode and 64x for differential mode   */
} PGA0CTL_BIT_GAINN;

#define PGA0CTL_ALL_GAINN_SINGLE_1X_DIFF_2X       ((0x0UL) << PGA0CTL_ALL_GAINN_Pos)
#define PGA0CTL_ALL_GAINN_SINGLE_2X_DIFF_4X       ((0x1UL) << PGA0CTL_ALL_GAINN_Pos)
#define PGA0CTL_ALL_GAINN_SINGLE_4X_DIFF_8X       ((0x2UL) << PGA0CTL_ALL_GAINN_Pos)
#define PGA0CTL_ALL_GAINN_SINGLE_8X_DIFF_16X      ((0x3UL) << PGA0CTL_ALL_GAINN_Pos)
#define PGA0CTL_ALL_GAINN_SINGLE_12X_DIFF_24X     ((0x4UL) << PGA0CTL_ALL_GAINN_Pos)
#define PGA0CTL_ALL_GAINN_SINGLE_16X_DIFF_32X     ((0x5UL) << PGA0CTL_ALL_GAINN_Pos)
#define PGA0CTL_ALL_GAINN_SINGLE_24X_DIFF_48X     ((0x6UL) << PGA0CTL_ALL_GAINN_Pos)
#define PGA0CTL_ALL_GAINN_SINGLE_32X_DIFF_64X     ((0x7UL) << PGA0CTL_ALL_GAINN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         BYPP
 *  @access     PGA->PGA0CTL.bit.BYPP
 *  @brief      PGA0 positive path bypass
 */
#define PGA0CTL_ALL_BYPP_Pos (16)
#define PGA0CTL_ALL_BYPP_Msk (0x1UL << PGA0CTL_ALL_BYPP_Pos)

typedef enum
{
    PGA0CTL_BIT_BYPP_DISABLE     = 0,  /*!< Not bypass   */
    PGA0CTL_BIT_BYPP_ENABLE      = 1,  /*!< Bypass       */
} PGA0CTL_BIT_BYPP;

#define PGA0CTL_ALL_BYPP_DISABLE     ((0x0UL) << PGA0CTL_ALL_BYPP_Pos)
#define PGA0CTL_ALL_BYPP_ENABLE      ((0x1UL) << PGA0CTL_ALL_BYPP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA0CTL         BYPN
 *  @access     PGA->PGA0CTL.bit.BYPN
 *  @brief      PGA0 negative path bypass
 */
#define PGA0CTL_ALL_BYPN_Pos (17)
#define PGA0CTL_ALL_BYPN_Msk (0x1UL << PGA0CTL_ALL_BYPN_Pos)

typedef enum
{
    PGA0CTL_BIT_BYPN_DISABLE     = 0,  /*!< Not bypass   */
    PGA0CTL_BIT_BYPN_ENABLE      = 1,  /*!< Bypass       */
} PGA0CTL_BIT_BYPN;

#define PGA0CTL_ALL_BYPN_DISABLE     ((0x0UL) << PGA0CTL_ALL_BYPN_Pos)
#define PGA0CTL_ALL_BYPN_ENABLE      ((0x1UL) << PGA0CTL_ALL_BYPN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         EN
 *  @access     PGA->PGA1CTL.bit.EN
 *  @brief      PGA1 enable
 */
#define PGA1CTL_ALL_EN_Pos (0)
#define PGA1CTL_ALL_EN_Msk (0x1UL << PGA1CTL_ALL_EN_Pos)

typedef enum
{
    PGA1CTL_BIT_EN_DISABLE     = 0,  /*!< Disable PGA1   */
    PGA1CTL_BIT_EN_ENABLE      = 1,  /*!< Enable PGA1    */
} PGA1CTL_BIT_EN;

#define PGA1CTL_ALL_EN_DISABLE     ((0x0UL) << PGA1CTL_ALL_EN_Pos)
#define PGA1CTL_ALL_EN_ENABLE      ((0x1UL) << PGA1CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         MODE
 *  @access     PGA->PGA1CTL.bit.MODE
 *  @brief      PGA1 mode
 */
#define PGA1CTL_ALL_MODE_Pos (1)
#define PGA1CTL_ALL_MODE_Msk (0x3UL << PGA1CTL_ALL_MODE_Pos)

typedef enum
{
    PGA1CTL_BIT_MODE_DIFF                = 0,  /*!< Differential mode                           */
    PGA1CTL_BIT_MODE_SINGLE_POSITIVE     = 1,  /*!< Single-ended mode with positive path only   */
    PGA1CTL_BIT_MODE_SINGLE_NEGATIVE     = 2,  /*!< Single-ended mode with negative path only   */
    PGA1CTL_BIT_MODE_SINGLE_BOTH         = 3,  /*!< Single-ended mode with both paths           */
} PGA1CTL_BIT_MODE;

#define PGA1CTL_ALL_MODE_DIFF                ((0x0UL) << PGA1CTL_ALL_MODE_Pos)
#define PGA1CTL_ALL_MODE_SINGLE_POSITIVE     ((0x1UL) << PGA1CTL_ALL_MODE_Pos)
#define PGA1CTL_ALL_MODE_SINGLE_NEGATIVE     ((0x2UL) << PGA1CTL_ALL_MODE_Pos)
#define PGA1CTL_ALL_MODE_SINGLE_BOTH         ((0x3UL) << PGA1CTL_ALL_MODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         CMSEL
 *  @access     PGA->PGA1CTL.bit.CMSEL
 *  @brief      PGA1 output common voltage selection for differential mode
 */
#define PGA1CTL_ALL_CMSEL_Pos (3)
#define PGA1CTL_ALL_CMSEL_Msk (0x1UL << PGA1CTL_ALL_CMSEL_Pos)

typedef enum
{
    PGA1CTL_BIT_CMSEL_NEGATIVE_AS_COMMON     = 0,  /*!< Select negative input voltage as output common voltage   */
    PGA1CTL_BIT_CMSEL_POSITIVE_AS_COMMON     = 1,  /*!< Select positive input voltage as output common voltage   */
} PGA1CTL_BIT_CMSEL;

#define PGA1CTL_ALL_CMSEL_NEGATIVE_AS_COMMON     ((0x0UL) << PGA1CTL_ALL_CMSEL_Pos)
#define PGA1CTL_ALL_CMSEL_POSITIVE_AS_COMMON     ((0x1UL) << PGA1CTL_ALL_CMSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         INSELP
 *  @access     PGA->PGA1CTL.bit.INSELP
 *  @brief      PGA1 positive input select
 */
#define PGA1CTL_ALL_INSELP_Pos (4)
#define PGA1CTL_ALL_INSELP_Msk (0x7UL << PGA1CTL_ALL_INSELP_Pos)

typedef enum
{
    PGA1CTL_BIT_INSELP_GND       = 0,  /*!< Analog ground             */
    PGA1CTL_BIT_INSELP_DAC1      = 1,  /*!< DAC1 for common input     */
    PGA1CTL_BIT_INSELP_ATEST     = 2,  /*!< ATEST output voltage      */
    PGA1CTL_BIT_INSELP_ADC0      = 3,  /*!< ADC0 input from GPIO0     */
    PGA1CTL_BIT_INSELP_ADC2      = 4,  /*!< ADC2 input from GPIO2     */
    PGA1CTL_BIT_INSELP_ADC8      = 5,  /*!< ADC8 input from GPIO8     */
    PGA1CTL_BIT_INSELP_ADC10     = 6,  /*!< ADC10 input from GPIO10   */
    PGA1CTL_BIT_INSELP_ADC9      = 7,  /*!< ADC9 input from GPIO9     */
} PGA1CTL_BIT_INSELP;

#define PGA1CTL_ALL_INSELP_GND       ((0x0UL) << PGA1CTL_ALL_INSELP_Pos)
#define PGA1CTL_ALL_INSELP_DAC1      ((0x1UL) << PGA1CTL_ALL_INSELP_Pos)
#define PGA1CTL_ALL_INSELP_ATEST     ((0x2UL) << PGA1CTL_ALL_INSELP_Pos)
#define PGA1CTL_ALL_INSELP_ADC0      ((0x3UL) << PGA1CTL_ALL_INSELP_Pos)
#define PGA1CTL_ALL_INSELP_ADC2      ((0x4UL) << PGA1CTL_ALL_INSELP_Pos)
#define PGA1CTL_ALL_INSELP_ADC8      ((0x5UL) << PGA1CTL_ALL_INSELP_Pos)
#define PGA1CTL_ALL_INSELP_ADC10     ((0x6UL) << PGA1CTL_ALL_INSELP_Pos)
#define PGA1CTL_ALL_INSELP_ADC9      ((0x7UL) << PGA1CTL_ALL_INSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         INSELN
 *  @access     PGA->PGA1CTL.bit.INSELN
 *  @brief      PGA1 negative input select
 */
#define PGA1CTL_ALL_INSELN_Pos (7)
#define PGA1CTL_ALL_INSELN_Msk (0x7UL << PGA1CTL_ALL_INSELN_Pos)

typedef enum
{
    PGA1CTL_BIT_INSELN_GND       = 0,  /*!< Analog ground             */
    PGA1CTL_BIT_INSELN_DAC1      = 1,  /*!< DAC1 for common input     */
    PGA1CTL_BIT_INSELN_VDD12     = 2,  /*!< Digital 1.2V power        */
    PGA1CTL_BIT_INSELN_ADC2      = 3,  /*!< ADC2 input from GPIO2     */
    PGA1CTL_BIT_INSELN_ADC3      = 4,  /*!< ADC3 input from GPIO3     */
    PGA1CTL_BIT_INSELN_ADC10     = 5,  /*!< ADC10 input from GPIO10   */
    PGA1CTL_BIT_INSELN_ADC11     = 6,  /*!< ADC11 input from GPIO11   */
    PGA1CTL_BIT_INSELN_ADC1      = 7,  /*!< ADC1 input from GPIO1     */
} PGA1CTL_BIT_INSELN;

#define PGA1CTL_ALL_INSELN_GND       ((0x0UL) << PGA1CTL_ALL_INSELN_Pos)
#define PGA1CTL_ALL_INSELN_DAC1      ((0x1UL) << PGA1CTL_ALL_INSELN_Pos)
#define PGA1CTL_ALL_INSELN_VDD12     ((0x2UL) << PGA1CTL_ALL_INSELN_Pos)
#define PGA1CTL_ALL_INSELN_ADC2      ((0x3UL) << PGA1CTL_ALL_INSELN_Pos)
#define PGA1CTL_ALL_INSELN_ADC3      ((0x4UL) << PGA1CTL_ALL_INSELN_Pos)
#define PGA1CTL_ALL_INSELN_ADC10     ((0x5UL) << PGA1CTL_ALL_INSELN_Pos)
#define PGA1CTL_ALL_INSELN_ADC11     ((0x6UL) << PGA1CTL_ALL_INSELN_Pos)
#define PGA1CTL_ALL_INSELN_ADC1      ((0x7UL) << PGA1CTL_ALL_INSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         GAINP
 *  @access     PGA->PGA1CTL.bit.GAINP
 *  @brief      PGA1 positive path gain
 */
#define PGA1CTL_ALL_GAINP_Pos (10)
#define PGA1CTL_ALL_GAINP_Msk (0x7UL << PGA1CTL_ALL_GAINP_Pos)

typedef enum
{
    PGA1CTL_BIT_GAINP_SINGLE_1X_DIFF_2X       = 0,  /*!< 1x for single-ended mode and 2x for differential mode     */
    PGA1CTL_BIT_GAINP_SINGLE_2X_DIFF_4X       = 1,  /*!< 2x for single-ended mode and 4x for differential mode     */
    PGA1CTL_BIT_GAINP_SINGLE_4X_DIFF_8X       = 2,  /*!< 4x for single-ended mode and 8x for differential mode     */
    PGA1CTL_BIT_GAINP_SINGLE_8X_DIFF_16X      = 3,  /*!< 8x for single-ended mode and 16x for differential mode    */
    PGA1CTL_BIT_GAINP_SINGLE_12X_DIFF_24X     = 4,  /*!< 12x for single-ended mode and 24x for differential mode   */
    PGA1CTL_BIT_GAINP_SINGLE_16X_DIFF_32X     = 5,  /*!< 16x for single-ended mode and 32x for differential mode   */
    PGA1CTL_BIT_GAINP_SINGLE_24X_DIFF_48X     = 6,  /*!< 24x for single-ended mode and 48x for differential mode   */
    PGA1CTL_BIT_GAINP_SINGLE_32X_DIFF_64X     = 7,  /*!< 32x for single-ended mode and 64x for differential mode   */
} PGA1CTL_BIT_GAINP;

#define PGA1CTL_ALL_GAINP_SINGLE_1X_DIFF_2X       ((0x0UL) << PGA1CTL_ALL_GAINP_Pos)
#define PGA1CTL_ALL_GAINP_SINGLE_2X_DIFF_4X       ((0x1UL) << PGA1CTL_ALL_GAINP_Pos)
#define PGA1CTL_ALL_GAINP_SINGLE_4X_DIFF_8X       ((0x2UL) << PGA1CTL_ALL_GAINP_Pos)
#define PGA1CTL_ALL_GAINP_SINGLE_8X_DIFF_16X      ((0x3UL) << PGA1CTL_ALL_GAINP_Pos)
#define PGA1CTL_ALL_GAINP_SINGLE_12X_DIFF_24X     ((0x4UL) << PGA1CTL_ALL_GAINP_Pos)
#define PGA1CTL_ALL_GAINP_SINGLE_16X_DIFF_32X     ((0x5UL) << PGA1CTL_ALL_GAINP_Pos)
#define PGA1CTL_ALL_GAINP_SINGLE_24X_DIFF_48X     ((0x6UL) << PGA1CTL_ALL_GAINP_Pos)
#define PGA1CTL_ALL_GAINP_SINGLE_32X_DIFF_64X     ((0x7UL) << PGA1CTL_ALL_GAINP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         GAINN
 *  @access     PGA->PGA1CTL.bit.GAINN
 *  @brief      PGA1 negative path gain
 */
#define PGA1CTL_ALL_GAINN_Pos (13)
#define PGA1CTL_ALL_GAINN_Msk (0x7UL << PGA1CTL_ALL_GAINN_Pos)

typedef enum
{
    PGA1CTL_BIT_GAINN_SINGLE_1X_DIFF_2X       = 0,  /*!< 1x for single-ended mode and 2x for differential mode     */
    PGA1CTL_BIT_GAINN_SINGLE_2X_DIFF_4X       = 1,  /*!< 2x for single-ended mode and 4x for differential mode     */
    PGA1CTL_BIT_GAINN_SINGLE_4X_DIFF_8X       = 2,  /*!< 4x for single-ended mode and 8x for differential mode     */
    PGA1CTL_BIT_GAINN_SINGLE_8X_DIFF_16X      = 3,  /*!< 8x for single-ended mode and 16x for differential mode    */
    PGA1CTL_BIT_GAINN_SINGLE_12X_DIFF_24X     = 4,  /*!< 12x for single-ended mode and 24x for differential mode   */
    PGA1CTL_BIT_GAINN_SINGLE_16X_DIFF_32X     = 5,  /*!< 16x for single-ended mode and 32x for differential mode   */
    PGA1CTL_BIT_GAINN_SINGLE_24X_DIFF_48X     = 6,  /*!< 24x for single-ended mode and 48x for differential mode   */
    PGA1CTL_BIT_GAINN_SINGLE_32X_DIFF_64X     = 7,  /*!< 32x for single-ended mode and 64x for differential mode   */
} PGA1CTL_BIT_GAINN;

#define PGA1CTL_ALL_GAINN_SINGLE_1X_DIFF_2X       ((0x0UL) << PGA1CTL_ALL_GAINN_Pos)
#define PGA1CTL_ALL_GAINN_SINGLE_2X_DIFF_4X       ((0x1UL) << PGA1CTL_ALL_GAINN_Pos)
#define PGA1CTL_ALL_GAINN_SINGLE_4X_DIFF_8X       ((0x2UL) << PGA1CTL_ALL_GAINN_Pos)
#define PGA1CTL_ALL_GAINN_SINGLE_8X_DIFF_16X      ((0x3UL) << PGA1CTL_ALL_GAINN_Pos)
#define PGA1CTL_ALL_GAINN_SINGLE_12X_DIFF_24X     ((0x4UL) << PGA1CTL_ALL_GAINN_Pos)
#define PGA1CTL_ALL_GAINN_SINGLE_16X_DIFF_32X     ((0x5UL) << PGA1CTL_ALL_GAINN_Pos)
#define PGA1CTL_ALL_GAINN_SINGLE_24X_DIFF_48X     ((0x6UL) << PGA1CTL_ALL_GAINN_Pos)
#define PGA1CTL_ALL_GAINN_SINGLE_32X_DIFF_64X     ((0x7UL) << PGA1CTL_ALL_GAINN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         BYPP
 *  @access     PGA->PGA1CTL.bit.BYPP
 *  @brief      PGA1 positive path bypass
 */
#define PGA1CTL_ALL_BYPP_Pos (16)
#define PGA1CTL_ALL_BYPP_Msk (0x1UL << PGA1CTL_ALL_BYPP_Pos)

typedef enum
{
    PGA1CTL_BIT_BYPP_DISABLE     = 0,  /*!< Not bypass   */
    PGA1CTL_BIT_BYPP_ENABLE      = 1,  /*!< Bypass       */
} PGA1CTL_BIT_BYPP;

#define PGA1CTL_ALL_BYPP_DISABLE     ((0x0UL) << PGA1CTL_ALL_BYPP_Pos)
#define PGA1CTL_ALL_BYPP_ENABLE      ((0x1UL) << PGA1CTL_ALL_BYPP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA1CTL         BYPN
 *  @access     PGA->PGA1CTL.bit.BYPN
 *  @brief      PGA1 negative path bypass
 */
#define PGA1CTL_ALL_BYPN_Pos (17)
#define PGA1CTL_ALL_BYPN_Msk (0x1UL << PGA1CTL_ALL_BYPN_Pos)

typedef enum
{
    PGA1CTL_BIT_BYPN_DISABLE     = 0,  /*!< Not bypass   */
    PGA1CTL_BIT_BYPN_ENABLE      = 1,  /*!< Bypass       */
} PGA1CTL_BIT_BYPN;

#define PGA1CTL_ALL_BYPN_DISABLE     ((0x0UL) << PGA1CTL_ALL_BYPN_Pos)
#define PGA1CTL_ALL_BYPN_ENABLE      ((0x1UL) << PGA1CTL_ALL_BYPN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         EN
 *  @access     PGA->PGA2CTL.bit.EN
 *  @brief      PGA2 enable
 */
#define PGA2CTL_ALL_EN_Pos (0)
#define PGA2CTL_ALL_EN_Msk (0x1UL << PGA2CTL_ALL_EN_Pos)

typedef enum
{
    PGA2CTL_BIT_EN_DISABLE     = 0,  /*!< Disable PGA2   */
    PGA2CTL_BIT_EN_ENABLE      = 1,  /*!< Enable PGA2    */
} PGA2CTL_BIT_EN;

#define PGA2CTL_ALL_EN_DISABLE     ((0x0UL) << PGA2CTL_ALL_EN_Pos)
#define PGA2CTL_ALL_EN_ENABLE      ((0x1UL) << PGA2CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         MODE
 *  @access     PGA->PGA2CTL.bit.MODE
 *  @brief      PGA2 mode
 */
#define PGA2CTL_ALL_MODE_Pos (1)
#define PGA2CTL_ALL_MODE_Msk (0x3UL << PGA2CTL_ALL_MODE_Pos)

typedef enum
{
    PGA2CTL_BIT_MODE_DIFF                = 0,  /*!< Differential mode                           */
    PGA2CTL_BIT_MODE_SINGLE_POSITIVE     = 1,  /*!< Single-ended mode with positive path only   */
    PGA2CTL_BIT_MODE_SINGLE_NEGATIVE     = 2,  /*!< Single-ended mode with negative path only   */
    PGA2CTL_BIT_MODE_SINGLE_BOTH         = 3,  /*!< Single-ended mode with both paths           */
} PGA2CTL_BIT_MODE;

#define PGA2CTL_ALL_MODE_DIFF                ((0x0UL) << PGA2CTL_ALL_MODE_Pos)
#define PGA2CTL_ALL_MODE_SINGLE_POSITIVE     ((0x1UL) << PGA2CTL_ALL_MODE_Pos)
#define PGA2CTL_ALL_MODE_SINGLE_NEGATIVE     ((0x2UL) << PGA2CTL_ALL_MODE_Pos)
#define PGA2CTL_ALL_MODE_SINGLE_BOTH         ((0x3UL) << PGA2CTL_ALL_MODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         CMSEL
 *  @access     PGA->PGA2CTL.bit.CMSEL
 *  @brief      PGA2 output common voltage selection for differential mode
 */
#define PGA2CTL_ALL_CMSEL_Pos (3)
#define PGA2CTL_ALL_CMSEL_Msk (0x1UL << PGA2CTL_ALL_CMSEL_Pos)

typedef enum
{
    PGA2CTL_BIT_CMSEL_NEGATIVE_AS_COMMON     = 0,  /*!< Select negative input voltage as output common voltage   */
    PGA2CTL_BIT_CMSEL_POSITIVE_AS_COMMON     = 1,  /*!< Select positive input voltage as output common voltage   */
} PGA2CTL_BIT_CMSEL;

#define PGA2CTL_ALL_CMSEL_NEGATIVE_AS_COMMON     ((0x0UL) << PGA2CTL_ALL_CMSEL_Pos)
#define PGA2CTL_ALL_CMSEL_POSITIVE_AS_COMMON     ((0x1UL) << PGA2CTL_ALL_CMSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         INSELP
 *  @access     PGA->PGA2CTL.bit.INSELP
 *  @brief      PGA2 positive input select
 */
#define PGA2CTL_ALL_INSELP_Pos (4)
#define PGA2CTL_ALL_INSELP_Msk (0x7UL << PGA2CTL_ALL_INSELP_Pos)

typedef enum
{
    PGA2CTL_BIT_INSELP_GND       = 0,  /*!< Analog ground             */
    PGA2CTL_BIT_INSELP_DAC1      = 1,  /*!< DAC1 for common input     */
    PGA2CTL_BIT_INSELP_TSEN1     = 2,  /*!< T-sensor output 1         */
    PGA2CTL_BIT_INSELP_ADC0      = 3,  /*!< ADC0 input from GPIO0     */
    PGA2CTL_BIT_INSELP_ADC4      = 4,  /*!< ADC4 input from GPIO4     */
    PGA2CTL_BIT_INSELP_ADC8      = 5,  /*!< ADC8 input from GPIO8     */
    PGA2CTL_BIT_INSELP_ADC12     = 6,  /*!< ADC12 input from GPIO12   */
    PGA2CTL_BIT_INSELP_ADC14     = 7,  /*!< ADC14 input from GPIO14   */
} PGA2CTL_BIT_INSELP;

#define PGA2CTL_ALL_INSELP_GND       ((0x0UL) << PGA2CTL_ALL_INSELP_Pos)
#define PGA2CTL_ALL_INSELP_DAC1      ((0x1UL) << PGA2CTL_ALL_INSELP_Pos)
#define PGA2CTL_ALL_INSELP_TSEN1     ((0x2UL) << PGA2CTL_ALL_INSELP_Pos)
#define PGA2CTL_ALL_INSELP_ADC0      ((0x3UL) << PGA2CTL_ALL_INSELP_Pos)
#define PGA2CTL_ALL_INSELP_ADC4      ((0x4UL) << PGA2CTL_ALL_INSELP_Pos)
#define PGA2CTL_ALL_INSELP_ADC8      ((0x5UL) << PGA2CTL_ALL_INSELP_Pos)
#define PGA2CTL_ALL_INSELP_ADC12     ((0x6UL) << PGA2CTL_ALL_INSELP_Pos)
#define PGA2CTL_ALL_INSELP_ADC14     ((0x7UL) << PGA2CTL_ALL_INSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         INSELN
 *  @access     PGA->PGA2CTL.bit.INSELN
 *  @brief      PGA2 negative input select
 */
#define PGA2CTL_ALL_INSELN_Pos (7)
#define PGA2CTL_ALL_INSELN_Msk (0x7UL << PGA2CTL_ALL_INSELN_Pos)

typedef enum
{
    PGA2CTL_BIT_INSELN_GND       = 0,  /*!< Analog ground             */
    PGA2CTL_BIT_INSELN_DAC1      = 1,  /*!< DAC1 for common input     */
    PGA2CTL_BIT_INSELN_TSEN0     = 2,  /*!< T-sensor output 0         */
    PGA2CTL_BIT_INSELN_ADC3      = 3,  /*!< ADC3 input from GPIO3     */
    PGA2CTL_BIT_INSELN_ADC5      = 4,  /*!< ADC5 input from GPIO5     */
    PGA2CTL_BIT_INSELN_ADC11     = 5,  /*!< ADC11 input from GPIO11   */
    PGA2CTL_BIT_INSELN_ADC13     = 6,  /*!< ADC13 input from GPIO13   */
    PGA2CTL_BIT_INSELN_ADC15     = 7,  /*!< ADC15 input from GPIO15   */
} PGA2CTL_BIT_INSELN;

#define PGA2CTL_ALL_INSELN_GND       ((0x0UL) << PGA2CTL_ALL_INSELN_Pos)
#define PGA2CTL_ALL_INSELN_DAC1      ((0x1UL) << PGA2CTL_ALL_INSELN_Pos)
#define PGA2CTL_ALL_INSELN_TSEN0     ((0x2UL) << PGA2CTL_ALL_INSELN_Pos)
#define PGA2CTL_ALL_INSELN_ADC3      ((0x3UL) << PGA2CTL_ALL_INSELN_Pos)
#define PGA2CTL_ALL_INSELN_ADC5      ((0x4UL) << PGA2CTL_ALL_INSELN_Pos)
#define PGA2CTL_ALL_INSELN_ADC11     ((0x5UL) << PGA2CTL_ALL_INSELN_Pos)
#define PGA2CTL_ALL_INSELN_ADC13     ((0x6UL) << PGA2CTL_ALL_INSELN_Pos)
#define PGA2CTL_ALL_INSELN_ADC15     ((0x7UL) << PGA2CTL_ALL_INSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         GAINP
 *  @access     PGA->PGA2CTL.bit.GAINP
 *  @brief      PGA2 positive path gain
 */
#define PGA2CTL_ALL_GAINP_Pos (10)
#define PGA2CTL_ALL_GAINP_Msk (0x7UL << PGA2CTL_ALL_GAINP_Pos)

typedef enum
{
    PGA2CTL_BIT_GAINP_SINGLE_1X_DIFF_2X       = 0,  /*!< 1x for single-ended mode and 2x for differential mode     */
    PGA2CTL_BIT_GAINP_SINGLE_2X_DIFF_4X       = 1,  /*!< 2x for single-ended mode and 4x for differential mode     */
    PGA2CTL_BIT_GAINP_SINGLE_4X_DIFF_8X       = 2,  /*!< 4x for single-ended mode and 8x for differential mode     */
    PGA2CTL_BIT_GAINP_SINGLE_8X_DIFF_16X      = 3,  /*!< 8x for single-ended mode and 16x for differential mode    */
    PGA2CTL_BIT_GAINP_SINGLE_12X_DIFF_24X     = 4,  /*!< 12x for single-ended mode and 24x for differential mode   */
    PGA2CTL_BIT_GAINP_SINGLE_16X_DIFF_32X     = 5,  /*!< 16x for single-ended mode and 32x for differential mode   */
    PGA2CTL_BIT_GAINP_SINGLE_24X_DIFF_48X     = 6,  /*!< 24x for single-ended mode and 48x for differential mode   */
    PGA2CTL_BIT_GAINP_SINGLE_32X_DIFF_64X     = 7,  /*!< 32x for single-ended mode and 64x for differential mode   */
} PGA2CTL_BIT_GAINP;

#define PGA2CTL_ALL_GAINP_SINGLE_1X_DIFF_2X       ((0x0UL) << PGA2CTL_ALL_GAINP_Pos)
#define PGA2CTL_ALL_GAINP_SINGLE_2X_DIFF_4X       ((0x1UL) << PGA2CTL_ALL_GAINP_Pos)
#define PGA2CTL_ALL_GAINP_SINGLE_4X_DIFF_8X       ((0x2UL) << PGA2CTL_ALL_GAINP_Pos)
#define PGA2CTL_ALL_GAINP_SINGLE_8X_DIFF_16X      ((0x3UL) << PGA2CTL_ALL_GAINP_Pos)
#define PGA2CTL_ALL_GAINP_SINGLE_12X_DIFF_24X     ((0x4UL) << PGA2CTL_ALL_GAINP_Pos)
#define PGA2CTL_ALL_GAINP_SINGLE_16X_DIFF_32X     ((0x5UL) << PGA2CTL_ALL_GAINP_Pos)
#define PGA2CTL_ALL_GAINP_SINGLE_24X_DIFF_48X     ((0x6UL) << PGA2CTL_ALL_GAINP_Pos)
#define PGA2CTL_ALL_GAINP_SINGLE_32X_DIFF_64X     ((0x7UL) << PGA2CTL_ALL_GAINP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         GAINN
 *  @access     PGA->PGA2CTL.bit.GAINN
 *  @brief      PGA2 negative path gain
 */
#define PGA2CTL_ALL_GAINN_Pos (13)
#define PGA2CTL_ALL_GAINN_Msk (0x7UL << PGA2CTL_ALL_GAINN_Pos)

typedef enum
{
    PGA2CTL_BIT_GAINN_SINGLE_1X_DIFF_2X       = 0,  /*!< 1x for single-ended mode and 2x for differential mode     */
    PGA2CTL_BIT_GAINN_SINGLE_2X_DIFF_4X       = 1,  /*!< 2x for single-ended mode and 4x for differential mode     */
    PGA2CTL_BIT_GAINN_SINGLE_4X_DIFF_8X       = 2,  /*!< 4x for single-ended mode and 8x for differential mode     */
    PGA2CTL_BIT_GAINN_SINGLE_8X_DIFF_16X      = 3,  /*!< 8x for single-ended mode and 16x for differential mode    */
    PGA2CTL_BIT_GAINN_SINGLE_12X_DIFF_24X     = 4,  /*!< 12x for single-ended mode and 24x for differential mode   */
    PGA2CTL_BIT_GAINN_SINGLE_16X_DIFF_32X     = 5,  /*!< 16x for single-ended mode and 32x for differential mode   */
    PGA2CTL_BIT_GAINN_SINGLE_24X_DIFF_48X     = 6,  /*!< 24x for single-ended mode and 48x for differential mode   */
    PGA2CTL_BIT_GAINN_SINGLE_32X_DIFF_64X     = 7,  /*!< 32x for single-ended mode and 64x for differential mode   */
} PGA2CTL_BIT_GAINN;

#define PGA2CTL_ALL_GAINN_SINGLE_1X_DIFF_2X       ((0x0UL) << PGA2CTL_ALL_GAINN_Pos)
#define PGA2CTL_ALL_GAINN_SINGLE_2X_DIFF_4X       ((0x1UL) << PGA2CTL_ALL_GAINN_Pos)
#define PGA2CTL_ALL_GAINN_SINGLE_4X_DIFF_8X       ((0x2UL) << PGA2CTL_ALL_GAINN_Pos)
#define PGA2CTL_ALL_GAINN_SINGLE_8X_DIFF_16X      ((0x3UL) << PGA2CTL_ALL_GAINN_Pos)
#define PGA2CTL_ALL_GAINN_SINGLE_12X_DIFF_24X     ((0x4UL) << PGA2CTL_ALL_GAINN_Pos)
#define PGA2CTL_ALL_GAINN_SINGLE_16X_DIFF_32X     ((0x5UL) << PGA2CTL_ALL_GAINN_Pos)
#define PGA2CTL_ALL_GAINN_SINGLE_24X_DIFF_48X     ((0x6UL) << PGA2CTL_ALL_GAINN_Pos)
#define PGA2CTL_ALL_GAINN_SINGLE_32X_DIFF_64X     ((0x7UL) << PGA2CTL_ALL_GAINN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         BYPP
 *  @access     PGA->PGA2CTL.bit.BYPP
 *  @brief      PGA2 positive path bypass
 */
#define PGA2CTL_ALL_BYPP_Pos (16)
#define PGA2CTL_ALL_BYPP_Msk (0x1UL << PGA2CTL_ALL_BYPP_Pos)

typedef enum
{
    PGA2CTL_BIT_BYPP_DISABLE     = 0,  /*!< Not bypass   */
    PGA2CTL_BIT_BYPP_ENABLE      = 1,  /*!< Bypass       */
} PGA2CTL_BIT_BYPP;

#define PGA2CTL_ALL_BYPP_DISABLE     ((0x0UL) << PGA2CTL_ALL_BYPP_Pos)
#define PGA2CTL_ALL_BYPP_ENABLE      ((0x1UL) << PGA2CTL_ALL_BYPP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGA2CTL         BYPN
 *  @access     PGA->PGA2CTL.bit.BYPN
 *  @brief      PGA2 negative path bypass
 */
#define PGA2CTL_ALL_BYPN_Pos (17)
#define PGA2CTL_ALL_BYPN_Msk (0x1UL << PGA2CTL_ALL_BYPN_Pos)

typedef enum
{
    PGA2CTL_BIT_BYPN_DISABLE     = 0,  /*!< Not bypass   */
    PGA2CTL_BIT_BYPN_ENABLE      = 1,  /*!< Bypass       */
} PGA2CTL_BIT_BYPN;

#define PGA2CTL_ALL_BYPN_DISABLE     ((0x0UL) << PGA2CTL_ALL_BYPN_Pos)
#define PGA2CTL_ALL_BYPN_ENABLE      ((0x1UL) << PGA2CTL_ALL_BYPN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PGA             PGAREGKEY       KEY
 *  @access     PGA->PGAREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected PGA registers
 */
#define PGAREGKEY_ALL_KEY_Pos (0)
#define PGAREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << PGAREGKEY_ALL_KEY_Pos)

#define PGAREGKEY_BIT_KEY

#define PGAREGKEY_ALL_KEY_(x) ((x) << PGAREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     COMP
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP0L
 *  @access     COMP->COMPFLTOUT.bit.COMP0L
 *  @brief      COMP0L filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP0L_Pos (0)
#define COMPFLTOUT_ALL_COMP0L_Msk (0x1UL << COMPFLTOUT_ALL_COMP0L_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP0L_LOW      = 0,  /*!< Input is higher than the low-boundary   */
    COMPFLTOUT_BIT_COMP0L_HIGH     = 1,  /*!< Input is lower than the low-boundary    */
} COMPFLTOUT_BIT_COMP0L;

#define COMPFLTOUT_ALL_COMP0L_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP0L_Pos)
#define COMPFLTOUT_ALL_COMP0L_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP0L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP0H
 *  @access     COMP->COMPFLTOUT.bit.COMP0H
 *  @brief      COMP0H filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP0H_Pos (1)
#define COMPFLTOUT_ALL_COMP0H_Msk (0x1UL << COMPFLTOUT_ALL_COMP0H_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP0H_LOW      = 0,  /*!< Input is lower than the high-boundary    */
    COMPFLTOUT_BIT_COMP0H_HIGH     = 1,  /*!< Input is higher than the high-boundary   */
} COMPFLTOUT_BIT_COMP0H;

#define COMPFLTOUT_ALL_COMP0H_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP0H_Pos)
#define COMPFLTOUT_ALL_COMP0H_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP0H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP1L
 *  @access     COMP->COMPFLTOUT.bit.COMP1L
 *  @brief      COMP1L filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP1L_Pos (2)
#define COMPFLTOUT_ALL_COMP1L_Msk (0x1UL << COMPFLTOUT_ALL_COMP1L_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP1L_LOW      = 0,  /*!< Input is higher than the low-boundary   */
    COMPFLTOUT_BIT_COMP1L_HIGH     = 1,  /*!< Input is lower than the low-boundary    */
} COMPFLTOUT_BIT_COMP1L;

#define COMPFLTOUT_ALL_COMP1L_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP1L_Pos)
#define COMPFLTOUT_ALL_COMP1L_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP1L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP1H
 *  @access     COMP->COMPFLTOUT.bit.COMP1H
 *  @brief      COMP1H filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP1H_Pos (3)
#define COMPFLTOUT_ALL_COMP1H_Msk (0x1UL << COMPFLTOUT_ALL_COMP1H_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP1H_LOW      = 0,  /*!< Input is lower than the high-boundary    */
    COMPFLTOUT_BIT_COMP1H_HIGH     = 1,  /*!< Input is higher than the high-boundary   */
} COMPFLTOUT_BIT_COMP1H;

#define COMPFLTOUT_ALL_COMP1H_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP1H_Pos)
#define COMPFLTOUT_ALL_COMP1H_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP1H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP2L
 *  @access     COMP->COMPFLTOUT.bit.COMP2L
 *  @brief      COMP2L filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP2L_Pos (4)
#define COMPFLTOUT_ALL_COMP2L_Msk (0x1UL << COMPFLTOUT_ALL_COMP2L_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP2L_LOW      = 0,  /*!< Input is higher than the low-boundary   */
    COMPFLTOUT_BIT_COMP2L_HIGH     = 1,  /*!< Input is lower than the low-boundary    */
} COMPFLTOUT_BIT_COMP2L;

#define COMPFLTOUT_ALL_COMP2L_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP2L_Pos)
#define COMPFLTOUT_ALL_COMP2L_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP2L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP2H
 *  @access     COMP->COMPFLTOUT.bit.COMP2H
 *  @brief      COMP2H filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP2H_Pos (5)
#define COMPFLTOUT_ALL_COMP2H_Msk (0x1UL << COMPFLTOUT_ALL_COMP2H_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP2H_LOW      = 0,  /*!< Input is lower than the high-boundary    */
    COMPFLTOUT_BIT_COMP2H_HIGH     = 1,  /*!< Input is higher than the high-boundary   */
} COMPFLTOUT_BIT_COMP2H;

#define COMPFLTOUT_ALL_COMP2H_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP2H_Pos)
#define COMPFLTOUT_ALL_COMP2H_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP2H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP3L
 *  @access     COMP->COMPFLTOUT.bit.COMP3L
 *  @brief      COMP3L filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP3L_Pos (6)
#define COMPFLTOUT_ALL_COMP3L_Msk (0x1UL << COMPFLTOUT_ALL_COMP3L_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP3L_LOW      = 0,  /*!< Input is higher than the low-boundary   */
    COMPFLTOUT_BIT_COMP3L_HIGH     = 1,  /*!< Input is lower than the low-boundary    */
} COMPFLTOUT_BIT_COMP3L;

#define COMPFLTOUT_ALL_COMP3L_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP3L_Pos)
#define COMPFLTOUT_ALL_COMP3L_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP3L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP3H
 *  @access     COMP->COMPFLTOUT.bit.COMP3H
 *  @brief      COMP3H filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP3H_Pos (7)
#define COMPFLTOUT_ALL_COMP3H_Msk (0x1UL << COMPFLTOUT_ALL_COMP3H_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP3H_LOW      = 0,  /*!< Input is lower than the high-boundary    */
    COMPFLTOUT_BIT_COMP3H_HIGH     = 1,  /*!< Input is higher than the high-boundary   */
} COMPFLTOUT_BIT_COMP3H;

#define COMPFLTOUT_ALL_COMP3H_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP3H_Pos)
#define COMPFLTOUT_ALL_COMP3H_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP3H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP4L
 *  @access     COMP->COMPFLTOUT.bit.COMP4L
 *  @brief      COMP4L filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP4L_Pos (8)
#define COMPFLTOUT_ALL_COMP4L_Msk (0x1UL << COMPFLTOUT_ALL_COMP4L_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP4L_LOW      = 0,  /*!< Input is higher than the low-boundary   */
    COMPFLTOUT_BIT_COMP4L_HIGH     = 1,  /*!< Input is lower than the low-boundary    */
} COMPFLTOUT_BIT_COMP4L;

#define COMPFLTOUT_ALL_COMP4L_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP4L_Pos)
#define COMPFLTOUT_ALL_COMP4L_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP4L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPFLTOUT      COMP4H
 *  @access     COMP->COMPFLTOUT.bit.COMP4H
 *  @brief      COMP4H filtered status without latch
 */
#define COMPFLTOUT_ALL_COMP4H_Pos (9)
#define COMPFLTOUT_ALL_COMP4H_Msk (0x1UL << COMPFLTOUT_ALL_COMP4H_Pos)

typedef enum
{
    COMPFLTOUT_BIT_COMP4H_LOW      = 0,  /*!< Input is lower than the high-boundary    */
    COMPFLTOUT_BIT_COMP4H_HIGH     = 1,  /*!< Input is higher than the high-boundary   */
} COMPFLTOUT_BIT_COMP4H;

#define COMPFLTOUT_ALL_COMP4H_LOW      ((0x0UL) << COMPFLTOUT_ALL_COMP4H_Pos)
#define COMPFLTOUT_ALL_COMP4H_HIGH     ((0x1UL) << COMPFLTOUT_ALL_COMP4H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP0L
 *  @access     COMP->COMPSTS.bit.COMP0L
 *  @brief      Latched COMPFLTOUT[COMP0L]
 */
#define COMPSTS_ALL_COMP0L_Pos (0)
#define COMPSTS_ALL_COMP0L_Msk (0x1UL << COMPSTS_ALL_COMP0L_Pos)

typedef enum
{
    COMPSTS_BIT_COMP0L_LOW      = 0,  /*!< Input has been higher than the low-boundary   */
    COMPSTS_BIT_COMP0L_HIGH     = 1,  /*!< Input has been lower than the low-boundary    */
} COMPSTS_BIT_COMP0L;

#define COMPSTS_ALL_COMP0L_LOW      ((0x0UL) << COMPSTS_ALL_COMP0L_Pos)
#define COMPSTS_ALL_COMP0L_HIGH     ((0x1UL) << COMPSTS_ALL_COMP0L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP0H
 *  @access     COMP->COMPSTS.bit.COMP0H
 *  @brief      Latched COMPFLTOUT[COMP0H]
 */
#define COMPSTS_ALL_COMP0H_Pos (1)
#define COMPSTS_ALL_COMP0H_Msk (0x1UL << COMPSTS_ALL_COMP0H_Pos)

typedef enum
{
    COMPSTS_BIT_COMP0H_LOW      = 0,  /*!< Input has been lower than the high-boundary    */
    COMPSTS_BIT_COMP0H_HIGH     = 1,  /*!< Input has been higher than the high-boundary   */
} COMPSTS_BIT_COMP0H;

#define COMPSTS_ALL_COMP0H_LOW      ((0x0UL) << COMPSTS_ALL_COMP0H_Pos)
#define COMPSTS_ALL_COMP0H_HIGH     ((0x1UL) << COMPSTS_ALL_COMP0H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP1L
 *  @access     COMP->COMPSTS.bit.COMP1L
 *  @brief      Latched COMPFLTOUT[COMP1L]
 */
#define COMPSTS_ALL_COMP1L_Pos (2)
#define COMPSTS_ALL_COMP1L_Msk (0x1UL << COMPSTS_ALL_COMP1L_Pos)

typedef enum
{
    COMPSTS_BIT_COMP1L_LOW      = 0,  /*!< Input has been higher than the low-boundary   */
    COMPSTS_BIT_COMP1L_HIGH     = 1,  /*!< Input has been lower than the low-boundary    */
} COMPSTS_BIT_COMP1L;

#define COMPSTS_ALL_COMP1L_LOW      ((0x0UL) << COMPSTS_ALL_COMP1L_Pos)
#define COMPSTS_ALL_COMP1L_HIGH     ((0x1UL) << COMPSTS_ALL_COMP1L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP1H
 *  @access     COMP->COMPSTS.bit.COMP1H
 *  @brief      Latched COMPFLTOUT[COMP1H]
 */
#define COMPSTS_ALL_COMP1H_Pos (3)
#define COMPSTS_ALL_COMP1H_Msk (0x1UL << COMPSTS_ALL_COMP1H_Pos)

typedef enum
{
    COMPSTS_BIT_COMP1H_LOW      = 0,  /*!< Input has been lower than the high-boundary    */
    COMPSTS_BIT_COMP1H_HIGH     = 1,  /*!< Input has been higher than the high-boundary   */
} COMPSTS_BIT_COMP1H;

#define COMPSTS_ALL_COMP1H_LOW      ((0x0UL) << COMPSTS_ALL_COMP1H_Pos)
#define COMPSTS_ALL_COMP1H_HIGH     ((0x1UL) << COMPSTS_ALL_COMP1H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP2L
 *  @access     COMP->COMPSTS.bit.COMP2L
 *  @brief      Latched COMPFLTOUT[COMP2L]
 */
#define COMPSTS_ALL_COMP2L_Pos (4)
#define COMPSTS_ALL_COMP2L_Msk (0x1UL << COMPSTS_ALL_COMP2L_Pos)

typedef enum
{
    COMPSTS_BIT_COMP2L_LOW      = 0,  /*!< Input has been higher than the low-boundary   */
    COMPSTS_BIT_COMP2L_HIGH     = 1,  /*!< Input has been lower than the low-boundary    */
} COMPSTS_BIT_COMP2L;

#define COMPSTS_ALL_COMP2L_LOW      ((0x0UL) << COMPSTS_ALL_COMP2L_Pos)
#define COMPSTS_ALL_COMP2L_HIGH     ((0x1UL) << COMPSTS_ALL_COMP2L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP2H
 *  @access     COMP->COMPSTS.bit.COMP2H
 *  @brief      Latched COMPFLTOUT[COMP2H]
 */
#define COMPSTS_ALL_COMP2H_Pos (5)
#define COMPSTS_ALL_COMP2H_Msk (0x1UL << COMPSTS_ALL_COMP2H_Pos)

typedef enum
{
    COMPSTS_BIT_COMP2H_LOW      = 0,  /*!< Input has been lower than the high-boundary    */
    COMPSTS_BIT_COMP2H_HIGH     = 1,  /*!< Input has been higher than the high-boundary   */
} COMPSTS_BIT_COMP2H;

#define COMPSTS_ALL_COMP2H_LOW      ((0x0UL) << COMPSTS_ALL_COMP2H_Pos)
#define COMPSTS_ALL_COMP2H_HIGH     ((0x1UL) << COMPSTS_ALL_COMP2H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP3L
 *  @access     COMP->COMPSTS.bit.COMP3L
 *  @brief      Latched COMPFLTOUT[COMP3L]
 */
#define COMPSTS_ALL_COMP3L_Pos (6)
#define COMPSTS_ALL_COMP3L_Msk (0x1UL << COMPSTS_ALL_COMP3L_Pos)

typedef enum
{
    COMPSTS_BIT_COMP3L_LOW      = 0,  /*!< Input has been higher than the low-boundary   */
    COMPSTS_BIT_COMP3L_HIGH     = 1,  /*!< Input has been lower than the low-boundary    */
} COMPSTS_BIT_COMP3L;

#define COMPSTS_ALL_COMP3L_LOW      ((0x0UL) << COMPSTS_ALL_COMP3L_Pos)
#define COMPSTS_ALL_COMP3L_HIGH     ((0x1UL) << COMPSTS_ALL_COMP3L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP3H
 *  @access     COMP->COMPSTS.bit.COMP3H
 *  @brief      Latched COMPFLTOUT[COMP3H]
 */
#define COMPSTS_ALL_COMP3H_Pos (7)
#define COMPSTS_ALL_COMP3H_Msk (0x1UL << COMPSTS_ALL_COMP3H_Pos)

typedef enum
{
    COMPSTS_BIT_COMP3H_LOW      = 0,  /*!< Input has been lower than the high-boundary    */
    COMPSTS_BIT_COMP3H_HIGH     = 1,  /*!< Input has been higher than the high-boundary   */
} COMPSTS_BIT_COMP3H;

#define COMPSTS_ALL_COMP3H_LOW      ((0x0UL) << COMPSTS_ALL_COMP3H_Pos)
#define COMPSTS_ALL_COMP3H_HIGH     ((0x1UL) << COMPSTS_ALL_COMP3H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP4L
 *  @access     COMP->COMPSTS.bit.COMP4L
 *  @brief      Latched COMPFLTOUT[COMP4L]
 */
#define COMPSTS_ALL_COMP4L_Pos (8)
#define COMPSTS_ALL_COMP4L_Msk (0x1UL << COMPSTS_ALL_COMP4L_Pos)

typedef enum
{
    COMPSTS_BIT_COMP4L_LOW      = 0,  /*!< Input has been higher than the low-boundary   */
    COMPSTS_BIT_COMP4L_HIGH     = 1,  /*!< Input has been lower than the low-boundary    */
} COMPSTS_BIT_COMP4L;

#define COMPSTS_ALL_COMP4L_LOW      ((0x0UL) << COMPSTS_ALL_COMP4L_Pos)
#define COMPSTS_ALL_COMP4L_HIGH     ((0x1UL) << COMPSTS_ALL_COMP4L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTS         COMP4H
 *  @access     COMP->COMPSTS.bit.COMP4H
 *  @brief      Latched COMPFLTOUT[COMP4H]
 */
#define COMPSTS_ALL_COMP4H_Pos (9)
#define COMPSTS_ALL_COMP4H_Msk (0x1UL << COMPSTS_ALL_COMP4H_Pos)

typedef enum
{
    COMPSTS_BIT_COMP4H_LOW      = 0,  /*!< Input has been lower than the high-boundary    */
    COMPSTS_BIT_COMP4H_HIGH     = 1,  /*!< Input has been higher than the high-boundary   */
} COMPSTS_BIT_COMP4H;

#define COMPSTS_ALL_COMP4H_LOW      ((0x0UL) << COMPSTS_ALL_COMP4H_Pos)
#define COMPSTS_ALL_COMP4H_HIGH     ((0x1UL) << COMPSTS_ALL_COMP4H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP0L
 *  @access     COMP->COMPSTSCLR.bit.COMP0L
 *  @brief      Latched COMP0L status clear
 */
#define COMPSTSCLR_ALL_COMP0L_Pos (0)
#define COMPSTSCLR_ALL_COMP0L_Msk (0x1UL << COMPSTSCLR_ALL_COMP0L_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP0L_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP0L_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP0L]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP0L;

#define COMPSTSCLR_ALL_COMP0L_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP0L_Pos)
#define COMPSTSCLR_ALL_COMP0L_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP0L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP0H
 *  @access     COMP->COMPSTSCLR.bit.COMP0H
 *  @brief      Latched COMP0H status clear
 */
#define COMPSTSCLR_ALL_COMP0H_Pos (1)
#define COMPSTSCLR_ALL_COMP0H_Msk (0x1UL << COMPSTSCLR_ALL_COMP0H_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP0H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP0H_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP0H]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP0H;

#define COMPSTSCLR_ALL_COMP0H_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP0H_Pos)
#define COMPSTSCLR_ALL_COMP0H_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP0H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP1L
 *  @access     COMP->COMPSTSCLR.bit.COMP1L
 *  @brief      Latched COMP1L status clear
 */
#define COMPSTSCLR_ALL_COMP1L_Pos (2)
#define COMPSTSCLR_ALL_COMP1L_Msk (0x1UL << COMPSTSCLR_ALL_COMP1L_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP1L_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP1L_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP1L]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP1L;

#define COMPSTSCLR_ALL_COMP1L_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP1L_Pos)
#define COMPSTSCLR_ALL_COMP1L_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP1L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP1H
 *  @access     COMP->COMPSTSCLR.bit.COMP1H
 *  @brief      Latched COMP1H status clear
 */
#define COMPSTSCLR_ALL_COMP1H_Pos (3)
#define COMPSTSCLR_ALL_COMP1H_Msk (0x1UL << COMPSTSCLR_ALL_COMP1H_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP1H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP1H_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP1H]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP1H;

#define COMPSTSCLR_ALL_COMP1H_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP1H_Pos)
#define COMPSTSCLR_ALL_COMP1H_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP1H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP2L
 *  @access     COMP->COMPSTSCLR.bit.COMP2L
 *  @brief      Latched COMP2L status clear
 */
#define COMPSTSCLR_ALL_COMP2L_Pos (4)
#define COMPSTSCLR_ALL_COMP2L_Msk (0x1UL << COMPSTSCLR_ALL_COMP2L_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP2L_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP2L_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP2L]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP2L;

#define COMPSTSCLR_ALL_COMP2L_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP2L_Pos)
#define COMPSTSCLR_ALL_COMP2L_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP2L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP2H
 *  @access     COMP->COMPSTSCLR.bit.COMP2H
 *  @brief      Latched COMP2H status clear
 */
#define COMPSTSCLR_ALL_COMP2H_Pos (5)
#define COMPSTSCLR_ALL_COMP2H_Msk (0x1UL << COMPSTSCLR_ALL_COMP2H_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP2H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP2H_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP2H]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP2H;

#define COMPSTSCLR_ALL_COMP2H_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP2H_Pos)
#define COMPSTSCLR_ALL_COMP2H_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP2H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP3L
 *  @access     COMP->COMPSTSCLR.bit.COMP3L
 *  @brief      Latched COMP3L status clear
 */
#define COMPSTSCLR_ALL_COMP3L_Pos (6)
#define COMPSTSCLR_ALL_COMP3L_Msk (0x1UL << COMPSTSCLR_ALL_COMP3L_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP3L_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP3L_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP3L]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP3L;

#define COMPSTSCLR_ALL_COMP3L_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP3L_Pos)
#define COMPSTSCLR_ALL_COMP3L_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP3L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP3H
 *  @access     COMP->COMPSTSCLR.bit.COMP3H
 *  @brief      Latched COMP3H status clear
 */
#define COMPSTSCLR_ALL_COMP3H_Pos (7)
#define COMPSTSCLR_ALL_COMP3H_Msk (0x1UL << COMPSTSCLR_ALL_COMP3H_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP3H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP3H_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP3H]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP3H;

#define COMPSTSCLR_ALL_COMP3H_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP3H_Pos)
#define COMPSTSCLR_ALL_COMP3H_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP3H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP4L
 *  @access     COMP->COMPSTSCLR.bit.COMP4L
 *  @brief      Latched COMP4L status clear
 */
#define COMPSTSCLR_ALL_COMP4L_Pos (8)
#define COMPSTSCLR_ALL_COMP4L_Msk (0x1UL << COMPSTSCLR_ALL_COMP4L_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP4L_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP4L_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP4L]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP4L;

#define COMPSTSCLR_ALL_COMP4L_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP4L_Pos)
#define COMPSTSCLR_ALL_COMP4L_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP4L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPSTSCLR      COMP4H
 *  @access     COMP->COMPSTSCLR.bit.COMP4H
 *  @brief      Latched COMP4H status clear
 */
#define COMPSTSCLR_ALL_COMP4H_Pos (9)
#define COMPSTSCLR_ALL_COMP4H_Msk (0x1UL << COMPSTSCLR_ALL_COMP4H_Pos)

typedef enum
{
    COMPSTSCLR_BIT_COMP4H_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    COMPSTSCLR_BIT_COMP4H_CLEAR         = 1,  /*!< Write a 1 clears COMPSTS[COMP4H]. This bit is self-cleared.   */
} COMPSTSCLR_BIT_COMP4H;

#define COMPSTSCLR_ALL_COMP4H_NO_EFFECT     ((0x0UL) << COMPSTSCLR_ALL_COMP4H_Pos)
#define COMPSTSCLR_ALL_COMP4H_CLEAR         ((0x1UL) << COMPSTSCLR_ALL_COMP4H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0CTL        ENL
 *  @access     COMP->COMP0CTL.bit.ENL
 *  @brief      COMP0L enable
 */
#define COMP0CTL_ALL_ENL_Pos (0)
#define COMP0CTL_ALL_ENL_Msk (0x1UL << COMP0CTL_ALL_ENL_Pos)

typedef enum
{
    COMP0CTL_BIT_ENL_DISABLE     = 0,  /*!< Disable COMP0L   */
    COMP0CTL_BIT_ENL_ENABLE      = 1,  /*!< Enable COMP0L    */
} COMP0CTL_BIT_ENL;

#define COMP0CTL_ALL_ENL_DISABLE     ((0x0UL) << COMP0CTL_ALL_ENL_Pos)
#define COMP0CTL_ALL_ENL_ENABLE      ((0x1UL) << COMP0CTL_ALL_ENL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0CTL        ENH
 *  @access     COMP->COMP0CTL.bit.ENH
 *  @brief      COMP0H enable
 */
#define COMP0CTL_ALL_ENH_Pos (1)
#define COMP0CTL_ALL_ENH_Msk (0x1UL << COMP0CTL_ALL_ENH_Pos)

typedef enum
{
    COMP0CTL_BIT_ENH_DISABLE     = 0,  /*!< Disable COMP0H   */
    COMP0CTL_BIT_ENH_ENABLE      = 1,  /*!< Enable COMP0H    */
} COMP0CTL_BIT_ENH;

#define COMP0CTL_ALL_ENH_DISABLE     ((0x0UL) << COMP0CTL_ALL_ENH_Pos)
#define COMP0CTL_ALL_ENH_ENABLE      ((0x1UL) << COMP0CTL_ALL_ENH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0CTL        PHCMPEN
 *  @access     COMP->COMP0CTL.bit.PHCMPEN
 *  @brief      COMP0 phase comparison enable
 */
#define COMP0CTL_ALL_PHCMPEN_Pos (2)
#define COMP0CTL_ALL_PHCMPEN_Msk (0x1UL << COMP0CTL_ALL_PHCMPEN_Pos)

typedef enum
{
    COMP0CTL_BIT_PHCMPEN_DISABLE     = 0,  /*!< Normal operation        */
    COMP0CTL_BIT_PHCMPEN_ENABLE      = 1,  /*!< Phase comparison mode   */
} COMP0CTL_BIT_PHCMPEN;

#define COMP0CTL_ALL_PHCMPEN_DISABLE     ((0x0UL) << COMP0CTL_ALL_PHCMPEN_Pos)
#define COMP0CTL_ALL_PHCMPEN_ENABLE      ((0x1UL) << COMP0CTL_ALL_PHCMPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0CTL        HYSTSEL
 *  @access     COMP->COMP0CTL.bit.HYSTSEL
 *  @brief      COMP0 hysteresis select
 */
#define COMP0CTL_ALL_HYSTSEL_Pos (3)
#define COMP0CTL_ALL_HYSTSEL_Msk (0x3UL << COMP0CTL_ALL_HYSTSEL_Pos)

typedef enum
{
    COMP0CTL_BIT_HYSTSEL_0_MV      = 0,  /*!< 0 mV    */
    COMP0CTL_BIT_HYSTSEL_12_MV     = 1,  /*!< 12 mV   */
    COMP0CTL_BIT_HYSTSEL_24_MV     = 2,  /*!< 24 mV   */
    COMP0CTL_BIT_HYSTSEL_36_MV     = 3,  /*!< 36 mV   */
} COMP0CTL_BIT_HYSTSEL;

#define COMP0CTL_ALL_HYSTSEL_0_MV      ((0x0UL) << COMP0CTL_ALL_HYSTSEL_Pos)
#define COMP0CTL_ALL_HYSTSEL_12_MV     ((0x1UL) << COMP0CTL_ALL_HYSTSEL_Pos)
#define COMP0CTL_ALL_HYSTSEL_24_MV     ((0x2UL) << COMP0CTL_ALL_HYSTSEL_Pos)
#define COMP0CTL_ALL_HYSTSEL_36_MV     ((0x3UL) << COMP0CTL_ALL_HYSTSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0CTL        INSEL
 *  @access     COMP->COMP0CTL.bit.INSEL
 *  @brief      COMP0 input select
 */
#define COMP0CTL_ALL_INSEL_Pos (5)
#define COMP0CTL_ALL_INSEL_Msk (0x3UL << COMP0CTL_ALL_INSEL_Pos)

typedef enum
{
    COMP0CTL_BIT_INSEL_PGA0N_OUT     = 0,  /*!< PGA0 negative output    */
    COMP0CTL_BIT_INSEL_PGA0P_OUT     = 1,  /*!< PGA0 positive output    */
    COMP0CTL_BIT_INSEL_ADC0          = 2,  /*!< ADC0 input from GPIO0   */
    COMP0CTL_BIT_INSEL_ADC8          = 3,  /*!< ADC8 input from GPIO8   */
} COMP0CTL_BIT_INSEL;

#define COMP0CTL_ALL_INSEL_PGA0N_OUT     ((0x0UL) << COMP0CTL_ALL_INSEL_Pos)
#define COMP0CTL_ALL_INSEL_PGA0P_OUT     ((0x1UL) << COMP0CTL_ALL_INSEL_Pos)
#define COMP0CTL_ALL_INSEL_ADC0          ((0x2UL) << COMP0CTL_ALL_INSEL_Pos)
#define COMP0CTL_ALL_INSEL_ADC8          ((0x3UL) << COMP0CTL_ALL_INSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0CTL        REFSEL
 *  @access     COMP->COMP0CTL.bit.REFSEL
 *  @brief      COMP0 reference select
 */
#define COMP0CTL_ALL_REFSEL_Pos (7)
#define COMP0CTL_ALL_REFSEL_Msk (0x3UL << COMP0CTL_ALL_REFSEL_Pos)

typedef enum
{
    COMP0CTL_BIT_REFSEL_PGA0P_OUT_OR_DAC0_DAC1     = 0,  /*!< PGA0 positive output when PHCMPEN = 1;                                     
                                                              DAC0 as too-high reference and DAC1 as too-low reference when PHCMPEN = 0   */
    COMP0CTL_BIT_REFSEL_PGA0N_OUT_OR_DAC1_DAC0     = 1,  /*!< PGA0 negative output when PHCMPEN = 1;                                     
                                                              DAC1 as too-high reference and DAC0 as too-low reference when PHCMPEN = 0   */
    COMP0CTL_BIT_REFSEL_ADC1_OR_DAC2_DAC3          = 2,  /*!< ADC1 input from GPIO1 when PHCMPEN = 1;                                    
                                                              DAC2 as too-high reference and DAC3 as too-low reference when PHCMPEN = 0   */
    COMP0CTL_BIT_REFSEL_ADC9_OR_DAC3_DAC2          = 3,  /*!< ADC9 input from GPIO9 when PHCMPEN = 1;                                    
                                                              DAC3 as too-high reference and DAC2 as too-low reference when PHCMPEN = 0   */
} COMP0CTL_BIT_REFSEL;

#define COMP0CTL_ALL_REFSEL_PGA0P_OUT_OR_DAC0_DAC1     ((0x0UL) << COMP0CTL_ALL_REFSEL_Pos)
#define COMP0CTL_ALL_REFSEL_PGA0N_OUT_OR_DAC1_DAC0     ((0x1UL) << COMP0CTL_ALL_REFSEL_Pos)
#define COMP0CTL_ALL_REFSEL_ADC1_OR_DAC2_DAC3          ((0x2UL) << COMP0CTL_ALL_REFSEL_Pos)
#define COMP0CTL_ALL_REFSEL_ADC9_OR_DAC3_DAC2          ((0x3UL) << COMP0CTL_ALL_REFSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0CTL        SYNCSEL
 *  @access     COMP->COMP0CTL.bit.SYNCSEL
 *  @brief      Select the synchronous output from PWM[SYNCSEL]
 */
#define COMP0CTL_ALL_SYNCSEL_Pos (9)
#define COMP0CTL_ALL_SYNCSEL_Msk (0x7UL << COMP0CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    COMP0CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    COMP0CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    COMP0CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    COMP0CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    COMP0CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    COMP0CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} COMP0CTL_BIT_SYNCSEL;

#define COMP0CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << COMP0CTL_ALL_SYNCSEL_Pos)
#define COMP0CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << COMP0CTL_ALL_SYNCSEL_Pos)
#define COMP0CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << COMP0CTL_ALL_SYNCSEL_Pos)
#define COMP0CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << COMP0CTL_ALL_SYNCSEL_Pos)
#define COMP0CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << COMP0CTL_ALL_SYNCSEL_Pos)
#define COMP0CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << COMP0CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       SEL4PWM
 *  @access     COMP->COMP0LCTL.bit.SEL4PWM
 *  @brief      COMP0L output select for PWM
 */
#define COMP0LCTL_ALL_SEL4PWM_Pos (0)
#define COMP0LCTL_ALL_SEL4PWM_Msk (0x7UL << COMP0LCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP0LCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP0LCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP0LCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP0LCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP0LCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP0LCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP0LCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP0LCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP0LCTL_BIT_SEL4PWM;

#define COMP0LCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP0LCTL_ALL_SEL4PWM_Pos)
#define COMP0LCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP0LCTL_ALL_SEL4PWM_Pos)
#define COMP0LCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP0LCTL_ALL_SEL4PWM_Pos)
#define COMP0LCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP0LCTL_ALL_SEL4PWM_Pos)
#define COMP0LCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP0LCTL_ALL_SEL4PWM_Pos)
#define COMP0LCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP0LCTL_ALL_SEL4PWM_Pos)
#define COMP0LCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP0LCTL_ALL_SEL4PWM_Pos)
#define COMP0LCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP0LCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       POL4PWM
 *  @access     COMP->COMP0LCTL.bit.POL4PWM
 *  @brief      COMP0L output polarity for PWM
 */
#define COMP0LCTL_ALL_POL4PWM_Pos (3)
#define COMP0LCTL_ALL_POL4PWM_Msk (0x1UL << COMP0LCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP0LCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP0LCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP0LCTL_BIT_POL4PWM;

#define COMP0LCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP0LCTL_ALL_POL4PWM_Pos)
#define COMP0LCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP0LCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       SEL4GPIO
 *  @access     COMP->COMP0LCTL.bit.SEL4GPIO
 *  @brief      COMP0L output select for GPIO
 */
#define COMP0LCTL_ALL_SEL4GPIO_Pos (4)
#define COMP0LCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP0LCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP0LCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP0LCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP0LCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP0LCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP0LCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP0LCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP0LCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP0LCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP0LCTL_BIT_SEL4GPIO;

#define COMP0LCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP0LCTL_ALL_SEL4GPIO_Pos)
#define COMP0LCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP0LCTL_ALL_SEL4GPIO_Pos)
#define COMP0LCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP0LCTL_ALL_SEL4GPIO_Pos)
#define COMP0LCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP0LCTL_ALL_SEL4GPIO_Pos)
#define COMP0LCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP0LCTL_ALL_SEL4GPIO_Pos)
#define COMP0LCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP0LCTL_ALL_SEL4GPIO_Pos)
#define COMP0LCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP0LCTL_ALL_SEL4GPIO_Pos)
#define COMP0LCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP0LCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       POL4GPIO
 *  @access     COMP->COMP0LCTL.bit.POL4GPIO
 *  @brief      COMP0L output polarity for GPIO
 */
#define COMP0LCTL_ALL_POL4GPIO_Pos (7)
#define COMP0LCTL_ALL_POL4GPIO_Msk (0x1UL << COMP0LCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP0LCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP0LCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP0LCTL_BIT_POL4GPIO;

#define COMP0LCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP0LCTL_ALL_POL4GPIO_Pos)
#define COMP0LCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP0LCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       SYNCCLREN
 *  @access     COMP->COMP0LCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP0L status clear by PWMSYNC
 */
#define COMP0LCTL_ALL_SYNCCLREN_Pos (8)
#define COMP0LCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP0LCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP0LCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP0L status   */
    COMP0LCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP0L status        */
} COMP0LCTL_BIT_SYNCCLREN;

#define COMP0LCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP0LCTL_ALL_SYNCCLREN_Pos)
#define COMP0LCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP0LCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       FLTDIV
 *  @access     COMP->COMP0LCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP0LCTL_ALL_FLTDIV_Pos (9)
#define COMP0LCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP0LCTL_ALL_FLTDIV_Pos)

#define COMP0LCTL_BIT_FLTDIV

#define COMP0LCTL_ALL_FLTDIV_(x) ((x) << COMP0LCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       FLTWIN
 *  @access     COMP->COMP0LCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP0LCTL_ALL_FLTWIN_Pos (19)
#define COMP0LCTL_ALL_FLTWIN_Msk (0x1FUL << COMP0LCTL_ALL_FLTWIN_Pos)

#define COMP0LCTL_BIT_FLTWIN

#define COMP0LCTL_ALL_FLTWIN_(x) ((x) << COMP0LCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       FLTTH
 *  @access     COMP->COMP0LCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP0LCTL_ALL_FLTTH_Pos (24)
#define COMP0LCTL_ALL_FLTTH_Msk (0x1FUL << COMP0LCTL_ALL_FLTTH_Pos)

#define COMP0LCTL_BIT_FLTTH

#define COMP0LCTL_ALL_FLTTH_(x) ((x) << COMP0LCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0LCTL       FLTRST
 *  @access     COMP->COMP0LCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP0LCTL_ALL_FLTRST_Pos (29)
#define COMP0LCTL_ALL_FLTRST_Msk (0x1UL << COMP0LCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP0LCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP0LCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP0LCTL_BIT_FLTRST;

#define COMP0LCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP0LCTL_ALL_FLTRST_Pos)
#define COMP0LCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP0LCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       SEL4PWM
 *  @access     COMP->COMP0HCTL.bit.SEL4PWM
 *  @brief      COMP0H output select for PWM
 */
#define COMP0HCTL_ALL_SEL4PWM_Pos (0)
#define COMP0HCTL_ALL_SEL4PWM_Msk (0x7UL << COMP0HCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP0HCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP0HCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP0HCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP0HCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP0HCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP0HCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP0HCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP0HCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP0HCTL_BIT_SEL4PWM;

#define COMP0HCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP0HCTL_ALL_SEL4PWM_Pos)
#define COMP0HCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP0HCTL_ALL_SEL4PWM_Pos)
#define COMP0HCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP0HCTL_ALL_SEL4PWM_Pos)
#define COMP0HCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP0HCTL_ALL_SEL4PWM_Pos)
#define COMP0HCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP0HCTL_ALL_SEL4PWM_Pos)
#define COMP0HCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP0HCTL_ALL_SEL4PWM_Pos)
#define COMP0HCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP0HCTL_ALL_SEL4PWM_Pos)
#define COMP0HCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP0HCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       POL4PWM
 *  @access     COMP->COMP0HCTL.bit.POL4PWM
 *  @brief      COMP0H output polarity for PWM
 */
#define COMP0HCTL_ALL_POL4PWM_Pos (3)
#define COMP0HCTL_ALL_POL4PWM_Msk (0x1UL << COMP0HCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP0HCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP0HCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP0HCTL_BIT_POL4PWM;

#define COMP0HCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP0HCTL_ALL_POL4PWM_Pos)
#define COMP0HCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP0HCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       SEL4GPIO
 *  @access     COMP->COMP0HCTL.bit.SEL4GPIO
 *  @brief      COMP0H output select for GPIO
 */
#define COMP0HCTL_ALL_SEL4GPIO_Pos (4)
#define COMP0HCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP0HCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP0HCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP0HCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP0HCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP0HCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP0HCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP0HCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP0HCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP0HCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP0HCTL_BIT_SEL4GPIO;

#define COMP0HCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP0HCTL_ALL_SEL4GPIO_Pos)
#define COMP0HCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP0HCTL_ALL_SEL4GPIO_Pos)
#define COMP0HCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP0HCTL_ALL_SEL4GPIO_Pos)
#define COMP0HCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP0HCTL_ALL_SEL4GPIO_Pos)
#define COMP0HCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP0HCTL_ALL_SEL4GPIO_Pos)
#define COMP0HCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP0HCTL_ALL_SEL4GPIO_Pos)
#define COMP0HCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP0HCTL_ALL_SEL4GPIO_Pos)
#define COMP0HCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP0HCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       POL4GPIO
 *  @access     COMP->COMP0HCTL.bit.POL4GPIO
 *  @brief      COMP0H output polarity for GPIO
 */
#define COMP0HCTL_ALL_POL4GPIO_Pos (7)
#define COMP0HCTL_ALL_POL4GPIO_Msk (0x1UL << COMP0HCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP0HCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP0HCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP0HCTL_BIT_POL4GPIO;

#define COMP0HCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP0HCTL_ALL_POL4GPIO_Pos)
#define COMP0HCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP0HCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       SYNCCLREN
 *  @access     COMP->COMP0HCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP0H status clear by PWMSYNC
 */
#define COMP0HCTL_ALL_SYNCCLREN_Pos (8)
#define COMP0HCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP0HCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP0HCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP0H status   */
    COMP0HCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP0H status        */
} COMP0HCTL_BIT_SYNCCLREN;

#define COMP0HCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP0HCTL_ALL_SYNCCLREN_Pos)
#define COMP0HCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP0HCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       FLTDIV
 *  @access     COMP->COMP0HCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP0HCTL_ALL_FLTDIV_Pos (9)
#define COMP0HCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP0HCTL_ALL_FLTDIV_Pos)

#define COMP0HCTL_BIT_FLTDIV

#define COMP0HCTL_ALL_FLTDIV_(x) ((x) << COMP0HCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       FLTWIN
 *  @access     COMP->COMP0HCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP0HCTL_ALL_FLTWIN_Pos (19)
#define COMP0HCTL_ALL_FLTWIN_Msk (0x1FUL << COMP0HCTL_ALL_FLTWIN_Pos)

#define COMP0HCTL_BIT_FLTWIN

#define COMP0HCTL_ALL_FLTWIN_(x) ((x) << COMP0HCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       FLTTH
 *  @access     COMP->COMP0HCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP0HCTL_ALL_FLTTH_Pos (24)
#define COMP0HCTL_ALL_FLTTH_Msk (0x1FUL << COMP0HCTL_ALL_FLTTH_Pos)

#define COMP0HCTL_BIT_FLTTH

#define COMP0HCTL_ALL_FLTTH_(x) ((x) << COMP0HCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP0HCTL       FLTRST
 *  @access     COMP->COMP0HCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP0HCTL_ALL_FLTRST_Pos (29)
#define COMP0HCTL_ALL_FLTRST_Msk (0x1UL << COMP0HCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP0HCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP0HCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP0HCTL_BIT_FLTRST;

#define COMP0HCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP0HCTL_ALL_FLTRST_Pos)
#define COMP0HCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP0HCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1CTL        ENL
 *  @access     COMP->COMP1CTL.bit.ENL
 *  @brief      COMP1L enable
 */
#define COMP1CTL_ALL_ENL_Pos (0)
#define COMP1CTL_ALL_ENL_Msk (0x1UL << COMP1CTL_ALL_ENL_Pos)

typedef enum
{
    COMP1CTL_BIT_ENL_DISABLE     = 0,  /*!< Disable COMP1L   */
    COMP1CTL_BIT_ENL_ENABLE      = 1,  /*!< Enable COMP1L    */
} COMP1CTL_BIT_ENL;

#define COMP1CTL_ALL_ENL_DISABLE     ((0x0UL) << COMP1CTL_ALL_ENL_Pos)
#define COMP1CTL_ALL_ENL_ENABLE      ((0x1UL) << COMP1CTL_ALL_ENL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1CTL        ENH
 *  @access     COMP->COMP1CTL.bit.ENH
 *  @brief      COMP1H enable
 */
#define COMP1CTL_ALL_ENH_Pos (1)
#define COMP1CTL_ALL_ENH_Msk (0x1UL << COMP1CTL_ALL_ENH_Pos)

typedef enum
{
    COMP1CTL_BIT_ENH_DISABLE     = 0,  /*!< Disable COMP1H   */
    COMP1CTL_BIT_ENH_ENABLE      = 1,  /*!< Enable COMP1H    */
} COMP1CTL_BIT_ENH;

#define COMP1CTL_ALL_ENH_DISABLE     ((0x0UL) << COMP1CTL_ALL_ENH_Pos)
#define COMP1CTL_ALL_ENH_ENABLE      ((0x1UL) << COMP1CTL_ALL_ENH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1CTL        PHCMPEN
 *  @access     COMP->COMP1CTL.bit.PHCMPEN
 *  @brief      COMP1 phase comparison enable
 */
#define COMP1CTL_ALL_PHCMPEN_Pos (2)
#define COMP1CTL_ALL_PHCMPEN_Msk (0x1UL << COMP1CTL_ALL_PHCMPEN_Pos)

typedef enum
{
    COMP1CTL_BIT_PHCMPEN_DISABLE     = 0,  /*!< Normal operation        */
    COMP1CTL_BIT_PHCMPEN_ENABLE      = 1,  /*!< Phase comparison mode   */
} COMP1CTL_BIT_PHCMPEN;

#define COMP1CTL_ALL_PHCMPEN_DISABLE     ((0x0UL) << COMP1CTL_ALL_PHCMPEN_Pos)
#define COMP1CTL_ALL_PHCMPEN_ENABLE      ((0x1UL) << COMP1CTL_ALL_PHCMPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1CTL        HYSTSEL
 *  @access     COMP->COMP1CTL.bit.HYSTSEL
 *  @brief      COMP1 hysterisis select
 */
#define COMP1CTL_ALL_HYSTSEL_Pos (3)
#define COMP1CTL_ALL_HYSTSEL_Msk (0x3UL << COMP1CTL_ALL_HYSTSEL_Pos)

typedef enum
{
    COMP1CTL_BIT_HYSTSEL_0_MV      = 0,  /*!< 0 mV    */
    COMP1CTL_BIT_HYSTSEL_12_MV     = 1,  /*!< 12 mV   */
    COMP1CTL_BIT_HYSTSEL_24_MV     = 2,  /*!< 24 mV   */
    COMP1CTL_BIT_HYSTSEL_36_MV     = 3,  /*!< 36 mV   */
} COMP1CTL_BIT_HYSTSEL;

#define COMP1CTL_ALL_HYSTSEL_0_MV      ((0x0UL) << COMP1CTL_ALL_HYSTSEL_Pos)
#define COMP1CTL_ALL_HYSTSEL_12_MV     ((0x1UL) << COMP1CTL_ALL_HYSTSEL_Pos)
#define COMP1CTL_ALL_HYSTSEL_24_MV     ((0x2UL) << COMP1CTL_ALL_HYSTSEL_Pos)
#define COMP1CTL_ALL_HYSTSEL_36_MV     ((0x3UL) << COMP1CTL_ALL_HYSTSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1CTL        INSEL
 *  @access     COMP->COMP1CTL.bit.INSEL
 *  @brief      COMP1 input select
 */
#define COMP1CTL_ALL_INSEL_Pos (5)
#define COMP1CTL_ALL_INSEL_Msk (0x3UL << COMP1CTL_ALL_INSEL_Pos)

typedef enum
{
    COMP1CTL_BIT_INSEL_PGA1N_OUT     = 0,  /*!< PGA1 negative output    */
    COMP1CTL_BIT_INSEL_PGA1P_OUT     = 1,  /*!< PGA1 positive output    */
    COMP1CTL_BIT_INSEL_ADC0          = 2,  /*!< ADC0 input from GPIO0   */
    COMP1CTL_BIT_INSEL_ADC8          = 3,  /*!< ADC8 input from GPIO8   */
} COMP1CTL_BIT_INSEL;

#define COMP1CTL_ALL_INSEL_PGA1N_OUT     ((0x0UL) << COMP1CTL_ALL_INSEL_Pos)
#define COMP1CTL_ALL_INSEL_PGA1P_OUT     ((0x1UL) << COMP1CTL_ALL_INSEL_Pos)
#define COMP1CTL_ALL_INSEL_ADC0          ((0x2UL) << COMP1CTL_ALL_INSEL_Pos)
#define COMP1CTL_ALL_INSEL_ADC8          ((0x3UL) << COMP1CTL_ALL_INSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1CTL        REFSEL
 *  @access     COMP->COMP1CTL.bit.REFSEL
 *  @brief      COMP1 reference select
 */
#define COMP1CTL_ALL_REFSEL_Pos (7)
#define COMP1CTL_ALL_REFSEL_Msk (0x3UL << COMP1CTL_ALL_REFSEL_Pos)

typedef enum
{
    COMP1CTL_BIT_REFSEL_PGA1P_OUT_OR_DAC0_DAC1     = 0,  /*!< PGA1 positive output when PHCMPEN = 1;                                     
                                                              DAC0 as too-high reference and DAC1 as too-low reference when PHCMPEN = 0   */
    COMP1CTL_BIT_REFSEL_PGA1N_OUT_OR_DAC1_DAC0     = 1,  /*!< PGA1 negative output when PHCMPEN = 1;                                     
                                                              DAC1 as too-high reference and DAC0 as too-low reference when PHCMPEN = 0   */
    COMP1CTL_BIT_REFSEL_ADC2_OR_DAC2_DAC3          = 2,  /*!< ADC2 input from GPIO2 when PHCMPEN = 1;                                    
                                                              DAC2 as too-high reference and DAC3 as too-low reference when PHCMPEN = 0   */
    COMP1CTL_BIT_REFSEL_ADC10_OR_DAC3_DAC2         = 3,  /*!< ADC10 input from GPIO10 when PHCMPEN = 1;                                  
                                                              DAC3 as too-high reference and DAC2 as too-low reference when PHCMPEN = 0   */
} COMP1CTL_BIT_REFSEL;

#define COMP1CTL_ALL_REFSEL_PGA1P_OUT_OR_DAC0_DAC1     ((0x0UL) << COMP1CTL_ALL_REFSEL_Pos)
#define COMP1CTL_ALL_REFSEL_PGA1N_OUT_OR_DAC1_DAC0     ((0x1UL) << COMP1CTL_ALL_REFSEL_Pos)
#define COMP1CTL_ALL_REFSEL_ADC2_OR_DAC2_DAC3          ((0x2UL) << COMP1CTL_ALL_REFSEL_Pos)
#define COMP1CTL_ALL_REFSEL_ADC10_OR_DAC3_DAC2         ((0x3UL) << COMP1CTL_ALL_REFSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1CTL        SYNCSEL
 *  @access     COMP->COMP1CTL.bit.SYNCSEL
 *  @brief      Select the synchronous output from PWM[SYNCSEL]
 */
#define COMP1CTL_ALL_SYNCSEL_Pos (9)
#define COMP1CTL_ALL_SYNCSEL_Msk (0x7UL << COMP1CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    COMP1CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    COMP1CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    COMP1CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    COMP1CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    COMP1CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    COMP1CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} COMP1CTL_BIT_SYNCSEL;

#define COMP1CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << COMP1CTL_ALL_SYNCSEL_Pos)
#define COMP1CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << COMP1CTL_ALL_SYNCSEL_Pos)
#define COMP1CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << COMP1CTL_ALL_SYNCSEL_Pos)
#define COMP1CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << COMP1CTL_ALL_SYNCSEL_Pos)
#define COMP1CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << COMP1CTL_ALL_SYNCSEL_Pos)
#define COMP1CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << COMP1CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       SEL4PWM
 *  @access     COMP->COMP1LCTL.bit.SEL4PWM
 *  @brief      COMP1L output select for PWM
 */
#define COMP1LCTL_ALL_SEL4PWM_Pos (0)
#define COMP1LCTL_ALL_SEL4PWM_Msk (0x7UL << COMP1LCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP1LCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP1LCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP1LCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP1LCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP1LCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP1LCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP1LCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP1LCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP1LCTL_BIT_SEL4PWM;

#define COMP1LCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP1LCTL_ALL_SEL4PWM_Pos)
#define COMP1LCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP1LCTL_ALL_SEL4PWM_Pos)
#define COMP1LCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP1LCTL_ALL_SEL4PWM_Pos)
#define COMP1LCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP1LCTL_ALL_SEL4PWM_Pos)
#define COMP1LCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP1LCTL_ALL_SEL4PWM_Pos)
#define COMP1LCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP1LCTL_ALL_SEL4PWM_Pos)
#define COMP1LCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP1LCTL_ALL_SEL4PWM_Pos)
#define COMP1LCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP1LCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       POL4PWM
 *  @access     COMP->COMP1LCTL.bit.POL4PWM
 *  @brief      COMP1L output polarity for PWM
 */
#define COMP1LCTL_ALL_POL4PWM_Pos (3)
#define COMP1LCTL_ALL_POL4PWM_Msk (0x1UL << COMP1LCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP1LCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP1LCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP1LCTL_BIT_POL4PWM;

#define COMP1LCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP1LCTL_ALL_POL4PWM_Pos)
#define COMP1LCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP1LCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       SEL4GPIO
 *  @access     COMP->COMP1LCTL.bit.SEL4GPIO
 *  @brief      COMP1L output select for GPIO
 */
#define COMP1LCTL_ALL_SEL4GPIO_Pos (4)
#define COMP1LCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP1LCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP1LCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP1LCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP1LCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP1LCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP1LCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP1LCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP1LCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP1LCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP1LCTL_BIT_SEL4GPIO;

#define COMP1LCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP1LCTL_ALL_SEL4GPIO_Pos)
#define COMP1LCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP1LCTL_ALL_SEL4GPIO_Pos)
#define COMP1LCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP1LCTL_ALL_SEL4GPIO_Pos)
#define COMP1LCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP1LCTL_ALL_SEL4GPIO_Pos)
#define COMP1LCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP1LCTL_ALL_SEL4GPIO_Pos)
#define COMP1LCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP1LCTL_ALL_SEL4GPIO_Pos)
#define COMP1LCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP1LCTL_ALL_SEL4GPIO_Pos)
#define COMP1LCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP1LCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       POL4GPIO
 *  @access     COMP->COMP1LCTL.bit.POL4GPIO
 *  @brief      COMP1L output polarity for GPIO
 */
#define COMP1LCTL_ALL_POL4GPIO_Pos (7)
#define COMP1LCTL_ALL_POL4GPIO_Msk (0x1UL << COMP1LCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP1LCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP1LCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP1LCTL_BIT_POL4GPIO;

#define COMP1LCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP1LCTL_ALL_POL4GPIO_Pos)
#define COMP1LCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP1LCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       SYNCCLREN
 *  @access     COMP->COMP1LCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP1L status clear by PWMSYNC
 */
#define COMP1LCTL_ALL_SYNCCLREN_Pos (8)
#define COMP1LCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP1LCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP1LCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP1L status   */
    COMP1LCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP1L status        */
} COMP1LCTL_BIT_SYNCCLREN;

#define COMP1LCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP1LCTL_ALL_SYNCCLREN_Pos)
#define COMP1LCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP1LCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       FLTDIV
 *  @access     COMP->COMP1LCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP1LCTL_ALL_FLTDIV_Pos (9)
#define COMP1LCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP1LCTL_ALL_FLTDIV_Pos)

#define COMP1LCTL_BIT_FLTDIV

#define COMP1LCTL_ALL_FLTDIV_(x) ((x) << COMP1LCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       FLTWIN
 *  @access     COMP->COMP1LCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP1LCTL_ALL_FLTWIN_Pos (19)
#define COMP1LCTL_ALL_FLTWIN_Msk (0x1FUL << COMP1LCTL_ALL_FLTWIN_Pos)

#define COMP1LCTL_BIT_FLTWIN

#define COMP1LCTL_ALL_FLTWIN_(x) ((x) << COMP1LCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       FLTTH
 *  @access     COMP->COMP1LCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP1LCTL_ALL_FLTTH_Pos (24)
#define COMP1LCTL_ALL_FLTTH_Msk (0x1FUL << COMP1LCTL_ALL_FLTTH_Pos)

#define COMP1LCTL_BIT_FLTTH

#define COMP1LCTL_ALL_FLTTH_(x) ((x) << COMP1LCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1LCTL       FLTRST
 *  @access     COMP->COMP1LCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP1LCTL_ALL_FLTRST_Pos (29)
#define COMP1LCTL_ALL_FLTRST_Msk (0x1UL << COMP1LCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP1LCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP1LCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP1LCTL_BIT_FLTRST;

#define COMP1LCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP1LCTL_ALL_FLTRST_Pos)
#define COMP1LCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP1LCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       SEL4PWM
 *  @access     COMP->COMP1HCTL.bit.SEL4PWM
 *  @brief      COMP1H output select for PWM
 */
#define COMP1HCTL_ALL_SEL4PWM_Pos (0)
#define COMP1HCTL_ALL_SEL4PWM_Msk (0x7UL << COMP1HCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP1HCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP1HCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP1HCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP1HCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP1HCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP1HCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP1HCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP1HCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP1HCTL_BIT_SEL4PWM;

#define COMP1HCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP1HCTL_ALL_SEL4PWM_Pos)
#define COMP1HCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP1HCTL_ALL_SEL4PWM_Pos)
#define COMP1HCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP1HCTL_ALL_SEL4PWM_Pos)
#define COMP1HCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP1HCTL_ALL_SEL4PWM_Pos)
#define COMP1HCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP1HCTL_ALL_SEL4PWM_Pos)
#define COMP1HCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP1HCTL_ALL_SEL4PWM_Pos)
#define COMP1HCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP1HCTL_ALL_SEL4PWM_Pos)
#define COMP1HCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP1HCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       POL4PWM
 *  @access     COMP->COMP1HCTL.bit.POL4PWM
 *  @brief      COMP1H output polarity for PWM
 */
#define COMP1HCTL_ALL_POL4PWM_Pos (3)
#define COMP1HCTL_ALL_POL4PWM_Msk (0x1UL << COMP1HCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP1HCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP1HCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP1HCTL_BIT_POL4PWM;

#define COMP1HCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP1HCTL_ALL_POL4PWM_Pos)
#define COMP1HCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP1HCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       SEL4GPIO
 *  @access     COMP->COMP1HCTL.bit.SEL4GPIO
 *  @brief      COMP1H output select for GPIO
 */
#define COMP1HCTL_ALL_SEL4GPIO_Pos (4)
#define COMP1HCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP1HCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP1HCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP1HCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP1HCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP1HCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP1HCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP1HCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP1HCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP1HCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP1HCTL_BIT_SEL4GPIO;

#define COMP1HCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP1HCTL_ALL_SEL4GPIO_Pos)
#define COMP1HCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP1HCTL_ALL_SEL4GPIO_Pos)
#define COMP1HCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP1HCTL_ALL_SEL4GPIO_Pos)
#define COMP1HCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP1HCTL_ALL_SEL4GPIO_Pos)
#define COMP1HCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP1HCTL_ALL_SEL4GPIO_Pos)
#define COMP1HCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP1HCTL_ALL_SEL4GPIO_Pos)
#define COMP1HCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP1HCTL_ALL_SEL4GPIO_Pos)
#define COMP1HCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP1HCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       POL4GPIO
 *  @access     COMP->COMP1HCTL.bit.POL4GPIO
 *  @brief      COMP1H output polarity for GPIO
 */
#define COMP1HCTL_ALL_POL4GPIO_Pos (7)
#define COMP1HCTL_ALL_POL4GPIO_Msk (0x1UL << COMP1HCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP1HCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP1HCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP1HCTL_BIT_POL4GPIO;

#define COMP1HCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP1HCTL_ALL_POL4GPIO_Pos)
#define COMP1HCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP1HCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       SYNCCLREN
 *  @access     COMP->COMP1HCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP1H status clear by PWMSYNC
 */
#define COMP1HCTL_ALL_SYNCCLREN_Pos (8)
#define COMP1HCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP1HCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP1HCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP1H status   */
    COMP1HCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP1H status        */
} COMP1HCTL_BIT_SYNCCLREN;

#define COMP1HCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP1HCTL_ALL_SYNCCLREN_Pos)
#define COMP1HCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP1HCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       FLTDIV
 *  @access     COMP->COMP1HCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP1HCTL_ALL_FLTDIV_Pos (9)
#define COMP1HCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP1HCTL_ALL_FLTDIV_Pos)

#define COMP1HCTL_BIT_FLTDIV

#define COMP1HCTL_ALL_FLTDIV_(x) ((x) << COMP1HCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       FLTWIN
 *  @access     COMP->COMP1HCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP1HCTL_ALL_FLTWIN_Pos (19)
#define COMP1HCTL_ALL_FLTWIN_Msk (0x1FUL << COMP1HCTL_ALL_FLTWIN_Pos)

#define COMP1HCTL_BIT_FLTWIN

#define COMP1HCTL_ALL_FLTWIN_(x) ((x) << COMP1HCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       FLTTH
 *  @access     COMP->COMP1HCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP1HCTL_ALL_FLTTH_Pos (24)
#define COMP1HCTL_ALL_FLTTH_Msk (0x1FUL << COMP1HCTL_ALL_FLTTH_Pos)

#define COMP1HCTL_BIT_FLTTH

#define COMP1HCTL_ALL_FLTTH_(x) ((x) << COMP1HCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP1HCTL       FLTRST
 *  @access     COMP->COMP1HCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP1HCTL_ALL_FLTRST_Pos (29)
#define COMP1HCTL_ALL_FLTRST_Msk (0x1UL << COMP1HCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP1HCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP1HCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP1HCTL_BIT_FLTRST;

#define COMP1HCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP1HCTL_ALL_FLTRST_Pos)
#define COMP1HCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP1HCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2CTL        ENL
 *  @access     COMP->COMP2CTL.bit.ENL
 *  @brief      COMP2L enable
 */
#define COMP2CTL_ALL_ENL_Pos (0)
#define COMP2CTL_ALL_ENL_Msk (0x1UL << COMP2CTL_ALL_ENL_Pos)

typedef enum
{
    COMP2CTL_BIT_ENL_DISABLE     = 0,  /*!< Disable COMP2L   */
    COMP2CTL_BIT_ENL_ENABLE      = 1,  /*!< Enable COMP2L    */
} COMP2CTL_BIT_ENL;

#define COMP2CTL_ALL_ENL_DISABLE     ((0x0UL) << COMP2CTL_ALL_ENL_Pos)
#define COMP2CTL_ALL_ENL_ENABLE      ((0x1UL) << COMP2CTL_ALL_ENL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2CTL        ENH
 *  @access     COMP->COMP2CTL.bit.ENH
 *  @brief      COMP2H enable
 */
#define COMP2CTL_ALL_ENH_Pos (1)
#define COMP2CTL_ALL_ENH_Msk (0x1UL << COMP2CTL_ALL_ENH_Pos)

typedef enum
{
    COMP2CTL_BIT_ENH_DISABLE     = 0,  /*!< Disable COMP2H   */
    COMP2CTL_BIT_ENH_ENABLE      = 1,  /*!< Enable COMP2H    */
} COMP2CTL_BIT_ENH;

#define COMP2CTL_ALL_ENH_DISABLE     ((0x0UL) << COMP2CTL_ALL_ENH_Pos)
#define COMP2CTL_ALL_ENH_ENABLE      ((0x1UL) << COMP2CTL_ALL_ENH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2CTL        PHCMPEN
 *  @access     COMP->COMP2CTL.bit.PHCMPEN
 *  @brief      COMP2 phase comparison enable
 */
#define COMP2CTL_ALL_PHCMPEN_Pos (2)
#define COMP2CTL_ALL_PHCMPEN_Msk (0x1UL << COMP2CTL_ALL_PHCMPEN_Pos)

typedef enum
{
    COMP2CTL_BIT_PHCMPEN_DISABLE     = 0,  /*!< Normal operation        */
    COMP2CTL_BIT_PHCMPEN_ENABLE      = 1,  /*!< Phase comparison mode   */
} COMP2CTL_BIT_PHCMPEN;

#define COMP2CTL_ALL_PHCMPEN_DISABLE     ((0x0UL) << COMP2CTL_ALL_PHCMPEN_Pos)
#define COMP2CTL_ALL_PHCMPEN_ENABLE      ((0x1UL) << COMP2CTL_ALL_PHCMPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2CTL        HYSTSEL
 *  @access     COMP->COMP2CTL.bit.HYSTSEL
 *  @brief      COMP2 hysteresis select
 */
#define COMP2CTL_ALL_HYSTSEL_Pos (3)
#define COMP2CTL_ALL_HYSTSEL_Msk (0x3UL << COMP2CTL_ALL_HYSTSEL_Pos)

typedef enum
{
    COMP2CTL_BIT_HYSTSEL_0_MV      = 0,  /*!< 0 mV    */
    COMP2CTL_BIT_HYSTSEL_12_MV     = 1,  /*!< 12 mV   */
    COMP2CTL_BIT_HYSTSEL_24_MV     = 2,  /*!< 24 mV   */
    COMP2CTL_BIT_HYSTSEL_36_MV     = 3,  /*!< 36 mV   */
} COMP2CTL_BIT_HYSTSEL;

#define COMP2CTL_ALL_HYSTSEL_0_MV      ((0x0UL) << COMP2CTL_ALL_HYSTSEL_Pos)
#define COMP2CTL_ALL_HYSTSEL_12_MV     ((0x1UL) << COMP2CTL_ALL_HYSTSEL_Pos)
#define COMP2CTL_ALL_HYSTSEL_24_MV     ((0x2UL) << COMP2CTL_ALL_HYSTSEL_Pos)
#define COMP2CTL_ALL_HYSTSEL_36_MV     ((0x3UL) << COMP2CTL_ALL_HYSTSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2CTL        INSEL
 *  @access     COMP->COMP2CTL.bit.INSEL
 *  @brief      COMP2 input select
 */
#define COMP2CTL_ALL_INSEL_Pos (5)
#define COMP2CTL_ALL_INSEL_Msk (0x3UL << COMP2CTL_ALL_INSEL_Pos)

typedef enum
{
    COMP2CTL_BIT_INSEL_PGA2N_OUT     = 0,  /*!< PGA2 negative output    */
    COMP2CTL_BIT_INSEL_PGA2P_OUT     = 1,  /*!< PGA2 positive output    */
    COMP2CTL_BIT_INSEL_ADC0          = 2,  /*!< ADC0 input from GPIO0   */
    COMP2CTL_BIT_INSEL_ADC8          = 3,  /*!< ADC8 input from GPIO8   */
} COMP2CTL_BIT_INSEL;

#define COMP2CTL_ALL_INSEL_PGA2N_OUT     ((0x0UL) << COMP2CTL_ALL_INSEL_Pos)
#define COMP2CTL_ALL_INSEL_PGA2P_OUT     ((0x1UL) << COMP2CTL_ALL_INSEL_Pos)
#define COMP2CTL_ALL_INSEL_ADC0          ((0x2UL) << COMP2CTL_ALL_INSEL_Pos)
#define COMP2CTL_ALL_INSEL_ADC8          ((0x3UL) << COMP2CTL_ALL_INSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2CTL        REFSEL
 *  @access     COMP->COMP2CTL.bit.REFSEL
 *  @brief      COMP2 reference select
 */
#define COMP2CTL_ALL_REFSEL_Pos (7)
#define COMP2CTL_ALL_REFSEL_Msk (0x3UL << COMP2CTL_ALL_REFSEL_Pos)

typedef enum
{
    COMP2CTL_BIT_REFSEL_PGA2P_OUT_OR_DAC0_DAC1     = 0,  /*!< PGA2 positive output when PHCMPEN = 1;                                     
                                                              DAC0 as too-high reference and DAC1 as too-low reference when PHCMPEN = 0   */
    COMP2CTL_BIT_REFSEL_PGA2N_OUT_OR_DAC1_DAC0     = 1,  /*!< PGA2 negative output when PHCMPEN = 1;                                     
                                                              DAC1 as too-high reference and DAC0 as too-low reference when PHCMPEN = 0   */
    COMP2CTL_BIT_REFSEL_ADC3_OR_DAC2_DAC3          = 2,  /*!< ADC3 input from GPIO3 when PHCMPEN = 1;                                    
                                                              DAC2 as too-high reference and DAC3 as too-low reference when PHCMPEN = 0   */
    COMP2CTL_BIT_REFSEL_ADC11_OR_DAC3_DAC2         = 3,  /*!< ADC11 input from GPIO11 when PHCMPEN = 1;                                  
                                                              DAC3 as too-high reference and DAC2 as too-low reference when PHCMPEN = 0   */
} COMP2CTL_BIT_REFSEL;

#define COMP2CTL_ALL_REFSEL_PGA2P_OUT_OR_DAC0_DAC1     ((0x0UL) << COMP2CTL_ALL_REFSEL_Pos)
#define COMP2CTL_ALL_REFSEL_PGA2N_OUT_OR_DAC1_DAC0     ((0x1UL) << COMP2CTL_ALL_REFSEL_Pos)
#define COMP2CTL_ALL_REFSEL_ADC3_OR_DAC2_DAC3          ((0x2UL) << COMP2CTL_ALL_REFSEL_Pos)
#define COMP2CTL_ALL_REFSEL_ADC11_OR_DAC3_DAC2         ((0x3UL) << COMP2CTL_ALL_REFSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2CTL        SYNCSEL
 *  @access     COMP->COMP2CTL.bit.SYNCSEL
 *  @brief      Select the synchronous output from PWM[SYNCSEL]
 */
#define COMP2CTL_ALL_SYNCSEL_Pos (9)
#define COMP2CTL_ALL_SYNCSEL_Msk (0x7UL << COMP2CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    COMP2CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    COMP2CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    COMP2CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    COMP2CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    COMP2CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    COMP2CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} COMP2CTL_BIT_SYNCSEL;

#define COMP2CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << COMP2CTL_ALL_SYNCSEL_Pos)
#define COMP2CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << COMP2CTL_ALL_SYNCSEL_Pos)
#define COMP2CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << COMP2CTL_ALL_SYNCSEL_Pos)
#define COMP2CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << COMP2CTL_ALL_SYNCSEL_Pos)
#define COMP2CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << COMP2CTL_ALL_SYNCSEL_Pos)
#define COMP2CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << COMP2CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       SEL4PWM
 *  @access     COMP->COMP2LCTL.bit.SEL4PWM
 *  @brief      COMP2L output select for PWM
 */
#define COMP2LCTL_ALL_SEL4PWM_Pos (0)
#define COMP2LCTL_ALL_SEL4PWM_Msk (0x7UL << COMP2LCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP2LCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP2LCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP2LCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP2LCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP2LCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP2LCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP2LCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP2LCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP2LCTL_BIT_SEL4PWM;

#define COMP2LCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP2LCTL_ALL_SEL4PWM_Pos)
#define COMP2LCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP2LCTL_ALL_SEL4PWM_Pos)
#define COMP2LCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP2LCTL_ALL_SEL4PWM_Pos)
#define COMP2LCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP2LCTL_ALL_SEL4PWM_Pos)
#define COMP2LCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP2LCTL_ALL_SEL4PWM_Pos)
#define COMP2LCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP2LCTL_ALL_SEL4PWM_Pos)
#define COMP2LCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP2LCTL_ALL_SEL4PWM_Pos)
#define COMP2LCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP2LCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       POL4PWM
 *  @access     COMP->COMP2LCTL.bit.POL4PWM
 *  @brief      COMP2L output polarity for PWM
 */
#define COMP2LCTL_ALL_POL4PWM_Pos (3)
#define COMP2LCTL_ALL_POL4PWM_Msk (0x1UL << COMP2LCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP2LCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP2LCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP2LCTL_BIT_POL4PWM;

#define COMP2LCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP2LCTL_ALL_POL4PWM_Pos)
#define COMP2LCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP2LCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       SEL4GPIO
 *  @access     COMP->COMP2LCTL.bit.SEL4GPIO
 *  @brief      COMP2L output select for GPIO
 */
#define COMP2LCTL_ALL_SEL4GPIO_Pos (4)
#define COMP2LCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP2LCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP2LCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP2LCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP2LCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP2LCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP2LCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP2LCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP2LCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP2LCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP2LCTL_BIT_SEL4GPIO;

#define COMP2LCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP2LCTL_ALL_SEL4GPIO_Pos)
#define COMP2LCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP2LCTL_ALL_SEL4GPIO_Pos)
#define COMP2LCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP2LCTL_ALL_SEL4GPIO_Pos)
#define COMP2LCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP2LCTL_ALL_SEL4GPIO_Pos)
#define COMP2LCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP2LCTL_ALL_SEL4GPIO_Pos)
#define COMP2LCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP2LCTL_ALL_SEL4GPIO_Pos)
#define COMP2LCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP2LCTL_ALL_SEL4GPIO_Pos)
#define COMP2LCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP2LCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       POL4GPIO
 *  @access     COMP->COMP2LCTL.bit.POL4GPIO
 *  @brief      COMP2L output polarity for GPIO
 */
#define COMP2LCTL_ALL_POL4GPIO_Pos (7)
#define COMP2LCTL_ALL_POL4GPIO_Msk (0x1UL << COMP2LCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP2LCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP2LCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP2LCTL_BIT_POL4GPIO;

#define COMP2LCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP2LCTL_ALL_POL4GPIO_Pos)
#define COMP2LCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP2LCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       SYNCCLREN
 *  @access     COMP->COMP2LCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP2L status clear by PWMSYNC
 */
#define COMP2LCTL_ALL_SYNCCLREN_Pos (8)
#define COMP2LCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP2LCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP2LCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP2L status   */
    COMP2LCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP2L status        */
} COMP2LCTL_BIT_SYNCCLREN;

#define COMP2LCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP2LCTL_ALL_SYNCCLREN_Pos)
#define COMP2LCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP2LCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       FLTDIV
 *  @access     COMP->COMP2LCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP2LCTL_ALL_FLTDIV_Pos (9)
#define COMP2LCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP2LCTL_ALL_FLTDIV_Pos)

#define COMP2LCTL_BIT_FLTDIV

#define COMP2LCTL_ALL_FLTDIV_(x) ((x) << COMP2LCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       FLTWIN
 *  @access     COMP->COMP2LCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP2LCTL_ALL_FLTWIN_Pos (19)
#define COMP2LCTL_ALL_FLTWIN_Msk (0x1FUL << COMP2LCTL_ALL_FLTWIN_Pos)

#define COMP2LCTL_BIT_FLTWIN

#define COMP2LCTL_ALL_FLTWIN_(x) ((x) << COMP2LCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       FLTTH
 *  @access     COMP->COMP2LCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP2LCTL_ALL_FLTTH_Pos (24)
#define COMP2LCTL_ALL_FLTTH_Msk (0x1FUL << COMP2LCTL_ALL_FLTTH_Pos)

#define COMP2LCTL_BIT_FLTTH

#define COMP2LCTL_ALL_FLTTH_(x) ((x) << COMP2LCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2LCTL       FLTRST
 *  @access     COMP->COMP2LCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP2LCTL_ALL_FLTRST_Pos (29)
#define COMP2LCTL_ALL_FLTRST_Msk (0x1UL << COMP2LCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP2LCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP2LCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP2LCTL_BIT_FLTRST;

#define COMP2LCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP2LCTL_ALL_FLTRST_Pos)
#define COMP2LCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP2LCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       SEL4PWM
 *  @access     COMP->COMP2HCTL.bit.SEL4PWM
 *  @brief      COMP2H output select for PWM
 */
#define COMP2HCTL_ALL_SEL4PWM_Pos (0)
#define COMP2HCTL_ALL_SEL4PWM_Msk (0x7UL << COMP2HCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP2HCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP2HCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP2HCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP2HCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP2HCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP2HCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP2HCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP2HCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP2HCTL_BIT_SEL4PWM;

#define COMP2HCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP2HCTL_ALL_SEL4PWM_Pos)
#define COMP2HCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP2HCTL_ALL_SEL4PWM_Pos)
#define COMP2HCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP2HCTL_ALL_SEL4PWM_Pos)
#define COMP2HCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP2HCTL_ALL_SEL4PWM_Pos)
#define COMP2HCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP2HCTL_ALL_SEL4PWM_Pos)
#define COMP2HCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP2HCTL_ALL_SEL4PWM_Pos)
#define COMP2HCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP2HCTL_ALL_SEL4PWM_Pos)
#define COMP2HCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP2HCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       POL4PWM
 *  @access     COMP->COMP2HCTL.bit.POL4PWM
 *  @brief      COMP2H output polarity for PWM
 */
#define COMP2HCTL_ALL_POL4PWM_Pos (3)
#define COMP2HCTL_ALL_POL4PWM_Msk (0x1UL << COMP2HCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP2HCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP2HCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP2HCTL_BIT_POL4PWM;

#define COMP2HCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP2HCTL_ALL_POL4PWM_Pos)
#define COMP2HCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP2HCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       SEL4GPIO
 *  @access     COMP->COMP2HCTL.bit.SEL4GPIO
 *  @brief      COMP2H output select for GPIO
 */
#define COMP2HCTL_ALL_SEL4GPIO_Pos (4)
#define COMP2HCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP2HCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP2HCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP2HCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP2HCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP2HCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP2HCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP2HCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP2HCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP2HCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP2HCTL_BIT_SEL4GPIO;

#define COMP2HCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP2HCTL_ALL_SEL4GPIO_Pos)
#define COMP2HCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP2HCTL_ALL_SEL4GPIO_Pos)
#define COMP2HCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP2HCTL_ALL_SEL4GPIO_Pos)
#define COMP2HCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP2HCTL_ALL_SEL4GPIO_Pos)
#define COMP2HCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP2HCTL_ALL_SEL4GPIO_Pos)
#define COMP2HCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP2HCTL_ALL_SEL4GPIO_Pos)
#define COMP2HCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP2HCTL_ALL_SEL4GPIO_Pos)
#define COMP2HCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP2HCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       POL4GPIO
 *  @access     COMP->COMP2HCTL.bit.POL4GPIO
 *  @brief      COMP2H output polarity for GPIO
 */
#define COMP2HCTL_ALL_POL4GPIO_Pos (7)
#define COMP2HCTL_ALL_POL4GPIO_Msk (0x1UL << COMP2HCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP2HCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP2HCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP2HCTL_BIT_POL4GPIO;

#define COMP2HCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP2HCTL_ALL_POL4GPIO_Pos)
#define COMP2HCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP2HCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       SYNCCLREN
 *  @access     COMP->COMP2HCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP2H status clear by PWMSYNC
 */
#define COMP2HCTL_ALL_SYNCCLREN_Pos (8)
#define COMP2HCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP2HCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP2HCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP2H status   */
    COMP2HCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP2H status        */
} COMP2HCTL_BIT_SYNCCLREN;

#define COMP2HCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP2HCTL_ALL_SYNCCLREN_Pos)
#define COMP2HCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP2HCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       FLTDIV
 *  @access     COMP->COMP2HCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP2HCTL_ALL_FLTDIV_Pos (9)
#define COMP2HCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP2HCTL_ALL_FLTDIV_Pos)

#define COMP2HCTL_BIT_FLTDIV

#define COMP2HCTL_ALL_FLTDIV_(x) ((x) << COMP2HCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       FLTWIN
 *  @access     COMP->COMP2HCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP2HCTL_ALL_FLTWIN_Pos (19)
#define COMP2HCTL_ALL_FLTWIN_Msk (0x1FUL << COMP2HCTL_ALL_FLTWIN_Pos)

#define COMP2HCTL_BIT_FLTWIN

#define COMP2HCTL_ALL_FLTWIN_(x) ((x) << COMP2HCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       FLTTH
 *  @access     COMP->COMP2HCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP2HCTL_ALL_FLTTH_Pos (24)
#define COMP2HCTL_ALL_FLTTH_Msk (0x1FUL << COMP2HCTL_ALL_FLTTH_Pos)

#define COMP2HCTL_BIT_FLTTH

#define COMP2HCTL_ALL_FLTTH_(x) ((x) << COMP2HCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP2HCTL       FLTRST
 *  @access     COMP->COMP2HCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP2HCTL_ALL_FLTRST_Pos (29)
#define COMP2HCTL_ALL_FLTRST_Msk (0x1UL << COMP2HCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP2HCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP2HCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP2HCTL_BIT_FLTRST;

#define COMP2HCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP2HCTL_ALL_FLTRST_Pos)
#define COMP2HCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP2HCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3CTL        ENL
 *  @access     COMP->COMP3CTL.bit.ENL
 *  @brief      COMP3L enable
 */
#define COMP3CTL_ALL_ENL_Pos (0)
#define COMP3CTL_ALL_ENL_Msk (0x1UL << COMP3CTL_ALL_ENL_Pos)

typedef enum
{
    COMP3CTL_BIT_ENL_DISABLE     = 0,  /*!< Disable COMP3L   */
    COMP3CTL_BIT_ENL_ENABLE      = 1,  /*!< Enable COMP3L    */
} COMP3CTL_BIT_ENL;

#define COMP3CTL_ALL_ENL_DISABLE     ((0x0UL) << COMP3CTL_ALL_ENL_Pos)
#define COMP3CTL_ALL_ENL_ENABLE      ((0x1UL) << COMP3CTL_ALL_ENL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3CTL        ENH
 *  @access     COMP->COMP3CTL.bit.ENH
 *  @brief      COMP3H enable
 */
#define COMP3CTL_ALL_ENH_Pos (1)
#define COMP3CTL_ALL_ENH_Msk (0x1UL << COMP3CTL_ALL_ENH_Pos)

typedef enum
{
    COMP3CTL_BIT_ENH_DISABLE     = 0,  /*!< Disable COMP3H   */
    COMP3CTL_BIT_ENH_ENABLE      = 1,  /*!< Enable COMP3H    */
} COMP3CTL_BIT_ENH;

#define COMP3CTL_ALL_ENH_DISABLE     ((0x0UL) << COMP3CTL_ALL_ENH_Pos)
#define COMP3CTL_ALL_ENH_ENABLE      ((0x1UL) << COMP3CTL_ALL_ENH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3CTL        PHCMPEN
 *  @access     COMP->COMP3CTL.bit.PHCMPEN
 *  @brief      COMP3 phase comparison enable
 */
#define COMP3CTL_ALL_PHCMPEN_Pos (2)
#define COMP3CTL_ALL_PHCMPEN_Msk (0x1UL << COMP3CTL_ALL_PHCMPEN_Pos)

typedef enum
{
    COMP3CTL_BIT_PHCMPEN_DISABLE     = 0,  /*!< Normal operation        */
    COMP3CTL_BIT_PHCMPEN_ENABLE      = 1,  /*!< Phase comparison mode   */
} COMP3CTL_BIT_PHCMPEN;

#define COMP3CTL_ALL_PHCMPEN_DISABLE     ((0x0UL) << COMP3CTL_ALL_PHCMPEN_Pos)
#define COMP3CTL_ALL_PHCMPEN_ENABLE      ((0x1UL) << COMP3CTL_ALL_PHCMPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3CTL        HYSTSEL
 *  @access     COMP->COMP3CTL.bit.HYSTSEL
 *  @brief      COMP3 hysteresis select
 */
#define COMP3CTL_ALL_HYSTSEL_Pos (3)
#define COMP3CTL_ALL_HYSTSEL_Msk (0x3UL << COMP3CTL_ALL_HYSTSEL_Pos)

typedef enum
{
    COMP3CTL_BIT_HYSTSEL_0_MV      = 0,  /*!< 0 mV    */
    COMP3CTL_BIT_HYSTSEL_12_MV     = 1,  /*!< 12 mV   */
    COMP3CTL_BIT_HYSTSEL_24_MV     = 2,  /*!< 24 mV   */
    COMP3CTL_BIT_HYSTSEL_36_MV     = 3,  /*!< 36 mV   */
} COMP3CTL_BIT_HYSTSEL;

#define COMP3CTL_ALL_HYSTSEL_0_MV      ((0x0UL) << COMP3CTL_ALL_HYSTSEL_Pos)
#define COMP3CTL_ALL_HYSTSEL_12_MV     ((0x1UL) << COMP3CTL_ALL_HYSTSEL_Pos)
#define COMP3CTL_ALL_HYSTSEL_24_MV     ((0x2UL) << COMP3CTL_ALL_HYSTSEL_Pos)
#define COMP3CTL_ALL_HYSTSEL_36_MV     ((0x3UL) << COMP3CTL_ALL_HYSTSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3CTL        INSEL
 *  @access     COMP->COMP3CTL.bit.INSEL
 *  @brief      COMP3 input select
 */
#define COMP3CTL_ALL_INSEL_Pos (5)
#define COMP3CTL_ALL_INSEL_Msk (0x3UL << COMP3CTL_ALL_INSEL_Pos)

typedef enum
{
    COMP3CTL_BIT_INSEL_ADC0      = 0,  /*!< ADC0 input from GPIO0     */
    COMP3CTL_BIT_INSEL_ADC4      = 1,  /*!< ADC4 input from GPIO4     */
    COMP3CTL_BIT_INSEL_ADC8      = 2,  /*!< ADC8 input from GPIO8     */
    COMP3CTL_BIT_INSEL_ADC12     = 3,  /*!< ADC12 input from GPIO12   */
} COMP3CTL_BIT_INSEL;

#define COMP3CTL_ALL_INSEL_ADC0      ((0x0UL) << COMP3CTL_ALL_INSEL_Pos)
#define COMP3CTL_ALL_INSEL_ADC4      ((0x1UL) << COMP3CTL_ALL_INSEL_Pos)
#define COMP3CTL_ALL_INSEL_ADC8      ((0x2UL) << COMP3CTL_ALL_INSEL_Pos)
#define COMP3CTL_ALL_INSEL_ADC12     ((0x3UL) << COMP3CTL_ALL_INSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3CTL        REFSEL
 *  @access     COMP->COMP3CTL.bit.REFSEL
 *  @brief      COMP3 reference select
 */
#define COMP3CTL_ALL_REFSEL_Pos (7)
#define COMP3CTL_ALL_REFSEL_Msk (0x3UL << COMP3CTL_ALL_REFSEL_Pos)

typedef enum
{
    COMP3CTL_BIT_REFSEL_ADC1_OR_DAC0_DAC1      = 0,  /*!< ADC1 input from GPIO1 when PHCMPEN = 1;                                    
                                                          DAC0 as too-high reference and DAC1 as too-low reference when PHCMPEN = 0   */
    COMP3CTL_BIT_REFSEL_ADC5_OR_DAC1_DAC0      = 1,  /*!< ADC5 input from GPIO5 when PHCMPEN = 1;                                    
                                                          DAC1 as too-high reference and DAC0 as too-low reference when PHCMPEN = 0   */
    COMP3CTL_BIT_REFSEL_ADC9_OR_DAC2_DAC3      = 2,  /*!< ADC9 input from GPIO9 when PHCMPEN = 1;                                    
                                                          DAC2 as too-high reference and DAC3 as too-low reference when PHCMPEN = 0   */
    COMP3CTL_BIT_REFSEL_ADC13_OR_DAC3_DAC2     = 3,  /*!< ADC13 input from GPIO13 when PHCMPEN = 1;                                  
                                                          DAC3 as too-high reference and DAC2 as too-low reference when PHCMPEN = 0   */
} COMP3CTL_BIT_REFSEL;

#define COMP3CTL_ALL_REFSEL_ADC1_OR_DAC0_DAC1      ((0x0UL) << COMP3CTL_ALL_REFSEL_Pos)
#define COMP3CTL_ALL_REFSEL_ADC5_OR_DAC1_DAC0      ((0x1UL) << COMP3CTL_ALL_REFSEL_Pos)
#define COMP3CTL_ALL_REFSEL_ADC9_OR_DAC2_DAC3      ((0x2UL) << COMP3CTL_ALL_REFSEL_Pos)
#define COMP3CTL_ALL_REFSEL_ADC13_OR_DAC3_DAC2     ((0x3UL) << COMP3CTL_ALL_REFSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3CTL        SYNCSEL
 *  @access     COMP->COMP3CTL.bit.SYNCSEL
 *  @brief      Select the synchronous output from PWM[SYNCSEL]
 */
#define COMP3CTL_ALL_SYNCSEL_Pos (9)
#define COMP3CTL_ALL_SYNCSEL_Msk (0x7UL << COMP3CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    COMP3CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    COMP3CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    COMP3CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    COMP3CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    COMP3CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    COMP3CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} COMP3CTL_BIT_SYNCSEL;

#define COMP3CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << COMP3CTL_ALL_SYNCSEL_Pos)
#define COMP3CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << COMP3CTL_ALL_SYNCSEL_Pos)
#define COMP3CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << COMP3CTL_ALL_SYNCSEL_Pos)
#define COMP3CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << COMP3CTL_ALL_SYNCSEL_Pos)
#define COMP3CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << COMP3CTL_ALL_SYNCSEL_Pos)
#define COMP3CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << COMP3CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       SEL4PWM
 *  @access     COMP->COMP3LCTL.bit.SEL4PWM
 *  @brief      COMP3L output select for PWM
 */
#define COMP3LCTL_ALL_SEL4PWM_Pos (0)
#define COMP3LCTL_ALL_SEL4PWM_Msk (0x7UL << COMP3LCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP3LCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP3LCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP3LCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP3LCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP3LCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP3LCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP3LCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP3LCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP3LCTL_BIT_SEL4PWM;

#define COMP3LCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP3LCTL_ALL_SEL4PWM_Pos)
#define COMP3LCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP3LCTL_ALL_SEL4PWM_Pos)
#define COMP3LCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP3LCTL_ALL_SEL4PWM_Pos)
#define COMP3LCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP3LCTL_ALL_SEL4PWM_Pos)
#define COMP3LCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP3LCTL_ALL_SEL4PWM_Pos)
#define COMP3LCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP3LCTL_ALL_SEL4PWM_Pos)
#define COMP3LCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP3LCTL_ALL_SEL4PWM_Pos)
#define COMP3LCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP3LCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       POL4PWM
 *  @access     COMP->COMP3LCTL.bit.POL4PWM
 *  @brief      COMP3L output polarity for PWM
 */
#define COMP3LCTL_ALL_POL4PWM_Pos (3)
#define COMP3LCTL_ALL_POL4PWM_Msk (0x1UL << COMP3LCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP3LCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP3LCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP3LCTL_BIT_POL4PWM;

#define COMP3LCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP3LCTL_ALL_POL4PWM_Pos)
#define COMP3LCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP3LCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       SEL4GPIO
 *  @access     COMP->COMP3LCTL.bit.SEL4GPIO
 *  @brief      COMP3L output select for GPIO
 */
#define COMP3LCTL_ALL_SEL4GPIO_Pos (4)
#define COMP3LCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP3LCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP3LCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP3LCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP3LCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP3LCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP3LCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP3LCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP3LCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP3LCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP3LCTL_BIT_SEL4GPIO;

#define COMP3LCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP3LCTL_ALL_SEL4GPIO_Pos)
#define COMP3LCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP3LCTL_ALL_SEL4GPIO_Pos)
#define COMP3LCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP3LCTL_ALL_SEL4GPIO_Pos)
#define COMP3LCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP3LCTL_ALL_SEL4GPIO_Pos)
#define COMP3LCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP3LCTL_ALL_SEL4GPIO_Pos)
#define COMP3LCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP3LCTL_ALL_SEL4GPIO_Pos)
#define COMP3LCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP3LCTL_ALL_SEL4GPIO_Pos)
#define COMP3LCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP3LCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       POL4GPIO
 *  @access     COMP->COMP3LCTL.bit.POL4GPIO
 *  @brief      COMP3L output polarity for GPIO
 */
#define COMP3LCTL_ALL_POL4GPIO_Pos (7)
#define COMP3LCTL_ALL_POL4GPIO_Msk (0x1UL << COMP3LCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP3LCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP3LCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP3LCTL_BIT_POL4GPIO;

#define COMP3LCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP3LCTL_ALL_POL4GPIO_Pos)
#define COMP3LCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP3LCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       SYNCCLREN
 *  @access     COMP->COMP3LCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP3L status clear by PWMSYNC
 */
#define COMP3LCTL_ALL_SYNCCLREN_Pos (8)
#define COMP3LCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP3LCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP3LCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP3L status   */
    COMP3LCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP3L status        */
} COMP3LCTL_BIT_SYNCCLREN;

#define COMP3LCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP3LCTL_ALL_SYNCCLREN_Pos)
#define COMP3LCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP3LCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       FLTDIV
 *  @access     COMP->COMP3LCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP3LCTL_ALL_FLTDIV_Pos (9)
#define COMP3LCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP3LCTL_ALL_FLTDIV_Pos)

#define COMP3LCTL_BIT_FLTDIV

#define COMP3LCTL_ALL_FLTDIV_(x) ((x) << COMP3LCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       FLTWIN
 *  @access     COMP->COMP3LCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP3LCTL_ALL_FLTWIN_Pos (19)
#define COMP3LCTL_ALL_FLTWIN_Msk (0x1FUL << COMP3LCTL_ALL_FLTWIN_Pos)

#define COMP3LCTL_BIT_FLTWIN

#define COMP3LCTL_ALL_FLTWIN_(x) ((x) << COMP3LCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       FLTTH
 *  @access     COMP->COMP3LCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP3LCTL_ALL_FLTTH_Pos (24)
#define COMP3LCTL_ALL_FLTTH_Msk (0x1FUL << COMP3LCTL_ALL_FLTTH_Pos)

#define COMP3LCTL_BIT_FLTTH

#define COMP3LCTL_ALL_FLTTH_(x) ((x) << COMP3LCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3LCTL       FLTRST
 *  @access     COMP->COMP3LCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP3LCTL_ALL_FLTRST_Pos (29)
#define COMP3LCTL_ALL_FLTRST_Msk (0x1UL << COMP3LCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP3LCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP3LCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP3LCTL_BIT_FLTRST;

#define COMP3LCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP3LCTL_ALL_FLTRST_Pos)
#define COMP3LCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP3LCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       SEL4PWM
 *  @access     COMP->COMP3HCTL.bit.SEL4PWM
 *  @brief      COMP3H output select for PWM
 */
#define COMP3HCTL_ALL_SEL4PWM_Pos (0)
#define COMP3HCTL_ALL_SEL4PWM_Msk (0x7UL << COMP3HCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP3HCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP3HCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP3HCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP3HCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP3HCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP3HCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP3HCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP3HCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP3HCTL_BIT_SEL4PWM;

#define COMP3HCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP3HCTL_ALL_SEL4PWM_Pos)
#define COMP3HCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP3HCTL_ALL_SEL4PWM_Pos)
#define COMP3HCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP3HCTL_ALL_SEL4PWM_Pos)
#define COMP3HCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP3HCTL_ALL_SEL4PWM_Pos)
#define COMP3HCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP3HCTL_ALL_SEL4PWM_Pos)
#define COMP3HCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP3HCTL_ALL_SEL4PWM_Pos)
#define COMP3HCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP3HCTL_ALL_SEL4PWM_Pos)
#define COMP3HCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP3HCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       POL4PWM
 *  @access     COMP->COMP3HCTL.bit.POL4PWM
 *  @brief      COMP3H output polarity for PWM
 */
#define COMP3HCTL_ALL_POL4PWM_Pos (3)
#define COMP3HCTL_ALL_POL4PWM_Msk (0x1UL << COMP3HCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP3HCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP3HCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP3HCTL_BIT_POL4PWM;

#define COMP3HCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP3HCTL_ALL_POL4PWM_Pos)
#define COMP3HCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP3HCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       SEL4GPIO
 *  @access     COMP->COMP3HCTL.bit.SEL4GPIO
 *  @brief      COMP3H output select for GPIO
 */
#define COMP3HCTL_ALL_SEL4GPIO_Pos (4)
#define COMP3HCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP3HCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP3HCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP3HCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP3HCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP3HCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP3HCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP3HCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP3HCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP3HCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP3HCTL_BIT_SEL4GPIO;

#define COMP3HCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP3HCTL_ALL_SEL4GPIO_Pos)
#define COMP3HCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP3HCTL_ALL_SEL4GPIO_Pos)
#define COMP3HCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP3HCTL_ALL_SEL4GPIO_Pos)
#define COMP3HCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP3HCTL_ALL_SEL4GPIO_Pos)
#define COMP3HCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP3HCTL_ALL_SEL4GPIO_Pos)
#define COMP3HCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP3HCTL_ALL_SEL4GPIO_Pos)
#define COMP3HCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP3HCTL_ALL_SEL4GPIO_Pos)
#define COMP3HCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP3HCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       POL4GPIO
 *  @access     COMP->COMP3HCTL.bit.POL4GPIO
 *  @brief      COMP3H output polarity for GPIO
 */
#define COMP3HCTL_ALL_POL4GPIO_Pos (7)
#define COMP3HCTL_ALL_POL4GPIO_Msk (0x1UL << COMP3HCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP3HCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP3HCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP3HCTL_BIT_POL4GPIO;

#define COMP3HCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP3HCTL_ALL_POL4GPIO_Pos)
#define COMP3HCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP3HCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       SYNCCLREN
 *  @access     COMP->COMP3HCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP3H status clear by PWMSYNC
 */
#define COMP3HCTL_ALL_SYNCCLREN_Pos (8)
#define COMP3HCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP3HCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP3HCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP3H status   */
    COMP3HCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP3H status        */
} COMP3HCTL_BIT_SYNCCLREN;

#define COMP3HCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP3HCTL_ALL_SYNCCLREN_Pos)
#define COMP3HCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP3HCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       FLTDIV
 *  @access     COMP->COMP3HCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP3HCTL_ALL_FLTDIV_Pos (9)
#define COMP3HCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP3HCTL_ALL_FLTDIV_Pos)

#define COMP3HCTL_BIT_FLTDIV

#define COMP3HCTL_ALL_FLTDIV_(x) ((x) << COMP3HCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       FLTWIN
 *  @access     COMP->COMP3HCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP3HCTL_ALL_FLTWIN_Pos (19)
#define COMP3HCTL_ALL_FLTWIN_Msk (0x1FUL << COMP3HCTL_ALL_FLTWIN_Pos)

#define COMP3HCTL_BIT_FLTWIN

#define COMP3HCTL_ALL_FLTWIN_(x) ((x) << COMP3HCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       FLTTH
 *  @access     COMP->COMP3HCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP3HCTL_ALL_FLTTH_Pos (24)
#define COMP3HCTL_ALL_FLTTH_Msk (0x1FUL << COMP3HCTL_ALL_FLTTH_Pos)

#define COMP3HCTL_BIT_FLTTH

#define COMP3HCTL_ALL_FLTTH_(x) ((x) << COMP3HCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP3HCTL       FLTRST
 *  @access     COMP->COMP3HCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP3HCTL_ALL_FLTRST_Pos (29)
#define COMP3HCTL_ALL_FLTRST_Msk (0x1UL << COMP3HCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP3HCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP3HCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP3HCTL_BIT_FLTRST;

#define COMP3HCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP3HCTL_ALL_FLTRST_Pos)
#define COMP3HCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP3HCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4CTL        ENL
 *  @access     COMP->COMP4CTL.bit.ENL
 *  @brief      COMP4L enable
 */
#define COMP4CTL_ALL_ENL_Pos (0)
#define COMP4CTL_ALL_ENL_Msk (0x1UL << COMP4CTL_ALL_ENL_Pos)

typedef enum
{
    COMP4CTL_BIT_ENL_DISABLE     = 0,  /*!< Disable COMP4L   */
    COMP4CTL_BIT_ENL_ENABLE      = 1,  /*!< Enable COMP4L    */
} COMP4CTL_BIT_ENL;

#define COMP4CTL_ALL_ENL_DISABLE     ((0x0UL) << COMP4CTL_ALL_ENL_Pos)
#define COMP4CTL_ALL_ENL_ENABLE      ((0x1UL) << COMP4CTL_ALL_ENL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4CTL        ENH
 *  @access     COMP->COMP4CTL.bit.ENH
 *  @brief      COMP4H enable
 */
#define COMP4CTL_ALL_ENH_Pos (1)
#define COMP4CTL_ALL_ENH_Msk (0x1UL << COMP4CTL_ALL_ENH_Pos)

typedef enum
{
    COMP4CTL_BIT_ENH_DISABLE     = 0,  /*!< Disable COMP4H   */
    COMP4CTL_BIT_ENH_ENABLE      = 1,  /*!< Enable COMP4H    */
} COMP4CTL_BIT_ENH;

#define COMP4CTL_ALL_ENH_DISABLE     ((0x0UL) << COMP4CTL_ALL_ENH_Pos)
#define COMP4CTL_ALL_ENH_ENABLE      ((0x1UL) << COMP4CTL_ALL_ENH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4CTL        PHCMPEN
 *  @access     COMP->COMP4CTL.bit.PHCMPEN
 *  @brief      COMP4 phase comparison enable
 */
#define COMP4CTL_ALL_PHCMPEN_Pos (2)
#define COMP4CTL_ALL_PHCMPEN_Msk (0x1UL << COMP4CTL_ALL_PHCMPEN_Pos)

typedef enum
{
    COMP4CTL_BIT_PHCMPEN_DISABLE     = 0,  /*!< Normal operation        */
    COMP4CTL_BIT_PHCMPEN_ENABLE      = 1,  /*!< Phase comparison mode   */
} COMP4CTL_BIT_PHCMPEN;

#define COMP4CTL_ALL_PHCMPEN_DISABLE     ((0x0UL) << COMP4CTL_ALL_PHCMPEN_Pos)
#define COMP4CTL_ALL_PHCMPEN_ENABLE      ((0x1UL) << COMP4CTL_ALL_PHCMPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4CTL        HYSTSEL
 *  @access     COMP->COMP4CTL.bit.HYSTSEL
 *  @brief      COMP4 hysteresis select
 */
#define COMP4CTL_ALL_HYSTSEL_Pos (3)
#define COMP4CTL_ALL_HYSTSEL_Msk (0x3UL << COMP4CTL_ALL_HYSTSEL_Pos)

typedef enum
{
    COMP4CTL_BIT_HYSTSEL_0_MV      = 0,  /*!< 0 mV    */
    COMP4CTL_BIT_HYSTSEL_12_MV     = 1,  /*!< 12 mV   */
    COMP4CTL_BIT_HYSTSEL_24_MV     = 2,  /*!< 24 mV   */
    COMP4CTL_BIT_HYSTSEL_36_MV     = 3,  /*!< 36 mV   */
} COMP4CTL_BIT_HYSTSEL;

#define COMP4CTL_ALL_HYSTSEL_0_MV      ((0x0UL) << COMP4CTL_ALL_HYSTSEL_Pos)
#define COMP4CTL_ALL_HYSTSEL_12_MV     ((0x1UL) << COMP4CTL_ALL_HYSTSEL_Pos)
#define COMP4CTL_ALL_HYSTSEL_24_MV     ((0x2UL) << COMP4CTL_ALL_HYSTSEL_Pos)
#define COMP4CTL_ALL_HYSTSEL_36_MV     ((0x3UL) << COMP4CTL_ALL_HYSTSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4CTL        INSEL
 *  @access     COMP->COMP4CTL.bit.INSEL
 *  @brief      COMP4 input select
 */
#define COMP4CTL_ALL_INSEL_Pos (5)
#define COMP4CTL_ALL_INSEL_Msk (0x3UL << COMP4CTL_ALL_INSEL_Pos)

typedef enum
{
    COMP4CTL_BIT_INSEL_ADC2      = 0,  /*!< ADC2 input from GPIO2     */
    COMP4CTL_BIT_INSEL_ADC6      = 1,  /*!< ADC6 input from GPIO6     */
    COMP4CTL_BIT_INSEL_ADC10     = 2,  /*!< ADC10 input from GPIO10   */
    COMP4CTL_BIT_INSEL_ADC14     = 3,  /*!< ADC14 input from GPIO14   */
} COMP4CTL_BIT_INSEL;

#define COMP4CTL_ALL_INSEL_ADC2      ((0x0UL) << COMP4CTL_ALL_INSEL_Pos)
#define COMP4CTL_ALL_INSEL_ADC6      ((0x1UL) << COMP4CTL_ALL_INSEL_Pos)
#define COMP4CTL_ALL_INSEL_ADC10     ((0x2UL) << COMP4CTL_ALL_INSEL_Pos)
#define COMP4CTL_ALL_INSEL_ADC14     ((0x3UL) << COMP4CTL_ALL_INSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4CTL        REFSEL
 *  @access     COMP->COMP4CTL.bit.REFSEL
 *  @brief      COMP4 reference select
 */
#define COMP4CTL_ALL_REFSEL_Pos (7)
#define COMP4CTL_ALL_REFSEL_Msk (0x3UL << COMP4CTL_ALL_REFSEL_Pos)

typedef enum
{
    COMP4CTL_BIT_REFSEL_ADC3_OR_DAC0_DAC1      = 0,  /*!< ADC3 input from GPIO3 when PHCMPEN = 1;                                    
                                                          DAC0 as too-high reference and DAC1 as too-low reference when PHCMPEN = 0   */
    COMP4CTL_BIT_REFSEL_ADC7_OR_DAC1_DAC0      = 1,  /*!< ADC7 input from GPIO7 when PHCMPEN = 1;                                    
                                                          DAC1 as too-high reference and DAC0 as too-low reference when PHCMPEN = 0   */
    COMP4CTL_BIT_REFSEL_ADC11_OR_DAC2_DAC3     = 2,  /*!< ADC11 input from GPIO11 when PHCMPEN = 1;                                  
                                                          DAC2 as too-high reference and DAC3 as too-low reference when PHCMPEN = 0   */
    COMP4CTL_BIT_REFSEL_ADC15_OR_DAC3_DAC2     = 3,  /*!< ADC15 input from GPIO15 when PHCMPEN = 1;                                  
                                                          DAC3 as too-high reference and DAC2 as too-low reference when PHCMPEN = 0   */
} COMP4CTL_BIT_REFSEL;

#define COMP4CTL_ALL_REFSEL_ADC3_OR_DAC0_DAC1      ((0x0UL) << COMP4CTL_ALL_REFSEL_Pos)
#define COMP4CTL_ALL_REFSEL_ADC7_OR_DAC1_DAC0      ((0x1UL) << COMP4CTL_ALL_REFSEL_Pos)
#define COMP4CTL_ALL_REFSEL_ADC11_OR_DAC2_DAC3     ((0x2UL) << COMP4CTL_ALL_REFSEL_Pos)
#define COMP4CTL_ALL_REFSEL_ADC15_OR_DAC3_DAC2     ((0x3UL) << COMP4CTL_ALL_REFSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4CTL        SYNCSEL
 *  @access     COMP->COMP4CTL.bit.SYNCSEL
 *  @brief      Select the synchronous output from PWM[SYNCSEL]
 */
#define COMP4CTL_ALL_SYNCSEL_Pos (9)
#define COMP4CTL_ALL_SYNCSEL_Msk (0x7UL << COMP4CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    COMP4CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    COMP4CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    COMP4CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    COMP4CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    COMP4CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    COMP4CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} COMP4CTL_BIT_SYNCSEL;

#define COMP4CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << COMP4CTL_ALL_SYNCSEL_Pos)
#define COMP4CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << COMP4CTL_ALL_SYNCSEL_Pos)
#define COMP4CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << COMP4CTL_ALL_SYNCSEL_Pos)
#define COMP4CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << COMP4CTL_ALL_SYNCSEL_Pos)
#define COMP4CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << COMP4CTL_ALL_SYNCSEL_Pos)
#define COMP4CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << COMP4CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       SEL4PWM
 *  @access     COMP->COMP4LCTL.bit.SEL4PWM
 *  @brief      COMP4L output select for PWM
 */
#define COMP4LCTL_ALL_SEL4PWM_Pos (0)
#define COMP4LCTL_ALL_SEL4PWM_Msk (0x7UL << COMP4LCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP4LCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP4LCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP4LCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP4LCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP4LCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP4LCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP4LCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP4LCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP4LCTL_BIT_SEL4PWM;

#define COMP4LCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP4LCTL_ALL_SEL4PWM_Pos)
#define COMP4LCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP4LCTL_ALL_SEL4PWM_Pos)
#define COMP4LCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP4LCTL_ALL_SEL4PWM_Pos)
#define COMP4LCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP4LCTL_ALL_SEL4PWM_Pos)
#define COMP4LCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP4LCTL_ALL_SEL4PWM_Pos)
#define COMP4LCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP4LCTL_ALL_SEL4PWM_Pos)
#define COMP4LCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP4LCTL_ALL_SEL4PWM_Pos)
#define COMP4LCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP4LCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       POL4PWM
 *  @access     COMP->COMP4LCTL.bit.POL4PWM
 *  @brief      COMP4L output polarity for PWM
 */
#define COMP4LCTL_ALL_POL4PWM_Pos (3)
#define COMP4LCTL_ALL_POL4PWM_Msk (0x1UL << COMP4LCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP4LCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP4LCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP4LCTL_BIT_POL4PWM;

#define COMP4LCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP4LCTL_ALL_POL4PWM_Pos)
#define COMP4LCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP4LCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       SEL4GPIO
 *  @access     COMP->COMP4LCTL.bit.SEL4GPIO
 *  @brief      COMP4L output select for GPIO
 */
#define COMP4LCTL_ALL_SEL4GPIO_Pos (4)
#define COMP4LCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP4LCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP4LCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP4LCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP4LCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP4LCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP4LCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP4LCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP4LCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP4LCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP4LCTL_BIT_SEL4GPIO;

#define COMP4LCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP4LCTL_ALL_SEL4GPIO_Pos)
#define COMP4LCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP4LCTL_ALL_SEL4GPIO_Pos)
#define COMP4LCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP4LCTL_ALL_SEL4GPIO_Pos)
#define COMP4LCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP4LCTL_ALL_SEL4GPIO_Pos)
#define COMP4LCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP4LCTL_ALL_SEL4GPIO_Pos)
#define COMP4LCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP4LCTL_ALL_SEL4GPIO_Pos)
#define COMP4LCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP4LCTL_ALL_SEL4GPIO_Pos)
#define COMP4LCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP4LCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       POL4GPIO
 *  @access     COMP->COMP4LCTL.bit.POL4GPIO
 *  @brief      COMP4L output polarity for GPIO
 */
#define COMP4LCTL_ALL_POL4GPIO_Pos (7)
#define COMP4LCTL_ALL_POL4GPIO_Msk (0x1UL << COMP4LCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP4LCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is lower than the reference   */
    COMP4LCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is lower than the reference   */
} COMP4LCTL_BIT_POL4GPIO;

#define COMP4LCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP4LCTL_ALL_POL4GPIO_Pos)
#define COMP4LCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP4LCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       SYNCCLREN
 *  @access     COMP->COMP4LCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP4L status clear by PWMSYNC
 */
#define COMP4LCTL_ALL_SYNCCLREN_Pos (8)
#define COMP4LCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP4LCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP4LCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP4L status   */
    COMP4LCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP4L status        */
} COMP4LCTL_BIT_SYNCCLREN;

#define COMP4LCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP4LCTL_ALL_SYNCCLREN_Pos)
#define COMP4LCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP4LCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       FLTDIV
 *  @access     COMP->COMP4LCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP4LCTL_ALL_FLTDIV_Pos (9)
#define COMP4LCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP4LCTL_ALL_FLTDIV_Pos)

#define COMP4LCTL_BIT_FLTDIV

#define COMP4LCTL_ALL_FLTDIV_(x) ((x) << COMP4LCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       FLTWIN
 *  @access     COMP->COMP4LCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP4LCTL_ALL_FLTWIN_Pos (19)
#define COMP4LCTL_ALL_FLTWIN_Msk (0x1FUL << COMP4LCTL_ALL_FLTWIN_Pos)

#define COMP4LCTL_BIT_FLTWIN

#define COMP4LCTL_ALL_FLTWIN_(x) ((x) << COMP4LCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       FLTTH
 *  @access     COMP->COMP4LCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP4LCTL_ALL_FLTTH_Pos (24)
#define COMP4LCTL_ALL_FLTTH_Msk (0x1FUL << COMP4LCTL_ALL_FLTTH_Pos)

#define COMP4LCTL_BIT_FLTTH

#define COMP4LCTL_ALL_FLTTH_(x) ((x) << COMP4LCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4LCTL       FLTRST
 *  @access     COMP->COMP4LCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP4LCTL_ALL_FLTRST_Pos (29)
#define COMP4LCTL_ALL_FLTRST_Msk (0x1UL << COMP4LCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP4LCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP4LCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP4LCTL_BIT_FLTRST;

#define COMP4LCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP4LCTL_ALL_FLTRST_Pos)
#define COMP4LCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP4LCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       SEL4PWM
 *  @access     COMP->COMP4HCTL.bit.SEL4PWM
 *  @brief      COMP4H output select for PWM
 */
#define COMP4HCTL_ALL_SEL4PWM_Pos (0)
#define COMP4HCTL_ALL_SEL4PWM_Msk (0x7UL << COMP4HCTL_ALL_SEL4PWM_Pos)

typedef enum
{
    COMP4HCTL_BIT_SEL4PWM_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP4HCTL_BIT_SEL4PWM_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP4HCTL_BIT_SEL4PWM_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP4HCTL_BIT_SEL4PWM_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP4HCTL_BIT_SEL4PWM_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP4HCTL_BIT_SEL4PWM_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP4HCTL_BIT_SEL4PWM_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP4HCTL_BIT_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP4HCTL_BIT_SEL4PWM;

#define COMP4HCTL_ALL_SEL4PWM_ORIGINAL                        ((0x0UL) << COMP4HCTL_ALL_SEL4PWM_Pos)
#define COMP4HCTL_ALL_SEL4PWM_SYNC                            ((0x1UL) << COMP4HCTL_ALL_SEL4PWM_Pos)
#define COMP4HCTL_ALL_SEL4PWM_FILTRED                         ((0x2UL) << COMP4HCTL_ALL_SEL4PWM_Pos)
#define COMP4HCTL_ALL_SEL4PWM_LATCHED                         ((0x3UL) << COMP4HCTL_ALL_SEL4PWM_Pos)
#define COMP4HCTL_ALL_SEL4PWM_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP4HCTL_ALL_SEL4PWM_Pos)
#define COMP4HCTL_ALL_SEL4PWM_SYNC_OR_LATCHED                 ((0x5UL) << COMP4HCTL_ALL_SEL4PWM_Pos)
#define COMP4HCTL_ALL_SEL4PWM_FILTERED_OR_LATCHED             ((0x6UL) << COMP4HCTL_ALL_SEL4PWM_Pos)
#define COMP4HCTL_ALL_SEL4PWM_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP4HCTL_ALL_SEL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       POL4PWM
 *  @access     COMP->COMP4HCTL.bit.POL4PWM
 *  @brief      COMP4H output polarity for PWM
 */
#define COMP4HCTL_ALL_POL4PWM_Pos (3)
#define COMP4HCTL_ALL_POL4PWM_Msk (0x1UL << COMP4HCTL_ALL_POL4PWM_Pos)

typedef enum
{
    COMP4HCTL_BIT_POL4PWM_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP4HCTL_BIT_POL4PWM_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP4HCTL_BIT_POL4PWM;

#define COMP4HCTL_ALL_POL4PWM_ACTIVE_LOW      ((0x0UL) << COMP4HCTL_ALL_POL4PWM_Pos)
#define COMP4HCTL_ALL_POL4PWM_ACTIVE_HIGH     ((0x1UL) << COMP4HCTL_ALL_POL4PWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       SEL4GPIO
 *  @access     COMP->COMP4HCTL.bit.SEL4GPIO
 *  @brief      COMP4H output select for GPIO
 */
#define COMP4HCTL_ALL_SEL4GPIO_Pos (4)
#define COMP4HCTL_ALL_SEL4GPIO_Msk (0x7UL << COMP4HCTL_ALL_SEL4GPIO_Pos)

typedef enum
{
    COMP4HCTL_BIT_SEL4GPIO_ORIGINAL                        = 0,  /*!< Original output                                                                         */
    COMP4HCTL_BIT_SEL4GPIO_SYNC                            = 1,  /*!< Synchronous output with PWM clock                                                       */
    COMP4HCTL_BIT_SEL4GPIO_FILTRED                         = 2,  /*!< Digital filter output                                                                   */
    COMP4HCTL_BIT_SEL4GPIO_LATCHED                         = 3,  /*!< Latched digital filter output                                                           */
    COMP4HCTL_BIT_SEL4GPIO_ORIGINAL_OR_LATCHED             = 4,  /*!< Original output or Latched digital filter output                                        */
    COMP4HCTL_BIT_SEL4GPIO_SYNC_OR_LATCHED                 = 5,  /*!< Synchronous output with PWM clock or Latched digital filter output                      */
    COMP4HCTL_BIT_SEL4GPIO_FILTERED_OR_LATCHED             = 6,  /*!< Digital filter output or the latched one                                                */
    COMP4HCTL_BIT_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     = 7,  /*!< Original output or Synchronous output with PWM clock or Latched digital filter output   */
} COMP4HCTL_BIT_SEL4GPIO;

#define COMP4HCTL_ALL_SEL4GPIO_ORIGINAL                        ((0x0UL) << COMP4HCTL_ALL_SEL4GPIO_Pos)
#define COMP4HCTL_ALL_SEL4GPIO_SYNC                            ((0x1UL) << COMP4HCTL_ALL_SEL4GPIO_Pos)
#define COMP4HCTL_ALL_SEL4GPIO_FILTRED                         ((0x2UL) << COMP4HCTL_ALL_SEL4GPIO_Pos)
#define COMP4HCTL_ALL_SEL4GPIO_LATCHED                         ((0x3UL) << COMP4HCTL_ALL_SEL4GPIO_Pos)
#define COMP4HCTL_ALL_SEL4GPIO_ORIGINAL_OR_LATCHED             ((0x4UL) << COMP4HCTL_ALL_SEL4GPIO_Pos)
#define COMP4HCTL_ALL_SEL4GPIO_SYNC_OR_LATCHED                 ((0x5UL) << COMP4HCTL_ALL_SEL4GPIO_Pos)
#define COMP4HCTL_ALL_SEL4GPIO_FILTERED_OR_LATCHED             ((0x6UL) << COMP4HCTL_ALL_SEL4GPIO_Pos)
#define COMP4HCTL_ALL_SEL4GPIO_ORIGINAL_OR_SYNC_OR_LATCHED     ((0x7UL) << COMP4HCTL_ALL_SEL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       POL4GPIO
 *  @access     COMP->COMP4HCTL.bit.POL4GPIO
 *  @brief      COMP4H output polarity for GPIO
 */
#define COMP4HCTL_ALL_POL4GPIO_Pos (7)
#define COMP4HCTL_ALL_POL4GPIO_Msk (0x1UL << COMP4HCTL_ALL_POL4GPIO_Pos)

typedef enum
{
    COMP4HCTL_BIT_POL4GPIO_ACTIVE_LOW      = 0,  /*!< Output 0 when the comparator input is higher than the reference   */
    COMP4HCTL_BIT_POL4GPIO_ACTIVE_HIGH     = 1,  /*!< Output 1 when the comparator input is higher than the reference   */
} COMP4HCTL_BIT_POL4GPIO;

#define COMP4HCTL_ALL_POL4GPIO_ACTIVE_LOW      ((0x0UL) << COMP4HCTL_ALL_POL4GPIO_Pos)
#define COMP4HCTL_ALL_POL4GPIO_ACTIVE_HIGH     ((0x1UL) << COMP4HCTL_ALL_POL4GPIO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       SYNCCLREN
 *  @access     COMP->COMP4HCTL.bit.SYNCCLREN
 *  @brief      Enable latched COMP4H status clear by PWMSYNC
 */
#define COMP4HCTL_ALL_SYNCCLREN_Pos (8)
#define COMP4HCTL_ALL_SYNCCLREN_Msk (0x1UL << COMP4HCTL_ALL_SYNCCLREN_Pos)

typedef enum
{
    COMP4HCTL_BIT_SYNCCLREN_DISABLE     = 0,  /*!< PWMSYNC does not affect the latched COMP4H status   */
    COMP4HCTL_BIT_SYNCCLREN_ENABLE      = 1,  /*!< PWMSYNC will clear the latched COMP4H status        */
} COMP4HCTL_BIT_SYNCCLREN;

#define COMP4HCTL_ALL_SYNCCLREN_DISABLE     ((0x0UL) << COMP4HCTL_ALL_SYNCCLREN_Pos)
#define COMP4HCTL_ALL_SYNCCLREN_ENABLE      ((0x1UL) << COMP4HCTL_ALL_SYNCCLREN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       FLTDIV
 *  @access     COMP->COMP4HCTL.bit.FLTDIV
 *  @brief      Filter's clock dividing ratio is (FLTDIV+1)
 */
#define COMP4HCTL_ALL_FLTDIV_Pos (9)
#define COMP4HCTL_ALL_FLTDIV_Msk (0x3FFUL << COMP4HCTL_ALL_FLTDIV_Pos)

#define COMP4HCTL_BIT_FLTDIV

#define COMP4HCTL_ALL_FLTDIV_(x) ((x) << COMP4HCTL_ALL_FLTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       FLTWIN
 *  @access     COMP->COMP4HCTL.bit.FLTWIN
 *  @brief      Filter's window size is (FLTWIN+1) samples
 */
#define COMP4HCTL_ALL_FLTWIN_Pos (19)
#define COMP4HCTL_ALL_FLTWIN_Msk (0x1FUL << COMP4HCTL_ALL_FLTWIN_Pos)

#define COMP4HCTL_BIT_FLTWIN

#define COMP4HCTL_ALL_FLTWIN_(x) ((x) << COMP4HCTL_ALL_FLTWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       FLTTH
 *  @access     COMP->COMP4HCTL.bit.FLTTH
 *  @brief      Filter's threshold is (FLTTH+1) 1's/0's for output to toggle
 */
#define COMP4HCTL_ALL_FLTTH_Pos (24)
#define COMP4HCTL_ALL_FLTTH_Msk (0x1FUL << COMP4HCTL_ALL_FLTTH_Pos)

#define COMP4HCTL_BIT_FLTTH

#define COMP4HCTL_ALL_FLTTH_(x) ((x) << COMP4HCTL_ALL_FLTTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMP4HCTL       FLTRST
 *  @access     COMP->COMP4HCTL.bit.FLTRST
 *  @brief      Reset all registers in the filter with the input
 */
#define COMP4HCTL_ALL_FLTRST_Pos (29)
#define COMP4HCTL_ALL_FLTRST_Msk (0x1UL << COMP4HCTL_ALL_FLTRST_Pos)

typedef enum
{
    COMP4HCTL_BIT_FLTRST_NO_EFFECT     = 0,  /*!< Write 0 has no effect. Always read back 0.                     */
    COMP4HCTL_BIT_FLTRST_RESET         = 1,  /*!< Write 1 will fill all registers in the filter with the input   */
} COMP4HCTL_BIT_FLTRST;

#define COMP4HCTL_ALL_FLTRST_NO_EFFECT     ((0x0UL) << COMP4HCTL_ALL_FLTRST_Pos)
#define COMP4HCTL_ALL_FLTRST_RESET         ((0x1UL) << COMP4HCTL_ALL_FLTRST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CTL         EN
 *  @access     COMP->DAC0CTL.bit.EN
 *  @brief      DAC enable
 */
#define DAC0CTL_ALL_EN_Pos (0)
#define DAC0CTL_ALL_EN_Msk (0x1UL << DAC0CTL_ALL_EN_Pos)

typedef enum
{
    DAC0CTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    DAC0CTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} DAC0CTL_BIT_EN;

#define DAC0CTL_ALL_EN_DISABLE     ((0x0UL) << DAC0CTL_ALL_EN_Pos)
#define DAC0CTL_ALL_EN_ENABLE      ((0x1UL) << DAC0CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CTL         CODELOAD
 *  @access     COMP->DAC0CTL.bit.CODELOAD
 *  @brief      DAC code load mode
 */
#define DAC0CTL_ALL_CODELOAD_Pos (1)
#define DAC0CTL_ALL_CODELOAD_Msk (0x1UL << DAC0CTL_ALL_CODELOAD_Pos)

typedef enum
{
    DAC0CTL_BIT_CODELOAD_SHADOW_MODE     = 0,  /*!< DAC code is updated upon PWMSYNC event                   */
    DAC0CTL_BIT_CODELOAD_DIRECT_MODE     = 1,  /*!< DAC code is immediately updated by writing to DAC0CODE   */
} DAC0CTL_BIT_CODELOAD;

#define DAC0CTL_ALL_CODELOAD_SHADOW_MODE     ((0x0UL) << DAC0CTL_ALL_CODELOAD_Pos)
#define DAC0CTL_ALL_CODELOAD_DIRECT_MODE     ((0x1UL) << DAC0CTL_ALL_CODELOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CTL         SYNCSEL
 *  @access     COMP->DAC0CTL.bit.SYNCSEL
 *  @brief      PWMSYNC is selected from PWM[SYNCSEL]
 */
#define DAC0CTL_ALL_SYNCSEL_Pos (2)
#define DAC0CTL_ALL_SYNCSEL_Msk (0x7UL << DAC0CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    DAC0CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    DAC0CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    DAC0CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    DAC0CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    DAC0CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    DAC0CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} DAC0CTL_BIT_SYNCSEL;

#define DAC0CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << DAC0CTL_ALL_SYNCSEL_Pos)
#define DAC0CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << DAC0CTL_ALL_SYNCSEL_Pos)
#define DAC0CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << DAC0CTL_ALL_SYNCSEL_Pos)
#define DAC0CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << DAC0CTL_ALL_SYNCSEL_Pos)
#define DAC0CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << DAC0CTL_ALL_SYNCSEL_Pos)
#define DAC0CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << DAC0CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CTL         RAMPEN
 *  @access     COMP->DAC0CTL.bit.RAMPEN
 *  @brief      DAC Ramping enable
 */
#define DAC0CTL_ALL_RAMPEN_Pos (5)
#define DAC0CTL_ALL_RAMPEN_Msk (0x1UL << DAC0CTL_ALL_RAMPEN_Pos)

typedef enum
{
    DAC0CTL_BIT_RAMPEN_DISABLE     = 0,  /*!< Disable ramping                                                      */
    DAC0CTL_BIT_RAMPEN_ENABLE      = 1,  /*!< Enable ramping. DAC0CODEA is equivalent to the 10 MSBs of RAMP0CNT   */
} DAC0CTL_BIT_RAMPEN;

#define DAC0CTL_ALL_RAMPEN_DISABLE     ((0x0UL) << DAC0CTL_ALL_RAMPEN_Pos)
#define DAC0CTL_ALL_RAMPEN_ENABLE      ((0x1UL) << DAC0CTL_ALL_RAMPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CTL         RAMPLOAD
 *  @access     COMP->DAC0CTL.bit.RAMPLOAD
 *  @brief      DAC Ramp load mode
 */
#define DAC0CTL_ALL_RAMPLOAD_Pos (6)
#define DAC0CTL_ALL_RAMPLOAD_Msk (0x1UL << DAC0CTL_ALL_RAMPLOAD_Pos)

typedef enum
{
    DAC0CTL_BIT_RAMPLOAD_SHADOW_MODE     = 0,  /*!< Register shadowing is applied for ramping counter load from RAMPMAX   */
    DAC0CTL_BIT_RAMPLOAD_DIRECT_MODE     = 1,  /*!< RAMP counter is directly loaded from the latest RAMPMAX               */
} DAC0CTL_BIT_RAMPLOAD;

#define DAC0CTL_ALL_RAMPLOAD_SHADOW_MODE     ((0x0UL) << DAC0CTL_ALL_RAMPLOAD_Pos)
#define DAC0CTL_ALL_RAMPLOAD_DIRECT_MODE     ((0x1UL) << DAC0CTL_ALL_RAMPLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CTL         COMPHSEL
 *  @access     COMP->DAC0CTL.bit.COMPHSEL
 *  @brief      Select COMPH from COMP[COMPHSEL]
 *              Note: This field is used for RAMP function.
 */
#define DAC0CTL_ALL_COMPHSEL_Pos (7)
#define DAC0CTL_ALL_COMPHSEL_Msk (0x7UL << DAC0CTL_ALL_COMPHSEL_Pos)

typedef enum
{
    DAC0CTL_BIT_COMPHSEL_COMP0H     = 0,  /*!< COMP0H   */
    DAC0CTL_BIT_COMPHSEL_COMP1H     = 1,  /*!< COMP1H   */
    DAC0CTL_BIT_COMPHSEL_COMP2H     = 2,  /*!< COMP2H   */
    DAC0CTL_BIT_COMPHSEL_COMP3H     = 3,  /*!< COMP3H   */
    DAC0CTL_BIT_COMPHSEL_COMP4H     = 4,  /*!< COMP4H   */
} DAC0CTL_BIT_COMPHSEL;

#define DAC0CTL_ALL_COMPHSEL_COMP0H     ((0x0UL) << DAC0CTL_ALL_COMPHSEL_Pos)
#define DAC0CTL_ALL_COMPHSEL_COMP1H     ((0x1UL) << DAC0CTL_ALL_COMPHSEL_Pos)
#define DAC0CTL_ALL_COMPHSEL_COMP2H     ((0x2UL) << DAC0CTL_ALL_COMPHSEL_Pos)
#define DAC0CTL_ALL_COMPHSEL_COMP3H     ((0x3UL) << DAC0CTL_ALL_COMPHSEL_Pos)
#define DAC0CTL_ALL_COMPHSEL_COMP4H     ((0x4UL) << DAC0CTL_ALL_COMPHSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CTL         DBGRUN
 *  @access     COMP->DAC0CTL.bit.DBGRUN
 *  @brief      Behavior on CPU halted or lockup
 */
#define DAC0CTL_ALL_DBGRUN_Pos (10)
#define DAC0CTL_ALL_DBGRUN_Msk (0x3UL << DAC0CTL_ALL_DBGRUN_Pos)

typedef enum
{
    DAC0CTL_BIT_DBGRUN_STOP_IMMEDIATELY     = 0,  /*!< Stop immediately                */
    DAC0CTL_BIT_DBGRUN_STOP_AT_PWMSYNC      = 1,  /*!< Stop at PWM synchronous event   */
    DAC0CTL_BIT_DBGRUN_KEEP_RUN             = 2,  /*!< Free running                    */
} DAC0CTL_BIT_DBGRUN;

#define DAC0CTL_ALL_DBGRUN_STOP_IMMEDIATELY     ((0x0UL) << DAC0CTL_ALL_DBGRUN_Pos)
#define DAC0CTL_ALL_DBGRUN_STOP_AT_PWMSYNC      ((0x1UL) << DAC0CTL_ALL_DBGRUN_Pos)
#define DAC0CTL_ALL_DBGRUN_KEEP_RUN             ((0x2UL) << DAC0CTL_ALL_DBGRUN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CODE        VAL
 *  @access     COMP->DAC0CODE.bit.VAL
 *  @brief      DAC code
 *              When DAC0CTL[CODELOAD]=0, write to this field only affects the shadow code.
 *              When DAC0CTL[CODELOAD]=1, write to this field affects both the shadow code and the
 *              active code.
 */
#define DAC0CODE_ALL_VAL_Pos (0)
#define DAC0CODE_ALL_VAL_Msk (0x3FFUL << DAC0CODE_ALL_VAL_Pos)

#define DAC0CODE_BIT_VAL

#define DAC0CODE_ALL_VAL_(x) ((x) << DAC0CODE_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC0CODEA       VAL
 *  @access     COMP->DAC0CODEA.bit.VAL
 *  @brief      Active DAC code
 */
#define DAC0CODEA_ALL_VAL_Pos (0)
#define DAC0CODEA_ALL_VAL_Msk (0x3FFUL << DAC0CODEA_ALL_VAL_Pos)

#define DAC0CODEA_BIT_VAL

#define DAC0CODEA_ALL_VAL_(x) ((x) << DAC0CODEA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP0DLY        VAL
 *  @access     COMP->RAMP0DLY.bit.VAL
 *  @brief      Delay from PWMSYNC to start of ramping
 */
#define RAMP0DLY_ALL_VAL_Pos (0)
#define RAMP0DLY_ALL_VAL_Msk (0xFFFFUL << RAMP0DLY_ALL_VAL_Pos)

#define RAMP0DLY_BIT_VAL

#define RAMP0DLY_ALL_VAL_(x) ((x) << RAMP0DLY_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP0DLYA       VAL
 *  @access     COMP->RAMP0DLYA.bit.VAL
 *  @brief      Delay from PWMSYNC to start of ramping
 */
#define RAMP0DLYA_ALL_VAL_Pos (0)
#define RAMP0DLYA_ALL_VAL_Msk (0xFFFFUL << RAMP0DLYA_ALL_VAL_Pos)

#define RAMP0DLYA_BIT_VAL

#define RAMP0DLYA_ALL_VAL_(x) ((x) << RAMP0DLYA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP0DEC        VAL
 *  @access     COMP->RAMP0DEC.bit.VAL
 *  @brief      Step size for decremental ramping
 */
#define RAMP0DEC_ALL_VAL_Pos (0)
#define RAMP0DEC_ALL_VAL_Msk (0xFFFFUL << RAMP0DEC_ALL_VAL_Pos)

#define RAMP0DEC_BIT_VAL

#define RAMP0DEC_ALL_VAL_(x) ((x) << RAMP0DEC_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP0DECA       VAL
 *  @access     COMP->RAMP0DECA.bit.VAL
 *  @brief      Step size for decremental ramping
 */
#define RAMP0DECA_ALL_VAL_Pos (0)
#define RAMP0DECA_ALL_VAL_Msk (0xFFFFUL << RAMP0DECA_ALL_VAL_Pos)

#define RAMP0DECA_BIT_VAL

#define RAMP0DECA_ALL_VAL_(x) ((x) << RAMP0DECA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP0MAX        VAL
 *  @access     COMP->RAMP0MAX.bit.VAL
 *  @brief      Maximum value when reset ramping
 */
#define RAMP0MAX_ALL_VAL_Pos (0)
#define RAMP0MAX_ALL_VAL_Msk (0xFFFFUL << RAMP0MAX_ALL_VAL_Pos)

#define RAMP0MAX_BIT_VAL

#define RAMP0MAX_ALL_VAL_(x) ((x) << RAMP0MAX_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP0MAXA       VAL
 *  @access     COMP->RAMP0MAXA.bit.VAL
 *  @brief      Maximum value when reset ramping
 */
#define RAMP0MAXA_ALL_VAL_Pos (0)
#define RAMP0MAXA_ALL_VAL_Msk (0xFFFFUL << RAMP0MAXA_ALL_VAL_Pos)

#define RAMP0MAXA_BIT_VAL

#define RAMP0MAXA_ALL_VAL_(x) ((x) << RAMP0MAXA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP0CNT        VAL
 *  @access     COMP->RAMP0CNT.bit.VAL
 *  @brief      Count number of RAMP0
 */
#define RAMP0CNT_ALL_VAL_Pos (0)
#define RAMP0CNT_ALL_VAL_Msk (0xFFFFUL << RAMP0CNT_ALL_VAL_Pos)

#define RAMP0CNT_BIT_VAL

#define RAMP0CNT_ALL_VAL_(x) ((x) << RAMP0CNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CTL         EN
 *  @access     COMP->DAC1CTL.bit.EN
 *  @brief      DAC enable
 */
#define DAC1CTL_ALL_EN_Pos (0)
#define DAC1CTL_ALL_EN_Msk (0x1UL << DAC1CTL_ALL_EN_Pos)

typedef enum
{
    DAC1CTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    DAC1CTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} DAC1CTL_BIT_EN;

#define DAC1CTL_ALL_EN_DISABLE     ((0x0UL) << DAC1CTL_ALL_EN_Pos)
#define DAC1CTL_ALL_EN_ENABLE      ((0x1UL) << DAC1CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CTL         CODELOAD
 *  @access     COMP->DAC1CTL.bit.CODELOAD
 *  @brief      DAC code load mode
 */
#define DAC1CTL_ALL_CODELOAD_Pos (1)
#define DAC1CTL_ALL_CODELOAD_Msk (0x1UL << DAC1CTL_ALL_CODELOAD_Pos)

typedef enum
{
    DAC1CTL_BIT_CODELOAD_SHADOW_MODE     = 0,  /*!< DAC code is updated upon PWMSYNC event                   */
    DAC1CTL_BIT_CODELOAD_DIRECT_MODE     = 1,  /*!< DAC code is immediately updated by writing to DAC1CODE   */
} DAC1CTL_BIT_CODELOAD;

#define DAC1CTL_ALL_CODELOAD_SHADOW_MODE     ((0x0UL) << DAC1CTL_ALL_CODELOAD_Pos)
#define DAC1CTL_ALL_CODELOAD_DIRECT_MODE     ((0x1UL) << DAC1CTL_ALL_CODELOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CTL         SYNCSEL
 *  @access     COMP->DAC1CTL.bit.SYNCSEL
 *  @brief      PWMSYNC is selected from PWM[SYNCSEL]
 */
#define DAC1CTL_ALL_SYNCSEL_Pos (2)
#define DAC1CTL_ALL_SYNCSEL_Msk (0x7UL << DAC1CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    DAC1CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    DAC1CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    DAC1CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    DAC1CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    DAC1CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    DAC1CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} DAC1CTL_BIT_SYNCSEL;

#define DAC1CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << DAC1CTL_ALL_SYNCSEL_Pos)
#define DAC1CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << DAC1CTL_ALL_SYNCSEL_Pos)
#define DAC1CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << DAC1CTL_ALL_SYNCSEL_Pos)
#define DAC1CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << DAC1CTL_ALL_SYNCSEL_Pos)
#define DAC1CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << DAC1CTL_ALL_SYNCSEL_Pos)
#define DAC1CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << DAC1CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CTL         RAMPEN
 *  @access     COMP->DAC1CTL.bit.RAMPEN
 *  @brief      DAC Ramping enable
 */
#define DAC1CTL_ALL_RAMPEN_Pos (5)
#define DAC1CTL_ALL_RAMPEN_Msk (0x1UL << DAC1CTL_ALL_RAMPEN_Pos)

typedef enum
{
    DAC1CTL_BIT_RAMPEN_DISABLE     = 0,  /*!< Disable ramping                                                      */
    DAC1CTL_BIT_RAMPEN_ENABLE      = 1,  /*!< Enable ramping. DAC1CODEA is equivalent to the 10 MSBs of RAMP1CNT   */
} DAC1CTL_BIT_RAMPEN;

#define DAC1CTL_ALL_RAMPEN_DISABLE     ((0x0UL) << DAC1CTL_ALL_RAMPEN_Pos)
#define DAC1CTL_ALL_RAMPEN_ENABLE      ((0x1UL) << DAC1CTL_ALL_RAMPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CTL         RAMPLOAD
 *  @access     COMP->DAC1CTL.bit.RAMPLOAD
 *  @brief      DAC Ramp load mode
 */
#define DAC1CTL_ALL_RAMPLOAD_Pos (6)
#define DAC1CTL_ALL_RAMPLOAD_Msk (0x1UL << DAC1CTL_ALL_RAMPLOAD_Pos)

typedef enum
{
    DAC1CTL_BIT_RAMPLOAD_SHADOW_MODE     = 0,  /*!< Register shadowing is applied for ramping counter load from RAMPMAX   */
    DAC1CTL_BIT_RAMPLOAD_DIRECT_MODE     = 1,  /*!< RAMP counter is directly loaded from the latest RAMPMAX               */
} DAC1CTL_BIT_RAMPLOAD;

#define DAC1CTL_ALL_RAMPLOAD_SHADOW_MODE     ((0x0UL) << DAC1CTL_ALL_RAMPLOAD_Pos)
#define DAC1CTL_ALL_RAMPLOAD_DIRECT_MODE     ((0x1UL) << DAC1CTL_ALL_RAMPLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CTL         COMPHSEL
 *  @access     COMP->DAC1CTL.bit.COMPHSEL
 *  @brief      Select COMPH from COMP[COMPHSEL]
 *              Note: This field is used for RAMP function.
 */
#define DAC1CTL_ALL_COMPHSEL_Pos (7)
#define DAC1CTL_ALL_COMPHSEL_Msk (0x7UL << DAC1CTL_ALL_COMPHSEL_Pos)

typedef enum
{
    DAC1CTL_BIT_COMPHSEL_COMP0H     = 0,  /*!< COMP0H   */
    DAC1CTL_BIT_COMPHSEL_COMP1H     = 1,  /*!< COMP1H   */
    DAC1CTL_BIT_COMPHSEL_COMP2H     = 2,  /*!< COMP2H   */
    DAC1CTL_BIT_COMPHSEL_COMP3H     = 3,  /*!< COMP3H   */
    DAC1CTL_BIT_COMPHSEL_COMP4H     = 4,  /*!< COMP4H   */
} DAC1CTL_BIT_COMPHSEL;

#define DAC1CTL_ALL_COMPHSEL_COMP0H     ((0x0UL) << DAC1CTL_ALL_COMPHSEL_Pos)
#define DAC1CTL_ALL_COMPHSEL_COMP1H     ((0x1UL) << DAC1CTL_ALL_COMPHSEL_Pos)
#define DAC1CTL_ALL_COMPHSEL_COMP2H     ((0x2UL) << DAC1CTL_ALL_COMPHSEL_Pos)
#define DAC1CTL_ALL_COMPHSEL_COMP3H     ((0x3UL) << DAC1CTL_ALL_COMPHSEL_Pos)
#define DAC1CTL_ALL_COMPHSEL_COMP4H     ((0x4UL) << DAC1CTL_ALL_COMPHSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CTL         DBGRUN
 *  @access     COMP->DAC1CTL.bit.DBGRUN
 *  @brief      Behavior on CPU halted or lockup
 */
#define DAC1CTL_ALL_DBGRUN_Pos (10)
#define DAC1CTL_ALL_DBGRUN_Msk (0x3UL << DAC1CTL_ALL_DBGRUN_Pos)

typedef enum
{
    DAC1CTL_BIT_DBGRUN_STOP_IMMEDIATELY     = 0,  /*!< Stop immediately                */
    DAC1CTL_BIT_DBGRUN_STOP_AT_PWMSYNC      = 1,  /*!< Stop at PWM synchronous event   */
    DAC1CTL_BIT_DBGRUN_KEEP_RUN             = 2,  /*!< Free running                    */
} DAC1CTL_BIT_DBGRUN;

#define DAC1CTL_ALL_DBGRUN_STOP_IMMEDIATELY     ((0x0UL) << DAC1CTL_ALL_DBGRUN_Pos)
#define DAC1CTL_ALL_DBGRUN_STOP_AT_PWMSYNC      ((0x1UL) << DAC1CTL_ALL_DBGRUN_Pos)
#define DAC1CTL_ALL_DBGRUN_KEEP_RUN             ((0x2UL) << DAC1CTL_ALL_DBGRUN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CODE        VAL
 *  @access     COMP->DAC1CODE.bit.VAL
 *  @brief      DAC code
 *              When DAC1CTL[CODELOAD]=0, write to this field only affects the shadow code.
 *              When DAC1CTL[CODELOAD]=1, write to this field affects both the shadow code and the
 *              active code.
 */
#define DAC1CODE_ALL_VAL_Pos (0)
#define DAC1CODE_ALL_VAL_Msk (0x3FFUL << DAC1CODE_ALL_VAL_Pos)

#define DAC1CODE_BIT_VAL

#define DAC1CODE_ALL_VAL_(x) ((x) << DAC1CODE_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC1CODEA       VAL
 *  @access     COMP->DAC1CODEA.bit.VAL
 *  @brief      Active DAC code
 */
#define DAC1CODEA_ALL_VAL_Pos (0)
#define DAC1CODEA_ALL_VAL_Msk (0x3FFUL << DAC1CODEA_ALL_VAL_Pos)

#define DAC1CODEA_BIT_VAL

#define DAC1CODEA_ALL_VAL_(x) ((x) << DAC1CODEA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP1DLY        VAL
 *  @access     COMP->RAMP1DLY.bit.VAL
 *  @brief      Delay from PWMSYNC to start of ramping
 */
#define RAMP1DLY_ALL_VAL_Pos (0)
#define RAMP1DLY_ALL_VAL_Msk (0xFFFFUL << RAMP1DLY_ALL_VAL_Pos)

#define RAMP1DLY_BIT_VAL

#define RAMP1DLY_ALL_VAL_(x) ((x) << RAMP1DLY_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP1DLYA       VAL
 *  @access     COMP->RAMP1DLYA.bit.VAL
 *  @brief      Delay from PWMSYNC to start of ramping
 */
#define RAMP1DLYA_ALL_VAL_Pos (0)
#define RAMP1DLYA_ALL_VAL_Msk (0xFFFFUL << RAMP1DLYA_ALL_VAL_Pos)

#define RAMP1DLYA_BIT_VAL

#define RAMP1DLYA_ALL_VAL_(x) ((x) << RAMP1DLYA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP1DEC        VAL
 *  @access     COMP->RAMP1DEC.bit.VAL
 *  @brief      Step size for decremental ramping
 */
#define RAMP1DEC_ALL_VAL_Pos (0)
#define RAMP1DEC_ALL_VAL_Msk (0xFFFFUL << RAMP1DEC_ALL_VAL_Pos)

#define RAMP1DEC_BIT_VAL

#define RAMP1DEC_ALL_VAL_(x) ((x) << RAMP1DEC_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP1DECA       VAL
 *  @access     COMP->RAMP1DECA.bit.VAL
 *  @brief      Step size for decremental ramping
 */
#define RAMP1DECA_ALL_VAL_Pos (0)
#define RAMP1DECA_ALL_VAL_Msk (0xFFFFUL << RAMP1DECA_ALL_VAL_Pos)

#define RAMP1DECA_BIT_VAL

#define RAMP1DECA_ALL_VAL_(x) ((x) << RAMP1DECA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP1MAX        VAL
 *  @access     COMP->RAMP1MAX.bit.VAL
 *  @brief      Maximum value when reset ramping
 */
#define RAMP1MAX_ALL_VAL_Pos (0)
#define RAMP1MAX_ALL_VAL_Msk (0xFFFFUL << RAMP1MAX_ALL_VAL_Pos)

#define RAMP1MAX_BIT_VAL

#define RAMP1MAX_ALL_VAL_(x) ((x) << RAMP1MAX_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP1MAXA       VAL
 *  @access     COMP->RAMP1MAXA.bit.VAL
 *  @brief      Maximum value when reset ramping
 */
#define RAMP1MAXA_ALL_VAL_Pos (0)
#define RAMP1MAXA_ALL_VAL_Msk (0xFFFFUL << RAMP1MAXA_ALL_VAL_Pos)

#define RAMP1MAXA_BIT_VAL

#define RAMP1MAXA_ALL_VAL_(x) ((x) << RAMP1MAXA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            RAMP1CNT        VAL
 *  @access     COMP->RAMP1CNT.bit.VAL
 *  @brief      Count number of RAMP1
 */
#define RAMP1CNT_ALL_VAL_Pos (0)
#define RAMP1CNT_ALL_VAL_Msk (0xFFFFUL << RAMP1CNT_ALL_VAL_Pos)

#define RAMP1CNT_BIT_VAL

#define RAMP1CNT_ALL_VAL_(x) ((x) << RAMP1CNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC2CTL         EN
 *  @access     COMP->DAC2CTL.bit.EN
 *  @brief      DAC enable
 */
#define DAC2CTL_ALL_EN_Pos (0)
#define DAC2CTL_ALL_EN_Msk (0x1UL << DAC2CTL_ALL_EN_Pos)

typedef enum
{
    DAC2CTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    DAC2CTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} DAC2CTL_BIT_EN;

#define DAC2CTL_ALL_EN_DISABLE     ((0x0UL) << DAC2CTL_ALL_EN_Pos)
#define DAC2CTL_ALL_EN_ENABLE      ((0x1UL) << DAC2CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC2CTL         CODELOAD
 *  @access     COMP->DAC2CTL.bit.CODELOAD
 *  @brief      DAC code load mode
 */
#define DAC2CTL_ALL_CODELOAD_Pos (1)
#define DAC2CTL_ALL_CODELOAD_Msk (0x1UL << DAC2CTL_ALL_CODELOAD_Pos)

typedef enum
{
    DAC2CTL_BIT_CODELOAD_SHADOW_MODE     = 0,  /*!< DAC code is updated upon PWMSYNC event                   */
    DAC2CTL_BIT_CODELOAD_DIRECT_MODE     = 1,  /*!< DAC code is immediately updated by writing to DAC2CODE   */
} DAC2CTL_BIT_CODELOAD;

#define DAC2CTL_ALL_CODELOAD_SHADOW_MODE     ((0x0UL) << DAC2CTL_ALL_CODELOAD_Pos)
#define DAC2CTL_ALL_CODELOAD_DIRECT_MODE     ((0x1UL) << DAC2CTL_ALL_CODELOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC2CTL         SYNCSEL
 *  @access     COMP->DAC2CTL.bit.SYNCSEL
 *  @brief      PWMSYNC is selected from PWM[SYNCSEL]
 */
#define DAC2CTL_ALL_SYNCSEL_Pos (2)
#define DAC2CTL_ALL_SYNCSEL_Msk (0x7UL << DAC2CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    DAC2CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    DAC2CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    DAC2CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    DAC2CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    DAC2CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    DAC2CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} DAC2CTL_BIT_SYNCSEL;

#define DAC2CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << DAC2CTL_ALL_SYNCSEL_Pos)
#define DAC2CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << DAC2CTL_ALL_SYNCSEL_Pos)
#define DAC2CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << DAC2CTL_ALL_SYNCSEL_Pos)
#define DAC2CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << DAC2CTL_ALL_SYNCSEL_Pos)
#define DAC2CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << DAC2CTL_ALL_SYNCSEL_Pos)
#define DAC2CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << DAC2CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC2CODE        VAL
 *  @access     COMP->DAC2CODE.bit.VAL
 *  @brief      DAC code
 *              When DAC2CTL[CODELOAD]=0, write to this field only affects the shadow code.
 *              When DAC2CTL[CODELOAD]=1, write to this field affects both the shadow code and the
 *              active code.
 */
#define DAC2CODE_ALL_VAL_Pos (0)
#define DAC2CODE_ALL_VAL_Msk (0x3FFUL << DAC2CODE_ALL_VAL_Pos)

#define DAC2CODE_BIT_VAL

#define DAC2CODE_ALL_VAL_(x) ((x) << DAC2CODE_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC2CODEA       VAL
 *  @access     COMP->DAC2CODEA.bit.VAL
 *  @brief      Active DAC code
 */
#define DAC2CODEA_ALL_VAL_Pos (0)
#define DAC2CODEA_ALL_VAL_Msk (0x3FFUL << DAC2CODEA_ALL_VAL_Pos)

#define DAC2CODEA_BIT_VAL

#define DAC2CODEA_ALL_VAL_(x) ((x) << DAC2CODEA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC3CTL         EN
 *  @access     COMP->DAC3CTL.bit.EN
 *  @brief      DAC enable
 */
#define DAC3CTL_ALL_EN_Pos (0)
#define DAC3CTL_ALL_EN_Msk (0x1UL << DAC3CTL_ALL_EN_Pos)

typedef enum
{
    DAC3CTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    DAC3CTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} DAC3CTL_BIT_EN;

#define DAC3CTL_ALL_EN_DISABLE     ((0x0UL) << DAC3CTL_ALL_EN_Pos)
#define DAC3CTL_ALL_EN_ENABLE      ((0x1UL) << DAC3CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC3CTL         CODELOAD
 *  @access     COMP->DAC3CTL.bit.CODELOAD
 *  @brief      DAC code load mode
 */
#define DAC3CTL_ALL_CODELOAD_Pos (1)
#define DAC3CTL_ALL_CODELOAD_Msk (0x1UL << DAC3CTL_ALL_CODELOAD_Pos)

typedef enum
{
    DAC3CTL_BIT_CODELOAD_SHADOW_MODE     = 0,  /*!< DAC code is updated upon PWMSYNC event                   */
    DAC3CTL_BIT_CODELOAD_DIRECT_MODE     = 1,  /*!< DAC code is immediately updated by writing to DAC3CODE   */
} DAC3CTL_BIT_CODELOAD;

#define DAC3CTL_ALL_CODELOAD_SHADOW_MODE     ((0x0UL) << DAC3CTL_ALL_CODELOAD_Pos)
#define DAC3CTL_ALL_CODELOAD_DIRECT_MODE     ((0x1UL) << DAC3CTL_ALL_CODELOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC3CTL         SYNCSEL
 *  @access     COMP->DAC3CTL.bit.SYNCSEL
 *  @brief      PWMSYNC is selected from PWM[SYNCSEL]
 */
#define DAC3CTL_ALL_SYNCSEL_Pos (2)
#define DAC3CTL_ALL_SYNCSEL_Msk (0x7UL << DAC3CTL_ALL_SYNCSEL_Pos)

typedef enum
{
    DAC3CTL_BIT_SYNCSEL_PWM0SYNCO     = 0,  /*!< PWM0 synchronous output   */
    DAC3CTL_BIT_SYNCSEL_PWM1SYNCO     = 1,  /*!< PWM1 synchronous output   */
    DAC3CTL_BIT_SYNCSEL_PWM2SYNCO     = 2,  /*!< PWM2 synchronous output   */
    DAC3CTL_BIT_SYNCSEL_PWM3SYNCO     = 3,  /*!< PWM3 synchronous output   */
    DAC3CTL_BIT_SYNCSEL_PWM4SYNCO     = 4,  /*!< PWM4 synchronous output   */
    DAC3CTL_BIT_SYNCSEL_PWM5SYNCO     = 5,  /*!< PWM5 synchronous output   */
} DAC3CTL_BIT_SYNCSEL;

#define DAC3CTL_ALL_SYNCSEL_PWM0SYNCO     ((0x0UL) << DAC3CTL_ALL_SYNCSEL_Pos)
#define DAC3CTL_ALL_SYNCSEL_PWM1SYNCO     ((0x1UL) << DAC3CTL_ALL_SYNCSEL_Pos)
#define DAC3CTL_ALL_SYNCSEL_PWM2SYNCO     ((0x2UL) << DAC3CTL_ALL_SYNCSEL_Pos)
#define DAC3CTL_ALL_SYNCSEL_PWM3SYNCO     ((0x3UL) << DAC3CTL_ALL_SYNCSEL_Pos)
#define DAC3CTL_ALL_SYNCSEL_PWM4SYNCO     ((0x4UL) << DAC3CTL_ALL_SYNCSEL_Pos)
#define DAC3CTL_ALL_SYNCSEL_PWM5SYNCO     ((0x5UL) << DAC3CTL_ALL_SYNCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC3CODE        VAL
 *  @access     COMP->DAC3CODE.bit.VAL
 *  @brief      DAC code
 *              When DAC3CTL[CODELOAD]=0, write to this field only affects the shadow code.
 *              When DAC3CTL[CODELOAD]=1, write to this field affects both the shadow code and the
 *              active code.
 */
#define DAC3CODE_ALL_VAL_Pos (0)
#define DAC3CODE_ALL_VAL_Msk (0x3FFUL << DAC3CODE_ALL_VAL_Pos)

#define DAC3CODE_BIT_VAL

#define DAC3CODE_ALL_VAL_(x) ((x) << DAC3CODE_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DAC3CODEA       VAL
 *  @access     COMP->DAC3CODEA.bit.VAL
 *  @brief      Active DAC code
 */
#define DAC3CODEA_ALL_VAL_Pos (0)
#define DAC3CODEA_ALL_VAL_Msk (0x3FFUL << DAC3CODEA_ALL_VAL_Pos)

#define DAC3CODEA_BIT_VAL

#define DAC3CODEA_ALL_VAL_(x) ((x) << DAC3CODEA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DACBUFCTL       EN
 *  @access     COMP->DACBUFCTL.bit.EN
 *  @brief      DAC buffer enable
 */
#define DACBUFCTL_ALL_EN_Pos (0)
#define DACBUFCTL_ALL_EN_Msk (0x1UL << DACBUFCTL_ALL_EN_Pos)

typedef enum
{
    DACBUFCTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    DACBUFCTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} DACBUFCTL_BIT_EN;

#define DACBUFCTL_ALL_EN_DISABLE     ((0x0UL) << DACBUFCTL_ALL_EN_Pos)
#define DACBUFCTL_ALL_EN_ENABLE      ((0x1UL) << DACBUFCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DACBUFCTL       INSEL
 *  @access     COMP->DACBUFCTL.bit.INSEL
 *  @brief      DAC buffer input select
 */
#define DACBUFCTL_ALL_INSEL_Pos (1)
#define DACBUFCTL_ALL_INSEL_Msk (0x3UL << DACBUFCTL_ALL_INSEL_Pos)

typedef enum
{
    DACBUFCTL_BIT_INSEL_DAC0     = 0,  /*!< DAC0   */
    DACBUFCTL_BIT_INSEL_DAC1     = 1,  /*!< DAC1   */
    DACBUFCTL_BIT_INSEL_DAC2     = 2,  /*!< DAC2   */
    DACBUFCTL_BIT_INSEL_DAC3     = 3,  /*!< DAC3   */
} DACBUFCTL_BIT_INSEL;

#define DACBUFCTL_ALL_INSEL_DAC0     ((0x0UL) << DACBUFCTL_ALL_INSEL_Pos)
#define DACBUFCTL_ALL_INSEL_DAC1     ((0x1UL) << DACBUFCTL_ALL_INSEL_Pos)
#define DACBUFCTL_ALL_INSEL_DAC2     ((0x2UL) << DACBUFCTL_ALL_INSEL_Pos)
#define DACBUFCTL_ALL_INSEL_DAC3     ((0x3UL) << DACBUFCTL_ALL_INSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DACBUFCTL       OE10
 *  @access     COMP->DACBUFCTL.bit.OE10
 *  @brief      Enable output to GPIO10 pin
 */
#define DACBUFCTL_ALL_OE10_Pos (3)
#define DACBUFCTL_ALL_OE10_Msk (0x1UL << DACBUFCTL_ALL_OE10_Pos)

typedef enum
{
    DACBUFCTL_BIT_OE10_DISABLE     = 0,  /*!< Disable   */
    DACBUFCTL_BIT_OE10_ENABLE      = 1,  /*!< Enable    */
} DACBUFCTL_BIT_OE10;

#define DACBUFCTL_ALL_OE10_DISABLE     ((0x0UL) << DACBUFCTL_ALL_OE10_Pos)
#define DACBUFCTL_ALL_OE10_ENABLE      ((0x1UL) << DACBUFCTL_ALL_OE10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            DACBUFCTL       OE13
 *  @access     COMP->DACBUFCTL.bit.OE13
 *  @brief      Enable output to GPIO13 pin
 */
#define DACBUFCTL_ALL_OE13_Pos (4)
#define DACBUFCTL_ALL_OE13_Msk (0x1UL << DACBUFCTL_ALL_OE13_Pos)

typedef enum
{
    DACBUFCTL_BIT_OE13_DISABLE     = 0,  /*!< Disable   */
    DACBUFCTL_BIT_OE13_ENABLE      = 1,  /*!< Enable    */
} DACBUFCTL_BIT_OE13;

#define DACBUFCTL_ALL_OE13_DISABLE     ((0x0UL) << DACBUFCTL_ALL_OE13_Pos)
#define DACBUFCTL_ALL_OE13_ENABLE      ((0x1UL) << DACBUFCTL_ALL_OE13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   COMP            COMPREGKEY      KEY
 *  @access     COMP->COMPREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected COMP registers
 */
#define COMPREGKEY_ALL_KEY_Pos (0)
#define COMPREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << COMPREGKEY_ALL_KEY_Pos)

#define COMPREGKEY_BIT_KEY

#define COMPREGKEY_ALL_KEY_(x) ((x) << COMPREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     ADC
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT0
 *  @access     ADC->ADCIF.bit.INT0
 *  @brief      ADC interrupt 0 flag
 */
#define ADCIF_ALL_INT0_Pos (0)
#define ADCIF_ALL_INT0_Msk (0x1UL << ADCIF_ALL_INT0_Pos)

typedef enum
{
    ADCIF_BIT_INT0_NOT_OCCUR     = 0,  /*!< ADC interrupt 0 does not happen   */
    ADCIF_BIT_INT0_OCCUR         = 1,  /*!< ADC interrupt 0 happened          */
} ADCIF_BIT_INT0;

#define ADCIF_ALL_INT0_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT0_Pos)
#define ADCIF_ALL_INT0_OCCUR         ((0x1UL) << ADCIF_ALL_INT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT1
 *  @access     ADC->ADCIF.bit.INT1
 *  @brief      ADC interrupt 1 flag
 */
#define ADCIF_ALL_INT1_Pos (1)
#define ADCIF_ALL_INT1_Msk (0x1UL << ADCIF_ALL_INT1_Pos)

typedef enum
{
    ADCIF_BIT_INT1_NOT_OCCUR     = 0,  /*!< ADC interrupt 1 does not happen   */
    ADCIF_BIT_INT1_OCCUR         = 1,  /*!< ADC interrupt 1 happened          */
} ADCIF_BIT_INT1;

#define ADCIF_ALL_INT1_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT1_Pos)
#define ADCIF_ALL_INT1_OCCUR         ((0x1UL) << ADCIF_ALL_INT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT2
 *  @access     ADC->ADCIF.bit.INT2
 *  @brief      ADC interrupt 2 flag
 */
#define ADCIF_ALL_INT2_Pos (2)
#define ADCIF_ALL_INT2_Msk (0x1UL << ADCIF_ALL_INT2_Pos)

typedef enum
{
    ADCIF_BIT_INT2_NOT_OCCUR     = 0,  /*!< ADC interrupt 2 does not happen   */
    ADCIF_BIT_INT2_OCCUR         = 1,  /*!< ADC interrupt 2 happened          */
} ADCIF_BIT_INT2;

#define ADCIF_ALL_INT2_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT2_Pos)
#define ADCIF_ALL_INT2_OCCUR         ((0x1UL) << ADCIF_ALL_INT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT3
 *  @access     ADC->ADCIF.bit.INT3
 *  @brief      ADC interrupt 3 flag
 */
#define ADCIF_ALL_INT3_Pos (3)
#define ADCIF_ALL_INT3_Msk (0x1UL << ADCIF_ALL_INT3_Pos)

typedef enum
{
    ADCIF_BIT_INT3_NOT_OCCUR     = 0,  /*!< ADC interrupt 3 does not happen   */
    ADCIF_BIT_INT3_OCCUR         = 1,  /*!< ADC interrupt 3 happened          */
} ADCIF_BIT_INT3;

#define ADCIF_ALL_INT3_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT3_Pos)
#define ADCIF_ALL_INT3_OCCUR         ((0x1UL) << ADCIF_ALL_INT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT4
 *  @access     ADC->ADCIF.bit.INT4
 *  @brief      ADC interrupt 4 flag
 */
#define ADCIF_ALL_INT4_Pos (4)
#define ADCIF_ALL_INT4_Msk (0x1UL << ADCIF_ALL_INT4_Pos)

typedef enum
{
    ADCIF_BIT_INT4_NOT_OCCUR     = 0,  /*!< ADC interrupt 4 does not happen   */
    ADCIF_BIT_INT4_OCCUR         = 1,  /*!< ADC interrupt 4 happened          */
} ADCIF_BIT_INT4;

#define ADCIF_ALL_INT4_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT4_Pos)
#define ADCIF_ALL_INT4_OCCUR         ((0x1UL) << ADCIF_ALL_INT4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT5
 *  @access     ADC->ADCIF.bit.INT5
 *  @brief      ADC interrupt 5 flag
 */
#define ADCIF_ALL_INT5_Pos (5)
#define ADCIF_ALL_INT5_Msk (0x1UL << ADCIF_ALL_INT5_Pos)

typedef enum
{
    ADCIF_BIT_INT5_NOT_OCCUR     = 0,  /*!< ADC interrupt 5 does not happen   */
    ADCIF_BIT_INT5_OCCUR         = 1,  /*!< ADC interrupt 5 happened          */
} ADCIF_BIT_INT5;

#define ADCIF_ALL_INT5_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT5_Pos)
#define ADCIF_ALL_INT5_OCCUR         ((0x1UL) << ADCIF_ALL_INT5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT6
 *  @access     ADC->ADCIF.bit.INT6
 *  @brief      ADC interrupt 6 flag
 */
#define ADCIF_ALL_INT6_Pos (6)
#define ADCIF_ALL_INT6_Msk (0x1UL << ADCIF_ALL_INT6_Pos)

typedef enum
{
    ADCIF_BIT_INT6_NOT_OCCUR     = 0,  /*!< ADC interrupt 6 does not happen   */
    ADCIF_BIT_INT6_OCCUR         = 1,  /*!< ADC interrupt 6 happened          */
} ADCIF_BIT_INT6;

#define ADCIF_ALL_INT6_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT6_Pos)
#define ADCIF_ALL_INT6_OCCUR         ((0x1UL) << ADCIF_ALL_INT6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT7
 *  @access     ADC->ADCIF.bit.INT7
 *  @brief      ADC interrupt 7 flag
 */
#define ADCIF_ALL_INT7_Pos (7)
#define ADCIF_ALL_INT7_Msk (0x1UL << ADCIF_ALL_INT7_Pos)

typedef enum
{
    ADCIF_BIT_INT7_NOT_OCCUR     = 0,  /*!< ADC interrupt 7 does not happen   */
    ADCIF_BIT_INT7_OCCUR         = 1,  /*!< ADC interrupt 7 happened          */
} ADCIF_BIT_INT7;

#define ADCIF_ALL_INT7_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT7_Pos)
#define ADCIF_ALL_INT7_OCCUR         ((0x1UL) << ADCIF_ALL_INT7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT8
 *  @access     ADC->ADCIF.bit.INT8
 *  @brief      ADC interrupt 8 flag
 */
#define ADCIF_ALL_INT8_Pos (8)
#define ADCIF_ALL_INT8_Msk (0x1UL << ADCIF_ALL_INT8_Pos)

typedef enum
{
    ADCIF_BIT_INT8_NOT_OCCUR     = 0,  /*!< ADC interrupt 8 does not happen   */
    ADCIF_BIT_INT8_OCCUR         = 1,  /*!< ADC interrupt 8 happened          */
} ADCIF_BIT_INT8;

#define ADCIF_ALL_INT8_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT8_Pos)
#define ADCIF_ALL_INT8_OCCUR         ((0x1UL) << ADCIF_ALL_INT8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT9
 *  @access     ADC->ADCIF.bit.INT9
 *  @brief      ADC interrupt 9 flag
 */
#define ADCIF_ALL_INT9_Pos (9)
#define ADCIF_ALL_INT9_Msk (0x1UL << ADCIF_ALL_INT9_Pos)

typedef enum
{
    ADCIF_BIT_INT9_NOT_OCCUR     = 0,  /*!< ADC interrupt 9 does not happen   */
    ADCIF_BIT_INT9_OCCUR         = 1,  /*!< ADC interrupt 9 happened          */
} ADCIF_BIT_INT9;

#define ADCIF_ALL_INT9_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT9_Pos)
#define ADCIF_ALL_INT9_OCCUR         ((0x1UL) << ADCIF_ALL_INT9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT10
 *  @access     ADC->ADCIF.bit.INT10
 *  @brief      ADC interrupt 10 flag
 */
#define ADCIF_ALL_INT10_Pos (10)
#define ADCIF_ALL_INT10_Msk (0x1UL << ADCIF_ALL_INT10_Pos)

typedef enum
{
    ADCIF_BIT_INT10_NOT_OCCUR     = 0,  /*!< ADC interrupt 10 does not happen   */
    ADCIF_BIT_INT10_OCCUR         = 1,  /*!< ADC interrupt 10 happened          */
} ADCIF_BIT_INT10;

#define ADCIF_ALL_INT10_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT10_Pos)
#define ADCIF_ALL_INT10_OCCUR         ((0x1UL) << ADCIF_ALL_INT10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT11
 *  @access     ADC->ADCIF.bit.INT11
 *  @brief      ADC interrupt 11 flag
 */
#define ADCIF_ALL_INT11_Pos (11)
#define ADCIF_ALL_INT11_Msk (0x1UL << ADCIF_ALL_INT11_Pos)

typedef enum
{
    ADCIF_BIT_INT11_NOT_OCCUR     = 0,  /*!< ADC interrupt 11 does not happen   */
    ADCIF_BIT_INT11_OCCUR         = 1,  /*!< ADC interrupt 11 happened          */
} ADCIF_BIT_INT11;

#define ADCIF_ALL_INT11_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT11_Pos)
#define ADCIF_ALL_INT11_OCCUR         ((0x1UL) << ADCIF_ALL_INT11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT12
 *  @access     ADC->ADCIF.bit.INT12
 *  @brief      ADC interrupt 12 flag
 */
#define ADCIF_ALL_INT12_Pos (12)
#define ADCIF_ALL_INT12_Msk (0x1UL << ADCIF_ALL_INT12_Pos)

typedef enum
{
    ADCIF_BIT_INT12_NOT_OCCUR     = 0,  /*!< ADC interrupt 12 does not happen   */
    ADCIF_BIT_INT12_OCCUR         = 1,  /*!< ADC interrupt 12 happened          */
} ADCIF_BIT_INT12;

#define ADCIF_ALL_INT12_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT12_Pos)
#define ADCIF_ALL_INT12_OCCUR         ((0x1UL) << ADCIF_ALL_INT12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT13
 *  @access     ADC->ADCIF.bit.INT13
 *  @brief      ADC interrupt 13 flag
 */
#define ADCIF_ALL_INT13_Pos (13)
#define ADCIF_ALL_INT13_Msk (0x1UL << ADCIF_ALL_INT13_Pos)

typedef enum
{
    ADCIF_BIT_INT13_NOT_OCCUR     = 0,  /*!< ADC interrupt 13 does not happen   */
    ADCIF_BIT_INT13_OCCUR         = 1,  /*!< ADC interrupt 13 happened          */
} ADCIF_BIT_INT13;

#define ADCIF_ALL_INT13_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT13_Pos)
#define ADCIF_ALL_INT13_OCCUR         ((0x1UL) << ADCIF_ALL_INT13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT14
 *  @access     ADC->ADCIF.bit.INT14
 *  @brief      ADC interrupt 14 flag
 */
#define ADCIF_ALL_INT14_Pos (14)
#define ADCIF_ALL_INT14_Msk (0x1UL << ADCIF_ALL_INT14_Pos)

typedef enum
{
    ADCIF_BIT_INT14_NOT_OCCUR     = 0,  /*!< ADC interrupt 14 does not happen   */
    ADCIF_BIT_INT14_OCCUR         = 1,  /*!< ADC interrupt 14 happened          */
} ADCIF_BIT_INT14;

#define ADCIF_ALL_INT14_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT14_Pos)
#define ADCIF_ALL_INT14_OCCUR         ((0x1UL) << ADCIF_ALL_INT14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIF           INT15
 *  @access     ADC->ADCIF.bit.INT15
 *  @brief      ADC interrupt 15 flag
 */
#define ADCIF_ALL_INT15_Pos (15)
#define ADCIF_ALL_INT15_Msk (0x1UL << ADCIF_ALL_INT15_Pos)

typedef enum
{
    ADCIF_BIT_INT15_NOT_OCCUR     = 0,  /*!< ADC interrupt 15 does not happen   */
    ADCIF_BIT_INT15_OCCUR         = 1,  /*!< ADC interrupt 15 happened          */
} ADCIF_BIT_INT15;

#define ADCIF_ALL_INT15_NOT_OCCUR     ((0x0UL) << ADCIF_ALL_INT15_Pos)
#define ADCIF_ALL_INT15_OCCUR         ((0x1UL) << ADCIF_ALL_INT15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT0
 *  @access     ADC->ADCIC.bit.INT0
 *  @brief      ADC Interrupt 0 flag clear
 */
#define ADCIC_ALL_INT0_Pos (0)
#define ADCIC_ALL_INT0_Msk (0x1UL << ADCIC_ALL_INT0_Pos)

typedef enum
{
    ADCIC_BIT_INT0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT0_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT0]. This bit is self-cleared.   */
} ADCIC_BIT_INT0;

#define ADCIC_ALL_INT0_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT0_Pos)
#define ADCIC_ALL_INT0_CLEAR         ((0x1UL) << ADCIC_ALL_INT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT1
 *  @access     ADC->ADCIC.bit.INT1
 *  @brief      ADC Interrupt 1 flag clear
 */
#define ADCIC_ALL_INT1_Pos (1)
#define ADCIC_ALL_INT1_Msk (0x1UL << ADCIC_ALL_INT1_Pos)

typedef enum
{
    ADCIC_BIT_INT1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT1_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT1]. This bit is self-cleared.   */
} ADCIC_BIT_INT1;

#define ADCIC_ALL_INT1_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT1_Pos)
#define ADCIC_ALL_INT1_CLEAR         ((0x1UL) << ADCIC_ALL_INT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT2
 *  @access     ADC->ADCIC.bit.INT2
 *  @brief      ADC Interrupt 2 flag clear
 */
#define ADCIC_ALL_INT2_Pos (2)
#define ADCIC_ALL_INT2_Msk (0x1UL << ADCIC_ALL_INT2_Pos)

typedef enum
{
    ADCIC_BIT_INT2_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT2_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT2]. This bit is self-cleared.   */
} ADCIC_BIT_INT2;

#define ADCIC_ALL_INT2_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT2_Pos)
#define ADCIC_ALL_INT2_CLEAR         ((0x1UL) << ADCIC_ALL_INT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT3
 *  @access     ADC->ADCIC.bit.INT3
 *  @brief      ADC Interrupt 3 flag clear
 */
#define ADCIC_ALL_INT3_Pos (3)
#define ADCIC_ALL_INT3_Msk (0x1UL << ADCIC_ALL_INT3_Pos)

typedef enum
{
    ADCIC_BIT_INT3_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT3_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT3]. This bit is self-cleared.   */
} ADCIC_BIT_INT3;

#define ADCIC_ALL_INT3_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT3_Pos)
#define ADCIC_ALL_INT3_CLEAR         ((0x1UL) << ADCIC_ALL_INT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT4
 *  @access     ADC->ADCIC.bit.INT4
 *  @brief      ADC Interrupt 4 flag clear
 */
#define ADCIC_ALL_INT4_Pos (4)
#define ADCIC_ALL_INT4_Msk (0x1UL << ADCIC_ALL_INT4_Pos)

typedef enum
{
    ADCIC_BIT_INT4_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT4_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT4]. This bit is self-cleared.   */
} ADCIC_BIT_INT4;

#define ADCIC_ALL_INT4_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT4_Pos)
#define ADCIC_ALL_INT4_CLEAR         ((0x1UL) << ADCIC_ALL_INT4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT5
 *  @access     ADC->ADCIC.bit.INT5
 *  @brief      ADC Interrupt 5 flag clear
 */
#define ADCIC_ALL_INT5_Pos (5)
#define ADCIC_ALL_INT5_Msk (0x1UL << ADCIC_ALL_INT5_Pos)

typedef enum
{
    ADCIC_BIT_INT5_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT5_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT5]. This bit is self-cleared.   */
} ADCIC_BIT_INT5;

#define ADCIC_ALL_INT5_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT5_Pos)
#define ADCIC_ALL_INT5_CLEAR         ((0x1UL) << ADCIC_ALL_INT5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT6
 *  @access     ADC->ADCIC.bit.INT6
 *  @brief      ADC Interrupt 6 flag clear
 */
#define ADCIC_ALL_INT6_Pos (6)
#define ADCIC_ALL_INT6_Msk (0x1UL << ADCIC_ALL_INT6_Pos)

typedef enum
{
    ADCIC_BIT_INT6_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT6_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT6]. This bit is self-cleared.   */
} ADCIC_BIT_INT6;

#define ADCIC_ALL_INT6_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT6_Pos)
#define ADCIC_ALL_INT6_CLEAR         ((0x1UL) << ADCIC_ALL_INT6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT7
 *  @access     ADC->ADCIC.bit.INT7
 *  @brief      ADC Interrupt 7 flag clear
 */
#define ADCIC_ALL_INT7_Pos (7)
#define ADCIC_ALL_INT7_Msk (0x1UL << ADCIC_ALL_INT7_Pos)

typedef enum
{
    ADCIC_BIT_INT7_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT7_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT7]. This bit is self-cleared.   */
} ADCIC_BIT_INT7;

#define ADCIC_ALL_INT7_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT7_Pos)
#define ADCIC_ALL_INT7_CLEAR         ((0x1UL) << ADCIC_ALL_INT7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT8
 *  @access     ADC->ADCIC.bit.INT8
 *  @brief      ADC Interrupt 8 flag clear
 */
#define ADCIC_ALL_INT8_Pos (8)
#define ADCIC_ALL_INT8_Msk (0x1UL << ADCIC_ALL_INT8_Pos)

typedef enum
{
    ADCIC_BIT_INT8_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT8_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT8]. This bit is self-cleared.   */
} ADCIC_BIT_INT8;

#define ADCIC_ALL_INT8_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT8_Pos)
#define ADCIC_ALL_INT8_CLEAR         ((0x1UL) << ADCIC_ALL_INT8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT9
 *  @access     ADC->ADCIC.bit.INT9
 *  @brief      ADC Interrupt 9 flag clear
 */
#define ADCIC_ALL_INT9_Pos (9)
#define ADCIC_ALL_INT9_Msk (0x1UL << ADCIC_ALL_INT9_Pos)

typedef enum
{
    ADCIC_BIT_INT9_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.               */
    ADCIC_BIT_INT9_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT9]. This bit is self-cleared.   */
} ADCIC_BIT_INT9;

#define ADCIC_ALL_INT9_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT9_Pos)
#define ADCIC_ALL_INT9_CLEAR         ((0x1UL) << ADCIC_ALL_INT9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT10
 *  @access     ADC->ADCIC.bit.INT10
 *  @brief      ADC Interrupt 10 flag clear
 */
#define ADCIC_ALL_INT10_Pos (10)
#define ADCIC_ALL_INT10_Msk (0x1UL << ADCIC_ALL_INT10_Pos)

typedef enum
{
    ADCIC_BIT_INT10_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.                */
    ADCIC_BIT_INT10_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT10]. This bit is self-cleared.   */
} ADCIC_BIT_INT10;

#define ADCIC_ALL_INT10_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT10_Pos)
#define ADCIC_ALL_INT10_CLEAR         ((0x1UL) << ADCIC_ALL_INT10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT11
 *  @access     ADC->ADCIC.bit.INT11
 *  @brief      ADC Interrupt 11 flag clear
 */
#define ADCIC_ALL_INT11_Pos (11)
#define ADCIC_ALL_INT11_Msk (0x1UL << ADCIC_ALL_INT11_Pos)

typedef enum
{
    ADCIC_BIT_INT11_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.                */
    ADCIC_BIT_INT11_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT11]. This bit is self-cleared.   */
} ADCIC_BIT_INT11;

#define ADCIC_ALL_INT11_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT11_Pos)
#define ADCIC_ALL_INT11_CLEAR         ((0x1UL) << ADCIC_ALL_INT11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT12
 *  @access     ADC->ADCIC.bit.INT12
 *  @brief      ADC Interrupt 12 flag clear
 */
#define ADCIC_ALL_INT12_Pos (12)
#define ADCIC_ALL_INT12_Msk (0x1UL << ADCIC_ALL_INT12_Pos)

typedef enum
{
    ADCIC_BIT_INT12_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 1.                */
    ADCIC_BIT_INT12_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT12]. This bit is self-cleared.   */
} ADCIC_BIT_INT12;

#define ADCIC_ALL_INT12_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT12_Pos)
#define ADCIC_ALL_INT12_CLEAR         ((0x1UL) << ADCIC_ALL_INT12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT13
 *  @access     ADC->ADCIC.bit.INT13
 *  @brief      ADC Interrupt 13 flag clear
 */
#define ADCIC_ALL_INT13_Pos (13)
#define ADCIC_ALL_INT13_Msk (0x1UL << ADCIC_ALL_INT13_Pos)

typedef enum
{
    ADCIC_BIT_INT13_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.                */
    ADCIC_BIT_INT13_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT13]. This bit is self-cleared.   */
} ADCIC_BIT_INT13;

#define ADCIC_ALL_INT13_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT13_Pos)
#define ADCIC_ALL_INT13_CLEAR         ((0x1UL) << ADCIC_ALL_INT13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT14
 *  @access     ADC->ADCIC.bit.INT14
 *  @brief      ADC Interrupt 14 flag clear
 */
#define ADCIC_ALL_INT14_Pos (14)
#define ADCIC_ALL_INT14_Msk (0x1UL << ADCIC_ALL_INT14_Pos)

typedef enum
{
    ADCIC_BIT_INT14_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.                */
    ADCIC_BIT_INT14_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT14]. This bit is self-cleared.   */
} ADCIC_BIT_INT14;

#define ADCIC_ALL_INT14_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT14_Pos)
#define ADCIC_ALL_INT14_CLEAR         ((0x1UL) << ADCIC_ALL_INT14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIC           INT15
 *  @access     ADC->ADCIC.bit.INT15
 *  @brief      ADC Interrupt 15 flag clear
 */
#define ADCIC_ALL_INT15_Pos (15)
#define ADCIC_ALL_INT15_Msk (0x1UL << ADCIC_ALL_INT15_Pos)

typedef enum
{
    ADCIC_BIT_INT15_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0.                */
    ADCIC_BIT_INT15_CLEAR         = 1,  /*!< Write a 1 clears ADCIF[INT15]. This bit is self-cleared.   */
} ADCIC_BIT_INT15;

#define ADCIC_ALL_INT15_NO_EFFECT     ((0x0UL) << ADCIC_ALL_INT15_Pos)
#define ADCIC_ALL_INT15_CLEAR         ((0x1UL) << ADCIC_ALL_INT15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT0
 *  @access     ADC->ADCIOVF.bit.INT0
 *  @brief      ADC interrupt 0 overflow flag
 */
#define ADCIOVF_ALL_INT0_Pos (0)
#define ADCIOVF_ALL_INT0_Msk (0x1UL << ADCIOVF_ALL_INT0_Pos)

typedef enum
{
    ADCIOVF_BIT_INT0_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT0_OCCUR         = 1,  /*!< ADC interrupt 0 overflow   */
} ADCIOVF_BIT_INT0;

#define ADCIOVF_ALL_INT0_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT0_Pos)
#define ADCIOVF_ALL_INT0_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT1
 *  @access     ADC->ADCIOVF.bit.INT1
 *  @brief      ADC interrupt 1 overflow flag
 */
#define ADCIOVF_ALL_INT1_Pos (1)
#define ADCIOVF_ALL_INT1_Msk (0x1UL << ADCIOVF_ALL_INT1_Pos)

typedef enum
{
    ADCIOVF_BIT_INT1_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT1_OCCUR         = 1,  /*!< ADC interrupt 1 overflow   */
} ADCIOVF_BIT_INT1;

#define ADCIOVF_ALL_INT1_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT1_Pos)
#define ADCIOVF_ALL_INT1_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT2
 *  @access     ADC->ADCIOVF.bit.INT2
 *  @brief      ADC interrupt 2 overflow flag
 */
#define ADCIOVF_ALL_INT2_Pos (2)
#define ADCIOVF_ALL_INT2_Msk (0x1UL << ADCIOVF_ALL_INT2_Pos)

typedef enum
{
    ADCIOVF_BIT_INT2_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT2_OCCUR         = 1,  /*!< ADC interrupt 2 overflow   */
} ADCIOVF_BIT_INT2;

#define ADCIOVF_ALL_INT2_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT2_Pos)
#define ADCIOVF_ALL_INT2_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT3
 *  @access     ADC->ADCIOVF.bit.INT3
 *  @brief      ADC interrupt 3 overflow flag
 */
#define ADCIOVF_ALL_INT3_Pos (3)
#define ADCIOVF_ALL_INT3_Msk (0x1UL << ADCIOVF_ALL_INT3_Pos)

typedef enum
{
    ADCIOVF_BIT_INT3_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT3_OCCUR         = 1,  /*!< ADC interrupt 3 overflow   */
} ADCIOVF_BIT_INT3;

#define ADCIOVF_ALL_INT3_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT3_Pos)
#define ADCIOVF_ALL_INT3_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT4
 *  @access     ADC->ADCIOVF.bit.INT4
 *  @brief      ADC interrupt 4 overflow flag
 */
#define ADCIOVF_ALL_INT4_Pos (4)
#define ADCIOVF_ALL_INT4_Msk (0x1UL << ADCIOVF_ALL_INT4_Pos)

typedef enum
{
    ADCIOVF_BIT_INT4_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT4_OCCUR         = 1,  /*!< ADC interrupt 4 overflow   */
} ADCIOVF_BIT_INT4;

#define ADCIOVF_ALL_INT4_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT4_Pos)
#define ADCIOVF_ALL_INT4_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT5
 *  @access     ADC->ADCIOVF.bit.INT5
 *  @brief      ADC interrupt 5 overflow flag
 */
#define ADCIOVF_ALL_INT5_Pos (5)
#define ADCIOVF_ALL_INT5_Msk (0x1UL << ADCIOVF_ALL_INT5_Pos)

typedef enum
{
    ADCIOVF_BIT_INT5_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT5_OCCUR         = 1,  /*!< ADC interrupt 5 overflow   */
} ADCIOVF_BIT_INT5;

#define ADCIOVF_ALL_INT5_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT5_Pos)
#define ADCIOVF_ALL_INT5_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT6
 *  @access     ADC->ADCIOVF.bit.INT6
 *  @brief      ADC interrupt 6 overflow flag
 */
#define ADCIOVF_ALL_INT6_Pos (6)
#define ADCIOVF_ALL_INT6_Msk (0x1UL << ADCIOVF_ALL_INT6_Pos)

typedef enum
{
    ADCIOVF_BIT_INT6_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT6_OCCUR         = 1,  /*!< ADC interrupt 6 overflow   */
} ADCIOVF_BIT_INT6;

#define ADCIOVF_ALL_INT6_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT6_Pos)
#define ADCIOVF_ALL_INT6_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT7
 *  @access     ADC->ADCIOVF.bit.INT7
 *  @brief      ADC interrupt 7 overflow flag
 */
#define ADCIOVF_ALL_INT7_Pos (7)
#define ADCIOVF_ALL_INT7_Msk (0x1UL << ADCIOVF_ALL_INT7_Pos)

typedef enum
{
    ADCIOVF_BIT_INT7_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT7_OCCUR         = 1,  /*!< ADC interrupt 7 overflow   */
} ADCIOVF_BIT_INT7;

#define ADCIOVF_ALL_INT7_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT7_Pos)
#define ADCIOVF_ALL_INT7_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT8
 *  @access     ADC->ADCIOVF.bit.INT8
 *  @brief      ADC interrupt 8 overflow flag
 */
#define ADCIOVF_ALL_INT8_Pos (8)
#define ADCIOVF_ALL_INT8_Msk (0x1UL << ADCIOVF_ALL_INT8_Pos)

typedef enum
{
    ADCIOVF_BIT_INT8_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT8_OCCUR         = 1,  /*!< ADC interrupt 8 overflow   */
} ADCIOVF_BIT_INT8;

#define ADCIOVF_ALL_INT8_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT8_Pos)
#define ADCIOVF_ALL_INT8_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT9
 *  @access     ADC->ADCIOVF.bit.INT9
 *  @brief      ADC interrupt 9 overflow flag
 */
#define ADCIOVF_ALL_INT9_Pos (9)
#define ADCIOVF_ALL_INT9_Msk (0x1UL << ADCIOVF_ALL_INT9_Pos)

typedef enum
{
    ADCIOVF_BIT_INT9_NOT_OCCUR     = 0,  /*!< No overflow                */
    ADCIOVF_BIT_INT9_OCCUR         = 1,  /*!< ADC interrupt 9 overflow   */
} ADCIOVF_BIT_INT9;

#define ADCIOVF_ALL_INT9_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT9_Pos)
#define ADCIOVF_ALL_INT9_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT10
 *  @access     ADC->ADCIOVF.bit.INT10
 *  @brief      ADC interrupt 10 overflow flag
 */
#define ADCIOVF_ALL_INT10_Pos (10)
#define ADCIOVF_ALL_INT10_Msk (0x1UL << ADCIOVF_ALL_INT10_Pos)

typedef enum
{
    ADCIOVF_BIT_INT10_NOT_OCCUR     = 0,  /*!< No overflow                 */
    ADCIOVF_BIT_INT10_OCCUR         = 1,  /*!< ADC interrupt 10 overflow   */
} ADCIOVF_BIT_INT10;

#define ADCIOVF_ALL_INT10_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT10_Pos)
#define ADCIOVF_ALL_INT10_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT11
 *  @access     ADC->ADCIOVF.bit.INT11
 *  @brief      ADC interrupt 11 overflow flag
 */
#define ADCIOVF_ALL_INT11_Pos (11)
#define ADCIOVF_ALL_INT11_Msk (0x1UL << ADCIOVF_ALL_INT11_Pos)

typedef enum
{
    ADCIOVF_BIT_INT11_NOT_OCCUR     = 0,  /*!< No overflow                 */
    ADCIOVF_BIT_INT11_OCCUR         = 1,  /*!< ADC interrupt 11 overflow   */
} ADCIOVF_BIT_INT11;

#define ADCIOVF_ALL_INT11_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT11_Pos)
#define ADCIOVF_ALL_INT11_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT12
 *  @access     ADC->ADCIOVF.bit.INT12
 *  @brief      ADC interrupt 12 overflow flag
 */
#define ADCIOVF_ALL_INT12_Pos (12)
#define ADCIOVF_ALL_INT12_Msk (0x1UL << ADCIOVF_ALL_INT12_Pos)

typedef enum
{
    ADCIOVF_BIT_INT12_NOT_OCCUR     = 0,  /*!< No overflow                 */
    ADCIOVF_BIT_INT12_OCCUR         = 1,  /*!< ADC interrupt 12 overflow   */
} ADCIOVF_BIT_INT12;

#define ADCIOVF_ALL_INT12_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT12_Pos)
#define ADCIOVF_ALL_INT12_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT13
 *  @access     ADC->ADCIOVF.bit.INT13
 *  @brief      ADC interrupt 13 overflow flag
 */
#define ADCIOVF_ALL_INT13_Pos (13)
#define ADCIOVF_ALL_INT13_Msk (0x1UL << ADCIOVF_ALL_INT13_Pos)

typedef enum
{
    ADCIOVF_BIT_INT13_NOT_OCCUR     = 0,  /*!< No overflow                 */
    ADCIOVF_BIT_INT13_OCCUR         = 1,  /*!< ADC interrupt 13 overflow   */
} ADCIOVF_BIT_INT13;

#define ADCIOVF_ALL_INT13_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT13_Pos)
#define ADCIOVF_ALL_INT13_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT14
 *  @access     ADC->ADCIOVF.bit.INT14
 *  @brief      ADC interrupt 14 overflow flag
 */
#define ADCIOVF_ALL_INT14_Pos (14)
#define ADCIOVF_ALL_INT14_Msk (0x1UL << ADCIOVF_ALL_INT14_Pos)

typedef enum
{
    ADCIOVF_BIT_INT14_NOT_OCCUR     = 0,  /*!< No overflow                 */
    ADCIOVF_BIT_INT14_OCCUR         = 1,  /*!< ADC interrupt 14 overflow   */
} ADCIOVF_BIT_INT14;

#define ADCIOVF_ALL_INT14_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT14_Pos)
#define ADCIOVF_ALL_INT14_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVF         INT15
 *  @access     ADC->ADCIOVF.bit.INT15
 *  @brief      ADC interrupt 15 overflow flag
 */
#define ADCIOVF_ALL_INT15_Pos (15)
#define ADCIOVF_ALL_INT15_Msk (0x1UL << ADCIOVF_ALL_INT15_Pos)

typedef enum
{
    ADCIOVF_BIT_INT15_NOT_OCCUR     = 0,  /*!< No overflow                 */
    ADCIOVF_BIT_INT15_OCCUR         = 1,  /*!< ADC interrupt 15 overflow   */
} ADCIOVF_BIT_INT15;

#define ADCIOVF_ALL_INT15_NOT_OCCUR     ((0x0UL) << ADCIOVF_ALL_INT15_Pos)
#define ADCIOVF_ALL_INT15_OCCUR         ((0x1UL) << ADCIOVF_ALL_INT15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT0
 *  @access     ADC->ADCIOVFC.bit.INT0
 *  @brief      ADC interrupt 0 overflow flag clear
 */
#define ADCIOVFC_ALL_INT0_Pos (0)
#define ADCIOVFC_ALL_INT0_Msk (0x1UL << ADCIOVFC_ALL_INT0_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT0_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT0]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT0;

#define ADCIOVFC_ALL_INT0_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT0_Pos)
#define ADCIOVFC_ALL_INT0_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT1
 *  @access     ADC->ADCIOVFC.bit.INT1
 *  @brief      ADC interrupt 1 overflow flag clear
 */
#define ADCIOVFC_ALL_INT1_Pos (1)
#define ADCIOVFC_ALL_INT1_Msk (0x1UL << ADCIOVFC_ALL_INT1_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT1_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT1]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT1;

#define ADCIOVFC_ALL_INT1_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT1_Pos)
#define ADCIOVFC_ALL_INT1_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT2
 *  @access     ADC->ADCIOVFC.bit.INT2
 *  @brief      ADC interrupt 2 overflow flag clear
 */
#define ADCIOVFC_ALL_INT2_Pos (2)
#define ADCIOVFC_ALL_INT2_Msk (0x1UL << ADCIOVFC_ALL_INT2_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT2_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT2_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT2]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT2;

#define ADCIOVFC_ALL_INT2_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT2_Pos)
#define ADCIOVFC_ALL_INT2_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT3
 *  @access     ADC->ADCIOVFC.bit.INT3
 *  @brief      ADC interrupt 3 overflow flag clear
 */
#define ADCIOVFC_ALL_INT3_Pos (3)
#define ADCIOVFC_ALL_INT3_Msk (0x1UL << ADCIOVFC_ALL_INT3_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT3_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT3_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT3]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT3;

#define ADCIOVFC_ALL_INT3_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT3_Pos)
#define ADCIOVFC_ALL_INT3_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT4
 *  @access     ADC->ADCIOVFC.bit.INT4
 *  @brief      ADC interrupt 4 overflow flag clear
 */
#define ADCIOVFC_ALL_INT4_Pos (4)
#define ADCIOVFC_ALL_INT4_Msk (0x1UL << ADCIOVFC_ALL_INT4_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT4_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT4_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT4]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT4;

#define ADCIOVFC_ALL_INT4_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT4_Pos)
#define ADCIOVFC_ALL_INT4_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT5
 *  @access     ADC->ADCIOVFC.bit.INT5
 *  @brief      ADC interrupt 5 overflow flag clear
 */
#define ADCIOVFC_ALL_INT5_Pos (5)
#define ADCIOVFC_ALL_INT5_Msk (0x1UL << ADCIOVFC_ALL_INT5_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT5_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT5_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT5]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT5;

#define ADCIOVFC_ALL_INT5_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT5_Pos)
#define ADCIOVFC_ALL_INT5_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT6
 *  @access     ADC->ADCIOVFC.bit.INT6
 *  @brief      ADC interrupt 6 overflow flag clear
 */
#define ADCIOVFC_ALL_INT6_Pos (6)
#define ADCIOVFC_ALL_INT6_Msk (0x1UL << ADCIOVFC_ALL_INT6_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT6_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT6_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT6]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT6;

#define ADCIOVFC_ALL_INT6_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT6_Pos)
#define ADCIOVFC_ALL_INT6_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT7
 *  @access     ADC->ADCIOVFC.bit.INT7
 *  @brief      ADC interrupt 7 overflow flag clear
 */
#define ADCIOVFC_ALL_INT7_Pos (7)
#define ADCIOVFC_ALL_INT7_Msk (0x1UL << ADCIOVFC_ALL_INT7_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT7_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT7_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT7]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT7;

#define ADCIOVFC_ALL_INT7_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT7_Pos)
#define ADCIOVFC_ALL_INT7_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT8
 *  @access     ADC->ADCIOVFC.bit.INT8
 *  @brief      ADC interrupt 8 overflow flag clear
 */
#define ADCIOVFC_ALL_INT8_Pos (8)
#define ADCIOVFC_ALL_INT8_Msk (0x1UL << ADCIOVFC_ALL_INT8_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT8_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT8_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT8]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT8;

#define ADCIOVFC_ALL_INT8_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT8_Pos)
#define ADCIOVFC_ALL_INT8_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT9
 *  @access     ADC->ADCIOVFC.bit.INT9
 *  @brief      ADC interrupt 9 overflow flag clear
 */
#define ADCIOVFC_ALL_INT9_Pos (9)
#define ADCIOVFC_ALL_INT9_Msk (0x1UL << ADCIOVFC_ALL_INT9_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT9_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                      */
    ADCIOVFC_BIT_INT9_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT9]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT9;

#define ADCIOVFC_ALL_INT9_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT9_Pos)
#define ADCIOVFC_ALL_INT9_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT10
 *  @access     ADC->ADCIOVFC.bit.INT10
 *  @brief      ADC interrupt 10 overflow flag clear
 */
#define ADCIOVFC_ALL_INT10_Pos (10)
#define ADCIOVFC_ALL_INT10_Msk (0x1UL << ADCIOVFC_ALL_INT10_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT10_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                       */
    ADCIOVFC_BIT_INT10_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT10]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT10;

#define ADCIOVFC_ALL_INT10_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT10_Pos)
#define ADCIOVFC_ALL_INT10_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT11
 *  @access     ADC->ADCIOVFC.bit.INT11
 *  @brief      ADC interrupt 11 overflow flag clear
 */
#define ADCIOVFC_ALL_INT11_Pos (11)
#define ADCIOVFC_ALL_INT11_Msk (0x1UL << ADCIOVFC_ALL_INT11_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT11_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                       */
    ADCIOVFC_BIT_INT11_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT11]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT11;

#define ADCIOVFC_ALL_INT11_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT11_Pos)
#define ADCIOVFC_ALL_INT11_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT12
 *  @access     ADC->ADCIOVFC.bit.INT12
 *  @brief      ADC interrupt 12 overflow flag clear
 */
#define ADCIOVFC_ALL_INT12_Pos (12)
#define ADCIOVFC_ALL_INT12_Msk (0x1UL << ADCIOVFC_ALL_INT12_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT12_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                       */
    ADCIOVFC_BIT_INT12_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT12]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT12;

#define ADCIOVFC_ALL_INT12_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT12_Pos)
#define ADCIOVFC_ALL_INT12_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT13
 *  @access     ADC->ADCIOVFC.bit.INT13
 *  @brief      ADC interrupt 13 overflow flag clear
 */
#define ADCIOVFC_ALL_INT13_Pos (13)
#define ADCIOVFC_ALL_INT13_Msk (0x1UL << ADCIOVFC_ALL_INT13_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT13_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                       */
    ADCIOVFC_BIT_INT13_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT13]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT13;

#define ADCIOVFC_ALL_INT13_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT13_Pos)
#define ADCIOVFC_ALL_INT13_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT14
 *  @access     ADC->ADCIOVFC.bit.INT14
 *  @brief      ADC interrupt 14 overflow flag clear
 */
#define ADCIOVFC_ALL_INT14_Pos (14)
#define ADCIOVFC_ALL_INT14_Msk (0x1UL << ADCIOVFC_ALL_INT14_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT14_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                       */
    ADCIOVFC_BIT_INT14_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT14]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT14;

#define ADCIOVFC_ALL_INT14_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT14_Pos)
#define ADCIOVFC_ALL_INT14_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIOVFC        INT15
 *  @access     ADC->ADCIOVFC.bit.INT15
 *  @brief      ADC interrupt 15 overflow flag clear
 */
#define ADCIOVFC_ALL_INT15_Pos (15)
#define ADCIOVFC_ALL_INT15_Msk (0x1UL << ADCIOVFC_ALL_INT15_Pos)

typedef enum
{
    ADCIOVFC_BIT_INT15_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                       */
    ADCIOVFC_BIT_INT15_CLEAR         = 1,  /*!< Write a 1 clears the ADCIOVF[INT15]. This bit is self-cleared.   */
} ADCIOVFC_BIT_INT15;

#define ADCIOVFC_ALL_INT15_NO_EFFECT     ((0x0UL) << ADCIOVFC_ALL_INT15_Pos)
#define ADCIOVFC_ALL_INT15_CLEAR         ((0x1UL) << ADCIOVFC_ALL_INT15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT0
 *  @access     ADC->ADCIE.bit.INT0
 *  @brief      ADC interrupt 0 enable
 */
#define ADCIE_ALL_INT0_Pos (0)
#define ADCIE_ALL_INT0_Msk (0x1UL << ADCIE_ALL_INT0_Pos)

typedef enum
{
    ADCIE_BIT_INT0_DISABLE     = 0,  /*!< Disable ADC interrupt 0   */
    ADCIE_BIT_INT0_ENABLE      = 1,  /*!< Enable ADC interrupt 0    */
} ADCIE_BIT_INT0;

#define ADCIE_ALL_INT0_DISABLE     ((0x0UL) << ADCIE_ALL_INT0_Pos)
#define ADCIE_ALL_INT0_ENABLE      ((0x1UL) << ADCIE_ALL_INT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT1
 *  @access     ADC->ADCIE.bit.INT1
 *  @brief      ADC interrupt 1 enable
 */
#define ADCIE_ALL_INT1_Pos (1)
#define ADCIE_ALL_INT1_Msk (0x1UL << ADCIE_ALL_INT1_Pos)

typedef enum
{
    ADCIE_BIT_INT1_DISABLE     = 0,  /*!< Disable ADC interrupt 1   */
    ADCIE_BIT_INT1_ENABLE      = 1,  /*!< Enable ADC interrupt 1    */
} ADCIE_BIT_INT1;

#define ADCIE_ALL_INT1_DISABLE     ((0x0UL) << ADCIE_ALL_INT1_Pos)
#define ADCIE_ALL_INT1_ENABLE      ((0x1UL) << ADCIE_ALL_INT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT2
 *  @access     ADC->ADCIE.bit.INT2
 *  @brief      ADC interrupt 2 enable
 */
#define ADCIE_ALL_INT2_Pos (2)
#define ADCIE_ALL_INT2_Msk (0x1UL << ADCIE_ALL_INT2_Pos)

typedef enum
{
    ADCIE_BIT_INT2_DISABLE     = 0,  /*!< Disable ADC interrupt 2   */
    ADCIE_BIT_INT2_ENABLE      = 1,  /*!< Enable ADC interrupt 2    */
} ADCIE_BIT_INT2;

#define ADCIE_ALL_INT2_DISABLE     ((0x0UL) << ADCIE_ALL_INT2_Pos)
#define ADCIE_ALL_INT2_ENABLE      ((0x1UL) << ADCIE_ALL_INT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT3
 *  @access     ADC->ADCIE.bit.INT3
 *  @brief      ADC interrupt 3 enable
 */
#define ADCIE_ALL_INT3_Pos (3)
#define ADCIE_ALL_INT3_Msk (0x1UL << ADCIE_ALL_INT3_Pos)

typedef enum
{
    ADCIE_BIT_INT3_DISABLE     = 0,  /*!< Disable ADC interrupt 3   */
    ADCIE_BIT_INT3_ENABLE      = 1,  /*!< Enable ADC interrupt 3    */
} ADCIE_BIT_INT3;

#define ADCIE_ALL_INT3_DISABLE     ((0x0UL) << ADCIE_ALL_INT3_Pos)
#define ADCIE_ALL_INT3_ENABLE      ((0x1UL) << ADCIE_ALL_INT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT4
 *  @access     ADC->ADCIE.bit.INT4
 *  @brief      ADC interrupt 4 enable
 */
#define ADCIE_ALL_INT4_Pos (4)
#define ADCIE_ALL_INT4_Msk (0x1UL << ADCIE_ALL_INT4_Pos)

typedef enum
{
    ADCIE_BIT_INT4_DISABLE     = 0,  /*!< Disable ADC interrupt 4   */
    ADCIE_BIT_INT4_ENABLE      = 1,  /*!< Enable ADC interrupt 4    */
} ADCIE_BIT_INT4;

#define ADCIE_ALL_INT4_DISABLE     ((0x0UL) << ADCIE_ALL_INT4_Pos)
#define ADCIE_ALL_INT4_ENABLE      ((0x1UL) << ADCIE_ALL_INT4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT5
 *  @access     ADC->ADCIE.bit.INT5
 *  @brief      ADC interrupt 5 enable
 */
#define ADCIE_ALL_INT5_Pos (5)
#define ADCIE_ALL_INT5_Msk (0x1UL << ADCIE_ALL_INT5_Pos)

typedef enum
{
    ADCIE_BIT_INT5_DISABLE     = 0,  /*!< Disable ADC interrupt 5   */
    ADCIE_BIT_INT5_ENABLE      = 1,  /*!< Enable ADC interrupt 5    */
} ADCIE_BIT_INT5;

#define ADCIE_ALL_INT5_DISABLE     ((0x0UL) << ADCIE_ALL_INT5_Pos)
#define ADCIE_ALL_INT5_ENABLE      ((0x1UL) << ADCIE_ALL_INT5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT6
 *  @access     ADC->ADCIE.bit.INT6
 *  @brief      ADC interrupt 6 enable
 */
#define ADCIE_ALL_INT6_Pos (6)
#define ADCIE_ALL_INT6_Msk (0x1UL << ADCIE_ALL_INT6_Pos)

typedef enum
{
    ADCIE_BIT_INT6_DISABLE     = 0,  /*!< Disable ADC interrupt 6   */
    ADCIE_BIT_INT6_ENABLE      = 1,  /*!< Enable ADC interrupt 6    */
} ADCIE_BIT_INT6;

#define ADCIE_ALL_INT6_DISABLE     ((0x0UL) << ADCIE_ALL_INT6_Pos)
#define ADCIE_ALL_INT6_ENABLE      ((0x1UL) << ADCIE_ALL_INT6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT7
 *  @access     ADC->ADCIE.bit.INT7
 *  @brief      ADC interrupt 7 enable
 */
#define ADCIE_ALL_INT7_Pos (7)
#define ADCIE_ALL_INT7_Msk (0x1UL << ADCIE_ALL_INT7_Pos)

typedef enum
{
    ADCIE_BIT_INT7_DISABLE     = 0,  /*!< Disable ADC interrupt 7   */
    ADCIE_BIT_INT7_ENABLE      = 1,  /*!< Enable ADC interrupt 7    */
} ADCIE_BIT_INT7;

#define ADCIE_ALL_INT7_DISABLE     ((0x0UL) << ADCIE_ALL_INT7_Pos)
#define ADCIE_ALL_INT7_ENABLE      ((0x1UL) << ADCIE_ALL_INT7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT8
 *  @access     ADC->ADCIE.bit.INT8
 *  @brief      ADC interrupt 8 enable
 */
#define ADCIE_ALL_INT8_Pos (8)
#define ADCIE_ALL_INT8_Msk (0x1UL << ADCIE_ALL_INT8_Pos)

typedef enum
{
    ADCIE_BIT_INT8_DISABLE     = 0,  /*!< Disable ADC interrupt 8   */
    ADCIE_BIT_INT8_ENABLE      = 1,  /*!< Enable ADC interrupt 8    */
} ADCIE_BIT_INT8;

#define ADCIE_ALL_INT8_DISABLE     ((0x0UL) << ADCIE_ALL_INT8_Pos)
#define ADCIE_ALL_INT8_ENABLE      ((0x1UL) << ADCIE_ALL_INT8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT9
 *  @access     ADC->ADCIE.bit.INT9
 *  @brief      ADC interrupt 9 enable
 */
#define ADCIE_ALL_INT9_Pos (9)
#define ADCIE_ALL_INT9_Msk (0x1UL << ADCIE_ALL_INT9_Pos)

typedef enum
{
    ADCIE_BIT_INT9_DISABLE     = 0,  /*!< Disable ADC interrupt 9   */
    ADCIE_BIT_INT9_ENABLE      = 1,  /*!< Enable ADC interrupt 9    */
} ADCIE_BIT_INT9;

#define ADCIE_ALL_INT9_DISABLE     ((0x0UL) << ADCIE_ALL_INT9_Pos)
#define ADCIE_ALL_INT9_ENABLE      ((0x1UL) << ADCIE_ALL_INT9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT10
 *  @access     ADC->ADCIE.bit.INT10
 *  @brief      ADC interrupt 10 enable
 */
#define ADCIE_ALL_INT10_Pos (10)
#define ADCIE_ALL_INT10_Msk (0x1UL << ADCIE_ALL_INT10_Pos)

typedef enum
{
    ADCIE_BIT_INT10_DISABLE     = 0,  /*!< Disable ADC interrupt 10   */
    ADCIE_BIT_INT10_ENABLE      = 1,  /*!< Enable ADC interrupt 10    */
} ADCIE_BIT_INT10;

#define ADCIE_ALL_INT10_DISABLE     ((0x0UL) << ADCIE_ALL_INT10_Pos)
#define ADCIE_ALL_INT10_ENABLE      ((0x1UL) << ADCIE_ALL_INT10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT11
 *  @access     ADC->ADCIE.bit.INT11
 *  @brief      ADC interrupt 11 enable
 */
#define ADCIE_ALL_INT11_Pos (11)
#define ADCIE_ALL_INT11_Msk (0x1UL << ADCIE_ALL_INT11_Pos)

typedef enum
{
    ADCIE_BIT_INT11_DISABLE     = 0,  /*!< Disable ADC interrupt 11   */
    ADCIE_BIT_INT11_ENABLE      = 1,  /*!< Enable ADC interrupt 11    */
} ADCIE_BIT_INT11;

#define ADCIE_ALL_INT11_DISABLE     ((0x0UL) << ADCIE_ALL_INT11_Pos)
#define ADCIE_ALL_INT11_ENABLE      ((0x1UL) << ADCIE_ALL_INT11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT12
 *  @access     ADC->ADCIE.bit.INT12
 *  @brief      ADC interrupt 12 enable
 */
#define ADCIE_ALL_INT12_Pos (12)
#define ADCIE_ALL_INT12_Msk (0x1UL << ADCIE_ALL_INT12_Pos)

typedef enum
{
    ADCIE_BIT_INT12_DISABLE     = 0,  /*!< Disable ADC interrupt 12   */
    ADCIE_BIT_INT12_ENABLE      = 1,  /*!< Enable ADC interrupt 12    */
} ADCIE_BIT_INT12;

#define ADCIE_ALL_INT12_DISABLE     ((0x0UL) << ADCIE_ALL_INT12_Pos)
#define ADCIE_ALL_INT12_ENABLE      ((0x1UL) << ADCIE_ALL_INT12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT13
 *  @access     ADC->ADCIE.bit.INT13
 *  @brief      ADC interrupt 13 enable
 */
#define ADCIE_ALL_INT13_Pos (13)
#define ADCIE_ALL_INT13_Msk (0x1UL << ADCIE_ALL_INT13_Pos)

typedef enum
{
    ADCIE_BIT_INT13_DISABLE     = 0,  /*!< Disable ADC interrupt 13   */
    ADCIE_BIT_INT13_ENABLE      = 1,  /*!< Enable ADC interrupt 13    */
} ADCIE_BIT_INT13;

#define ADCIE_ALL_INT13_DISABLE     ((0x0UL) << ADCIE_ALL_INT13_Pos)
#define ADCIE_ALL_INT13_ENABLE      ((0x1UL) << ADCIE_ALL_INT13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT14
 *  @access     ADC->ADCIE.bit.INT14
 *  @brief      ADC interrupt 14 enable
 */
#define ADCIE_ALL_INT14_Pos (14)
#define ADCIE_ALL_INT14_Msk (0x1UL << ADCIE_ALL_INT14_Pos)

typedef enum
{
    ADCIE_BIT_INT14_DISABLE     = 0,  /*!< Disable ADC interrupt 14   */
    ADCIE_BIT_INT14_ENABLE      = 1,  /*!< Enable ADC interrupt 14    */
} ADCIE_BIT_INT14;

#define ADCIE_ALL_INT14_DISABLE     ((0x0UL) << ADCIE_ALL_INT14_Pos)
#define ADCIE_ALL_INT14_ENABLE      ((0x1UL) << ADCIE_ALL_INT14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCIE           INT15
 *  @access     ADC->ADCIE.bit.INT15
 *  @brief      ADC interrupt 15 enable
 */
#define ADCIE_ALL_INT15_Pos (15)
#define ADCIE_ALL_INT15_Msk (0x1UL << ADCIE_ALL_INT15_Pos)

typedef enum
{
    ADCIE_BIT_INT15_DISABLE     = 0,  /*!< Disable ADC interrupt 15   */
    ADCIE_BIT_INT15_ENABLE      = 1,  /*!< Enable ADC interrupt 15    */
} ADCIE_BIT_INT15;

#define ADCIE_ALL_INT15_DISABLE     ((0x0UL) << ADCIE_ALL_INT15_Pos)
#define ADCIE_ALL_INT15_ENABLE      ((0x1UL) << ADCIE_ALL_INT15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCPRICTL    PRIORITY
 *  @access     ADC->ADCSOCPRICTL.bit.PRIORITY
 *  @brief      SOC (Start of Conversion) Priority
 *              Determineds the cutoff point for priority mode and round arbitration of SOCs
 */
#define ADCSOCPRICTL_ALL_PRIORITY_Pos (0)
#define ADCSOCPRICTL_ALL_PRIORITY_Msk (0xFUL << ADCSOCPRICTL_ALL_PRIORITY_Pos)

typedef enum
{
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC0      = 0,  /*!< All SOCs priority follow the rule of round mode              */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC1      = 1,  /*!< SOC0 are high priority, SOC1-SOC15 is in round mode          */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC2      = 2,  /*!< SOC0-SOC1 are high priority, SOC2-SOC15 is in round mode     */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC3      = 3,  /*!< SOC0-SOC2 are high priority, SOC3-SOC15 is in round mode     */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC4      = 4,  /*!< SOC0-SOC3 are high priority, SOC4-SOC15 is in round mode     */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC5      = 5,  /*!< SOC0-SOC4 are high priority, SOC5-SOC15 is in round mode     */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC6      = 6,  /*!< SOC0-SOC5 are high priority, SOC6-SOC15 is in round mode     */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC7      = 7,  /*!< SOC0-SOC6 are high priority, SOC7-SOC15 is in round mode     */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC8      = 8,  /*!< SOC0-SOC7 are high priority, SOC8-SOC15 is in round mode     */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC9      = 9,  /*!< SOC0-SOC8 are high priority, SOC9-SOC15 is in round mode     */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC10     = 10,  /*!< SOC0-SOC9 are high priority, SOC10-SOC15 is in round mode    */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC11     = 11,  /*!< SOC0-SOC10 are high priority, SOC11-SOC15 is in round mode   */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC12     = 12,  /*!< SOC0-SOC11 are high priority, SOC12-SOC15 is in round mode   */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC13     = 13,  /*!< SOC0-SOC12 are high priority, SOC13-SOC15 is in round mode   */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC14     = 14,  /*!< SOC0-SOC13 are high priority, SOC14-SOC15 is in round mode   */
    ADCSOCPRICTL_BIT_PRIORITY_CUTOFF_AT_SOC15     = 15,  /*!< SOC0-SOC14 are high priority, SOC15 is in round mode         */
} ADCSOCPRICTL_BIT_PRIORITY;

#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC0      ((0x00UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC1      ((0x01UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC2      ((0x02UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC3      ((0x03UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC4      ((0x04UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC5      ((0x05UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC6      ((0x06UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC7      ((0x07UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC8      ((0x08UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC9      ((0x09UL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC10     ((0x0AUL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC11     ((0x0BUL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC12     ((0x0CUL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC13     ((0x0DUL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC14     ((0x0EUL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)
#define ADCSOCPRICTL_ALL_PRIORITY_CUTOFF_AT_SOC15     ((0x0FUL) << ADCSOCPRICTL_ALL_PRIORITY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC0
 *  @access     ADC->ADCSOCFLG.bit.SOC0
 *  @brief      SOC0 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC0_Pos (0)
#define ADCSOCFLG_ALL_SOC0_Msk (0x1UL << ADCSOCFLG_ALL_SOC0_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC0_NO_PENDING        = 0,  /*!< No sample pending for SOC0                                  */
    ADCSOCFLG_BIT_SOC0_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC0.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC0;

#define ADCSOCFLG_ALL_SOC0_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC0_Pos)
#define ADCSOCFLG_ALL_SOC0_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC1
 *  @access     ADC->ADCSOCFLG.bit.SOC1
 *  @brief      SOC1 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC1_Pos (1)
#define ADCSOCFLG_ALL_SOC1_Msk (0x1UL << ADCSOCFLG_ALL_SOC1_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC1_NO_PENDING        = 0,  /*!< No sample pending for SOC1                                  */
    ADCSOCFLG_BIT_SOC1_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC1.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC1;

#define ADCSOCFLG_ALL_SOC1_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC1_Pos)
#define ADCSOCFLG_ALL_SOC1_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC2
 *  @access     ADC->ADCSOCFLG.bit.SOC2
 *  @brief      SOC2 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC2_Pos (2)
#define ADCSOCFLG_ALL_SOC2_Msk (0x1UL << ADCSOCFLG_ALL_SOC2_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC2_NO_PENDING        = 0,  /*!< No sample pending for SOC2                                  */
    ADCSOCFLG_BIT_SOC2_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC2.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC2;

#define ADCSOCFLG_ALL_SOC2_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC2_Pos)
#define ADCSOCFLG_ALL_SOC2_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC3
 *  @access     ADC->ADCSOCFLG.bit.SOC3
 *  @brief      SOC3 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC3_Pos (3)
#define ADCSOCFLG_ALL_SOC3_Msk (0x1UL << ADCSOCFLG_ALL_SOC3_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC3_NO_PENDING        = 0,  /*!< No sample pending for SOC3                                  */
    ADCSOCFLG_BIT_SOC3_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC3.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC3;

#define ADCSOCFLG_ALL_SOC3_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC3_Pos)
#define ADCSOCFLG_ALL_SOC3_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC4
 *  @access     ADC->ADCSOCFLG.bit.SOC4
 *  @brief      SOC4 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC4_Pos (4)
#define ADCSOCFLG_ALL_SOC4_Msk (0x1UL << ADCSOCFLG_ALL_SOC4_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC4_NO_PENDING        = 0,  /*!< No sample pending for SOC4                                  */
    ADCSOCFLG_BIT_SOC4_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC4.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC4;

#define ADCSOCFLG_ALL_SOC4_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC4_Pos)
#define ADCSOCFLG_ALL_SOC4_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC5
 *  @access     ADC->ADCSOCFLG.bit.SOC5
 *  @brief      SOC5 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC5_Pos (5)
#define ADCSOCFLG_ALL_SOC5_Msk (0x1UL << ADCSOCFLG_ALL_SOC5_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC5_NO_PENDING        = 0,  /*!< No sample pending for SOC5                                  */
    ADCSOCFLG_BIT_SOC5_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC5.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC5;

#define ADCSOCFLG_ALL_SOC5_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC5_Pos)
#define ADCSOCFLG_ALL_SOC5_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC6
 *  @access     ADC->ADCSOCFLG.bit.SOC6
 *  @brief      SOC6 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC6_Pos (6)
#define ADCSOCFLG_ALL_SOC6_Msk (0x1UL << ADCSOCFLG_ALL_SOC6_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC6_NO_PENDING        = 0,  /*!< No sample pending for SOC6                                  */
    ADCSOCFLG_BIT_SOC6_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC6.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC6;

#define ADCSOCFLG_ALL_SOC6_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC6_Pos)
#define ADCSOCFLG_ALL_SOC6_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC7
 *  @access     ADC->ADCSOCFLG.bit.SOC7
 *  @brief      SOC7 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC7_Pos (7)
#define ADCSOCFLG_ALL_SOC7_Msk (0x1UL << ADCSOCFLG_ALL_SOC7_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC7_NO_PENDING        = 0,  /*!< No sample pending for SOC7                                  */
    ADCSOCFLG_BIT_SOC7_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC7.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC7;

#define ADCSOCFLG_ALL_SOC7_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC7_Pos)
#define ADCSOCFLG_ALL_SOC7_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC8
 *  @access     ADC->ADCSOCFLG.bit.SOC8
 *  @brief      SOC8 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC8_Pos (8)
#define ADCSOCFLG_ALL_SOC8_Msk (0x1UL << ADCSOCFLG_ALL_SOC8_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC8_NO_PENDING        = 0,  /*!< No sample pending for SOC8                                  */
    ADCSOCFLG_BIT_SOC8_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC8.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC8;

#define ADCSOCFLG_ALL_SOC8_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC8_Pos)
#define ADCSOCFLG_ALL_SOC8_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC9
 *  @access     ADC->ADCSOCFLG.bit.SOC9
 *  @brief      SOC9 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC9_Pos (9)
#define ADCSOCFLG_ALL_SOC9_Msk (0x1UL << ADCSOCFLG_ALL_SOC9_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC9_NO_PENDING        = 0,  /*!< No sample pending for SOC9                                  */
    ADCSOCFLG_BIT_SOC9_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC9.  
                                                    Self-cleared when sample starts.                            */
} ADCSOCFLG_BIT_SOC9;

#define ADCSOCFLG_ALL_SOC9_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC9_Pos)
#define ADCSOCFLG_ALL_SOC9_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC10
 *  @access     ADC->ADCSOCFLG.bit.SOC10
 *  @brief      SOC10 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC10_Pos (10)
#define ADCSOCFLG_ALL_SOC10_Msk (0x1UL << ADCSOCFLG_ALL_SOC10_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC10_NO_PENDING        = 0,  /*!< No sample pending for SOC10                                  */
    ADCSOCFLG_BIT_SOC10_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC10.  
                                                     Self-cleared when sample starts.                             */
} ADCSOCFLG_BIT_SOC10;

#define ADCSOCFLG_ALL_SOC10_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC10_Pos)
#define ADCSOCFLG_ALL_SOC10_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC11
 *  @access     ADC->ADCSOCFLG.bit.SOC11
 *  @brief      SOC11 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC11_Pos (11)
#define ADCSOCFLG_ALL_SOC11_Msk (0x1UL << ADCSOCFLG_ALL_SOC11_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC11_NO_PENDING        = 0,  /*!< No sample pending for SOC11                                  */
    ADCSOCFLG_BIT_SOC11_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC11.  
                                                     Self-cleared when sample starts.                             */
} ADCSOCFLG_BIT_SOC11;

#define ADCSOCFLG_ALL_SOC11_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC11_Pos)
#define ADCSOCFLG_ALL_SOC11_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC12
 *  @access     ADC->ADCSOCFLG.bit.SOC12
 *  @brief      SOC12 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC12_Pos (12)
#define ADCSOCFLG_ALL_SOC12_Msk (0x1UL << ADCSOCFLG_ALL_SOC12_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC12_NO_PENDING        = 0,  /*!< No sample pending for SOC12                                  */
    ADCSOCFLG_BIT_SOC12_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC12.  
                                                     Self-cleared when sample starts.                             */
} ADCSOCFLG_BIT_SOC12;

#define ADCSOCFLG_ALL_SOC12_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC12_Pos)
#define ADCSOCFLG_ALL_SOC12_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC13
 *  @access     ADC->ADCSOCFLG.bit.SOC13
 *  @brief      SOC13 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC13_Pos (13)
#define ADCSOCFLG_ALL_SOC13_Msk (0x1UL << ADCSOCFLG_ALL_SOC13_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC13_NO_PENDING        = 0,  /*!< No sample pending for SOC13                                  */
    ADCSOCFLG_BIT_SOC13_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC13.  
                                                     Self-cleared when sample starts.                             */
} ADCSOCFLG_BIT_SOC13;

#define ADCSOCFLG_ALL_SOC13_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC13_Pos)
#define ADCSOCFLG_ALL_SOC13_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC14
 *  @access     ADC->ADCSOCFLG.bit.SOC14
 *  @brief      SOC14 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC14_Pos (14)
#define ADCSOCFLG_ALL_SOC14_Msk (0x1UL << ADCSOCFLG_ALL_SOC14_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC14_NO_PENDING        = 0,  /*!< No sample pending for SOC14                                  */
    ADCSOCFLG_BIT_SOC14_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC14.  
                                                     Self-cleared when sample starts.                             */
} ADCSOCFLG_BIT_SOC14;

#define ADCSOCFLG_ALL_SOC14_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC14_Pos)
#define ADCSOCFLG_ALL_SOC14_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFLG       SOC15
 *  @access     ADC->ADCSOCFLG.bit.SOC15
 *  @brief      SOC15 (Start of Conversion) flag
 */
#define ADCSOCFLG_ALL_SOC15_Pos (15)
#define ADCSOCFLG_ALL_SOC15_Msk (0x1UL << ADCSOCFLG_ALL_SOC15_Pos)

typedef enum
{
    ADCSOCFLG_BIT_SOC15_NO_PENDING        = 0,  /*!< No sample pending for SOC15                                  */
    ADCSOCFLG_BIT_SOC15_TRIG_RECEIVED     = 1,  /*!< Trigger has been received and sample is pending for SOC15.  
                                                     Self-cleared when sample starts.                             */
} ADCSOCFLG_BIT_SOC15;

#define ADCSOCFLG_ALL_SOC15_NO_PENDING        ((0x0UL) << ADCSOCFLG_ALL_SOC15_Pos)
#define ADCSOCFLG_ALL_SOC15_TRIG_RECEIVED     ((0x1UL) << ADCSOCFLG_ALL_SOC15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC0
 *  @access     ADC->ADCSOCFRC.bit.SOC0
 *  @brief      SOC0 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC0_Pos (0)
#define ADCSOCFRC_ALL_SOC0_Msk (0x1UL << ADCSOCFRC_ALL_SOC0_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC0_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC0_FORCE_CONVERT     = 1,  /*!< Force high to SOC0 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC0;

#define ADCSOCFRC_ALL_SOC0_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC0_Pos)
#define ADCSOCFRC_ALL_SOC0_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC1
 *  @access     ADC->ADCSOCFRC.bit.SOC1
 *  @brief      SOC1 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC1_Pos (1)
#define ADCSOCFRC_ALL_SOC1_Msk (0x1UL << ADCSOCFRC_ALL_SOC1_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC1_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC1_FORCE_CONVERT     = 1,  /*!< Force high to SOC1 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC1;

#define ADCSOCFRC_ALL_SOC1_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC1_Pos)
#define ADCSOCFRC_ALL_SOC1_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC2
 *  @access     ADC->ADCSOCFRC.bit.SOC2
 *  @brief      SOC2 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC2_Pos (2)
#define ADCSOCFRC_ALL_SOC2_Msk (0x1UL << ADCSOCFRC_ALL_SOC2_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC2_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC2_FORCE_CONVERT     = 1,  /*!< Force high to SOC2 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC2;

#define ADCSOCFRC_ALL_SOC2_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC2_Pos)
#define ADCSOCFRC_ALL_SOC2_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC3
 *  @access     ADC->ADCSOCFRC.bit.SOC3
 *  @brief      SOC3 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC3_Pos (3)
#define ADCSOCFRC_ALL_SOC3_Msk (0x1UL << ADCSOCFRC_ALL_SOC3_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC3_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC3_FORCE_CONVERT     = 1,  /*!< Force high to SOC3 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC3;

#define ADCSOCFRC_ALL_SOC3_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC3_Pos)
#define ADCSOCFRC_ALL_SOC3_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC4
 *  @access     ADC->ADCSOCFRC.bit.SOC4
 *  @brief      SOC4 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC4_Pos (4)
#define ADCSOCFRC_ALL_SOC4_Msk (0x1UL << ADCSOCFRC_ALL_SOC4_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC4_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC4_FORCE_CONVERT     = 1,  /*!< Force high to SOC4 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC4;

#define ADCSOCFRC_ALL_SOC4_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC4_Pos)
#define ADCSOCFRC_ALL_SOC4_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC5
 *  @access     ADC->ADCSOCFRC.bit.SOC5
 *  @brief      SOC5 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC5_Pos (5)
#define ADCSOCFRC_ALL_SOC5_Msk (0x1UL << ADCSOCFRC_ALL_SOC5_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC5_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC5_FORCE_CONVERT     = 1,  /*!< Force high to SOC5 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC5;

#define ADCSOCFRC_ALL_SOC5_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC5_Pos)
#define ADCSOCFRC_ALL_SOC5_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC6
 *  @access     ADC->ADCSOCFRC.bit.SOC6
 *  @brief      SOC6 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC6_Pos (6)
#define ADCSOCFRC_ALL_SOC6_Msk (0x1UL << ADCSOCFRC_ALL_SOC6_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC6_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC6_FORCE_CONVERT     = 1,  /*!< Force high to SOC6 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC6;

#define ADCSOCFRC_ALL_SOC6_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC6_Pos)
#define ADCSOCFRC_ALL_SOC6_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC7
 *  @access     ADC->ADCSOCFRC.bit.SOC7
 *  @brief      SOC7 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC7_Pos (7)
#define ADCSOCFRC_ALL_SOC7_Msk (0x1UL << ADCSOCFRC_ALL_SOC7_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC7_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC7_FORCE_CONVERT     = 1,  /*!< Force high to SOC7 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC7;

#define ADCSOCFRC_ALL_SOC7_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC7_Pos)
#define ADCSOCFRC_ALL_SOC7_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC8
 *  @access     ADC->ADCSOCFRC.bit.SOC8
 *  @brief      SOC8 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC8_Pos (8)
#define ADCSOCFRC_ALL_SOC8_Msk (0x1UL << ADCSOCFRC_ALL_SOC8_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC8_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC8_FORCE_CONVERT     = 1,  /*!< Force high to SOC8 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC8;

#define ADCSOCFRC_ALL_SOC8_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC8_Pos)
#define ADCSOCFRC_ALL_SOC8_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC9
 *  @access     ADC->ADCSOCFRC.bit.SOC9
 *  @brief      SOC9 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC9_Pos (9)
#define ADCSOCFRC_ALL_SOC9_Msk (0x1UL << ADCSOCFRC_ALL_SOC9_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC9_NO_EFFECT         = 0,  /*!< No action                                      */
    ADCSOCFRC_BIT_SOC9_FORCE_CONVERT     = 1,  /*!< Force high to SOC9 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC9;

#define ADCSOCFRC_ALL_SOC9_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC9_Pos)
#define ADCSOCFRC_ALL_SOC9_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC10
 *  @access     ADC->ADCSOCFRC.bit.SOC10
 *  @brief      SOC10 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC10_Pos (10)
#define ADCSOCFRC_ALL_SOC10_Msk (0x1UL << ADCSOCFRC_ALL_SOC10_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC10_NO_EFFECT         = 0,  /*!< No action                                       */
    ADCSOCFRC_BIT_SOC10_FORCE_CONVERT     = 1,  /*!< Force high to SOC10 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC10;

#define ADCSOCFRC_ALL_SOC10_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC10_Pos)
#define ADCSOCFRC_ALL_SOC10_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC11
 *  @access     ADC->ADCSOCFRC.bit.SOC11
 *  @brief      SOC11 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC11_Pos (11)
#define ADCSOCFRC_ALL_SOC11_Msk (0x1UL << ADCSOCFRC_ALL_SOC11_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC11_NO_EFFECT         = 0,  /*!< No action                                       */
    ADCSOCFRC_BIT_SOC11_FORCE_CONVERT     = 1,  /*!< Force high to SOC11 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC11;

#define ADCSOCFRC_ALL_SOC11_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC11_Pos)
#define ADCSOCFRC_ALL_SOC11_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC12
 *  @access     ADC->ADCSOCFRC.bit.SOC12
 *  @brief      SOC12 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC12_Pos (12)
#define ADCSOCFRC_ALL_SOC12_Msk (0x1UL << ADCSOCFRC_ALL_SOC12_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC12_NO_EFFECT         = 0,  /*!< No action                                       */
    ADCSOCFRC_BIT_SOC12_FORCE_CONVERT     = 1,  /*!< Force high to SOC12 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC12;

#define ADCSOCFRC_ALL_SOC12_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC12_Pos)
#define ADCSOCFRC_ALL_SOC12_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC13
 *  @access     ADC->ADCSOCFRC.bit.SOC13
 *  @brief      SOC13 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC13_Pos (13)
#define ADCSOCFRC_ALL_SOC13_Msk (0x1UL << ADCSOCFRC_ALL_SOC13_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC13_NO_EFFECT         = 0,  /*!< No action                                       */
    ADCSOCFRC_BIT_SOC13_FORCE_CONVERT     = 1,  /*!< Force high to SOC13 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC13;

#define ADCSOCFRC_ALL_SOC13_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC13_Pos)
#define ADCSOCFRC_ALL_SOC13_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC14
 *  @access     ADC->ADCSOCFRC.bit.SOC14
 *  @brief      SOC14 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC14_Pos (14)
#define ADCSOCFRC_ALL_SOC14_Msk (0x1UL << ADCSOCFRC_ALL_SOC14_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC14_NO_EFFECT         = 0,  /*!< No action                                       */
    ADCSOCFRC_BIT_SOC14_FORCE_CONVERT     = 1,  /*!< Force high to SOC14 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC14;

#define ADCSOCFRC_ALL_SOC14_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC14_Pos)
#define ADCSOCFRC_ALL_SOC14_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCFRC       SOC15
 *  @access     ADC->ADCSOCFRC.bit.SOC15
 *  @brief      SOC15 (Start of Conversion) flag force
 */
#define ADCSOCFRC_ALL_SOC15_Pos (15)
#define ADCSOCFRC_ALL_SOC15_Msk (0x1UL << ADCSOCFRC_ALL_SOC15_Pos)

typedef enum
{
    ADCSOCFRC_BIT_SOC15_NO_EFFECT         = 0,  /*!< No action                                       */
    ADCSOCFRC_BIT_SOC15_FORCE_CONVERT     = 1,  /*!< Force high to SOC15 bit in ADCSOCFLG register   */
} ADCSOCFRC_BIT_SOC15;

#define ADCSOCFRC_ALL_SOC15_NO_EFFECT         ((0x0UL) << ADCSOCFRC_ALL_SOC15_Pos)
#define ADCSOCFRC_ALL_SOC15_FORCE_CONVERT     ((0x1UL) << ADCSOCFRC_ALL_SOC15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC0
 *  @access     ADC->ADCSOCOVF.bit.SOC0
 *  @brief      SOC0 (Start of Conversion) overflow flag
 *              This indicates an SOC0 interrupt was generated while an existing SOC0 interrupt was
 *              already pending. This overflow flag can't stop SOC0 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC0_Pos (0)
#define ADCSOCOVF_ALL_SOC0_Msk (0x1UL << ADCSOCOVF_ALL_SOC0_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC0_NOT_OCCUR     = 0,  /*!< No SOC0 interrupt overflow   */
    ADCSOCOVF_BIT_SOC0_OCCUR         = 1,  /*!< SOC0 interrupt overflow      */
} ADCSOCOVF_BIT_SOC0;

#define ADCSOCOVF_ALL_SOC0_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC0_Pos)
#define ADCSOCOVF_ALL_SOC0_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC1
 *  @access     ADC->ADCSOCOVF.bit.SOC1
 *  @brief      SOC1 (Start of Conversion) overflow flag
 *              This indicates an SOC1 interrupt was generated while an existing SOC1 interrupt was
 *              already pending. This overflow flag can't stop SOC1 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC1_Pos (1)
#define ADCSOCOVF_ALL_SOC1_Msk (0x1UL << ADCSOCOVF_ALL_SOC1_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC1_NOT_OCCUR     = 0,  /*!< No SOC1 interrupt overflow   */
    ADCSOCOVF_BIT_SOC1_OCCUR         = 1,  /*!< SOC1 interrupt overflow      */
} ADCSOCOVF_BIT_SOC1;

#define ADCSOCOVF_ALL_SOC1_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC1_Pos)
#define ADCSOCOVF_ALL_SOC1_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC2
 *  @access     ADC->ADCSOCOVF.bit.SOC2
 *  @brief      SOC2 (Start of Conversion) overflow flag
 *              This indicates an SOC2 interrupt was generated while an existing SOC2 interrupt was
 *              already pending. This overflow flag can't stop SOC2 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC2_Pos (2)
#define ADCSOCOVF_ALL_SOC2_Msk (0x1UL << ADCSOCOVF_ALL_SOC2_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC2_NOT_OCCUR     = 0,  /*!< No SOC2 interrupt overflow   */
    ADCSOCOVF_BIT_SOC2_OCCUR         = 1,  /*!< SOC2 interrupt overflow      */
} ADCSOCOVF_BIT_SOC2;

#define ADCSOCOVF_ALL_SOC2_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC2_Pos)
#define ADCSOCOVF_ALL_SOC2_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC3
 *  @access     ADC->ADCSOCOVF.bit.SOC3
 *  @brief      SOC3 (Start of Conversion) overflow flag
 *              This indicates an SOC3 interrupt was generated while an existing SOC3 interrupt was
 *              already pending. This overflow flag can't stop SOC3 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC3_Pos (3)
#define ADCSOCOVF_ALL_SOC3_Msk (0x1UL << ADCSOCOVF_ALL_SOC3_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC3_NOT_OCCUR     = 0,  /*!< No SOC3 interrupt overflow   */
    ADCSOCOVF_BIT_SOC3_OCCUR         = 1,  /*!< SOC3 interrupt overflow      */
} ADCSOCOVF_BIT_SOC3;

#define ADCSOCOVF_ALL_SOC3_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC3_Pos)
#define ADCSOCOVF_ALL_SOC3_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC4
 *  @access     ADC->ADCSOCOVF.bit.SOC4
 *  @brief      SOC4 (Start of Conversion) overflow flag
 *              This indicates an SOC4 interrupt was generated while an existing SOC4 interrupt was
 *              already pending. This overflow flag can't stop SOC4 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC4_Pos (4)
#define ADCSOCOVF_ALL_SOC4_Msk (0x1UL << ADCSOCOVF_ALL_SOC4_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC4_NOT_OCCUR     = 0,  /*!< No SOC4 interrupt overflow   */
    ADCSOCOVF_BIT_SOC4_OCCUR         = 1,  /*!< SOC4 interrupt overflow      */
} ADCSOCOVF_BIT_SOC4;

#define ADCSOCOVF_ALL_SOC4_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC4_Pos)
#define ADCSOCOVF_ALL_SOC4_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC5
 *  @access     ADC->ADCSOCOVF.bit.SOC5
 *  @brief      SOC5 (Start of Conversion) overflow flag
 *              This indicates an SOC5 interrupt was generated while an existing SOC5 interrupt was
 *              already pending. This overflow flag can't stop SOC5 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC5_Pos (5)
#define ADCSOCOVF_ALL_SOC5_Msk (0x1UL << ADCSOCOVF_ALL_SOC5_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC5_NOT_OCCUR     = 0,  /*!< No SOC5 interrupt overflow   */
    ADCSOCOVF_BIT_SOC5_OCCUR         = 1,  /*!< SOC5 interrupt overflow      */
} ADCSOCOVF_BIT_SOC5;

#define ADCSOCOVF_ALL_SOC5_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC5_Pos)
#define ADCSOCOVF_ALL_SOC5_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC6
 *  @access     ADC->ADCSOCOVF.bit.SOC6
 *  @brief      SOC6 (Start of Conversion) overflow flag
 *              This indicates an SOC6 interrupt was generated while an existing SOC6 interrupt was
 *              already pending. This overflow flag can't stop SOC6 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC6_Pos (6)
#define ADCSOCOVF_ALL_SOC6_Msk (0x1UL << ADCSOCOVF_ALL_SOC6_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC6_NOT_OCCUR     = 0,  /*!< No SOC6 interrupt overflow   */
    ADCSOCOVF_BIT_SOC6_OCCUR         = 1,  /*!< SOC6 interrupt overflow      */
} ADCSOCOVF_BIT_SOC6;

#define ADCSOCOVF_ALL_SOC6_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC6_Pos)
#define ADCSOCOVF_ALL_SOC6_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC7
 *  @access     ADC->ADCSOCOVF.bit.SOC7
 *  @brief      SOC7 (Start of Conversion) overflow flag
 *              This indicates an SOC7 interrupt was generated while an existing SOC7 interrupt was
 *              already pending. This overflow flag can't stop SOC7 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC7_Pos (7)
#define ADCSOCOVF_ALL_SOC7_Msk (0x1UL << ADCSOCOVF_ALL_SOC7_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC7_NOT_OCCUR     = 0,  /*!< No SOC7 interrupt overflow   */
    ADCSOCOVF_BIT_SOC7_OCCUR         = 1,  /*!< SOC7 interrupt overflow      */
} ADCSOCOVF_BIT_SOC7;

#define ADCSOCOVF_ALL_SOC7_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC7_Pos)
#define ADCSOCOVF_ALL_SOC7_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC8
 *  @access     ADC->ADCSOCOVF.bit.SOC8
 *  @brief      SOC8 (Start of Conversion) overflow flag
 *              This indicates an SOC8 interrupt was generated while an existing SOC8 interrupt was
 *              already pending. This overflow flag can't stop SOC8 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC8_Pos (8)
#define ADCSOCOVF_ALL_SOC8_Msk (0x1UL << ADCSOCOVF_ALL_SOC8_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC8_NOT_OCCUR     = 0,  /*!< No SOC8 interrupt overflow   */
    ADCSOCOVF_BIT_SOC8_OCCUR         = 1,  /*!< SOC8 interrupt overflow      */
} ADCSOCOVF_BIT_SOC8;

#define ADCSOCOVF_ALL_SOC8_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC8_Pos)
#define ADCSOCOVF_ALL_SOC8_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC9
 *  @access     ADC->ADCSOCOVF.bit.SOC9
 *  @brief      SOC9 (Start of Conversion) overflow flag
 *              This indicates an SOC9 interrupt was generated while an existing SOC9 interrupt was
 *              already pending. This overflow flag can't stop SOC9 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC9_Pos (9)
#define ADCSOCOVF_ALL_SOC9_Msk (0x1UL << ADCSOCOVF_ALL_SOC9_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC9_NOT_OCCUR     = 0,  /*!< No SOC9 interrupt overflow   */
    ADCSOCOVF_BIT_SOC9_OCCUR         = 1,  /*!< SOC9 interrupt overflow      */
} ADCSOCOVF_BIT_SOC9;

#define ADCSOCOVF_ALL_SOC9_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC9_Pos)
#define ADCSOCOVF_ALL_SOC9_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC10
 *  @access     ADC->ADCSOCOVF.bit.SOC10
 *  @brief      SOC10 (Start of Conversion) overflow flag
 *              This indicates an SOC10 interrupt was generated while an existing SOC10 interrupt
 *              was already pending. This overflow flag can't stop SOC10 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC10_Pos (10)
#define ADCSOCOVF_ALL_SOC10_Msk (0x1UL << ADCSOCOVF_ALL_SOC10_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC10_NOT_OCCUR     = 0,  /*!< No SOC10 interrupt overflow   */
    ADCSOCOVF_BIT_SOC10_OCCUR         = 1,  /*!< SOC10 interrupt overflow      */
} ADCSOCOVF_BIT_SOC10;

#define ADCSOCOVF_ALL_SOC10_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC10_Pos)
#define ADCSOCOVF_ALL_SOC10_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC11
 *  @access     ADC->ADCSOCOVF.bit.SOC11
 *  @brief      SOC11 (Start of Conversion) overflow flag
 *              This indicates an SOC11 interrupt was generated while an existing SOC11 interrupt
 *              was already pending. This overflow flag can't stop SOC11 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC11_Pos (11)
#define ADCSOCOVF_ALL_SOC11_Msk (0x1UL << ADCSOCOVF_ALL_SOC11_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC11_NOT_OCCUR     = 0,  /*!< No SOC11 interrupt overflow   */
    ADCSOCOVF_BIT_SOC11_OCCUR         = 1,  /*!< SOC11 interrupt overflow      */
} ADCSOCOVF_BIT_SOC11;

#define ADCSOCOVF_ALL_SOC11_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC11_Pos)
#define ADCSOCOVF_ALL_SOC11_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC12
 *  @access     ADC->ADCSOCOVF.bit.SOC12
 *  @brief      SOC12 (Start of Conversion) overflow flag
 *              This indicates an SOC12 interrupt was generated while an existing SOC12 interrupt
 *              was already pending. This overflow flag can't stop SOC12 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC12_Pos (12)
#define ADCSOCOVF_ALL_SOC12_Msk (0x1UL << ADCSOCOVF_ALL_SOC12_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC12_NOT_OCCUR     = 0,  /*!< No SOC12 interrupt overflow   */
    ADCSOCOVF_BIT_SOC12_OCCUR         = 1,  /*!< SOC12 interrupt overflow      */
} ADCSOCOVF_BIT_SOC12;

#define ADCSOCOVF_ALL_SOC12_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC12_Pos)
#define ADCSOCOVF_ALL_SOC12_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC13
 *  @access     ADC->ADCSOCOVF.bit.SOC13
 *  @brief      SOC13 (Start of Conversion) overflow flag
 *              This indicates an SOC13 interrupt was generated while an existing SOC13 interrupt
 *              was already pending. This overflow flag can't stop SOC13 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC13_Pos (13)
#define ADCSOCOVF_ALL_SOC13_Msk (0x1UL << ADCSOCOVF_ALL_SOC13_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC13_NOT_OCCUR     = 0,  /*!< No SOC13 interrupt overflow   */
    ADCSOCOVF_BIT_SOC13_OCCUR         = 1,  /*!< SOC13 interrupt overflow      */
} ADCSOCOVF_BIT_SOC13;

#define ADCSOCOVF_ALL_SOC13_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC13_Pos)
#define ADCSOCOVF_ALL_SOC13_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC14
 *  @access     ADC->ADCSOCOVF.bit.SOC14
 *  @brief      SOC14 (Start of Conversion) overflow flag
 *              This indicates an SOC14 interrupt was generated while an existing SOC14 interrupt
 *              was already pending. This overflow flag can't stop SOC14 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC14_Pos (14)
#define ADCSOCOVF_ALL_SOC14_Msk (0x1UL << ADCSOCOVF_ALL_SOC14_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC14_NOT_OCCUR     = 0,  /*!< No SOC14 interrupt overflow   */
    ADCSOCOVF_BIT_SOC14_OCCUR         = 1,  /*!< SOC14 interrupt overflow      */
} ADCSOCOVF_BIT_SOC14;

#define ADCSOCOVF_ALL_SOC14_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC14_Pos)
#define ADCSOCOVF_ALL_SOC14_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVF       SOC15
 *  @access     ADC->ADCSOCOVF.bit.SOC15
 *  @brief      SOC15 (Start of Conversion) overflow flag
 *              This indicates an SOC15 interrupt was generated while an existing SOC15 interrupt
 *              was already pending. This overflow flag can't stop SOC15 interrupts from being processing.
 *              It just show that a trigger was missed.
 */
#define ADCSOCOVF_ALL_SOC15_Pos (15)
#define ADCSOCOVF_ALL_SOC15_Msk (0x1UL << ADCSOCOVF_ALL_SOC15_Pos)

typedef enum
{
    ADCSOCOVF_BIT_SOC15_NOT_OCCUR     = 0,  /*!< No SOC15 interrupt overflow   */
    ADCSOCOVF_BIT_SOC15_OCCUR         = 1,  /*!< SOC15 interrupt overflow      */
} ADCSOCOVF_BIT_SOC15;

#define ADCSOCOVF_ALL_SOC15_NOT_OCCUR     ((0x0UL) << ADCSOCOVF_ALL_SOC15_Pos)
#define ADCSOCOVF_ALL_SOC15_OCCUR         ((0x1UL) << ADCSOCOVF_ALL_SOC15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC0
 *  @access     ADC->ADCSOCOVFC.bit.SOC0
 *  @brief      Clear SOC0 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC0 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC0_Pos (0)
#define ADCSOCOVFC_ALL_SOC0_Msk (0x1UL << ADCSOCOVFC_ALL_SOC0_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC0_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC0_CLEAR         = 1,  /*!< Clear SOC0 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC0;

#define ADCSOCOVFC_ALL_SOC0_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC0_Pos)
#define ADCSOCOVFC_ALL_SOC0_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC1
 *  @access     ADC->ADCSOCOVFC.bit.SOC1
 *  @brief      Clear SOC1 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC1 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC1_Pos (1)
#define ADCSOCOVFC_ALL_SOC1_Msk (0x1UL << ADCSOCOVFC_ALL_SOC1_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC1_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC1_CLEAR         = 1,  /*!< Clear SOC1 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC1;

#define ADCSOCOVFC_ALL_SOC1_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC1_Pos)
#define ADCSOCOVFC_ALL_SOC1_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC2
 *  @access     ADC->ADCSOCOVFC.bit.SOC2
 *  @brief      Clear SOC2 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC2 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC2_Pos (2)
#define ADCSOCOVFC_ALL_SOC2_Msk (0x1UL << ADCSOCOVFC_ALL_SOC2_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC2_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC2_CLEAR         = 1,  /*!< Clear SOC2 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC2;

#define ADCSOCOVFC_ALL_SOC2_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC2_Pos)
#define ADCSOCOVFC_ALL_SOC2_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC3
 *  @access     ADC->ADCSOCOVFC.bit.SOC3
 *  @brief      Clear SOC3 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC3 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC3_Pos (3)
#define ADCSOCOVFC_ALL_SOC3_Msk (0x1UL << ADCSOCOVFC_ALL_SOC3_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC3_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC3_CLEAR         = 1,  /*!< Clear SOC3 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC3;

#define ADCSOCOVFC_ALL_SOC3_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC3_Pos)
#define ADCSOCOVFC_ALL_SOC3_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC4
 *  @access     ADC->ADCSOCOVFC.bit.SOC4
 *  @brief      Clear SOC4 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC4 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC4_Pos (4)
#define ADCSOCOVFC_ALL_SOC4_Msk (0x1UL << ADCSOCOVFC_ALL_SOC4_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC4_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC4_CLEAR         = 1,  /*!< Clear SOC4 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC4;

#define ADCSOCOVFC_ALL_SOC4_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC4_Pos)
#define ADCSOCOVFC_ALL_SOC4_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC5
 *  @access     ADC->ADCSOCOVFC.bit.SOC5
 *  @brief      Clear SOC5 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC5 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC5_Pos (5)
#define ADCSOCOVFC_ALL_SOC5_Msk (0x1UL << ADCSOCOVFC_ALL_SOC5_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC5_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC5_CLEAR         = 1,  /*!< Clear SOC5 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC5;

#define ADCSOCOVFC_ALL_SOC5_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC5_Pos)
#define ADCSOCOVFC_ALL_SOC5_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC6
 *  @access     ADC->ADCSOCOVFC.bit.SOC6
 *  @brief      Clear SOC6 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC6 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC6_Pos (6)
#define ADCSOCOVFC_ALL_SOC6_Msk (0x1UL << ADCSOCOVFC_ALL_SOC6_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC6_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC6_CLEAR         = 1,  /*!< Clear SOC6 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC6;

#define ADCSOCOVFC_ALL_SOC6_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC6_Pos)
#define ADCSOCOVFC_ALL_SOC6_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC7
 *  @access     ADC->ADCSOCOVFC.bit.SOC7
 *  @brief      Clear SOC7 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC7 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC7_Pos (7)
#define ADCSOCOVFC_ALL_SOC7_Msk (0x1UL << ADCSOCOVFC_ALL_SOC7_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC7_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC7_CLEAR         = 1,  /*!< Clear SOC7 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC7;

#define ADCSOCOVFC_ALL_SOC7_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC7_Pos)
#define ADCSOCOVFC_ALL_SOC7_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC8
 *  @access     ADC->ADCSOCOVFC.bit.SOC8
 *  @brief      Clear SOC8 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC8 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC8_Pos (8)
#define ADCSOCOVFC_ALL_SOC8_Msk (0x1UL << ADCSOCOVFC_ALL_SOC8_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC8_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC8_CLEAR         = 1,  /*!< Clear SOC8 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC8;

#define ADCSOCOVFC_ALL_SOC8_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC8_Pos)
#define ADCSOCOVFC_ALL_SOC8_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC9
 *  @access     ADC->ADCSOCOVFC.bit.SOC9
 *  @brief      Clear SOC9 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC9 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC9_Pos (9)
#define ADCSOCOVFC_ALL_SOC9_Msk (0x1UL << ADCSOCOVFC_ALL_SOC9_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC9_NO_EFFECT     = 0,  /*!< No clear                   */
    ADCSOCOVFC_BIT_SOC9_CLEAR         = 1,  /*!< Clear SOC9 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC9;

#define ADCSOCOVFC_ALL_SOC9_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC9_Pos)
#define ADCSOCOVFC_ALL_SOC9_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC10
 *  @access     ADC->ADCSOCOVFC.bit.SOC10
 *  @brief      Clear SOC10 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC10 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC10_Pos (10)
#define ADCSOCOVFC_ALL_SOC10_Msk (0x1UL << ADCSOCOVFC_ALL_SOC10_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC10_NO_EFFECT     = 0,  /*!< No clear                    */
    ADCSOCOVFC_BIT_SOC10_CLEAR         = 1,  /*!< Clear SOC10 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC10;

#define ADCSOCOVFC_ALL_SOC10_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC10_Pos)
#define ADCSOCOVFC_ALL_SOC10_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC11
 *  @access     ADC->ADCSOCOVFC.bit.SOC11
 *  @brief      Clear SOC11 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC11 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC11_Pos (11)
#define ADCSOCOVFC_ALL_SOC11_Msk (0x1UL << ADCSOCOVFC_ALL_SOC11_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC11_NO_EFFECT      = 0,  /*!< No clear                    */
    ADCSOCOVFC_BIT_SOC11_CLEAR_FLAG     = 1,  /*!< Clear SOC11 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC11;

#define ADCSOCOVFC_ALL_SOC11_NO_EFFECT      ((0x0UL) << ADCSOCOVFC_ALL_SOC11_Pos)
#define ADCSOCOVFC_ALL_SOC11_CLEAR_FLAG     ((0x1UL) << ADCSOCOVFC_ALL_SOC11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC12
 *  @access     ADC->ADCSOCOVFC.bit.SOC12
 *  @brief      Clear SOC12 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC12 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC12_Pos (12)
#define ADCSOCOVFC_ALL_SOC12_Msk (0x1UL << ADCSOCOVFC_ALL_SOC12_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC12_NO_EFFECT     = 0,  /*!< No clear                    */
    ADCSOCOVFC_BIT_SOC12_CLEAR         = 1,  /*!< Clear SOC12 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC12;

#define ADCSOCOVFC_ALL_SOC12_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC12_Pos)
#define ADCSOCOVFC_ALL_SOC12_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC13
 *  @access     ADC->ADCSOCOVFC.bit.SOC13
 *  @brief      Clear SOC13 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC13 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC13_Pos (13)
#define ADCSOCOVFC_ALL_SOC13_Msk (0x1UL << ADCSOCOVFC_ALL_SOC13_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC13_NO_EFFECT     = 0,  /*!< No clear                    */
    ADCSOCOVFC_BIT_SOC13_CLEAR         = 1,  /*!< Clear SOC13 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC13;

#define ADCSOCOVFC_ALL_SOC13_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC13_Pos)
#define ADCSOCOVFC_ALL_SOC13_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC14
 *  @access     ADC->ADCSOCOVFC.bit.SOC14
 *  @brief      Clear SOC14 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC14 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC14_Pos (14)
#define ADCSOCOVFC_ALL_SOC14_Msk (0x1UL << ADCSOCOVFC_ALL_SOC14_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC14_NO_EFFECT     = 0,  /*!< No clear                    */
    ADCSOCOVFC_BIT_SOC14_CLEAR         = 1,  /*!< Clear SOC14 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC14;

#define ADCSOCOVFC_ALL_SOC14_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC14_Pos)
#define ADCSOCOVFC_ALL_SOC14_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCOVFC      SOC15
 *  @access     ADC->ADCSOCOVFC.bit.SOC15
 *  @brief      Clear SOC15 overflow flag
 *              If this bit receive a request to set from software and hardware try to set respective
 *              SOC15 overflow bit in ADCSOCOVF register simultaneously, then hardware has priority
 *              and ADCSOCOVF register will be set.
 */
#define ADCSOCOVFC_ALL_SOC15_Pos (15)
#define ADCSOCOVFC_ALL_SOC15_Msk (0x1UL << ADCSOCOVFC_ALL_SOC15_Pos)

typedef enum
{
    ADCSOCOVFC_BIT_SOC15_NO_EFFECT     = 0,  /*!< No clear                    */
    ADCSOCOVFC_BIT_SOC15_CLEAR         = 1,  /*!< Clear SOC15 Overflow Flag   */
} ADCSOCOVFC_BIT_SOC15;

#define ADCSOCOVFC_ALL_SOC15_NO_EFFECT     ((0x0UL) << ADCSOCOVFC_ALL_SOC15_Pos)
#define ADCSOCOVFC_ALL_SOC15_CLEAR         ((0x1UL) << ADCSOCOVFC_ALL_SOC15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC0
 *  @access     ADC->ADCINTSOCEN.bit.SOC0
 *  @brief      ADC interrupt trigger SOC0 enable
 */
#define ADCINTSOCEN_ALL_SOC0_Pos (0)
#define ADCINTSOCEN_ALL_SOC0_Msk (0x1UL << ADCINTSOCEN_ALL_SOC0_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC0_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC0] is ignored                            */
    ADCINTSOCEN_BIT_SOC0_ENABLE      = 1,  /*!< ADCSOCCTL0[TRIGSEL] is overriden by ADCINTSOCSEL0[SOC0]   */
} ADCINTSOCEN_BIT_SOC0;

#define ADCINTSOCEN_ALL_SOC0_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC0_Pos)
#define ADCINTSOCEN_ALL_SOC0_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC1
 *  @access     ADC->ADCINTSOCEN.bit.SOC1
 *  @brief      ADC interrupt trigger SOC1 enable
 */
#define ADCINTSOCEN_ALL_SOC1_Pos (1)
#define ADCINTSOCEN_ALL_SOC1_Msk (0x1UL << ADCINTSOCEN_ALL_SOC1_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC1_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC1] is ignored                            */
    ADCINTSOCEN_BIT_SOC1_ENABLE      = 1,  /*!< ADCSOCCTL1[TRIGSEL] is overriden by ADCINTSOCSEL0[SOC1]   */
} ADCINTSOCEN_BIT_SOC1;

#define ADCINTSOCEN_ALL_SOC1_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC1_Pos)
#define ADCINTSOCEN_ALL_SOC1_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC2
 *  @access     ADC->ADCINTSOCEN.bit.SOC2
 *  @brief      ADC interrupt trigger SOC2 enable
 */
#define ADCINTSOCEN_ALL_SOC2_Pos (2)
#define ADCINTSOCEN_ALL_SOC2_Msk (0x1UL << ADCINTSOCEN_ALL_SOC2_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC2_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC2] is ignored                            */
    ADCINTSOCEN_BIT_SOC2_ENABLE      = 1,  /*!< ADCSOCCTL2[TRIGSEL] is overriden by ADCINTSOCSEL0[SOC2]   */
} ADCINTSOCEN_BIT_SOC2;

#define ADCINTSOCEN_ALL_SOC2_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC2_Pos)
#define ADCINTSOCEN_ALL_SOC2_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC3
 *  @access     ADC->ADCINTSOCEN.bit.SOC3
 *  @brief      ADC interrupt trigger SOC3 enable
 */
#define ADCINTSOCEN_ALL_SOC3_Pos (3)
#define ADCINTSOCEN_ALL_SOC3_Msk (0x1UL << ADCINTSOCEN_ALL_SOC3_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC3_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC3] is ignored                            */
    ADCINTSOCEN_BIT_SOC3_ENABLE      = 1,  /*!< ADCSOCCTL3[TRIGSEL] is overriden by ADCINTSOCSEL0[SOC3]   */
} ADCINTSOCEN_BIT_SOC3;

#define ADCINTSOCEN_ALL_SOC3_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC3_Pos)
#define ADCINTSOCEN_ALL_SOC3_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC4
 *  @access     ADC->ADCINTSOCEN.bit.SOC4
 *  @brief      ADC interrupt trigger SOC4 enable
 */
#define ADCINTSOCEN_ALL_SOC4_Pos (4)
#define ADCINTSOCEN_ALL_SOC4_Msk (0x1UL << ADCINTSOCEN_ALL_SOC4_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC4_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC4] is ignored                            */
    ADCINTSOCEN_BIT_SOC4_ENABLE      = 1,  /*!< ADCSOCCTL4[TRIGSEL] is overriden by ADCINTSOCSEL0[SOC4]   */
} ADCINTSOCEN_BIT_SOC4;

#define ADCINTSOCEN_ALL_SOC4_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC4_Pos)
#define ADCINTSOCEN_ALL_SOC4_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC5
 *  @access     ADC->ADCINTSOCEN.bit.SOC5
 *  @brief      ADC interrupt trigger SOC5 enable
 */
#define ADCINTSOCEN_ALL_SOC5_Pos (5)
#define ADCINTSOCEN_ALL_SOC5_Msk (0x1UL << ADCINTSOCEN_ALL_SOC5_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC5_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC5] is ignored                            */
    ADCINTSOCEN_BIT_SOC5_ENABLE      = 1,  /*!< ADCSOCCTL5[TRIGSEL] is overriden by ADCINTSOCSEL0[SOC5]   */
} ADCINTSOCEN_BIT_SOC5;

#define ADCINTSOCEN_ALL_SOC5_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC5_Pos)
#define ADCINTSOCEN_ALL_SOC5_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC6
 *  @access     ADC->ADCINTSOCEN.bit.SOC6
 *  @brief      ADC interrupt trigger SOC6 enable
 */
#define ADCINTSOCEN_ALL_SOC6_Pos (6)
#define ADCINTSOCEN_ALL_SOC6_Msk (0x1UL << ADCINTSOCEN_ALL_SOC6_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC6_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC6] is ignored                            */
    ADCINTSOCEN_BIT_SOC6_ENABLE      = 1,  /*!< ADCSOCCTL6[TRIGSEL] is overriden by ADCINTSOCSEL0[SOC6]   */
} ADCINTSOCEN_BIT_SOC6;

#define ADCINTSOCEN_ALL_SOC6_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC6_Pos)
#define ADCINTSOCEN_ALL_SOC6_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC7
 *  @access     ADC->ADCINTSOCEN.bit.SOC7
 *  @brief      ADC interrupt trigger SOC7 enable
 */
#define ADCINTSOCEN_ALL_SOC7_Pos (7)
#define ADCINTSOCEN_ALL_SOC7_Msk (0x1UL << ADCINTSOCEN_ALL_SOC7_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC7_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC7] is ignored                            */
    ADCINTSOCEN_BIT_SOC7_ENABLE      = 1,  /*!< ADCSOCCTL7[TRIGSEL] is overriden by ADCINTSOCSEL0[SOC7]   */
} ADCINTSOCEN_BIT_SOC7;

#define ADCINTSOCEN_ALL_SOC7_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC7_Pos)
#define ADCINTSOCEN_ALL_SOC7_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC8
 *  @access     ADC->ADCINTSOCEN.bit.SOC8
 *  @brief      ADC interrupt trigger SOC8 enable
 */
#define ADCINTSOCEN_ALL_SOC8_Pos (8)
#define ADCINTSOCEN_ALL_SOC8_Msk (0x1UL << ADCINTSOCEN_ALL_SOC8_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC8_DISABLE     = 0,  /*!< ADCINTSOCSEL0[SOC8] is ignored                            */
    ADCINTSOCEN_BIT_SOC8_ENABLE      = 1,  /*!< ADCSOCCTL8[TRIGSEL] is overriden by ADCINTSOCSEL1[SOC8]   */
} ADCINTSOCEN_BIT_SOC8;

#define ADCINTSOCEN_ALL_SOC8_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC8_Pos)
#define ADCINTSOCEN_ALL_SOC8_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC9
 *  @access     ADC->ADCINTSOCEN.bit.SOC9
 *  @brief      ADC interrupt trigger SOC9 enable
 */
#define ADCINTSOCEN_ALL_SOC9_Pos (9)
#define ADCINTSOCEN_ALL_SOC9_Msk (0x1UL << ADCINTSOCEN_ALL_SOC9_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC9_DISABLE     = 0,  /*!< ADCINTSOCSEL1[SOC9] is ignored                            */
    ADCINTSOCEN_BIT_SOC9_ENABLE      = 1,  /*!< ADCSOCCTL9[TRIGSEL] is overriden by ADCINTSOCSEL1[SOC9]   */
} ADCINTSOCEN_BIT_SOC9;

#define ADCINTSOCEN_ALL_SOC9_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC9_Pos)
#define ADCINTSOCEN_ALL_SOC9_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC10
 *  @access     ADC->ADCINTSOCEN.bit.SOC10
 *  @brief      ADC interrupt trigger SOC10 enable
 */
#define ADCINTSOCEN_ALL_SOC10_Pos (10)
#define ADCINTSOCEN_ALL_SOC10_Msk (0x1UL << ADCINTSOCEN_ALL_SOC10_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC10_DISABLE     = 0,  /*!< ADCINTSOCSEL1[SOC10] is ignored                             */
    ADCINTSOCEN_BIT_SOC10_ENABLE      = 1,  /*!< ADCSOCCTL10[TRIGSEL] is overriden by ADCINTSOCSEL1[SOC10]   */
} ADCINTSOCEN_BIT_SOC10;

#define ADCINTSOCEN_ALL_SOC10_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC10_Pos)
#define ADCINTSOCEN_ALL_SOC10_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC11
 *  @access     ADC->ADCINTSOCEN.bit.SOC11
 *  @brief      ADC interrupt trigger SOC11 enable
 */
#define ADCINTSOCEN_ALL_SOC11_Pos (11)
#define ADCINTSOCEN_ALL_SOC11_Msk (0x1UL << ADCINTSOCEN_ALL_SOC11_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC11_DISABLE     = 0,  /*!< ADCINTSOCSEL1[SOC11] is ignored                             */
    ADCINTSOCEN_BIT_SOC11_ENABLE      = 1,  /*!< ADCSOCCTL11[TRIGSEL] is overriden by ADCINTSOCSEL1[SOC11]   */
} ADCINTSOCEN_BIT_SOC11;

#define ADCINTSOCEN_ALL_SOC11_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC11_Pos)
#define ADCINTSOCEN_ALL_SOC11_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC12
 *  @access     ADC->ADCINTSOCEN.bit.SOC12
 *  @brief      ADC interrupt trigger SOC12 enable
 */
#define ADCINTSOCEN_ALL_SOC12_Pos (12)
#define ADCINTSOCEN_ALL_SOC12_Msk (0x1UL << ADCINTSOCEN_ALL_SOC12_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC12_DISABLE     = 0,  /*!< ADCINTSOCSEL1[SOC12] is ignored                             */
    ADCINTSOCEN_BIT_SOC12_ENABLE      = 1,  /*!< ADCSOCCTL12[TRIGSEL] is overriden by ADCINTSOCSEL1[SOC12]   */
} ADCINTSOCEN_BIT_SOC12;

#define ADCINTSOCEN_ALL_SOC12_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC12_Pos)
#define ADCINTSOCEN_ALL_SOC12_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC13
 *  @access     ADC->ADCINTSOCEN.bit.SOC13
 *  @brief      ADC interrupt trigger SOC13 enable
 */
#define ADCINTSOCEN_ALL_SOC13_Pos (13)
#define ADCINTSOCEN_ALL_SOC13_Msk (0x1UL << ADCINTSOCEN_ALL_SOC13_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC13_DISABLE     = 0,  /*!< ADCINTSOCSEL1[SOC13] is ignored                             */
    ADCINTSOCEN_BIT_SOC13_ENABLE      = 1,  /*!< ADCSOCCTL13[TRIGSEL] is overriden by ADCINTSOCSEL1[SOC13]   */
} ADCINTSOCEN_BIT_SOC13;

#define ADCINTSOCEN_ALL_SOC13_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC13_Pos)
#define ADCINTSOCEN_ALL_SOC13_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC14
 *  @access     ADC->ADCINTSOCEN.bit.SOC14
 *  @brief      ADC interrupt trigger SOC14 enable
 */
#define ADCINTSOCEN_ALL_SOC14_Pos (14)
#define ADCINTSOCEN_ALL_SOC14_Msk (0x1UL << ADCINTSOCEN_ALL_SOC14_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC14_DISABLE     = 0,  /*!< ADCINTSOCSEL1[SOC14] is ignored                             */
    ADCINTSOCEN_BIT_SOC14_ENABLE      = 1,  /*!< ADCSOCCTL14[TRIGSEL] is overriden by ADCINTSOCSEL1[SOC14]   */
} ADCINTSOCEN_BIT_SOC14;

#define ADCINTSOCEN_ALL_SOC14_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC14_Pos)
#define ADCINTSOCEN_ALL_SOC14_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCEN     SOC15
 *  @access     ADC->ADCINTSOCEN.bit.SOC15
 *  @brief      ADC interrupt trigger SOC15 enable
 */
#define ADCINTSOCEN_ALL_SOC15_Pos (15)
#define ADCINTSOCEN_ALL_SOC15_Msk (0x1UL << ADCINTSOCEN_ALL_SOC15_Pos)

typedef enum
{
    ADCINTSOCEN_BIT_SOC15_DISABLE     = 0,  /*!< ADCINTSOCSEL1[SOC15] is ignored                             */
    ADCINTSOCEN_BIT_SOC15_ENABLE      = 1,  /*!< ADCSOCCTL15[TRIGSEL] is overriden by ADCINTSOCSEL1[SOC15]   */
} ADCINTSOCEN_BIT_SOC15;

#define ADCINTSOCEN_ALL_SOC15_DISABLE     ((0x0UL) << ADCINTSOCEN_ALL_SOC15_Pos)
#define ADCINTSOCEN_ALL_SOC15_ENABLE      ((0x1UL) << ADCINTSOCEN_ALL_SOC15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL0   SOC0
 *  @access     ADC->ADCINTSOCSEL0.bit.SOC0
 *  @brief      ADC interrupt source for SOC0
 */
#define ADCINTSOCSEL0_ALL_SOC0_Pos (0)
#define ADCINTSOCSEL0_ALL_SOC0_Msk (0xFUL << ADCINTSOCSEL0_ALL_SOC0_Pos)

#define ADCINTSOCSEL0_BIT_SOC0

#define ADCINTSOCSEL0_ALL_SOC0_(x) ((x) << ADCINTSOCSEL0_ALL_SOC0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL0   SOC1
 *  @access     ADC->ADCINTSOCSEL0.bit.SOC1
 *  @brief      ADC interrupt source for SOC1
 */
#define ADCINTSOCSEL0_ALL_SOC1_Pos (4)
#define ADCINTSOCSEL0_ALL_SOC1_Msk (0xFUL << ADCINTSOCSEL0_ALL_SOC1_Pos)

#define ADCINTSOCSEL0_BIT_SOC1

#define ADCINTSOCSEL0_ALL_SOC1_(x) ((x) << ADCINTSOCSEL0_ALL_SOC1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL0   SOC2
 *  @access     ADC->ADCINTSOCSEL0.bit.SOC2
 *  @brief      ADC interrupt source for SOC2
 */
#define ADCINTSOCSEL0_ALL_SOC2_Pos (8)
#define ADCINTSOCSEL0_ALL_SOC2_Msk (0xFUL << ADCINTSOCSEL0_ALL_SOC2_Pos)

#define ADCINTSOCSEL0_BIT_SOC2

#define ADCINTSOCSEL0_ALL_SOC2_(x) ((x) << ADCINTSOCSEL0_ALL_SOC2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL0   SOC3
 *  @access     ADC->ADCINTSOCSEL0.bit.SOC3
 *  @brief      ADC interrupt source for SOC3
 */
#define ADCINTSOCSEL0_ALL_SOC3_Pos (12)
#define ADCINTSOCSEL0_ALL_SOC3_Msk (0xFUL << ADCINTSOCSEL0_ALL_SOC3_Pos)

#define ADCINTSOCSEL0_BIT_SOC3

#define ADCINTSOCSEL0_ALL_SOC3_(x) ((x) << ADCINTSOCSEL0_ALL_SOC3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL0   SOC4
 *  @access     ADC->ADCINTSOCSEL0.bit.SOC4
 *  @brief      ADC interrupt source for SOC4
 */
#define ADCINTSOCSEL0_ALL_SOC4_Pos (16)
#define ADCINTSOCSEL0_ALL_SOC4_Msk (0xFUL << ADCINTSOCSEL0_ALL_SOC4_Pos)

#define ADCINTSOCSEL0_BIT_SOC4

#define ADCINTSOCSEL0_ALL_SOC4_(x) ((x) << ADCINTSOCSEL0_ALL_SOC4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL0   SOC5
 *  @access     ADC->ADCINTSOCSEL0.bit.SOC5
 *  @brief      ADC interrupt source for SOC5
 */
#define ADCINTSOCSEL0_ALL_SOC5_Pos (20)
#define ADCINTSOCSEL0_ALL_SOC5_Msk (0xFUL << ADCINTSOCSEL0_ALL_SOC5_Pos)

#define ADCINTSOCSEL0_BIT_SOC5

#define ADCINTSOCSEL0_ALL_SOC5_(x) ((x) << ADCINTSOCSEL0_ALL_SOC5_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL0   SOC6
 *  @access     ADC->ADCINTSOCSEL0.bit.SOC6
 *  @brief      ADC interrupt source for SOC6
 */
#define ADCINTSOCSEL0_ALL_SOC6_Pos (24)
#define ADCINTSOCSEL0_ALL_SOC6_Msk (0xFUL << ADCINTSOCSEL0_ALL_SOC6_Pos)

#define ADCINTSOCSEL0_BIT_SOC6

#define ADCINTSOCSEL0_ALL_SOC6_(x) ((x) << ADCINTSOCSEL0_ALL_SOC6_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL0   SOC7
 *  @access     ADC->ADCINTSOCSEL0.bit.SOC7
 *  @brief      ADC interrupt source for SOC7
 */
#define ADCINTSOCSEL0_ALL_SOC7_Pos (28)
#define ADCINTSOCSEL0_ALL_SOC7_Msk (0xFUL << ADCINTSOCSEL0_ALL_SOC7_Pos)

#define ADCINTSOCSEL0_BIT_SOC7

#define ADCINTSOCSEL0_ALL_SOC7_(x) ((x) << ADCINTSOCSEL0_ALL_SOC7_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL1   SOC8
 *  @access     ADC->ADCINTSOCSEL1.bit.SOC8
 *  @brief      ADC interrupt source for SOC8
 */
#define ADCINTSOCSEL1_ALL_SOC8_Pos (0)
#define ADCINTSOCSEL1_ALL_SOC8_Msk (0xFUL << ADCINTSOCSEL1_ALL_SOC8_Pos)

#define ADCINTSOCSEL1_BIT_SOC8

#define ADCINTSOCSEL1_ALL_SOC8_(x) ((x) << ADCINTSOCSEL1_ALL_SOC8_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL1   SOC9
 *  @access     ADC->ADCINTSOCSEL1.bit.SOC9
 *  @brief      ADC interrupt source for SOC9
 */
#define ADCINTSOCSEL1_ALL_SOC9_Pos (4)
#define ADCINTSOCSEL1_ALL_SOC9_Msk (0xFUL << ADCINTSOCSEL1_ALL_SOC9_Pos)

#define ADCINTSOCSEL1_BIT_SOC9

#define ADCINTSOCSEL1_ALL_SOC9_(x) ((x) << ADCINTSOCSEL1_ALL_SOC9_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL1   SOC10
 *  @access     ADC->ADCINTSOCSEL1.bit.SOC10
 *  @brief      ADC interrupt source for SOC10
 */
#define ADCINTSOCSEL1_ALL_SOC10_Pos (8)
#define ADCINTSOCSEL1_ALL_SOC10_Msk (0xFUL << ADCINTSOCSEL1_ALL_SOC10_Pos)

#define ADCINTSOCSEL1_BIT_SOC10

#define ADCINTSOCSEL1_ALL_SOC10_(x) ((x) << ADCINTSOCSEL1_ALL_SOC10_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL1   SOC11
 *  @access     ADC->ADCINTSOCSEL1.bit.SOC11
 *  @brief      ADC interrupt source for SOC11
 */
#define ADCINTSOCSEL1_ALL_SOC11_Pos (12)
#define ADCINTSOCSEL1_ALL_SOC11_Msk (0xFUL << ADCINTSOCSEL1_ALL_SOC11_Pos)

#define ADCINTSOCSEL1_BIT_SOC11

#define ADCINTSOCSEL1_ALL_SOC11_(x) ((x) << ADCINTSOCSEL1_ALL_SOC11_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL1   SOC12
 *  @access     ADC->ADCINTSOCSEL1.bit.SOC12
 *  @brief      ADC interrupt source for SOC12
 */
#define ADCINTSOCSEL1_ALL_SOC12_Pos (16)
#define ADCINTSOCSEL1_ALL_SOC12_Msk (0xFUL << ADCINTSOCSEL1_ALL_SOC12_Pos)

#define ADCINTSOCSEL1_BIT_SOC12

#define ADCINTSOCSEL1_ALL_SOC12_(x) ((x) << ADCINTSOCSEL1_ALL_SOC12_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL1   SOC13
 *  @access     ADC->ADCINTSOCSEL1.bit.SOC13
 *  @brief      ADC interrupt source for SOC13
 */
#define ADCINTSOCSEL1_ALL_SOC13_Pos (20)
#define ADCINTSOCSEL1_ALL_SOC13_Msk (0xFUL << ADCINTSOCSEL1_ALL_SOC13_Pos)

#define ADCINTSOCSEL1_BIT_SOC13

#define ADCINTSOCSEL1_ALL_SOC13_(x) ((x) << ADCINTSOCSEL1_ALL_SOC13_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL1   SOC14
 *  @access     ADC->ADCINTSOCSEL1.bit.SOC14
 *  @brief      ADC interrupt source for SOC14
 */
#define ADCINTSOCSEL1_ALL_SOC14_Pos (24)
#define ADCINTSOCSEL1_ALL_SOC14_Msk (0xFUL << ADCINTSOCSEL1_ALL_SOC14_Pos)

#define ADCINTSOCSEL1_BIT_SOC14

#define ADCINTSOCSEL1_ALL_SOC14_(x) ((x) << ADCINTSOCSEL1_ALL_SOC14_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCINTSOCSEL1   SOC15
 *  @access     ADC->ADCINTSOCSEL1.bit.SOC15
 *  @brief      ADC interrupt source for SOC15
 */
#define ADCINTSOCSEL1_ALL_SOC15_Pos (28)
#define ADCINTSOCSEL1_ALL_SOC15_Msk (0xFUL << ADCINTSOCSEL1_ALL_SOC15_Pos)

#define ADCINTSOCSEL1_BIT_SOC15

#define ADCINTSOCSEL1_ALL_SOC15_(x) ((x) << ADCINTSOCSEL1_ALL_SOC15_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCEXTSOCCTL    IOSEL
 *  @access     ADC->ADCEXTSOCCTL.bit.IOSEL
 *  @brief      GPIO number for EXTSOC
 */
#define ADCEXTSOCCTL_ALL_IOSEL_Pos (0)
#define ADCEXTSOCCTL_ALL_IOSEL_Msk (0x3FUL << ADCEXTSOCCTL_ALL_IOSEL_Pos)

#define ADCEXTSOCCTL_BIT_IOSEL

#define ADCEXTSOCCTL_ALL_IOSEL_(x) ((x) << ADCEXTSOCCTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCEXTSOCCTL    POL
 *  @access     ADC->ADCEXTSOCCTL.bit.POL
 *  @brief      EXTSOC polarity
 */
#define ADCEXTSOCCTL_ALL_POL_Pos (6)
#define ADCEXTSOCCTL_ALL_POL_Msk (0x1UL << ADCEXTSOCCTL_ALL_POL_Pos)

typedef enum
{
    ADCEXTSOCCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    ADCEXTSOCCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} ADCEXTSOCCTL_BIT_POL;

#define ADCEXTSOCCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << ADCEXTSOCCTL_ALL_POL_Pos)
#define ADCEXTSOCCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << ADCEXTSOCCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL0      SAMPCNT
 *  @access     ADC->ADCSOCCTL0.bit.SAMPCNT
 *  @brief      Select SOC0 sample window size
 */
#define ADCSOCCTL0_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL0_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL0_ALL_SAMPCNT_Pos)

#define ADCSOCCTL0_BIT_SAMPCNT

#define ADCSOCCTL0_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL0_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL0      CONVCNT
 *  @access     ADC->ADCSOCCTL0.bit.CONVCNT
 *  @brief      Select SOC0 convert window size
 */
#define ADCSOCCTL0_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL0_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL0_ALL_CONVCNT_Pos)

#define ADCSOCCTL0_BIT_CONVCNT

#define ADCSOCCTL0_ALL_CONVCNT_(x) ((x) << ADCSOCCTL0_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL0      AVGCNT
 *  @access     ADC->ADCSOCCTL0.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL0_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL0_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL0_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL0_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL0_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL0_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL0_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL0_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL0_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL0_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL0_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL0_BIT_AVGCNT;

#define ADCSOCCTL0_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL0_ALL_AVGCNT_Pos)
#define ADCSOCCTL0_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL0_ALL_AVGCNT_Pos)
#define ADCSOCCTL0_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL0_ALL_AVGCNT_Pos)
#define ADCSOCCTL0_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL0_ALL_AVGCNT_Pos)
#define ADCSOCCTL0_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL0_ALL_AVGCNT_Pos)
#define ADCSOCCTL0_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL0_ALL_AVGCNT_Pos)
#define ADCSOCCTL0_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL0_ALL_AVGCNT_Pos)
#define ADCSOCCTL0_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL0_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL0      CHSELP
 *  @access     ADC->ADCSOCCTL0.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC0
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL0_ALL_CHSELP_Pos (18)
#define ADCSOCCTL0_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL0_ALL_CHSELP_Pos)

#define ADCSOCCTL0_BIT_CHSELP

#define ADCSOCCTL0_ALL_CHSELP_(x) ((x) << ADCSOCCTL0_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL0      CHSELN
 *  @access     ADC->ADCSOCCTL0.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC0
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL0_ALL_CHSELN_Pos (21)
#define ADCSOCCTL0_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL0_ALL_CHSELN_Pos)

#define ADCSOCCTL0_BIT_CHSELN

#define ADCSOCCTL0_ALL_CHSELN_(x) ((x) << ADCSOCCTL0_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL0      TRIGSEL
 *  @access     ADC->ADCSOCCTL0.bit.TRIGSEL
 *  @brief      Select SOC0 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC0]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC0. This setting can be
 *              overridden by the ADCINTSOCSEL0[SOC0].
 */
#define ADCSOCCTL0_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL0_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL0_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL0_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL0_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL0_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL0_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL0_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL0_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL0_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL0_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL0_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL0_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL0_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL0_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL0_BIT_TRIGSEL;

#define ADCSOCCTL0_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)
#define ADCSOCCTL0_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL0_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL0      SHEN
 *  @access     ADC->ADCSOCCTL0.bit.SHEN
 *  @brief      SH enable
 */
#define ADCSOCCTL0_ALL_SHEN_Pos (29)
#define ADCSOCCTL0_ALL_SHEN_Msk (0x7UL << ADCSOCCTL0_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL0_BIT_SHEN_DISABLE                 = 0,  /*!< Disable all SHs                       */
    ADCSOCCTL0_BIT_SHEN_SHA                     = 1,  /*!< Enable SHA                            */
    ADCSOCCTL0_BIT_SHEN_SHB                     = 2,  /*!< Enable SHB                            */
    ADCSOCCTL0_BIT_SHEN_SHC                     = 3,  /*!< Enable SHC                            */
    ADCSOCCTL0_BIT_SHEN_SHA_AND_SHB             = 4,  /*!< Enable SHA and SHB simultaneously     */
    ADCSOCCTL0_BIT_SHEN_SHB_AND_SHC             = 5,  /*!< Enable SHB and SHC simultaneously     */
    ADCSOCCTL0_BIT_SHEN_SHA_AND_SHC             = 6,  /*!< Enable SHA and SHC simultaneously     */
    ADCSOCCTL0_BIT_SHEN_SHA_AND_SHB_AND_SHC     = 7,  /*!< Enable SHA, SHB, SHC simultaneously   */
} ADCSOCCTL0_BIT_SHEN;

#define ADCSOCCTL0_ALL_SHEN_DISABLE                 ((0x0UL) << ADCSOCCTL0_ALL_SHEN_Pos)
#define ADCSOCCTL0_ALL_SHEN_SHA                     ((0x1UL) << ADCSOCCTL0_ALL_SHEN_Pos)
#define ADCSOCCTL0_ALL_SHEN_SHB                     ((0x2UL) << ADCSOCCTL0_ALL_SHEN_Pos)
#define ADCSOCCTL0_ALL_SHEN_SHC                     ((0x3UL) << ADCSOCCTL0_ALL_SHEN_Pos)
#define ADCSOCCTL0_ALL_SHEN_SHA_AND_SHB             ((0x4UL) << ADCSOCCTL0_ALL_SHEN_Pos)
#define ADCSOCCTL0_ALL_SHEN_SHB_AND_SHC             ((0x5UL) << ADCSOCCTL0_ALL_SHEN_Pos)
#define ADCSOCCTL0_ALL_SHEN_SHA_AND_SHC             ((0x6UL) << ADCSOCCTL0_ALL_SHEN_Pos)
#define ADCSOCCTL0_ALL_SHEN_SHA_AND_SHB_AND_SHC     ((0x7UL) << ADCSOCCTL0_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL1      SAMPCNT
 *  @access     ADC->ADCSOCCTL1.bit.SAMPCNT
 *  @brief      Select SOC1 sample window size
 */
#define ADCSOCCTL1_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL1_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL1_ALL_SAMPCNT_Pos)

#define ADCSOCCTL1_BIT_SAMPCNT

#define ADCSOCCTL1_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL1_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL1      CONVCNT
 *  @access     ADC->ADCSOCCTL1.bit.CONVCNT
 *  @brief      Select SOC1 convert window size
 */
#define ADCSOCCTL1_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL1_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL1_ALL_CONVCNT_Pos)

#define ADCSOCCTL1_BIT_CONVCNT

#define ADCSOCCTL1_ALL_CONVCNT_(x) ((x) << ADCSOCCTL1_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL1      AVGCNT
 *  @access     ADC->ADCSOCCTL1.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL1_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL1_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL1_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL1_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL1_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL1_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL1_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL1_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL1_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL1_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL1_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL1_BIT_AVGCNT;

#define ADCSOCCTL1_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL1_ALL_AVGCNT_Pos)
#define ADCSOCCTL1_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL1_ALL_AVGCNT_Pos)
#define ADCSOCCTL1_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL1_ALL_AVGCNT_Pos)
#define ADCSOCCTL1_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL1_ALL_AVGCNT_Pos)
#define ADCSOCCTL1_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL1_ALL_AVGCNT_Pos)
#define ADCSOCCTL1_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL1_ALL_AVGCNT_Pos)
#define ADCSOCCTL1_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL1_ALL_AVGCNT_Pos)
#define ADCSOCCTL1_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL1_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL1      CHSELP
 *  @access     ADC->ADCSOCCTL1.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC1
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL0[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC0
 */
#define ADCSOCCTL1_ALL_CHSELP_Pos (18)
#define ADCSOCCTL1_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL1_ALL_CHSELP_Pos)

#define ADCSOCCTL1_BIT_CHSELP

#define ADCSOCCTL1_ALL_CHSELP_(x) ((x) << ADCSOCCTL1_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL1      CHSELN
 *  @access     ADC->ADCSOCCTL1.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC1
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL0[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC0
 */
#define ADCSOCCTL1_ALL_CHSELN_Pos (21)
#define ADCSOCCTL1_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL1_ALL_CHSELN_Pos)

#define ADCSOCCTL1_BIT_CHSELN

#define ADCSOCCTL1_ALL_CHSELN_(x) ((x) << ADCSOCCTL1_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL1      TRIGSEL
 *  @access     ADC->ADCSOCCTL1.bit.TRIGSEL
 *  @brief      Select SOC1 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC1]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC1. This setting can be
 *              overridden by the ADCINTSOCSEL0[SOC1].
 *              This field is not used when ADCSOCCTL0[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL1_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL1_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL1_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL1_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL1_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL1_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL1_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL1_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL1_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL1_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL1_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL1_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL1_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL1_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL1_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL1_BIT_TRIGSEL;

#define ADCSOCCTL1_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)
#define ADCSOCCTL1_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL1_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL1      SHEN
 *  @access     ADC->ADCSOCCTL1.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL0[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL1_ALL_SHEN_Pos (29)
#define ADCSOCCTL1_ALL_SHEN_Msk (0x3UL << ADCSOCCTL1_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL1_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL1_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL1_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL1_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL1_BIT_SHEN;

#define ADCSOCCTL1_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL1_ALL_SHEN_Pos)
#define ADCSOCCTL1_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL1_ALL_SHEN_Pos)
#define ADCSOCCTL1_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL1_ALL_SHEN_Pos)
#define ADCSOCCTL1_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL1_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL2      SAMPCNT
 *  @access     ADC->ADCSOCCTL2.bit.SAMPCNT
 *  @brief      Select SOC2 sample window size
 */
#define ADCSOCCTL2_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL2_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL2_ALL_SAMPCNT_Pos)

#define ADCSOCCTL2_BIT_SAMPCNT

#define ADCSOCCTL2_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL2_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL2      CONVCNT
 *  @access     ADC->ADCSOCCTL2.bit.CONVCNT
 *  @brief      Select SOC2 convert window size
 */
#define ADCSOCCTL2_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL2_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL2_ALL_CONVCNT_Pos)

#define ADCSOCCTL2_BIT_CONVCNT

#define ADCSOCCTL2_ALL_CONVCNT_(x) ((x) << ADCSOCCTL2_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL2      AVGCNT
 *  @access     ADC->ADCSOCCTL2.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL2_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL2_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL2_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL2_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL2_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL2_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL2_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL2_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL2_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL2_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL2_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL2_BIT_AVGCNT;

#define ADCSOCCTL2_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL2_ALL_AVGCNT_Pos)
#define ADCSOCCTL2_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL2_ALL_AVGCNT_Pos)
#define ADCSOCCTL2_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL2_ALL_AVGCNT_Pos)
#define ADCSOCCTL2_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL2_ALL_AVGCNT_Pos)
#define ADCSOCCTL2_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL2_ALL_AVGCNT_Pos)
#define ADCSOCCTL2_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL2_ALL_AVGCNT_Pos)
#define ADCSOCCTL2_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL2_ALL_AVGCNT_Pos)
#define ADCSOCCTL2_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL2_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL2      CHSELP
 *  @access     ADC->ADCSOCCTL2.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC2
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL0[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC0
 */
#define ADCSOCCTL2_ALL_CHSELP_Pos (18)
#define ADCSOCCTL2_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL2_ALL_CHSELP_Pos)

#define ADCSOCCTL2_BIT_CHSELP

#define ADCSOCCTL2_ALL_CHSELP_(x) ((x) << ADCSOCCTL2_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL2      CHSELN
 *  @access     ADC->ADCSOCCTL2.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC2
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL0[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC0
 */
#define ADCSOCCTL2_ALL_CHSELN_Pos (21)
#define ADCSOCCTL2_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL2_ALL_CHSELN_Pos)

#define ADCSOCCTL2_BIT_CHSELN

#define ADCSOCCTL2_ALL_CHSELN_(x) ((x) << ADCSOCCTL2_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL2      TRIGSEL
 *  @access     ADC->ADCSOCCTL2.bit.TRIGSEL
 *  @brief      Select SOC2 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC2]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC2. This setting can be
 *              overridden by the ADCINTSOCSEL0[SOC2].
 *              This field is not used when ADCSOCCTL0[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL2_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL2_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL2_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL2_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL2_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL2_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL2_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL2_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL2_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL2_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL2_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL2_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL2_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL2_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL2_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL2_BIT_TRIGSEL;

#define ADCSOCCTL2_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)
#define ADCSOCCTL2_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL2_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL2      SHEN
 *  @access     ADC->ADCSOCCTL2.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL0[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL2_ALL_SHEN_Pos (29)
#define ADCSOCCTL2_ALL_SHEN_Msk (0x3UL << ADCSOCCTL2_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL2_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL2_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL2_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL2_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL2_BIT_SHEN;

#define ADCSOCCTL2_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL2_ALL_SHEN_Pos)
#define ADCSOCCTL2_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL2_ALL_SHEN_Pos)
#define ADCSOCCTL2_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL2_ALL_SHEN_Pos)
#define ADCSOCCTL2_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL2_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL3      SAMPCNT
 *  @access     ADC->ADCSOCCTL3.bit.SAMPCNT
 *  @brief      Select SOC3 sample window size
 */
#define ADCSOCCTL3_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL3_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL3_ALL_SAMPCNT_Pos)

#define ADCSOCCTL3_BIT_SAMPCNT

#define ADCSOCCTL3_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL3_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL3      CONVCNT
 *  @access     ADC->ADCSOCCTL3.bit.CONVCNT
 *  @brief      Select SOC3 convert window size
 */
#define ADCSOCCTL3_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL3_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL3_ALL_CONVCNT_Pos)

#define ADCSOCCTL3_BIT_CONVCNT

#define ADCSOCCTL3_ALL_CONVCNT_(x) ((x) << ADCSOCCTL3_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL3      AVGCNT
 *  @access     ADC->ADCSOCCTL3.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL3_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL3_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL3_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL3_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL3_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL3_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL3_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL3_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL3_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL3_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL3_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL3_BIT_AVGCNT;

#define ADCSOCCTL3_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL3_ALL_AVGCNT_Pos)
#define ADCSOCCTL3_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL3_ALL_AVGCNT_Pos)
#define ADCSOCCTL3_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL3_ALL_AVGCNT_Pos)
#define ADCSOCCTL3_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL3_ALL_AVGCNT_Pos)
#define ADCSOCCTL3_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL3_ALL_AVGCNT_Pos)
#define ADCSOCCTL3_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL3_ALL_AVGCNT_Pos)
#define ADCSOCCTL3_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL3_ALL_AVGCNT_Pos)
#define ADCSOCCTL3_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL3_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL3      CHSELP
 *  @access     ADC->ADCSOCCTL3.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC3
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL3_ALL_CHSELP_Pos (18)
#define ADCSOCCTL3_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL3_ALL_CHSELP_Pos)

#define ADCSOCCTL3_BIT_CHSELP

#define ADCSOCCTL3_ALL_CHSELP_(x) ((x) << ADCSOCCTL3_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL3      CHSELN
 *  @access     ADC->ADCSOCCTL3.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC3
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL3_ALL_CHSELN_Pos (21)
#define ADCSOCCTL3_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL3_ALL_CHSELN_Pos)

#define ADCSOCCTL3_BIT_CHSELN

#define ADCSOCCTL3_ALL_CHSELN_(x) ((x) << ADCSOCCTL3_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL3      TRIGSEL
 *  @access     ADC->ADCSOCCTL3.bit.TRIGSEL
 *  @brief      Select SOC3 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC3]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC3. This setting can be
 *              overridden by the ADCINTSOCSEL0[SOC3].
 */
#define ADCSOCCTL3_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL3_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL3_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL3_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL3_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL3_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL3_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL3_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL3_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL3_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL3_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL3_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL3_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL3_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL3_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL3_BIT_TRIGSEL;

#define ADCSOCCTL3_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)
#define ADCSOCCTL3_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL3_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL3      SHEN
 *  @access     ADC->ADCSOCCTL3.bit.SHEN
 *  @brief      SH enable
 */
#define ADCSOCCTL3_ALL_SHEN_Pos (29)
#define ADCSOCCTL3_ALL_SHEN_Msk (0x7UL << ADCSOCCTL3_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL3_BIT_SHEN_DISABLE                 = 0,  /*!< Disable all SHs                       */
    ADCSOCCTL3_BIT_SHEN_SHA                     = 1,  /*!< Enable SHA                            */
    ADCSOCCTL3_BIT_SHEN_SHB                     = 2,  /*!< Enable SHB                            */
    ADCSOCCTL3_BIT_SHEN_SHC                     = 3,  /*!< Enable SHC                            */
    ADCSOCCTL3_BIT_SHEN_SHA_AND_SHB             = 4,  /*!< Enable SHA and SHB simultaneously     */
    ADCSOCCTL3_BIT_SHEN_SHB_AND_SHC             = 5,  /*!< Enable SHB and SHC simultaneously     */
    ADCSOCCTL3_BIT_SHEN_SHA_AND_SHC             = 6,  /*!< Enable SHA and SHC simultaneously     */
    ADCSOCCTL3_BIT_SHEN_SHA_AND_SHB_AND_SHC     = 7,  /*!< Enable SHA, SHB, SHC simultaneously   */
} ADCSOCCTL3_BIT_SHEN;

#define ADCSOCCTL3_ALL_SHEN_DISABLE                 ((0x0UL) << ADCSOCCTL3_ALL_SHEN_Pos)
#define ADCSOCCTL3_ALL_SHEN_SHA                     ((0x1UL) << ADCSOCCTL3_ALL_SHEN_Pos)
#define ADCSOCCTL3_ALL_SHEN_SHB                     ((0x2UL) << ADCSOCCTL3_ALL_SHEN_Pos)
#define ADCSOCCTL3_ALL_SHEN_SHC                     ((0x3UL) << ADCSOCCTL3_ALL_SHEN_Pos)
#define ADCSOCCTL3_ALL_SHEN_SHA_AND_SHB             ((0x4UL) << ADCSOCCTL3_ALL_SHEN_Pos)
#define ADCSOCCTL3_ALL_SHEN_SHB_AND_SHC             ((0x5UL) << ADCSOCCTL3_ALL_SHEN_Pos)
#define ADCSOCCTL3_ALL_SHEN_SHA_AND_SHC             ((0x6UL) << ADCSOCCTL3_ALL_SHEN_Pos)
#define ADCSOCCTL3_ALL_SHEN_SHA_AND_SHB_AND_SHC     ((0x7UL) << ADCSOCCTL3_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL4      SAMPCNT
 *  @access     ADC->ADCSOCCTL4.bit.SAMPCNT
 *  @brief      Select SOC4 sample window size
 */
#define ADCSOCCTL4_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL4_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL4_ALL_SAMPCNT_Pos)

#define ADCSOCCTL4_BIT_SAMPCNT

#define ADCSOCCTL4_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL4_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL4      CONVCNT
 *  @access     ADC->ADCSOCCTL4.bit.CONVCNT
 *  @brief      Select SOC4 convert window size
 */
#define ADCSOCCTL4_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL4_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL4_ALL_CONVCNT_Pos)

#define ADCSOCCTL4_BIT_CONVCNT

#define ADCSOCCTL4_ALL_CONVCNT_(x) ((x) << ADCSOCCTL4_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL4      AVGCNT
 *  @access     ADC->ADCSOCCTL4.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL4_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL4_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL4_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL4_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL4_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL4_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL4_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL4_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL4_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL4_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL4_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL4_BIT_AVGCNT;

#define ADCSOCCTL4_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL4_ALL_AVGCNT_Pos)
#define ADCSOCCTL4_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL4_ALL_AVGCNT_Pos)
#define ADCSOCCTL4_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL4_ALL_AVGCNT_Pos)
#define ADCSOCCTL4_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL4_ALL_AVGCNT_Pos)
#define ADCSOCCTL4_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL4_ALL_AVGCNT_Pos)
#define ADCSOCCTL4_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL4_ALL_AVGCNT_Pos)
#define ADCSOCCTL4_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL4_ALL_AVGCNT_Pos)
#define ADCSOCCTL4_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL4_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL4      CHSELP
 *  @access     ADC->ADCSOCCTL4.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC4
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL3[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC3
 */
#define ADCSOCCTL4_ALL_CHSELP_Pos (18)
#define ADCSOCCTL4_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL4_ALL_CHSELP_Pos)

#define ADCSOCCTL4_BIT_CHSELP

#define ADCSOCCTL4_ALL_CHSELP_(x) ((x) << ADCSOCCTL4_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL4      CHSELN
 *  @access     ADC->ADCSOCCTL4.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC4
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL3[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC3
 */
#define ADCSOCCTL4_ALL_CHSELN_Pos (21)
#define ADCSOCCTL4_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL4_ALL_CHSELN_Pos)

#define ADCSOCCTL4_BIT_CHSELN

#define ADCSOCCTL4_ALL_CHSELN_(x) ((x) << ADCSOCCTL4_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL4      TRIGSEL
 *  @access     ADC->ADCSOCCTL4.bit.TRIGSEL
 *  @brief      Select SOC4 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC4]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC4. This setting can be
 *              overridden by the ADCINTSOCSEL0[SOC4].
 *              This field is not used when ADCSOCCTL3[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL4_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL4_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL4_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL4_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL4_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL4_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL4_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL4_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL4_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL4_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL4_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL4_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL4_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL4_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL4_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL4_BIT_TRIGSEL;

#define ADCSOCCTL4_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)
#define ADCSOCCTL4_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL4_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL4      SHEN
 *  @access     ADC->ADCSOCCTL4.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL3[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL4_ALL_SHEN_Pos (29)
#define ADCSOCCTL4_ALL_SHEN_Msk (0x3UL << ADCSOCCTL4_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL4_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL4_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL4_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL4_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL4_BIT_SHEN;

#define ADCSOCCTL4_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL4_ALL_SHEN_Pos)
#define ADCSOCCTL4_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL4_ALL_SHEN_Pos)
#define ADCSOCCTL4_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL4_ALL_SHEN_Pos)
#define ADCSOCCTL4_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL4_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL5      SAMPCNT
 *  @access     ADC->ADCSOCCTL5.bit.SAMPCNT
 *  @brief      Select SOC5 sample window size
 */
#define ADCSOCCTL5_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL5_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL5_ALL_SAMPCNT_Pos)

#define ADCSOCCTL5_BIT_SAMPCNT

#define ADCSOCCTL5_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL5_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL5      CONVCNT
 *  @access     ADC->ADCSOCCTL5.bit.CONVCNT
 *  @brief      Select SOC5 convert window size
 */
#define ADCSOCCTL5_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL5_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL5_ALL_CONVCNT_Pos)

#define ADCSOCCTL5_BIT_CONVCNT

#define ADCSOCCTL5_ALL_CONVCNT_(x) ((x) << ADCSOCCTL5_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL5      AVGCNT
 *  @access     ADC->ADCSOCCTL5.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL5_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL5_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL5_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL5_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL5_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL5_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL5_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL5_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL5_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL5_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL5_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL5_BIT_AVGCNT;

#define ADCSOCCTL5_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL5_ALL_AVGCNT_Pos)
#define ADCSOCCTL5_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL5_ALL_AVGCNT_Pos)
#define ADCSOCCTL5_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL5_ALL_AVGCNT_Pos)
#define ADCSOCCTL5_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL5_ALL_AVGCNT_Pos)
#define ADCSOCCTL5_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL5_ALL_AVGCNT_Pos)
#define ADCSOCCTL5_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL5_ALL_AVGCNT_Pos)
#define ADCSOCCTL5_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL5_ALL_AVGCNT_Pos)
#define ADCSOCCTL5_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL5_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL5      CHSELP
 *  @access     ADC->ADCSOCCTL5.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC5
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL3[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC3
 */
#define ADCSOCCTL5_ALL_CHSELP_Pos (18)
#define ADCSOCCTL5_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL5_ALL_CHSELP_Pos)

#define ADCSOCCTL5_BIT_CHSELP

#define ADCSOCCTL5_ALL_CHSELP_(x) ((x) << ADCSOCCTL5_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL5      CHSELN
 *  @access     ADC->ADCSOCCTL5.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC5
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL3[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC3
 */
#define ADCSOCCTL5_ALL_CHSELN_Pos (21)
#define ADCSOCCTL5_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL5_ALL_CHSELN_Pos)

#define ADCSOCCTL5_BIT_CHSELN

#define ADCSOCCTL5_ALL_CHSELN_(x) ((x) << ADCSOCCTL5_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL5      TRIGSEL
 *  @access     ADC->ADCSOCCTL5.bit.TRIGSEL
 *  @brief      Select SOC5 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC5]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC5. This setting can be
 *              overridden by the ADCINTSOCSEL0[SOC5].
 *              This field is not used when ADCSOCCTL3[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL5_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL5_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL5_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL5_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL5_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL5_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL5_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL5_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL5_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL5_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL5_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL5_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL5_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL5_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL5_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL5_BIT_TRIGSEL;

#define ADCSOCCTL5_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)
#define ADCSOCCTL5_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL5_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL5      SHEN
 *  @access     ADC->ADCSOCCTL5.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL3[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL5_ALL_SHEN_Pos (29)
#define ADCSOCCTL5_ALL_SHEN_Msk (0x3UL << ADCSOCCTL5_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL5_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL5_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL5_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL5_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL5_BIT_SHEN;

#define ADCSOCCTL5_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL5_ALL_SHEN_Pos)
#define ADCSOCCTL5_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL5_ALL_SHEN_Pos)
#define ADCSOCCTL5_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL5_ALL_SHEN_Pos)
#define ADCSOCCTL5_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL5_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL6      SAMPCNT
 *  @access     ADC->ADCSOCCTL6.bit.SAMPCNT
 *  @brief      Select SOC6 sample window size
 */
#define ADCSOCCTL6_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL6_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL6_ALL_SAMPCNT_Pos)

#define ADCSOCCTL6_BIT_SAMPCNT

#define ADCSOCCTL6_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL6_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL6      CONVCNT
 *  @access     ADC->ADCSOCCTL6.bit.CONVCNT
 *  @brief      Select SOC6 convert window size
 */
#define ADCSOCCTL6_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL6_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL6_ALL_CONVCNT_Pos)

#define ADCSOCCTL6_BIT_CONVCNT

#define ADCSOCCTL6_ALL_CONVCNT_(x) ((x) << ADCSOCCTL6_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL6      AVGCNT
 *  @access     ADC->ADCSOCCTL6.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL6_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL6_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL6_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL6_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL6_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL6_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL6_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL6_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL6_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL6_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL6_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL6_BIT_AVGCNT;

#define ADCSOCCTL6_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL6_ALL_AVGCNT_Pos)
#define ADCSOCCTL6_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL6_ALL_AVGCNT_Pos)
#define ADCSOCCTL6_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL6_ALL_AVGCNT_Pos)
#define ADCSOCCTL6_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL6_ALL_AVGCNT_Pos)
#define ADCSOCCTL6_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL6_ALL_AVGCNT_Pos)
#define ADCSOCCTL6_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL6_ALL_AVGCNT_Pos)
#define ADCSOCCTL6_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL6_ALL_AVGCNT_Pos)
#define ADCSOCCTL6_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL6_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL6      CHSELP
 *  @access     ADC->ADCSOCCTL6.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC6
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL6_ALL_CHSELP_Pos (18)
#define ADCSOCCTL6_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL6_ALL_CHSELP_Pos)

#define ADCSOCCTL6_BIT_CHSELP

#define ADCSOCCTL6_ALL_CHSELP_(x) ((x) << ADCSOCCTL6_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL6      CHSELN
 *  @access     ADC->ADCSOCCTL6.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC6
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL6_ALL_CHSELN_Pos (21)
#define ADCSOCCTL6_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL6_ALL_CHSELN_Pos)

#define ADCSOCCTL6_BIT_CHSELN

#define ADCSOCCTL6_ALL_CHSELN_(x) ((x) << ADCSOCCTL6_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL6      TRIGSEL
 *  @access     ADC->ADCSOCCTL6.bit.TRIGSEL
 *  @brief      Select SOC6 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC6]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC6. This setting can be
 *              overridden by the ADCINTSOCSEL0[SOC6].
 */
#define ADCSOCCTL6_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL6_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL6_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL6_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL6_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL6_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL6_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL6_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL6_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL6_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL6_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL6_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL6_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL6_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL6_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL6_BIT_TRIGSEL;

#define ADCSOCCTL6_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)
#define ADCSOCCTL6_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL6_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL6      SHEN
 *  @access     ADC->ADCSOCCTL6.bit.SHEN
 *  @brief      SH enable
 */
#define ADCSOCCTL6_ALL_SHEN_Pos (29)
#define ADCSOCCTL6_ALL_SHEN_Msk (0x7UL << ADCSOCCTL6_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL6_BIT_SHEN_DISABLE                 = 0,  /*!< Disable all SHs                       */
    ADCSOCCTL6_BIT_SHEN_SHA                     = 1,  /*!< Enable SHA                            */
    ADCSOCCTL6_BIT_SHEN_SHB                     = 2,  /*!< Enable SHB                            */
    ADCSOCCTL6_BIT_SHEN_SHC                     = 3,  /*!< Enable SHC                            */
    ADCSOCCTL6_BIT_SHEN_SHA_AND_SHB             = 4,  /*!< Enable SHA and SHB simultaneously     */
    ADCSOCCTL6_BIT_SHEN_SHB_AND_SHC             = 5,  /*!< Enable SHB and SHC simultaneously     */
    ADCSOCCTL6_BIT_SHEN_SHA_AND_SHC             = 6,  /*!< Enable SHA and SHC simultaneously     */
    ADCSOCCTL6_BIT_SHEN_SHA_AND_SHB_AND_SHC     = 7,  /*!< Enable SHA, SHB, SHC simultaneously   */
} ADCSOCCTL6_BIT_SHEN;

#define ADCSOCCTL6_ALL_SHEN_DISABLE                 ((0x0UL) << ADCSOCCTL6_ALL_SHEN_Pos)
#define ADCSOCCTL6_ALL_SHEN_SHA                     ((0x1UL) << ADCSOCCTL6_ALL_SHEN_Pos)
#define ADCSOCCTL6_ALL_SHEN_SHB                     ((0x2UL) << ADCSOCCTL6_ALL_SHEN_Pos)
#define ADCSOCCTL6_ALL_SHEN_SHC                     ((0x3UL) << ADCSOCCTL6_ALL_SHEN_Pos)
#define ADCSOCCTL6_ALL_SHEN_SHA_AND_SHB             ((0x4UL) << ADCSOCCTL6_ALL_SHEN_Pos)
#define ADCSOCCTL6_ALL_SHEN_SHB_AND_SHC             ((0x5UL) << ADCSOCCTL6_ALL_SHEN_Pos)
#define ADCSOCCTL6_ALL_SHEN_SHA_AND_SHC             ((0x6UL) << ADCSOCCTL6_ALL_SHEN_Pos)
#define ADCSOCCTL6_ALL_SHEN_SHA_AND_SHB_AND_SHC     ((0x7UL) << ADCSOCCTL6_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL7      SAMPCNT
 *  @access     ADC->ADCSOCCTL7.bit.SAMPCNT
 *  @brief      Select SOC7 sample window size
 */
#define ADCSOCCTL7_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL7_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL7_ALL_SAMPCNT_Pos)

#define ADCSOCCTL7_BIT_SAMPCNT

#define ADCSOCCTL7_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL7_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL7      CONVCNT
 *  @access     ADC->ADCSOCCTL7.bit.CONVCNT
 *  @brief      Select SOC7 convert window size
 */
#define ADCSOCCTL7_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL7_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL7_ALL_CONVCNT_Pos)

#define ADCSOCCTL7_BIT_CONVCNT

#define ADCSOCCTL7_ALL_CONVCNT_(x) ((x) << ADCSOCCTL7_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL7      AVGCNT
 *  @access     ADC->ADCSOCCTL7.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL7_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL7_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL7_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL7_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL7_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL7_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL7_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL7_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL7_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL7_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL7_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL7_BIT_AVGCNT;

#define ADCSOCCTL7_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL7_ALL_AVGCNT_Pos)
#define ADCSOCCTL7_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL7_ALL_AVGCNT_Pos)
#define ADCSOCCTL7_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL7_ALL_AVGCNT_Pos)
#define ADCSOCCTL7_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL7_ALL_AVGCNT_Pos)
#define ADCSOCCTL7_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL7_ALL_AVGCNT_Pos)
#define ADCSOCCTL7_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL7_ALL_AVGCNT_Pos)
#define ADCSOCCTL7_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL7_ALL_AVGCNT_Pos)
#define ADCSOCCTL7_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL7_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL7      CHSELP
 *  @access     ADC->ADCSOCCTL7.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC6
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL6[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC6
 */
#define ADCSOCCTL7_ALL_CHSELP_Pos (18)
#define ADCSOCCTL7_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL7_ALL_CHSELP_Pos)

#define ADCSOCCTL7_BIT_CHSELP

#define ADCSOCCTL7_ALL_CHSELP_(x) ((x) << ADCSOCCTL7_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL7      CHSELN
 *  @access     ADC->ADCSOCCTL7.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC7
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL6[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC6
 */
#define ADCSOCCTL7_ALL_CHSELN_Pos (21)
#define ADCSOCCTL7_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL7_ALL_CHSELN_Pos)

#define ADCSOCCTL7_BIT_CHSELN

#define ADCSOCCTL7_ALL_CHSELN_(x) ((x) << ADCSOCCTL7_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL7      TRIGSEL
 *  @access     ADC->ADCSOCCTL7.bit.TRIGSEL
 *  @brief      Select SOC7 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC7]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC7. This setting can be
 *              overridden by the ADCINTSOCSEL0[SOC7].
 *              This field is not used when ADCSOCCTL6[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL7_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL7_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL7_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL7_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL7_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL7_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL7_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL7_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL7_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL7_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL7_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL7_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL7_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL7_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL7_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL7_BIT_TRIGSEL;

#define ADCSOCCTL7_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)
#define ADCSOCCTL7_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL7_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL7      SHEN
 *  @access     ADC->ADCSOCCTL7.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL6[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL7_ALL_SHEN_Pos (29)
#define ADCSOCCTL7_ALL_SHEN_Msk (0x3UL << ADCSOCCTL7_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL7_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL7_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL7_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL7_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL7_BIT_SHEN;

#define ADCSOCCTL7_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL7_ALL_SHEN_Pos)
#define ADCSOCCTL7_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL7_ALL_SHEN_Pos)
#define ADCSOCCTL7_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL7_ALL_SHEN_Pos)
#define ADCSOCCTL7_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL7_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL8      SAMPCNT
 *  @access     ADC->ADCSOCCTL8.bit.SAMPCNT
 *  @brief      Select SOC8 sample window size
 */
#define ADCSOCCTL8_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL8_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL8_ALL_SAMPCNT_Pos)

#define ADCSOCCTL8_BIT_SAMPCNT

#define ADCSOCCTL8_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL8_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL8      CONVCNT
 *  @access     ADC->ADCSOCCTL8.bit.CONVCNT
 *  @brief      Select SOC8 convert window size
 */
#define ADCSOCCTL8_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL8_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL8_ALL_CONVCNT_Pos)

#define ADCSOCCTL8_BIT_CONVCNT

#define ADCSOCCTL8_ALL_CONVCNT_(x) ((x) << ADCSOCCTL8_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL8      AVGCNT
 *  @access     ADC->ADCSOCCTL8.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL8_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL8_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL8_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL8_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL8_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL8_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL8_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL8_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL8_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL8_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL8_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL8_BIT_AVGCNT;

#define ADCSOCCTL8_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL8_ALL_AVGCNT_Pos)
#define ADCSOCCTL8_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL8_ALL_AVGCNT_Pos)
#define ADCSOCCTL8_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL8_ALL_AVGCNT_Pos)
#define ADCSOCCTL8_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL8_ALL_AVGCNT_Pos)
#define ADCSOCCTL8_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL8_ALL_AVGCNT_Pos)
#define ADCSOCCTL8_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL8_ALL_AVGCNT_Pos)
#define ADCSOCCTL8_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL8_ALL_AVGCNT_Pos)
#define ADCSOCCTL8_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL8_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL8      CHSELP
 *  @access     ADC->ADCSOCCTL8.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC8
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL6[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC6
 */
#define ADCSOCCTL8_ALL_CHSELP_Pos (18)
#define ADCSOCCTL8_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL8_ALL_CHSELP_Pos)

#define ADCSOCCTL8_BIT_CHSELP

#define ADCSOCCTL8_ALL_CHSELP_(x) ((x) << ADCSOCCTL8_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL8      CHSELN
 *  @access     ADC->ADCSOCCTL8.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC8
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL6[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC6
 */
#define ADCSOCCTL8_ALL_CHSELN_Pos (21)
#define ADCSOCCTL8_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL8_ALL_CHSELN_Pos)

#define ADCSOCCTL8_BIT_CHSELN

#define ADCSOCCTL8_ALL_CHSELN_(x) ((x) << ADCSOCCTL8_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL8      TRIGSEL
 *  @access     ADC->ADCSOCCTL8.bit.TRIGSEL
 *  @brief      Select SOC8 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC8]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC8. This setting can be
 *              overridden by the ADCINTSOCSEL1[SOC8].
 *              This field is not used when ADCSOCCTL6[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL8_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL8_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL8_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL8_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL8_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL8_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL8_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL8_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL8_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL8_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL8_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL8_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL8_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL8_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL8_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL8_BIT_TRIGSEL;

#define ADCSOCCTL8_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)
#define ADCSOCCTL8_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL8_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL8      SHEN
 *  @access     ADC->ADCSOCCTL8.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL6[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL8_ALL_SHEN_Pos (29)
#define ADCSOCCTL8_ALL_SHEN_Msk (0x3UL << ADCSOCCTL8_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL8_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL8_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL8_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL8_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL8_BIT_SHEN;

#define ADCSOCCTL8_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL8_ALL_SHEN_Pos)
#define ADCSOCCTL8_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL8_ALL_SHEN_Pos)
#define ADCSOCCTL8_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL8_ALL_SHEN_Pos)
#define ADCSOCCTL8_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL8_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL9      SAMPCNT
 *  @access     ADC->ADCSOCCTL9.bit.SAMPCNT
 *  @brief      Select SOC9 sample window size
 */
#define ADCSOCCTL9_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL9_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL9_ALL_SAMPCNT_Pos)

#define ADCSOCCTL9_BIT_SAMPCNT

#define ADCSOCCTL9_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL9_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL9      CONVCNT
 *  @access     ADC->ADCSOCCTL9.bit.CONVCNT
 *  @brief      Select SOC9 convert window size
 */
#define ADCSOCCTL9_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL9_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL9_ALL_CONVCNT_Pos)

#define ADCSOCCTL9_BIT_CONVCNT

#define ADCSOCCTL9_ALL_CONVCNT_(x) ((x) << ADCSOCCTL9_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL9      AVGCNT
 *  @access     ADC->ADCSOCCTL9.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL9_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL9_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL9_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL9_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL9_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL9_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL9_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL9_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL9_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL9_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL9_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL9_BIT_AVGCNT;

#define ADCSOCCTL9_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL9_ALL_AVGCNT_Pos)
#define ADCSOCCTL9_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL9_ALL_AVGCNT_Pos)
#define ADCSOCCTL9_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL9_ALL_AVGCNT_Pos)
#define ADCSOCCTL9_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL9_ALL_AVGCNT_Pos)
#define ADCSOCCTL9_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL9_ALL_AVGCNT_Pos)
#define ADCSOCCTL9_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL9_ALL_AVGCNT_Pos)
#define ADCSOCCTL9_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL9_ALL_AVGCNT_Pos)
#define ADCSOCCTL9_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL9_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL9      CHSELP
 *  @access     ADC->ADCSOCCTL9.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC9
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL9_ALL_CHSELP_Pos (18)
#define ADCSOCCTL9_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL9_ALL_CHSELP_Pos)

#define ADCSOCCTL9_BIT_CHSELP

#define ADCSOCCTL9_ALL_CHSELP_(x) ((x) << ADCSOCCTL9_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL9      CHSELN
 *  @access     ADC->ADCSOCCTL9.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC9
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL9_ALL_CHSELN_Pos (21)
#define ADCSOCCTL9_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL9_ALL_CHSELN_Pos)

#define ADCSOCCTL9_BIT_CHSELN

#define ADCSOCCTL9_ALL_CHSELN_(x) ((x) << ADCSOCCTL9_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL9      TRIGSEL
 *  @access     ADC->ADCSOCCTL9.bit.TRIGSEL
 *  @brief      Select SOC9 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC9]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC9. This setting can be
 *              overridden by the ADCINTSOCSEL1[SOC9].
 */
#define ADCSOCCTL9_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL9_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL9_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL9_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL9_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL9_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL9_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL9_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL9_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL9_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL9_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL9_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL9_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL9_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL9_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL9_BIT_TRIGSEL;

#define ADCSOCCTL9_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)
#define ADCSOCCTL9_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL9_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL9      SHEN
 *  @access     ADC->ADCSOCCTL9.bit.SHEN
 *  @brief      SH enable
 */
#define ADCSOCCTL9_ALL_SHEN_Pos (29)
#define ADCSOCCTL9_ALL_SHEN_Msk (0x7UL << ADCSOCCTL9_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL9_BIT_SHEN_DISABLE                 = 0,  /*!< Disable all SHs                       */
    ADCSOCCTL9_BIT_SHEN_SHA                     = 1,  /*!< Enable SHA                            */
    ADCSOCCTL9_BIT_SHEN_SHB                     = 2,  /*!< Enable SHB                            */
    ADCSOCCTL9_BIT_SHEN_SHC                     = 3,  /*!< Enable SHC                            */
    ADCSOCCTL9_BIT_SHEN_SHA_AND_SHB             = 4,  /*!< Enable SHA and SHB simultaneously     */
    ADCSOCCTL9_BIT_SHEN_SHB_AND_SHC             = 5,  /*!< Enable SHB and SHC simultaneously     */
    ADCSOCCTL9_BIT_SHEN_SHA_AND_SHC             = 6,  /*!< Enable SHA and SHC simultaneously     */
    ADCSOCCTL9_BIT_SHEN_SHA_AND_SHB_AND_SHC     = 7,  /*!< Enable SHA, SHB, SHC simultaneously   */
} ADCSOCCTL9_BIT_SHEN;

#define ADCSOCCTL9_ALL_SHEN_DISABLE                 ((0x0UL) << ADCSOCCTL9_ALL_SHEN_Pos)
#define ADCSOCCTL9_ALL_SHEN_SHA                     ((0x1UL) << ADCSOCCTL9_ALL_SHEN_Pos)
#define ADCSOCCTL9_ALL_SHEN_SHB                     ((0x2UL) << ADCSOCCTL9_ALL_SHEN_Pos)
#define ADCSOCCTL9_ALL_SHEN_SHC                     ((0x3UL) << ADCSOCCTL9_ALL_SHEN_Pos)
#define ADCSOCCTL9_ALL_SHEN_SHA_AND_SHB             ((0x4UL) << ADCSOCCTL9_ALL_SHEN_Pos)
#define ADCSOCCTL9_ALL_SHEN_SHB_AND_SHC             ((0x5UL) << ADCSOCCTL9_ALL_SHEN_Pos)
#define ADCSOCCTL9_ALL_SHEN_SHA_AND_SHC             ((0x6UL) << ADCSOCCTL9_ALL_SHEN_Pos)
#define ADCSOCCTL9_ALL_SHEN_SHA_AND_SHB_AND_SHC     ((0x7UL) << ADCSOCCTL9_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL10     SAMPCNT
 *  @access     ADC->ADCSOCCTL10.bit.SAMPCNT
 *  @brief      Select SOC10 sample window size
 */
#define ADCSOCCTL10_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL10_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL10_ALL_SAMPCNT_Pos)

#define ADCSOCCTL10_BIT_SAMPCNT

#define ADCSOCCTL10_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL10_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL10     CONVCNT
 *  @access     ADC->ADCSOCCTL10.bit.CONVCNT
 *  @brief      Select SOC10 convert window size
 */
#define ADCSOCCTL10_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL10_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL10_ALL_CONVCNT_Pos)

#define ADCSOCCTL10_BIT_CONVCNT

#define ADCSOCCTL10_ALL_CONVCNT_(x) ((x) << ADCSOCCTL10_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL10     AVGCNT
 *  @access     ADC->ADCSOCCTL10.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL10_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL10_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL10_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL10_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL10_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL10_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL10_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL10_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL10_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL10_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL10_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL10_BIT_AVGCNT;

#define ADCSOCCTL10_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL10_ALL_AVGCNT_Pos)
#define ADCSOCCTL10_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL10_ALL_AVGCNT_Pos)
#define ADCSOCCTL10_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL10_ALL_AVGCNT_Pos)
#define ADCSOCCTL10_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL10_ALL_AVGCNT_Pos)
#define ADCSOCCTL10_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL10_ALL_AVGCNT_Pos)
#define ADCSOCCTL10_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL10_ALL_AVGCNT_Pos)
#define ADCSOCCTL10_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL10_ALL_AVGCNT_Pos)
#define ADCSOCCTL10_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL10_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL10     CHSELP
 *  @access     ADC->ADCSOCCTL10.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC10
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL9[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC9
 */
#define ADCSOCCTL10_ALL_CHSELP_Pos (18)
#define ADCSOCCTL10_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL10_ALL_CHSELP_Pos)

#define ADCSOCCTL10_BIT_CHSELP

#define ADCSOCCTL10_ALL_CHSELP_(x) ((x) << ADCSOCCTL10_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL10     CHSELN
 *  @access     ADC->ADCSOCCTL10.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC10
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL9[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC9
 */
#define ADCSOCCTL10_ALL_CHSELN_Pos (21)
#define ADCSOCCTL10_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL10_ALL_CHSELN_Pos)

#define ADCSOCCTL10_BIT_CHSELN

#define ADCSOCCTL10_ALL_CHSELN_(x) ((x) << ADCSOCCTL10_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL10     TRIGSEL
 *  @access     ADC->ADCSOCCTL10.bit.TRIGSEL
 *  @brief      Select SOC10 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC10]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC10. This setting can be
 *              overridden by the ADCINTSOCSEL1[SOC10].
 *              This field is not used when ADCSOCCTL9[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL10_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL10_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL10_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL10_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL10_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL10_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL10_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL10_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL10_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL10_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL10_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL10_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL10_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL10_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL10_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL10_BIT_TRIGSEL;

#define ADCSOCCTL10_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)
#define ADCSOCCTL10_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL10_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL10     SHEN
 *  @access     ADC->ADCSOCCTL10.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL9[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL10_ALL_SHEN_Pos (29)
#define ADCSOCCTL10_ALL_SHEN_Msk (0x3UL << ADCSOCCTL10_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL10_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL10_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL10_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL10_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL10_BIT_SHEN;

#define ADCSOCCTL10_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL10_ALL_SHEN_Pos)
#define ADCSOCCTL10_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL10_ALL_SHEN_Pos)
#define ADCSOCCTL10_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL10_ALL_SHEN_Pos)
#define ADCSOCCTL10_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL10_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL11     SAMPCNT
 *  @access     ADC->ADCSOCCTL11.bit.SAMPCNT
 *  @brief      Select SOC9 sample window size
 */
#define ADCSOCCTL11_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL11_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL11_ALL_SAMPCNT_Pos)

#define ADCSOCCTL11_BIT_SAMPCNT

#define ADCSOCCTL11_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL11_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL11     CONVCNT
 *  @access     ADC->ADCSOCCTL11.bit.CONVCNT
 *  @brief      Select SOC9 convert window size
 */
#define ADCSOCCTL11_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL11_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL11_ALL_CONVCNT_Pos)

#define ADCSOCCTL11_BIT_CONVCNT

#define ADCSOCCTL11_ALL_CONVCNT_(x) ((x) << ADCSOCCTL11_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL11     AVGCNT
 *  @access     ADC->ADCSOCCTL11.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL11_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL11_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL11_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL11_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL11_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL11_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL11_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL11_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL11_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL11_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL11_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL11_BIT_AVGCNT;

#define ADCSOCCTL11_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL11_ALL_AVGCNT_Pos)
#define ADCSOCCTL11_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL11_ALL_AVGCNT_Pos)
#define ADCSOCCTL11_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL11_ALL_AVGCNT_Pos)
#define ADCSOCCTL11_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL11_ALL_AVGCNT_Pos)
#define ADCSOCCTL11_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL11_ALL_AVGCNT_Pos)
#define ADCSOCCTL11_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL11_ALL_AVGCNT_Pos)
#define ADCSOCCTL11_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL11_ALL_AVGCNT_Pos)
#define ADCSOCCTL11_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL11_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL11     CHSELP
 *  @access     ADC->ADCSOCCTL11.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC11
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL9[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC9
 */
#define ADCSOCCTL11_ALL_CHSELP_Pos (18)
#define ADCSOCCTL11_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL11_ALL_CHSELP_Pos)

#define ADCSOCCTL11_BIT_CHSELP

#define ADCSOCCTL11_ALL_CHSELP_(x) ((x) << ADCSOCCTL11_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL11     CHSELN
 *  @access     ADC->ADCSOCCTL11.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC11
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL9[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC9
 */
#define ADCSOCCTL11_ALL_CHSELN_Pos (21)
#define ADCSOCCTL11_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL11_ALL_CHSELN_Pos)

#define ADCSOCCTL11_BIT_CHSELN

#define ADCSOCCTL11_ALL_CHSELN_(x) ((x) << ADCSOCCTL11_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL11     TRIGSEL
 *  @access     ADC->ADCSOCCTL11.bit.TRIGSEL
 *  @brief      Select SOC11 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC11]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC11. This setting can be
 *              overridden by the ADCINTSOCSEL1[SOC11].
 *              This field is not used when ADCSOCCTL9[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL11_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL11_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL11_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL11_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL11_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL11_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL11_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL11_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL11_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL11_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL11_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL11_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL11_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL11_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL11_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL11_BIT_TRIGSEL;

#define ADCSOCCTL11_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)
#define ADCSOCCTL11_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL11_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL11     SHEN
 *  @access     ADC->ADCSOCCTL11.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL9[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL11_ALL_SHEN_Pos (29)
#define ADCSOCCTL11_ALL_SHEN_Msk (0x3UL << ADCSOCCTL11_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL11_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL11_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL11_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL11_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL11_BIT_SHEN;

#define ADCSOCCTL11_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL11_ALL_SHEN_Pos)
#define ADCSOCCTL11_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL11_ALL_SHEN_Pos)
#define ADCSOCCTL11_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL11_ALL_SHEN_Pos)
#define ADCSOCCTL11_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL11_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL12     SAMPCNT
 *  @access     ADC->ADCSOCCTL12.bit.SAMPCNT
 *  @brief      Select SOC12 sample window size
 */
#define ADCSOCCTL12_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL12_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL12_ALL_SAMPCNT_Pos)

#define ADCSOCCTL12_BIT_SAMPCNT

#define ADCSOCCTL12_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL12_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL12     CONVCNT
 *  @access     ADC->ADCSOCCTL12.bit.CONVCNT
 *  @brief      Select SOC12 convert window size
 */
#define ADCSOCCTL12_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL12_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL12_ALL_CONVCNT_Pos)

#define ADCSOCCTL12_BIT_CONVCNT

#define ADCSOCCTL12_ALL_CONVCNT_(x) ((x) << ADCSOCCTL12_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL12     AVGCNT
 *  @access     ADC->ADCSOCCTL12.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL12_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL12_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL12_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL12_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL12_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL12_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL12_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL12_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL12_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL12_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL12_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL12_BIT_AVGCNT;

#define ADCSOCCTL12_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL12_ALL_AVGCNT_Pos)
#define ADCSOCCTL12_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL12_ALL_AVGCNT_Pos)
#define ADCSOCCTL12_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL12_ALL_AVGCNT_Pos)
#define ADCSOCCTL12_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL12_ALL_AVGCNT_Pos)
#define ADCSOCCTL12_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL12_ALL_AVGCNT_Pos)
#define ADCSOCCTL12_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL12_ALL_AVGCNT_Pos)
#define ADCSOCCTL12_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL12_ALL_AVGCNT_Pos)
#define ADCSOCCTL12_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL12_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL12     CHSELP
 *  @access     ADC->ADCSOCCTL12.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC12
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL12_ALL_CHSELP_Pos (18)
#define ADCSOCCTL12_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL12_ALL_CHSELP_Pos)

#define ADCSOCCTL12_BIT_CHSELP

#define ADCSOCCTL12_ALL_CHSELP_(x) ((x) << ADCSOCCTL12_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL12     CHSELN
 *  @access     ADC->ADCSOCCTL12.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC12
 *              When SHEN=1, 4, 6 or 7, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When SHEN=5, this field is not used.
 */
#define ADCSOCCTL12_ALL_CHSELN_Pos (21)
#define ADCSOCCTL12_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL12_ALL_CHSELN_Pos)

#define ADCSOCCTL12_BIT_CHSELN

#define ADCSOCCTL12_ALL_CHSELN_(x) ((x) << ADCSOCCTL12_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL12     TRIGSEL
 *  @access     ADC->ADCSOCCTL12.bit.TRIGSEL
 *  @brief      Select SOC12 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC12]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC12. This setting can be
 *              overridden by the ADCINTSOCSEL1[SOC12].
 */
#define ADCSOCCTL12_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL12_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL12_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL12_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL12_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL12_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL12_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL12_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL12_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL12_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL12_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL12_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL12_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL12_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL12_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL12_BIT_TRIGSEL;

#define ADCSOCCTL12_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)
#define ADCSOCCTL12_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL12_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL12     SHEN
 *  @access     ADC->ADCSOCCTL12.bit.SHEN
 *  @brief      SH enable
 */
#define ADCSOCCTL12_ALL_SHEN_Pos (29)
#define ADCSOCCTL12_ALL_SHEN_Msk (0x7UL << ADCSOCCTL12_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL12_BIT_SHEN_DISABLE                 = 0,  /*!< Disable all SHs                       */
    ADCSOCCTL12_BIT_SHEN_SHA                     = 1,  /*!< Enable SHA                            */
    ADCSOCCTL12_BIT_SHEN_SHB                     = 2,  /*!< Enable SHB                            */
    ADCSOCCTL12_BIT_SHEN_SHC                     = 3,  /*!< Enable SHC                            */
    ADCSOCCTL12_BIT_SHEN_SHA_AND_SHB             = 4,  /*!< Enable SHA and SHB simultaneously     */
    ADCSOCCTL12_BIT_SHEN_SHB_AND_SHC             = 5,  /*!< Enable SHB and SHC simultaneously     */
    ADCSOCCTL12_BIT_SHEN_SHA_AND_SHC             = 6,  /*!< Enable SHA and SHC simultaneously     */
    ADCSOCCTL12_BIT_SHEN_SHA_AND_SHB_AND_SHC     = 7,  /*!< Enable SHA, SHB, SHC simultaneously   */
} ADCSOCCTL12_BIT_SHEN;

#define ADCSOCCTL12_ALL_SHEN_DISABLE                 ((0x0UL) << ADCSOCCTL12_ALL_SHEN_Pos)
#define ADCSOCCTL12_ALL_SHEN_SHA                     ((0x1UL) << ADCSOCCTL12_ALL_SHEN_Pos)
#define ADCSOCCTL12_ALL_SHEN_SHB                     ((0x2UL) << ADCSOCCTL12_ALL_SHEN_Pos)
#define ADCSOCCTL12_ALL_SHEN_SHC                     ((0x3UL) << ADCSOCCTL12_ALL_SHEN_Pos)
#define ADCSOCCTL12_ALL_SHEN_SHA_AND_SHB             ((0x4UL) << ADCSOCCTL12_ALL_SHEN_Pos)
#define ADCSOCCTL12_ALL_SHEN_SHB_AND_SHC             ((0x5UL) << ADCSOCCTL12_ALL_SHEN_Pos)
#define ADCSOCCTL12_ALL_SHEN_SHA_AND_SHC             ((0x6UL) << ADCSOCCTL12_ALL_SHEN_Pos)
#define ADCSOCCTL12_ALL_SHEN_SHA_AND_SHB_AND_SHC     ((0x7UL) << ADCSOCCTL12_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL13     SAMPCNT
 *  @access     ADC->ADCSOCCTL13.bit.SAMPCNT
 *  @brief      Select SOC13 sample window size
 */
#define ADCSOCCTL13_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL13_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL13_ALL_SAMPCNT_Pos)

#define ADCSOCCTL13_BIT_SAMPCNT

#define ADCSOCCTL13_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL13_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL13     CONVCNT
 *  @access     ADC->ADCSOCCTL13.bit.CONVCNT
 *  @brief      Select SOC13 convert window size
 */
#define ADCSOCCTL13_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL13_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL13_ALL_CONVCNT_Pos)

#define ADCSOCCTL13_BIT_CONVCNT

#define ADCSOCCTL13_ALL_CONVCNT_(x) ((x) << ADCSOCCTL13_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL13     AVGCNT
 *  @access     ADC->ADCSOCCTL13.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL13_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL13_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL13_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL13_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL13_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL13_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL13_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL13_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL13_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL13_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL13_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL13_BIT_AVGCNT;

#define ADCSOCCTL13_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL13_ALL_AVGCNT_Pos)
#define ADCSOCCTL13_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL13_ALL_AVGCNT_Pos)
#define ADCSOCCTL13_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL13_ALL_AVGCNT_Pos)
#define ADCSOCCTL13_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL13_ALL_AVGCNT_Pos)
#define ADCSOCCTL13_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL13_ALL_AVGCNT_Pos)
#define ADCSOCCTL13_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL13_ALL_AVGCNT_Pos)
#define ADCSOCCTL13_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL13_ALL_AVGCNT_Pos)
#define ADCSOCCTL13_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL13_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL13     CHSELP
 *  @access     ADC->ADCSOCCTL13.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC13
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL12[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC12
 */
#define ADCSOCCTL13_ALL_CHSELP_Pos (18)
#define ADCSOCCTL13_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL13_ALL_CHSELP_Pos)

#define ADCSOCCTL13_BIT_CHSELP

#define ADCSOCCTL13_ALL_CHSELP_(x) ((x) << ADCSOCCTL13_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL13     CHSELN
 *  @access     ADC->ADCSOCCTL13.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC13
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL12[SHEN] is set to 4, 5 or 7, SHB is controlled for SOC12
 */
#define ADCSOCCTL13_ALL_CHSELN_Pos (21)
#define ADCSOCCTL13_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL13_ALL_CHSELN_Pos)

#define ADCSOCCTL13_BIT_CHSELN

#define ADCSOCCTL13_ALL_CHSELN_(x) ((x) << ADCSOCCTL13_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL13     TRIGSEL
 *  @access     ADC->ADCSOCCTL13.bit.TRIGSEL
 *  @brief      Select SOC13 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC13]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC13. This setting can be
 *              overridden by the ADCINTSOCSEL1[SOC13].
 *              This field is not used when ADCSOCCTL12[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL13_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL13_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL13_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL13_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL13_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL13_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL13_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL13_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL13_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL13_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL13_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL13_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL13_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL13_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL13_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL13_BIT_TRIGSEL;

#define ADCSOCCTL13_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)
#define ADCSOCCTL13_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL13_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL13     SHEN
 *  @access     ADC->ADCSOCCTL13.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL12[SHEN] is set to 4,5 or 7.
 */
#define ADCSOCCTL13_ALL_SHEN_Pos (29)
#define ADCSOCCTL13_ALL_SHEN_Msk (0x3UL << ADCSOCCTL13_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL13_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL13_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL13_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL13_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL13_BIT_SHEN;

#define ADCSOCCTL13_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL13_ALL_SHEN_Pos)
#define ADCSOCCTL13_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL13_ALL_SHEN_Pos)
#define ADCSOCCTL13_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL13_ALL_SHEN_Pos)
#define ADCSOCCTL13_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL13_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL14     SAMPCNT
 *  @access     ADC->ADCSOCCTL14.bit.SAMPCNT
 *  @brief      Select SOC14 sample window size
 */
#define ADCSOCCTL14_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL14_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL14_ALL_SAMPCNT_Pos)

#define ADCSOCCTL14_BIT_SAMPCNT

#define ADCSOCCTL14_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL14_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL14     CONVCNT
 *  @access     ADC->ADCSOCCTL14.bit.CONVCNT
 *  @brief      Select SOC14 convert window size
 */
#define ADCSOCCTL14_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL14_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL14_ALL_CONVCNT_Pos)

#define ADCSOCCTL14_BIT_CONVCNT

#define ADCSOCCTL14_ALL_CONVCNT_(x) ((x) << ADCSOCCTL14_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL14     AVGCNT
 *  @access     ADC->ADCSOCCTL14.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL14_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL14_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL14_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL14_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL14_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL14_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL14_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL14_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL14_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL14_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL14_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL14_BIT_AVGCNT;

#define ADCSOCCTL14_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL14_ALL_AVGCNT_Pos)
#define ADCSOCCTL14_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL14_ALL_AVGCNT_Pos)
#define ADCSOCCTL14_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL14_ALL_AVGCNT_Pos)
#define ADCSOCCTL14_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL14_ALL_AVGCNT_Pos)
#define ADCSOCCTL14_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL14_ALL_AVGCNT_Pos)
#define ADCSOCCTL14_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL14_ALL_AVGCNT_Pos)
#define ADCSOCCTL14_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL14_ALL_AVGCNT_Pos)
#define ADCSOCCTL14_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL14_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL14     CHSELP
 *  @access     ADC->ADCSOCCTL14.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC14
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL12[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC12
 */
#define ADCSOCCTL14_ALL_CHSELP_Pos (18)
#define ADCSOCCTL14_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL14_ALL_CHSELP_Pos)

#define ADCSOCCTL14_BIT_CHSELP

#define ADCSOCCTL14_ALL_CHSELP_(x) ((x) << ADCSOCCTL14_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL14     CHSELN
 *  @access     ADC->ADCSOCCTL14.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC14
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 *              When ADCSOCCTL12[SHEN] is set to 5, 6 or 7, SHC is controlled for SOC12
 */
#define ADCSOCCTL14_ALL_CHSELN_Pos (21)
#define ADCSOCCTL14_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL14_ALL_CHSELN_Pos)

#define ADCSOCCTL14_BIT_CHSELN

#define ADCSOCCTL14_ALL_CHSELN_(x) ((x) << ADCSOCCTL14_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL14     TRIGSEL
 *  @access     ADC->ADCSOCCTL14.bit.TRIGSEL
 *  @brief      Select SOC14 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC14]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC14. This setting can be
 *              overridden by the ADCINTSOCSEL1[SOC14].
 *              This field is not used when ADCSOCCTL12[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL14_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL14_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL14_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL14_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL14_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL14_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL14_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL14_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL14_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL14_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL14_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL14_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL14_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL14_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL14_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL14_BIT_TRIGSEL;

#define ADCSOCCTL14_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)
#define ADCSOCCTL14_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL14_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL14     SHEN
 *  @access     ADC->ADCSOCCTL14.bit.SHEN
 *  @brief      SH enable
 *              This field is not used when ADCSOCCTL12[SHEN] is set to 5,6 or 7.
 */
#define ADCSOCCTL14_ALL_SHEN_Pos (29)
#define ADCSOCCTL14_ALL_SHEN_Msk (0x3UL << ADCSOCCTL14_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL14_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL14_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL14_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL14_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL14_BIT_SHEN;

#define ADCSOCCTL14_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL14_ALL_SHEN_Pos)
#define ADCSOCCTL14_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL14_ALL_SHEN_Pos)
#define ADCSOCCTL14_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL14_ALL_SHEN_Pos)
#define ADCSOCCTL14_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL14_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL15     SAMPCNT
 *  @access     ADC->ADCSOCCTL15.bit.SAMPCNT
 *  @brief      Select SOC15 sample window size
 */
#define ADCSOCCTL15_ALL_SAMPCNT_Pos (0)
#define ADCSOCCTL15_ALL_SAMPCNT_Msk (0xFFUL << ADCSOCCTL15_ALL_SAMPCNT_Pos)

#define ADCSOCCTL15_BIT_SAMPCNT

#define ADCSOCCTL15_ALL_SAMPCNT_(x) ((x) << ADCSOCCTL15_ALL_SAMPCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL15     CONVCNT
 *  @access     ADC->ADCSOCCTL15.bit.CONVCNT
 *  @brief      Select SOC15 convert window size
 */
#define ADCSOCCTL15_ALL_CONVCNT_Pos (8)
#define ADCSOCCTL15_ALL_CONVCNT_Msk (0x7FUL << ADCSOCCTL15_ALL_CONVCNT_Pos)

#define ADCSOCCTL15_BIT_CONVCNT

#define ADCSOCCTL15_ALL_CONVCNT_(x) ((x) << ADCSOCCTL15_ALL_CONVCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL15     AVGCNT
 *  @access     ADC->ADCSOCCTL15.bit.AVGCNT
 *  @brief      Select average counts for the ADC result
 */
#define ADCSOCCTL15_ALL_AVGCNT_Pos (15)
#define ADCSOCCTL15_ALL_AVGCNT_Msk (0x7UL << ADCSOCCTL15_ALL_AVGCNT_Pos)

typedef enum
{
    ADCSOCCTL15_BIT_AVGCNT_NO_AVG      = 0,  /*!< No average                                                              */
    ADCSOCCTL15_BIT_AVGCNT_AVG_2       = 1,  /*!< Each SOC will trigger 2 consecutive ADC operations and then average     */
    ADCSOCCTL15_BIT_AVGCNT_AVG_4       = 2,  /*!< Each SOC will trigger 4 consecutive ADC operations and then average     */
    ADCSOCCTL15_BIT_AVGCNT_AVG_8       = 3,  /*!< Each SOC will trigger 8 consecutive ADC operations and then average     */
    ADCSOCCTL15_BIT_AVGCNT_AVG_16      = 4,  /*!< Each SOC will trigger 16 consecutive ADC operations and then average    */
    ADCSOCCTL15_BIT_AVGCNT_AVG_32      = 5,  /*!< Each SOC will trigger 32 consecutive ADC operations and then average    */
    ADCSOCCTL15_BIT_AVGCNT_AVG_64      = 6,  /*!< Each SOC will trigger 64 consecutive ADC operations and then average    */
    ADCSOCCTL15_BIT_AVGCNT_AVG_128     = 7,  /*!< Each SOC will trigger 128 consecutive ADC operations and then average   */
} ADCSOCCTL15_BIT_AVGCNT;

#define ADCSOCCTL15_ALL_AVGCNT_NO_AVG      ((0x0UL) << ADCSOCCTL15_ALL_AVGCNT_Pos)
#define ADCSOCCTL15_ALL_AVGCNT_AVG_2       ((0x1UL) << ADCSOCCTL15_ALL_AVGCNT_Pos)
#define ADCSOCCTL15_ALL_AVGCNT_AVG_4       ((0x2UL) << ADCSOCCTL15_ALL_AVGCNT_Pos)
#define ADCSOCCTL15_ALL_AVGCNT_AVG_8       ((0x3UL) << ADCSOCCTL15_ALL_AVGCNT_Pos)
#define ADCSOCCTL15_ALL_AVGCNT_AVG_16      ((0x4UL) << ADCSOCCTL15_ALL_AVGCNT_Pos)
#define ADCSOCCTL15_ALL_AVGCNT_AVG_32      ((0x5UL) << ADCSOCCTL15_ALL_AVGCNT_Pos)
#define ADCSOCCTL15_ALL_AVGCNT_AVG_64      ((0x6UL) << ADCSOCCTL15_ALL_AVGCNT_Pos)
#define ADCSOCCTL15_ALL_AVGCNT_AVG_128     ((0x7UL) << ADCSOCCTL15_ALL_AVGCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL15     CHSELP
 *  @access     ADC->ADCSOCCTL15.bit.CHSELP
 *  @brief      Select channel to positive terminal of SH for SOC15
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 */
#define ADCSOCCTL15_ALL_CHSELP_Pos (18)
#define ADCSOCCTL15_ALL_CHSELP_Msk (0x7UL << ADCSOCCTL15_ALL_CHSELP_Pos)

#define ADCSOCCTL15_BIT_CHSELP

#define ADCSOCCTL15_ALL_CHSELP_(x) ((x) << ADCSOCCTL15_ALL_CHSELP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL15     CHSELN
 *  @access     ADC->ADCSOCCTL15.bit.CHSELN
 *  @brief      Select channel to negative terminal of SH for SOC15
 *              When SHEN=1, SHA is controlled.
 *              When SHEN=2, SHB is controlled.
 *              When SHEN=3, SHC is controlled.
 */
#define ADCSOCCTL15_ALL_CHSELN_Pos (21)
#define ADCSOCCTL15_ALL_CHSELN_Msk (0x7UL << ADCSOCCTL15_ALL_CHSELN_Pos)

#define ADCSOCCTL15_BIT_CHSELN

#define ADCSOCCTL15_ALL_CHSELN_(x) ((x) << ADCSOCCTL15_ALL_CHSELN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL15     TRIGSEL
 *  @access     ADC->ADCSOCCTL15.bit.TRIGSEL
 *  @brief      Select SOC15 Trigger Source
 *              Configures which trigger source will set ADCSOCFLG[SOC15]. The flag will initiate
 *              a conversion to start once and the priority is given to SOC15. This setting can be
 *              overridden by the ADCINTSOCSEL1[SOC15].
 */
#define ADCSOCCTL15_ALL_TRIGSEL_Pos (24)
#define ADCSOCCTL15_ALL_TRIGSEL_Msk (0x1FUL << ADCSOCCTL15_ALL_TRIGSEL_Pos)

typedef enum
{
    ADCSOCCTL15_BIT_TRIGSEL_SOFTWARE     = 0,  /*!< ADCTRIG0 - Software only   */
    ADCSOCCTL15_BIT_TRIGSEL_TIMER0       = 1,  /*!< ADCTRIG1 - CPU Timer 0     */
    ADCSOCCTL15_BIT_TRIGSEL_TIMER1       = 2,  /*!< ADCTRIG2 - CPU Timer 1     */
    ADCSOCCTL15_BIT_TRIGSEL_TIMER2       = 3,  /*!< ADCTRIG3 - CPU Timer 2     */
    ADCSOCCTL15_BIT_TRIGSEL_EXTSOC       = 4,  /*!< ADCTRIG4 - EXTSOC          */
    ADCSOCCTL15_BIT_TRIGSEL_PWM0SOCA     = 5,  /*!< ADCTRIG5 - PWM0SOCA        */
    ADCSOCCTL15_BIT_TRIGSEL_PWM0SOCB     = 6,  /*!< ADCTRIG6 - PWM0SOCB        */
    ADCSOCCTL15_BIT_TRIGSEL_PWM0SOCC     = 7,  /*!< ADCTRIG7 - PWM0SOCC        */
    ADCSOCCTL15_BIT_TRIGSEL_PWM1SOCA     = 8,  /*!< ADCTRIG8 - PWM1SOCA        */
    ADCSOCCTL15_BIT_TRIGSEL_PWM1SOCB     = 9,  /*!< ADCTRIG9 - PWM1SOCB        */
    ADCSOCCTL15_BIT_TRIGSEL_PWM1SOCC     = 10,  /*!< ADCTRIG10 - PWM1SOCC       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM2SOCA     = 11,  /*!< ADCTRIG11 - PWM2SOCA       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM2SOCB     = 12,  /*!< ADCTRIG12 - PWM2SOCB       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM2SOCC     = 13,  /*!< ADCTRIG13 - PWM2SOCC       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM3SOCA     = 14,  /*!< ADCTRIG14 - PWM3SOCA       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM3SOCB     = 15,  /*!< ADCTRIG15 - PWM3SOCB       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM3SOCC     = 16,  /*!< ADCTRIG16 - PWM3SOCC       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM4SOCA     = 17,  /*!< ADCTRIG17 - PWM4SOCA       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM4SOCB     = 18,  /*!< ADCTRIG18 - PWM4SOCB       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM4SOCC     = 19,  /*!< ADCTRIG19 - PWM4SOCC       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM5SOCA     = 20,  /*!< ADCTRIG20 - PWM5SOCA       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM5SOCB     = 21,  /*!< ADCTRIG21 - PWM5SOCB       */
    ADCSOCCTL15_BIT_TRIGSEL_PWM5SOCC     = 22,  /*!< ADCTRIG22 - PWM5SOCC       */
} ADCSOCCTL15_BIT_TRIGSEL;

#define ADCSOCCTL15_ALL_TRIGSEL_SOFTWARE     ((0x00UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_TIMER0       ((0x01UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_TIMER1       ((0x02UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_TIMER2       ((0x03UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_EXTSOC       ((0x04UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM0SOCA     ((0x05UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM0SOCB     ((0x06UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM0SOCC     ((0x07UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM1SOCA     ((0x08UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM1SOCB     ((0x09UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM1SOCC     ((0x0AUL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM2SOCA     ((0x0BUL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM2SOCB     ((0x0CUL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM2SOCC     ((0x0DUL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM3SOCA     ((0x0EUL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM3SOCB     ((0x0FUL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM3SOCC     ((0x10UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM4SOCA     ((0x11UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM4SOCB     ((0x12UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM4SOCC     ((0x13UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM5SOCA     ((0x14UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM5SOCB     ((0x15UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)
#define ADCSOCCTL15_ALL_TRIGSEL_PWM5SOCC     ((0x16UL) << ADCSOCCTL15_ALL_TRIGSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSOCCTL15     SHEN
 *  @access     ADC->ADCSOCCTL15.bit.SHEN
 *  @brief      SH enable.
 */
#define ADCSOCCTL15_ALL_SHEN_Pos (29)
#define ADCSOCCTL15_ALL_SHEN_Msk (0x3UL << ADCSOCCTL15_ALL_SHEN_Pos)

typedef enum
{
    ADCSOCCTL15_BIT_SHEN_DISABLE     = 0,  /*!< Disable all SHs   */
    ADCSOCCTL15_BIT_SHEN_SHA         = 1,  /*!< Enable SHA        */
    ADCSOCCTL15_BIT_SHEN_SHB         = 2,  /*!< Enable SHB        */
    ADCSOCCTL15_BIT_SHEN_SHC         = 3,  /*!< Enable SHC        */
} ADCSOCCTL15_BIT_SHEN;

#define ADCSOCCTL15_ALL_SHEN_DISABLE     ((0x0UL) << ADCSOCCTL15_ALL_SHEN_Pos)
#define ADCSOCCTL15_ALL_SHEN_SHA         ((0x1UL) << ADCSOCCTL15_ALL_SHEN_Pos)
#define ADCSOCCTL15_ALL_SHEN_SHB         ((0x2UL) << ADCSOCCTL15_ALL_SHEN_Pos)
#define ADCSOCCTL15_ALL_SHEN_SHC         ((0x3UL) << ADCSOCCTL15_ALL_SHEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET0      VAL
 *  @access     ADC->ADCOFFSET0.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT0
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET0_ALL_VAL_Pos (0)
#define ADCOFFSET0_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET0_ALL_VAL_Pos)

#define ADCOFFSET0_BIT_VAL

#define ADCOFFSET0_ALL_VAL_(x) ((x) << ADCOFFSET0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET1      VAL
 *  @access     ADC->ADCOFFSET1.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT1
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET1_ALL_VAL_Pos (0)
#define ADCOFFSET1_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET1_ALL_VAL_Pos)

#define ADCOFFSET1_BIT_VAL

#define ADCOFFSET1_ALL_VAL_(x) ((x) << ADCOFFSET1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET2      VAL
 *  @access     ADC->ADCOFFSET2.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT2
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET2_ALL_VAL_Pos (0)
#define ADCOFFSET2_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET2_ALL_VAL_Pos)

#define ADCOFFSET2_BIT_VAL

#define ADCOFFSET2_ALL_VAL_(x) ((x) << ADCOFFSET2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET3      VAL
 *  @access     ADC->ADCOFFSET3.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT3
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET3_ALL_VAL_Pos (0)
#define ADCOFFSET3_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET3_ALL_VAL_Pos)

#define ADCOFFSET3_BIT_VAL

#define ADCOFFSET3_ALL_VAL_(x) ((x) << ADCOFFSET3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET4      VAL
 *  @access     ADC->ADCOFFSET4.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT4
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET4_ALL_VAL_Pos (0)
#define ADCOFFSET4_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET4_ALL_VAL_Pos)

#define ADCOFFSET4_BIT_VAL

#define ADCOFFSET4_ALL_VAL_(x) ((x) << ADCOFFSET4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET5      VAL
 *  @access     ADC->ADCOFFSET5.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT5
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET5_ALL_VAL_Pos (0)
#define ADCOFFSET5_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET5_ALL_VAL_Pos)

#define ADCOFFSET5_BIT_VAL

#define ADCOFFSET5_ALL_VAL_(x) ((x) << ADCOFFSET5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET6      VAL
 *  @access     ADC->ADCOFFSET6.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT6
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET6_ALL_VAL_Pos (0)
#define ADCOFFSET6_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET6_ALL_VAL_Pos)

#define ADCOFFSET6_BIT_VAL

#define ADCOFFSET6_ALL_VAL_(x) ((x) << ADCOFFSET6_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET7      VAL
 *  @access     ADC->ADCOFFSET7.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT7
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET7_ALL_VAL_Pos (0)
#define ADCOFFSET7_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET7_ALL_VAL_Pos)

#define ADCOFFSET7_BIT_VAL

#define ADCOFFSET7_ALL_VAL_(x) ((x) << ADCOFFSET7_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET8      VAL
 *  @access     ADC->ADCOFFSET8.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT8
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET8_ALL_VAL_Pos (0)
#define ADCOFFSET8_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET8_ALL_VAL_Pos)

#define ADCOFFSET8_BIT_VAL

#define ADCOFFSET8_ALL_VAL_(x) ((x) << ADCOFFSET8_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET9      VAL
 *  @access     ADC->ADCOFFSET9.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT9
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET9_ALL_VAL_Pos (0)
#define ADCOFFSET9_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET9_ALL_VAL_Pos)

#define ADCOFFSET9_BIT_VAL

#define ADCOFFSET9_ALL_VAL_(x) ((x) << ADCOFFSET9_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET10     VAL
 *  @access     ADC->ADCOFFSET10.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT10
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET10_ALL_VAL_Pos (0)
#define ADCOFFSET10_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET10_ALL_VAL_Pos)

#define ADCOFFSET10_BIT_VAL

#define ADCOFFSET10_ALL_VAL_(x) ((x) << ADCOFFSET10_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET11     VAL
 *  @access     ADC->ADCOFFSET11.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT11
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET11_ALL_VAL_Pos (0)
#define ADCOFFSET11_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET11_ALL_VAL_Pos)

#define ADCOFFSET11_BIT_VAL

#define ADCOFFSET11_ALL_VAL_(x) ((x) << ADCOFFSET11_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET12     VAL
 *  @access     ADC->ADCOFFSET12.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT12
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET12_ALL_VAL_Pos (0)
#define ADCOFFSET12_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET12_ALL_VAL_Pos)

#define ADCOFFSET12_BIT_VAL

#define ADCOFFSET12_ALL_VAL_(x) ((x) << ADCOFFSET12_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET13     VAL
 *  @access     ADC->ADCOFFSET13.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT13
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET13_ALL_VAL_Pos (0)
#define ADCOFFSET13_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET13_ALL_VAL_Pos)

#define ADCOFFSET13_BIT_VAL

#define ADCOFFSET13_ALL_VAL_(x) ((x) << ADCOFFSET13_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET14     VAL
 *  @access     ADC->ADCOFFSET14.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT14
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET14_ALL_VAL_Pos (0)
#define ADCOFFSET14_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET14_ALL_VAL_Pos)

#define ADCOFFSET14_BIT_VAL

#define ADCOFFSET14_ALL_VAL_(x) ((x) << ADCOFFSET14_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSET15     VAL
 *  @access     ADC->ADCOFFSET15.bit.VAL
 *  @brief      Offset trimming (signed number) for ADCRESULT15
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSET15_ALL_VAL_Pos (0)
#define ADCOFFSET15_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSET15_ALL_VAL_Pos)

#define ADCOFFSET15_BIT_VAL

#define ADCOFFSET15_ALL_VAL_(x) ((x) << ADCOFFSET15_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN0        VAL
 *  @access     ADC->ADCGAIN0.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT0
 */
#define ADCGAIN0_ALL_VAL_Pos (0)
#define ADCGAIN0_ALL_VAL_Msk (0xFFFFUL << ADCGAIN0_ALL_VAL_Pos)

#define ADCGAIN0_BIT_VAL

#define ADCGAIN0_ALL_VAL_(x) ((x) << ADCGAIN0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN1        VAL
 *  @access     ADC->ADCGAIN1.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT1
 */
#define ADCGAIN1_ALL_VAL_Pos (0)
#define ADCGAIN1_ALL_VAL_Msk (0xFFFFUL << ADCGAIN1_ALL_VAL_Pos)

#define ADCGAIN1_BIT_VAL

#define ADCGAIN1_ALL_VAL_(x) ((x) << ADCGAIN1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN2        VAL
 *  @access     ADC->ADCGAIN2.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT2
 */
#define ADCGAIN2_ALL_VAL_Pos (0)
#define ADCGAIN2_ALL_VAL_Msk (0xFFFFUL << ADCGAIN2_ALL_VAL_Pos)

#define ADCGAIN2_BIT_VAL

#define ADCGAIN2_ALL_VAL_(x) ((x) << ADCGAIN2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN3        VAL
 *  @access     ADC->ADCGAIN3.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT3
 */
#define ADCGAIN3_ALL_VAL_Pos (0)
#define ADCGAIN3_ALL_VAL_Msk (0xFFFFUL << ADCGAIN3_ALL_VAL_Pos)

#define ADCGAIN3_BIT_VAL

#define ADCGAIN3_ALL_VAL_(x) ((x) << ADCGAIN3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN4        VAL
 *  @access     ADC->ADCGAIN4.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT4
 */
#define ADCGAIN4_ALL_VAL_Pos (0)
#define ADCGAIN4_ALL_VAL_Msk (0xFFFFUL << ADCGAIN4_ALL_VAL_Pos)

#define ADCGAIN4_BIT_VAL

#define ADCGAIN4_ALL_VAL_(x) ((x) << ADCGAIN4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN5        VAL
 *  @access     ADC->ADCGAIN5.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT5
 */
#define ADCGAIN5_ALL_VAL_Pos (0)
#define ADCGAIN5_ALL_VAL_Msk (0xFFFFUL << ADCGAIN5_ALL_VAL_Pos)

#define ADCGAIN5_BIT_VAL

#define ADCGAIN5_ALL_VAL_(x) ((x) << ADCGAIN5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN6        VAL
 *  @access     ADC->ADCGAIN6.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT6
 */
#define ADCGAIN6_ALL_VAL_Pos (0)
#define ADCGAIN6_ALL_VAL_Msk (0xFFFFUL << ADCGAIN6_ALL_VAL_Pos)

#define ADCGAIN6_BIT_VAL

#define ADCGAIN6_ALL_VAL_(x) ((x) << ADCGAIN6_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN7        VAL
 *  @access     ADC->ADCGAIN7.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT7
 */
#define ADCGAIN7_ALL_VAL_Pos (0)
#define ADCGAIN7_ALL_VAL_Msk (0xFFFFUL << ADCGAIN7_ALL_VAL_Pos)

#define ADCGAIN7_BIT_VAL

#define ADCGAIN7_ALL_VAL_(x) ((x) << ADCGAIN7_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN8        VAL
 *  @access     ADC->ADCGAIN8.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT8
 */
#define ADCGAIN8_ALL_VAL_Pos (0)
#define ADCGAIN8_ALL_VAL_Msk (0xFFFFUL << ADCGAIN8_ALL_VAL_Pos)

#define ADCGAIN8_BIT_VAL

#define ADCGAIN8_ALL_VAL_(x) ((x) << ADCGAIN8_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN9        VAL
 *  @access     ADC->ADCGAIN9.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT9
 */
#define ADCGAIN9_ALL_VAL_Pos (0)
#define ADCGAIN9_ALL_VAL_Msk (0xFFFFUL << ADCGAIN9_ALL_VAL_Pos)

#define ADCGAIN9_BIT_VAL

#define ADCGAIN9_ALL_VAL_(x) ((x) << ADCGAIN9_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN10       VAL
 *  @access     ADC->ADCGAIN10.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT10
 */
#define ADCGAIN10_ALL_VAL_Pos (0)
#define ADCGAIN10_ALL_VAL_Msk (0xFFFFUL << ADCGAIN10_ALL_VAL_Pos)

#define ADCGAIN10_BIT_VAL

#define ADCGAIN10_ALL_VAL_(x) ((x) << ADCGAIN10_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN11       VAL
 *  @access     ADC->ADCGAIN11.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT11
 */
#define ADCGAIN11_ALL_VAL_Pos (0)
#define ADCGAIN11_ALL_VAL_Msk (0xFFFFUL << ADCGAIN11_ALL_VAL_Pos)

#define ADCGAIN11_BIT_VAL

#define ADCGAIN11_ALL_VAL_(x) ((x) << ADCGAIN11_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN12       VAL
 *  @access     ADC->ADCGAIN12.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT12
 */
#define ADCGAIN12_ALL_VAL_Pos (0)
#define ADCGAIN12_ALL_VAL_Msk (0xFFFFUL << ADCGAIN12_ALL_VAL_Pos)

#define ADCGAIN12_BIT_VAL

#define ADCGAIN12_ALL_VAL_(x) ((x) << ADCGAIN12_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN13       VAL
 *  @access     ADC->ADCGAIN13.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT13
 */
#define ADCGAIN13_ALL_VAL_Pos (0)
#define ADCGAIN13_ALL_VAL_Msk (0xFFFFUL << ADCGAIN13_ALL_VAL_Pos)

#define ADCGAIN13_BIT_VAL

#define ADCGAIN13_ALL_VAL_(x) ((x) << ADCGAIN13_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN14       VAL
 *  @access     ADC->ADCGAIN14.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT14
 */
#define ADCGAIN14_ALL_VAL_Pos (0)
#define ADCGAIN14_ALL_VAL_Msk (0xFFFFUL << ADCGAIN14_ALL_VAL_Pos)

#define ADCGAIN14_BIT_VAL

#define ADCGAIN14_ALL_VAL_(x) ((x) << ADCGAIN14_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAIN15       VAL
 *  @access     ADC->ADCGAIN15.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for ADCRESULT15
 */
#define ADCGAIN15_ALL_VAL_Pos (0)
#define ADCGAIN15_ALL_VAL_Msk (0xFFFFUL << ADCGAIN15_ALL_VAL_Pos)

#define ADCGAIN15_BIT_VAL

#define ADCGAIN15_ALL_VAL_(x) ((x) << ADCGAIN15_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSETA      VAL
 *  @access     ADC->ADCOFFSETA.bit.VAL
 *  @brief      Offset trimming (signed number) for SHA
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSETA_ALL_VAL_Pos (0)
#define ADCOFFSETA_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSETA_ALL_VAL_Pos)

#define ADCOFFSETA_BIT_VAL

#define ADCOFFSETA_ALL_VAL_(x) ((x) << ADCOFFSETA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSETB      VAL
 *  @access     ADC->ADCOFFSETB.bit.VAL
 *  @brief      Offset trimming (signed number) for SHB
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSETB_ALL_VAL_Pos (0)
#define ADCOFFSETB_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSETB_ALL_VAL_Pos)

#define ADCOFFSETB_BIT_VAL

#define ADCOFFSETB_ALL_VAL_(x) ((x) << ADCOFFSETB_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCOFFSETC      VAL
 *  @access     ADC->ADCOFFSETC.bit.VAL
 *  @brief      Offset trimming (signed number) for SHC
 *              Should be within [-8192, 8191]
 */
#define ADCOFFSETC_ALL_VAL_Pos (0)
#define ADCOFFSETC_ALL_VAL_Msk (0xFFFFFFFFUL << ADCOFFSETC_ALL_VAL_Pos)

#define ADCOFFSETC_BIT_VAL

#define ADCOFFSETC_ALL_VAL_(x) ((x) << ADCOFFSETC_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAINA        VAL
 *  @access     ADC->ADCGAINA.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for SHA
 */
#define ADCGAINA_ALL_VAL_Pos (0)
#define ADCGAINA_ALL_VAL_Msk (0xFFFFUL << ADCGAINA_ALL_VAL_Pos)

#define ADCGAINA_BIT_VAL

#define ADCGAINA_ALL_VAL_(x) ((x) << ADCGAINA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAINB        VAL
 *  @access     ADC->ADCGAINB.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for SHB
 */
#define ADCGAINB_ALL_VAL_Pos (0)
#define ADCGAINB_ALL_VAL_Msk (0xFFFFUL << ADCGAINB_ALL_VAL_Pos)

#define ADCGAINB_BIT_VAL

#define ADCGAINB_ALL_VAL_(x) ((x) << ADCGAINB_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCGAINC        VAL
 *  @access     ADC->ADCGAINC.bit.VAL
 *  @brief      Gain trimming (VAL/32768) for SHC
 */
#define ADCGAINC_ALL_VAL_Pos (0)
#define ADCGAINC_ALL_VAL_Msk (0xFFFFUL << ADCGAINC_ALL_VAL_Pos)

#define ADCGAINC_BIT_VAL

#define ADCGAINC_ALL_VAL_(x) ((x) << ADCGAINC_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSTS          CODEARDY
 *  @access     ADC->ADCSTS.bit.CODEARDY
 *  @brief      ADCRAWCODEA ready flag
 */
#define ADCSTS_ALL_CODEARDY_Pos (0)
#define ADCSTS_ALL_CODEARDY_Msk (0x1UL << ADCSTS_ALL_CODEARDY_Pos)

typedef enum
{
    ADCSTS_BIT_CODEARDY_NOT_READY     = 0,  /*!< ADCRAWCODEA not ready   */
    ADCSTS_BIT_CODEARDY_READY         = 1,  /*!< ADCRAWCODEA ready       */
} ADCSTS_BIT_CODEARDY;

#define ADCSTS_ALL_CODEARDY_NOT_READY     ((0x0UL) << ADCSTS_ALL_CODEARDY_Pos)
#define ADCSTS_ALL_CODEARDY_READY         ((0x1UL) << ADCSTS_ALL_CODEARDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSTS          CODEBRDY
 *  @access     ADC->ADCSTS.bit.CODEBRDY
 *  @brief      ADCRAWCODEB ready flag
 */
#define ADCSTS_ALL_CODEBRDY_Pos (1)
#define ADCSTS_ALL_CODEBRDY_Msk (0x1UL << ADCSTS_ALL_CODEBRDY_Pos)

typedef enum
{
    ADCSTS_BIT_CODEBRDY_NOT_READY     = 0,  /*!< ADCRAWCODEB not ready   */
    ADCSTS_BIT_CODEBRDY_READY         = 1,  /*!< ADCRAWCODEB ready       */
} ADCSTS_BIT_CODEBRDY;

#define ADCSTS_ALL_CODEBRDY_NOT_READY     ((0x0UL) << ADCSTS_ALL_CODEBRDY_Pos)
#define ADCSTS_ALL_CODEBRDY_READY         ((0x1UL) << ADCSTS_ALL_CODEBRDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSTS          CODECRDY
 *  @access     ADC->ADCSTS.bit.CODECRDY
 *  @brief      ADCRAWCODEC ready flag
 */
#define ADCSTS_ALL_CODECRDY_Pos (2)
#define ADCSTS_ALL_CODECRDY_Msk (0x1UL << ADCSTS_ALL_CODECRDY_Pos)

typedef enum
{
    ADCSTS_BIT_CODECRDY_NOT_READY     = 0,  /*!< ADCRAWCODEC not ready   */
    ADCSTS_BIT_CODECRDY_READY         = 1,  /*!< ADCRAWCODEC ready       */
} ADCSTS_BIT_CODECRDY;

#define ADCSTS_ALL_CODECRDY_NOT_READY     ((0x0UL) << ADCSTS_ALL_CODECRDY_Pos)
#define ADCSTS_ALL_CODECRDY_READY         ((0x1UL) << ADCSTS_ALL_CODECRDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSTSCLR       CODEARDY
 *  @access     ADC->ADCSTSCLR.bit.CODEARDY
 *  @brief      ADCRAWCODEA ready flag clear
 */
#define ADCSTSCLR_ALL_CODEARDY_Pos (0)
#define ADCSTSCLR_ALL_CODEARDY_Msk (0x1UL << ADCSTSCLR_ALL_CODEARDY_Pos)

typedef enum
{
    ADCSTSCLR_BIT_CODEARDY_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                     */
    ADCSTSCLR_BIT_CODEARDY_CLEAR         = 1,  /*!< Write a 1 clears ADCSTS[CODEARDY]. This bit is self-cleared.   */
} ADCSTSCLR_BIT_CODEARDY;

#define ADCSTSCLR_ALL_CODEARDY_NO_EFFECT     ((0x0UL) << ADCSTSCLR_ALL_CODEARDY_Pos)
#define ADCSTSCLR_ALL_CODEARDY_CLEAR         ((0x1UL) << ADCSTSCLR_ALL_CODEARDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSTSCLR       CODEBRDY
 *  @access     ADC->ADCSTSCLR.bit.CODEBRDY
 *  @brief      ADCRAWCODEB ready flag clear
 */
#define ADCSTSCLR_ALL_CODEBRDY_Pos (1)
#define ADCSTSCLR_ALL_CODEBRDY_Msk (0x1UL << ADCSTSCLR_ALL_CODEBRDY_Pos)

typedef enum
{
    ADCSTSCLR_BIT_CODEBRDY_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                     */
    ADCSTSCLR_BIT_CODEBRDY_CLEAR         = 1,  /*!< Write a 1 clears ADCSTS[CODEBRDY]. This bit is self-cleared.   */
} ADCSTSCLR_BIT_CODEBRDY;

#define ADCSTSCLR_ALL_CODEBRDY_NO_EFFECT     ((0x0UL) << ADCSTSCLR_ALL_CODEBRDY_Pos)
#define ADCSTSCLR_ALL_CODEBRDY_CLEAR         ((0x1UL) << ADCSTSCLR_ALL_CODEBRDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCSTSCLR       CODECRDY
 *  @access     ADC->ADCSTSCLR.bit.CODECRDY
 *  @brief      ADCRAWCODEC ready flag clear
 */
#define ADCSTSCLR_ALL_CODECRDY_Pos (2)
#define ADCSTSCLR_ALL_CODECRDY_Msk (0x1UL << ADCSTSCLR_ALL_CODECRDY_Pos)

typedef enum
{
    ADCSTSCLR_BIT_CODECRDY_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                     */
    ADCSTSCLR_BIT_CODECRDY_CLEAR         = 1,  /*!< Write a 1 clears ADCSTS[CODECRDY]. This bit is self-cleared.   */
} ADCSTSCLR_BIT_CODECRDY;

#define ADCSTSCLR_ALL_CODECRDY_NO_EFFECT     ((0x0UL) << ADCSTSCLR_ALL_CODECRDY_Pos)
#define ADCSTSCLR_ALL_CODECRDY_CLEAR         ((0x1UL) << ADCSTSCLR_ALL_CODECRDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          EN
 *  @access     ADC->ADCCTL.bit.EN
 *  @brief      ADC enable
 */
#define ADCCTL_ALL_EN_Pos (0)
#define ADCCTL_ALL_EN_Msk (0x1UL << ADCCTL_ALL_EN_Pos)

typedef enum
{
    ADCCTL_BIT_EN_DISABLE_ADC     = 0,  /*!< Disable ADC   */
    ADCCTL_BIT_EN_ENABLE_ADC      = 1,  /*!< Enable ADC    */
} ADCCTL_BIT_EN;

#define ADCCTL_ALL_EN_DISABLE_ADC     ((0x0UL) << ADCCTL_ALL_EN_Pos)
#define ADCCTL_ALL_EN_ENABLE_ADC      ((0x1UL) << ADCCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          RST
 *  @access     ADC->ADCCTL.bit.RST
 *  @brief      ADC digital reset
 */
#define ADCCTL_ALL_RST_Pos (1)
#define ADCCTL_ALL_RST_Msk (0x1UL << ADCCTL_ALL_RST_Pos)

typedef enum
{
    ADCCTL_BIT_RST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                       */
    ADCCTL_BIT_RST_RESET_ADC     = 1,  /*!< Write a 1 reset the ADC digital part. This bit is self-cleared   */
} ADCCTL_BIT_RST;

#define ADCCTL_ALL_RST_NO_EFFECT     ((0x0UL) << ADCCTL_ALL_RST_Pos)
#define ADCCTL_ALL_RST_RESET_ADC     ((0x1UL) << ADCCTL_ALL_RST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          SYNCEN
 *  @access     ADC->ADCCTL.bit.SYNCEN
 *  @brief      Enable sample/convert control re-synchronization with local clean clock
 */
#define ADCCTL_ALL_SYNCEN_Pos (2)
#define ADCCTL_ALL_SYNCEN_Msk (0x1UL << ADCCTL_ALL_SYNCEN_Pos)

typedef enum
{
    ADCCTL_BIT_SYNCEN_DISABLE     = 0,  /*!< Disable   */
    ADCCTL_BIT_SYNCEN_ENABLE      = 1,  /*!< Enable    */
} ADCCTL_BIT_SYNCEN;

#define ADCCTL_ALL_SYNCEN_DISABLE     ((0x0UL) << ADCCTL_ALL_SYNCEN_Pos)
#define ADCCTL_ALL_SYNCEN_ENABLE      ((0x1UL) << ADCCTL_ALL_SYNCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          SYNCEDGE
 *  @access     ADC->ADCCTL.bit.SYNCEDGE
 *  @brief      Clock edge for sample/convert control re-synchronization
 */
#define ADCCTL_ALL_SYNCEDGE_Pos (3)
#define ADCCTL_ALL_SYNCEDGE_Msk (0x1UL << ADCCTL_ALL_SYNCEDGE_Pos)

typedef enum
{
    ADCCTL_BIT_SYNCEDGE_NEGATIVE_EDGE     = 0,  /*!< Negative edge   */
    ADCCTL_BIT_SYNCEDGE_POSITIVE_EDGE     = 1,  /*!< Positve edge    */
} ADCCTL_BIT_SYNCEDGE;

#define ADCCTL_ALL_SYNCEDGE_NEGATIVE_EDGE     ((0x0UL) << ADCCTL_ALL_SYNCEDGE_Pos)
#define ADCCTL_ALL_SYNCEDGE_POSITIVE_EDGE     ((0x1UL) << ADCCTL_ALL_SYNCEDGE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          TIEAP
 *  @access     ADC->ADCCTL.bit.TIEAP
 *  @brief      Force SHA positive input connection
 */
#define ADCCTL_ALL_TIEAP_Pos (4)
#define ADCCTL_ALL_TIEAP_Msk (0x3UL << ADCCTL_ALL_TIEAP_Pos)

typedef enum
{
    ADCCTL_BIT_TIEAP_DISABLE        = 0,  /*!< Disable                             */
    ADCCTL_BIT_TIEAP_FORCE_LOW      = 2,  /*!< Force SHA positve input tied low    */
    ADCCTL_BIT_TIEAP_FORCE_HIGH     = 3,  /*!< Force SHA positve input tied high   */
} ADCCTL_BIT_TIEAP;

#define ADCCTL_ALL_TIEAP_DISABLE        ((0x0UL) << ADCCTL_ALL_TIEAP_Pos)
#define ADCCTL_ALL_TIEAP_FORCE_LOW      ((0x2UL) << ADCCTL_ALL_TIEAP_Pos)
#define ADCCTL_ALL_TIEAP_FORCE_HIGH     ((0x3UL) << ADCCTL_ALL_TIEAP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          TIEAN
 *  @access     ADC->ADCCTL.bit.TIEAN
 *  @brief      Force SHA negative input connection
 */
#define ADCCTL_ALL_TIEAN_Pos (6)
#define ADCCTL_ALL_TIEAN_Msk (0x3UL << ADCCTL_ALL_TIEAN_Pos)

typedef enum
{
    ADCCTL_BIT_TIEAN_DISABLE        = 0,  /*!< Disable                              */
    ADCCTL_BIT_TIEAN_FORCE_LOW      = 2,  /*!< Force SHA negative input tied low    */
    ADCCTL_BIT_TIEAN_FORCE_HIGH     = 3,  /*!< Force SHA negative input tied high   */
} ADCCTL_BIT_TIEAN;

#define ADCCTL_ALL_TIEAN_DISABLE        ((0x0UL) << ADCCTL_ALL_TIEAN_Pos)
#define ADCCTL_ALL_TIEAN_FORCE_LOW      ((0x2UL) << ADCCTL_ALL_TIEAN_Pos)
#define ADCCTL_ALL_TIEAN_FORCE_HIGH     ((0x3UL) << ADCCTL_ALL_TIEAN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          TIEBP
 *  @access     ADC->ADCCTL.bit.TIEBP
 *  @brief      Force SHB positive input connection
 */
#define ADCCTL_ALL_TIEBP_Pos (8)
#define ADCCTL_ALL_TIEBP_Msk (0x3UL << ADCCTL_ALL_TIEBP_Pos)

typedef enum
{
    ADCCTL_BIT_TIEBP_DISABLE        = 0,  /*!< Disable                             */
    ADCCTL_BIT_TIEBP_FORCE_LOW      = 2,  /*!< Force SHB positve input tied low    */
    ADCCTL_BIT_TIEBP_FORCE_HIGH     = 3,  /*!< Force SHB positve input tied high   */
} ADCCTL_BIT_TIEBP;

#define ADCCTL_ALL_TIEBP_DISABLE        ((0x0UL) << ADCCTL_ALL_TIEBP_Pos)
#define ADCCTL_ALL_TIEBP_FORCE_LOW      ((0x2UL) << ADCCTL_ALL_TIEBP_Pos)
#define ADCCTL_ALL_TIEBP_FORCE_HIGH     ((0x3UL) << ADCCTL_ALL_TIEBP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          TIEBN
 *  @access     ADC->ADCCTL.bit.TIEBN
 *  @brief      Force SHB negative input connection
 */
#define ADCCTL_ALL_TIEBN_Pos (10)
#define ADCCTL_ALL_TIEBN_Msk (0x3UL << ADCCTL_ALL_TIEBN_Pos)

typedef enum
{
    ADCCTL_BIT_TIEBN_DISABLE        = 0,  /*!< Disable                              */
    ADCCTL_BIT_TIEBN_FORCE_LOW      = 2,  /*!< Force SHB negative input tied low    */
    ADCCTL_BIT_TIEBN_FORCE_HIGH     = 3,  /*!< Force SHB negative input tied high   */
} ADCCTL_BIT_TIEBN;

#define ADCCTL_ALL_TIEBN_DISABLE        ((0x0UL) << ADCCTL_ALL_TIEBN_Pos)
#define ADCCTL_ALL_TIEBN_FORCE_LOW      ((0x2UL) << ADCCTL_ALL_TIEBN_Pos)
#define ADCCTL_ALL_TIEBN_FORCE_HIGH     ((0x3UL) << ADCCTL_ALL_TIEBN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          TIECP
 *  @access     ADC->ADCCTL.bit.TIECP
 *  @brief      Force SHC positive input connection
 */
#define ADCCTL_ALL_TIECP_Pos (12)
#define ADCCTL_ALL_TIECP_Msk (0x3UL << ADCCTL_ALL_TIECP_Pos)

typedef enum
{
    ADCCTL_BIT_TIECP_DISABLE        = 0,  /*!< Disable                             */
    ADCCTL_BIT_TIECP_FORCE_LOW      = 2,  /*!< Force SHC positve input tied low    */
    ADCCTL_BIT_TIECP_FORCE_HIGH     = 3,  /*!< Force SHC positve input tied high   */
} ADCCTL_BIT_TIECP;

#define ADCCTL_ALL_TIECP_DISABLE        ((0x0UL) << ADCCTL_ALL_TIECP_Pos)
#define ADCCTL_ALL_TIECP_FORCE_LOW      ((0x2UL) << ADCCTL_ALL_TIECP_Pos)
#define ADCCTL_ALL_TIECP_FORCE_HIGH     ((0x3UL) << ADCCTL_ALL_TIECP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCCTL          TIECN
 *  @access     ADC->ADCCTL.bit.TIECN
 *  @brief      Force SHC negative input connection
 */
#define ADCCTL_ALL_TIECN_Pos (14)
#define ADCCTL_ALL_TIECN_Msk (0x3UL << ADCCTL_ALL_TIECN_Pos)

typedef enum
{
    ADCCTL_BIT_TIECN_DISABLE        = 0,  /*!< Disable                              */
    ADCCTL_BIT_TIECN_FORCE_LOW      = 2,  /*!< Force SHC negative input tied low    */
    ADCCTL_BIT_TIECN_FORCE_HIGH     = 3,  /*!< Force SHC negative input tied high   */
} ADCCTL_BIT_TIECN;

#define ADCCTL_ALL_TIECN_DISABLE        ((0x0UL) << ADCCTL_ALL_TIECN_Pos)
#define ADCCTL_ALL_TIECN_FORCE_LOW      ((0x2UL) << ADCCTL_ALL_TIECN_Pos)
#define ADCCTL_ALL_TIECN_FORCE_HIGH     ((0x3UL) << ADCCTL_ALL_TIECN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCBGCTL        EN
 *  @access     ADC->ADCBGCTL.bit.EN
 *  @brief      ADC bandgap enable
 */
#define ADCBGCTL_ALL_EN_Pos (0)
#define ADCBGCTL_ALL_EN_Msk (0x1UL << ADCBGCTL_ALL_EN_Pos)

typedef enum
{
    ADCBGCTL_BIT_EN_DISABLE     = 0,  /*!< Disable ADC bandgap   */
    ADCBGCTL_BIT_EN_ENABLE      = 1,  /*!< Enable ADC bandgap    */
} ADCBGCTL_BIT_EN;

#define ADCBGCTL_ALL_EN_DISABLE     ((0x0UL) << ADCBGCTL_ALL_EN_Pos)
#define ADCBGCTL_ALL_EN_ENABLE      ((0x1UL) << ADCBGCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCREFCTL       EN
 *  @access     ADC->ADCREFCTL.bit.EN
 *  @brief      Reference enable
 */
#define ADCREFCTL_ALL_EN_Pos (0)
#define ADCREFCTL_ALL_EN_Msk (0x1UL << ADCREFCTL_ALL_EN_Pos)

typedef enum
{
    ADCREFCTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    ADCREFCTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} ADCREFCTL_BIT_EN;

#define ADCREFCTL_ALL_EN_DISABLE     ((0x0UL) << ADCREFCTL_ALL_EN_Pos)
#define ADCREFCTL_ALL_EN_ENABLE      ((0x1UL) << ADCREFCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCREFCTL       EXTREF
 *  @access     ADC->ADCREFCTL.bit.EXTREF
 *  @brief      External reference enable
 */
#define ADCREFCTL_ALL_EXTREF_Pos (1)
#define ADCREFCTL_ALL_EXTREF_Msk (0x1UL << ADCREFCTL_ALL_EXTREF_Pos)

typedef enum
{
    ADCREFCTL_BIT_EXTREF_DISABLE     = 0,  /*!< Disable   */
    ADCREFCTL_BIT_EXTREF_ENABLE      = 1,  /*!< Enable    */
} ADCREFCTL_BIT_EXTREF;

#define ADCREFCTL_ALL_EXTREF_DISABLE     ((0x0UL) << ADCREFCTL_ALL_EXTREF_Pos)
#define ADCREFCTL_ALL_EXTREF_ENABLE      ((0x1UL) << ADCREFCTL_ALL_EXTREF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCREFCTL       VREFTRIM
 *  @access     ADC->ADCREFCTL.bit.VREFTRIM
 *  @brief      VREF trimming
 */
#define ADCREFCTL_ALL_VREFTRIM_Pos (2)
#define ADCREFCTL_ALL_VREFTRIM_Msk (0x1FUL << ADCREFCTL_ALL_VREFTRIM_Pos)

#define ADCREFCTL_BIT_VREFTRIM

#define ADCREFCTL_ALL_VREFTRIM_(x) ((x) << ADCREFCTL_ALL_VREFTRIM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCREFCTL       VDIGTRIM
 *  @access     ADC->ADCREFCTL.bit.VDIGTRIM
 *  @brief      VDIG trimming
 */
#define ADCREFCTL_ALL_VDIGTRIM_Pos (7)
#define ADCREFCTL_ALL_VDIGTRIM_Msk (0x3UL << ADCREFCTL_ALL_VDIGTRIM_Pos)

#define ADCREFCTL_BIT_VDIGTRIM

#define ADCREFCTL_ALL_VDIGTRIM_(x) ((x) << ADCREFCTL_ALL_VDIGTRIM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCREFCTL       VANATRIM
 *  @access     ADC->ADCREFCTL.bit.VANATRIM
 *  @brief      VANA trimming
 */
#define ADCREFCTL_ALL_VANATRIM_Pos (9)
#define ADCREFCTL_ALL_VANATRIM_Msk (0x3UL << ADCREFCTL_ALL_VANATRIM_Pos)

#define ADCREFCTL_BIT_VANATRIM

#define ADCREFCTL_ALL_VANATRIM_(x) ((x) << ADCREFCTL_ALL_VANATRIM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCREFCTL       VDDTRIM
 *  @access     ADC->ADCREFCTL.bit.VDDTRIM
 *  @brief      VDD trimming
 */
#define ADCREFCTL_ALL_VDDTRIM_Pos (11)
#define ADCREFCTL_ALL_VDDTRIM_Msk (0xFUL << ADCREFCTL_ALL_VDDTRIM_Pos)

#define ADCREFCTL_BIT_VDDTRIM

#define ADCREFCTL_ALL_VDDTRIM_(x) ((x) << ADCREFCTL_ALL_VDDTRIM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRAWCODEA     VAL
 *  @access     ADC->ADCRAWCODEA.bit.VAL
 *  @brief      Raw code (Signed number from -8192 to 8191) for SHA.
 */
#define ADCRAWCODEA_ALL_VAL_Pos (0)
#define ADCRAWCODEA_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRAWCODEA_ALL_VAL_Pos)

#define ADCRAWCODEA_BIT_VAL

#define ADCRAWCODEA_ALL_VAL_(x) ((x) << ADCRAWCODEA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRAWCODEB     VAL
 *  @access     ADC->ADCRAWCODEB.bit.VAL
 *  @brief      Raw code (Signed number from -8192 to 8191) for SHB.
 */
#define ADCRAWCODEB_ALL_VAL_Pos (0)
#define ADCRAWCODEB_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRAWCODEB_ALL_VAL_Pos)

#define ADCRAWCODEB_BIT_VAL

#define ADCRAWCODEB_ALL_VAL_(x) ((x) << ADCRAWCODEB_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRAWCODEC     VAL
 *  @access     ADC->ADCRAWCODEC.bit.VAL
 *  @brief      Raw code (Signed number from -8192 to 8191) for SHC.
 */
#define ADCRAWCODEC_ALL_VAL_Pos (0)
#define ADCRAWCODEC_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRAWCODEC_ALL_VAL_Pos)

#define ADCRAWCODEC_BIT_VAL

#define ADCRAWCODEC_ALL_VAL_(x) ((x) << ADCRAWCODEC_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT0      VAL
 *  @access     ADC->ADCRESULT0.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL0.
 *              In simultaneous sampling mode enabled by ADCSOCCTL0[SHEN], it is the result of SHA
 *              configured in ADCSOCCTL0
 */
#define ADCRESULT0_ALL_VAL_Pos (0)
#define ADCRESULT0_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT0_ALL_VAL_Pos)

#define ADCRESULT0_BIT_VAL

#define ADCRESULT0_ALL_VAL_(x) ((x) << ADCRESULT0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT1      VAL
 *  @access     ADC->ADCRESULT1.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL1.
 *              In simultaneous sampling mode enabled by ADCSOCCTL0[SHBEN], it is the result of SHB
 *              configured in ADCSOCCTL1
 */
#define ADCRESULT1_ALL_VAL_Pos (0)
#define ADCRESULT1_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT1_ALL_VAL_Pos)

#define ADCRESULT1_BIT_VAL

#define ADCRESULT1_ALL_VAL_(x) ((x) << ADCRESULT1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT2      VAL
 *  @access     ADC->ADCRESULT2.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL2.
 *              In simultaneous sampling mode enabled by ADCSOCCTL0[SHCEN], it is the result of SHC
 *              configured in ADCSOCCTL2
 */
#define ADCRESULT2_ALL_VAL_Pos (0)
#define ADCRESULT2_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT2_ALL_VAL_Pos)

#define ADCRESULT2_BIT_VAL

#define ADCRESULT2_ALL_VAL_(x) ((x) << ADCRESULT2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT3      VAL
 *  @access     ADC->ADCRESULT3.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL3.
 *              In simultaneous sampling mode enabled by ADCSOCCTL3[SHAEN], it is the result of SHA
 *              configured in ADCSOCCTL3
 */
#define ADCRESULT3_ALL_VAL_Pos (0)
#define ADCRESULT3_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT3_ALL_VAL_Pos)

#define ADCRESULT3_BIT_VAL

#define ADCRESULT3_ALL_VAL_(x) ((x) << ADCRESULT3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT4      VAL
 *  @access     ADC->ADCRESULT4.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL4.
 *              In simultaneous sampling mode enabled by ADCSOCCTL3[SHBEN], it is the result of SHB
 *              configured in ADCSOCCTL4
 */
#define ADCRESULT4_ALL_VAL_Pos (0)
#define ADCRESULT4_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT4_ALL_VAL_Pos)

#define ADCRESULT4_BIT_VAL

#define ADCRESULT4_ALL_VAL_(x) ((x) << ADCRESULT4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT5      VAL
 *  @access     ADC->ADCRESULT5.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL5.
 *              In simultaneous sampling mode enabled by ADCSOCCTL3[SHCEN], it is the result of SHC
 *              configured in ADCSOCCTL5
 */
#define ADCRESULT5_ALL_VAL_Pos (0)
#define ADCRESULT5_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT5_ALL_VAL_Pos)

#define ADCRESULT5_BIT_VAL

#define ADCRESULT5_ALL_VAL_(x) ((x) << ADCRESULT5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT6      VAL
 *  @access     ADC->ADCRESULT6.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL6.
 *              In simultaneous sampling mode enabled by ADCSOCCTL6[SHAEN], it is the result of SHA
 *              configured in ADCSOCCTL6
 */
#define ADCRESULT6_ALL_VAL_Pos (0)
#define ADCRESULT6_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT6_ALL_VAL_Pos)

#define ADCRESULT6_BIT_VAL

#define ADCRESULT6_ALL_VAL_(x) ((x) << ADCRESULT6_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT7      VAL
 *  @access     ADC->ADCRESULT7.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL7.
 *              In simultaneous sampling mode enabled by ADCSOCCTL6[SHBEN], it is the result of SHB
 *              configured in ADCSOCCTL7
 */
#define ADCRESULT7_ALL_VAL_Pos (0)
#define ADCRESULT7_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT7_ALL_VAL_Pos)

#define ADCRESULT7_BIT_VAL

#define ADCRESULT7_ALL_VAL_(x) ((x) << ADCRESULT7_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT8      VAL
 *  @access     ADC->ADCRESULT8.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL8.
 *              In simultaneous sampling mode enabled by ADCSOCCTL6[SHCEN], it is the result of SHC
 *              configured in ADCSOCCTL8
 */
#define ADCRESULT8_ALL_VAL_Pos (0)
#define ADCRESULT8_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT8_ALL_VAL_Pos)

#define ADCRESULT8_BIT_VAL

#define ADCRESULT8_ALL_VAL_(x) ((x) << ADCRESULT8_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT9      VAL
 *  @access     ADC->ADCRESULT9.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL9.
 *              In simultaneous sampling mode enabled by ADCSOCCTL9[SHAEN], it is the result of SHA
 *              configured in ADCSOCCTL9
 */
#define ADCRESULT9_ALL_VAL_Pos (0)
#define ADCRESULT9_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT9_ALL_VAL_Pos)

#define ADCRESULT9_BIT_VAL

#define ADCRESULT9_ALL_VAL_(x) ((x) << ADCRESULT9_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT10     VAL
 *  @access     ADC->ADCRESULT10.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL10.
 *              In simultaneous sampling mode enabled by ADCSOCCTL9[SHBEN], it is the result of SHB
 *              configured in ADCSOCCTL10
 */
#define ADCRESULT10_ALL_VAL_Pos (0)
#define ADCRESULT10_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT10_ALL_VAL_Pos)

#define ADCRESULT10_BIT_VAL

#define ADCRESULT10_ALL_VAL_(x) ((x) << ADCRESULT10_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT11     VAL
 *  @access     ADC->ADCRESULT11.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL11.
 *              In simultaneous sampling mode enabled by ADCSOCCTL9[SHCEN], it is the result of SHC
 *              configured in ADCSOCCTL11
 */
#define ADCRESULT11_ALL_VAL_Pos (0)
#define ADCRESULT11_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT11_ALL_VAL_Pos)

#define ADCRESULT11_BIT_VAL

#define ADCRESULT11_ALL_VAL_(x) ((x) << ADCRESULT11_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT12     VAL
 *  @access     ADC->ADCRESULT12.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL12.
 *              In simultaneous sampling mode enabled by ADCSOCCTL12[SHAEN], it is the result of
 *              SHA configured in ADCSOCCTL12
 */
#define ADCRESULT12_ALL_VAL_Pos (0)
#define ADCRESULT12_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT12_ALL_VAL_Pos)

#define ADCRESULT12_BIT_VAL

#define ADCRESULT12_ALL_VAL_(x) ((x) << ADCRESULT12_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT13     VAL
 *  @access     ADC->ADCRESULT13.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL13.
 *              In simultaneous sampling mode enabled by ADCSOCCTL12[SHBEN], it is the result of
 *              SHB configured in ADCSOCCTL13
 */
#define ADCRESULT13_ALL_VAL_Pos (0)
#define ADCRESULT13_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT13_ALL_VAL_Pos)

#define ADCRESULT13_BIT_VAL

#define ADCRESULT13_ALL_VAL_(x) ((x) << ADCRESULT13_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT14     VAL
 *  @access     ADC->ADCRESULT14.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL14.
 *              In simultaneous sampling mode enabled by ADCSOCCTL12[SHCEN], it is the result of
 *              SHC configured in ADCSOCCTL14
 */
#define ADCRESULT14_ALL_VAL_Pos (0)
#define ADCRESULT14_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT14_ALL_VAL_Pos)

#define ADCRESULT14_BIT_VAL

#define ADCRESULT14_ALL_VAL_(x) ((x) << ADCRESULT14_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCRESULT15     VAL
 *  @access     ADC->ADCRESULT15.bit.VAL
 *  @brief      14-bit ADC result with extended sign bit
 *              In sequential mode, it is the result of the corresponding SH enabled in ADCSOCCTL15.
 *              Simultaneous sample mode is not supported.
 */
#define ADCRESULT15_ALL_VAL_Pos (0)
#define ADCRESULT15_ALL_VAL_Msk (0xFFFFFFFFUL << ADCRESULT15_ALL_VAL_Pos)

#define ADCRESULT15_BIT_VAL

#define ADCRESULT15_ALL_VAL_(x) ((x) << ADCRESULT15_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPURESULT0   VAL
 *  @access     ADC->ADCPPURESULT0.bit.VAL
 *  @brief      Comparison result with extended sign bit
 */
#define ADCPPURESULT0_ALL_VAL_Pos (0)
#define ADCPPURESULT0_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPURESULT0_ALL_VAL_Pos)

#define ADCPPURESULT0_BIT_VAL

#define ADCPPURESULT0_ALL_VAL_(x) ((x) << ADCPPURESULT0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPURESULT1   VAL
 *  @access     ADC->ADCPPURESULT1.bit.VAL
 *  @brief      Comparison result with extended sign bit
 */
#define ADCPPURESULT1_ALL_VAL_Pos (0)
#define ADCPPURESULT1_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPURESULT1_ALL_VAL_Pos)

#define ADCPPURESULT1_BIT_VAL

#define ADCPPURESULT1_ALL_VAL_(x) ((x) << ADCPPURESULT1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPURESULT2   VAL
 *  @access     ADC->ADCPPURESULT2.bit.VAL
 *  @brief      Comparison result with extended sign bit
 */
#define ADCPPURESULT2_ALL_VAL_Pos (0)
#define ADCPPURESULT2_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPURESULT2_ALL_VAL_Pos)

#define ADCPPURESULT2_BIT_VAL

#define ADCPPURESULT2_ALL_VAL_(x) ((x) << ADCPPURESULT2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPURESULT3   VAL
 *  @access     ADC->ADCPPURESULT3.bit.VAL
 *  @brief      Comparison result with extended sign bit
 */
#define ADCPPURESULT3_ALL_VAL_Pos (0)
#define ADCPPURESULT3_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPURESULT3_ALL_VAL_Pos)

#define ADCPPURESULT3_BIT_VAL

#define ADCPPURESULT3_ALL_VAL_(x) ((x) << ADCPPURESULT3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPURESULT4   VAL
 *  @access     ADC->ADCPPURESULT4.bit.VAL
 *  @brief      Comparison result with extended sign bit
 */
#define ADCPPURESULT4_ALL_VAL_Pos (0)
#define ADCPPURESULT4_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPURESULT4_ALL_VAL_Pos)

#define ADCPPURESULT4_BIT_VAL

#define ADCPPURESULT4_ALL_VAL_(x) ((x) << ADCPPURESULT4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPURESULT5   VAL
 *  @access     ADC->ADCPPURESULT5.bit.VAL
 *  @brief      Comparison result with extended sign bit
 */
#define ADCPPURESULT5_ALL_VAL_Pos (0)
#define ADCPPURESULT5_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPURESULT5_ALL_VAL_Pos)

#define ADCPPURESULT5_BIT_VAL

#define ADCPPURESULT5_ALL_VAL_(x) ((x) << ADCPPURESULT5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUSOCDLY0   VAL
 *  @access     ADC->ADCPPUSOCDLY0.bit.VAL
 *  @brief      Delay from trigger to execution for SOC selected by ADCPPU0CTL[SOCSEL]
 */
#define ADCPPUSOCDLY0_ALL_VAL_Pos (0)
#define ADCPPUSOCDLY0_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUSOCDLY0_ALL_VAL_Pos)

#define ADCPPUSOCDLY0_BIT_VAL

#define ADCPPUSOCDLY0_ALL_VAL_(x) ((x) << ADCPPUSOCDLY0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUSOCDLY1   VAL
 *  @access     ADC->ADCPPUSOCDLY1.bit.VAL
 *  @brief      Delay from trigger to execution for SOC selected by ADCPPU1CTL[SOCSEL]
 */
#define ADCPPUSOCDLY1_ALL_VAL_Pos (0)
#define ADCPPUSOCDLY1_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUSOCDLY1_ALL_VAL_Pos)

#define ADCPPUSOCDLY1_BIT_VAL

#define ADCPPUSOCDLY1_ALL_VAL_(x) ((x) << ADCPPUSOCDLY1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUSOCDLY2   VAL
 *  @access     ADC->ADCPPUSOCDLY2.bit.VAL
 *  @brief      Delay from trigger to execution for SOC selected by ADCPPU2CTL[SOCSEL]
 */
#define ADCPPUSOCDLY2_ALL_VAL_Pos (0)
#define ADCPPUSOCDLY2_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUSOCDLY2_ALL_VAL_Pos)

#define ADCPPUSOCDLY2_BIT_VAL

#define ADCPPUSOCDLY2_ALL_VAL_(x) ((x) << ADCPPUSOCDLY2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUSOCDLY3   VAL
 *  @access     ADC->ADCPPUSOCDLY3.bit.VAL
 *  @brief      Delay from trigger to execution for SOC selected by ADCPPU3CTL[SOCSEL]
 */
#define ADCPPUSOCDLY3_ALL_VAL_Pos (0)
#define ADCPPUSOCDLY3_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUSOCDLY3_ALL_VAL_Pos)

#define ADCPPUSOCDLY3_BIT_VAL

#define ADCPPUSOCDLY3_ALL_VAL_(x) ((x) << ADCPPUSOCDLY3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUSOCDLY4   VAL
 *  @access     ADC->ADCPPUSOCDLY4.bit.VAL
 *  @brief      Delay from trigger to execution for SOC selected by ADCPPU4CTL[SOCSEL]
 */
#define ADCPPUSOCDLY4_ALL_VAL_Pos (0)
#define ADCPPUSOCDLY4_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUSOCDLY4_ALL_VAL_Pos)

#define ADCPPUSOCDLY4_BIT_VAL

#define ADCPPUSOCDLY4_ALL_VAL_(x) ((x) << ADCPPUSOCDLY4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUSOCDLY5   VAL
 *  @access     ADC->ADCPPUSOCDLY5.bit.VAL
 *  @brief      Delay from trigger to execution for SOC selected by ADCPPU5CTL[SOCSEL]
 */
#define ADCPPUSOCDLY5_ALL_VAL_Pos (0)
#define ADCPPUSOCDLY5_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUSOCDLY5_ALL_VAL_Pos)

#define ADCPPUSOCDLY5_BIT_VAL

#define ADCPPUSOCDLY5_ALL_VAL_(x) ((x) << ADCPPUSOCDLY5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF0       TZLO
 *  @access     ADC->ADCPPUIF0.bit.TZLO
 *  @brief      Latched ADCPPU0 too-low status
 */
#define ADCPPUIF0_ALL_TZLO_Pos (0)
#define ADCPPUIF0_ALL_TZLO_Msk (0x1UL << ADCPPUIF0_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIF0_BIT_TZLO_NOT_OCCUR     = 0,  /*!< ADCPPU0 too-low does not happen   */
    ADCPPUIF0_BIT_TZLO_OCCUR         = 1,  /*!< ADCPPU0 too-low happened          */
} ADCPPUIF0_BIT_TZLO;

#define ADCPPUIF0_ALL_TZLO_NOT_OCCUR     ((0x0UL) << ADCPPUIF0_ALL_TZLO_Pos)
#define ADCPPUIF0_ALL_TZLO_OCCUR         ((0x1UL) << ADCPPUIF0_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF0       TZHI
 *  @access     ADC->ADCPPUIF0.bit.TZHI
 *  @brief      Latched ADCPPU0 too-high status
 */
#define ADCPPUIF0_ALL_TZHI_Pos (1)
#define ADCPPUIF0_ALL_TZHI_Msk (0x1UL << ADCPPUIF0_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIF0_BIT_TZHI_NOT_OCCUR     = 0,  /*!< ADCPPU0 too-high does not happen   */
    ADCPPUIF0_BIT_TZHI_OCCUR         = 1,  /*!< ADCPPU0 too-high happened          */
} ADCPPUIF0_BIT_TZHI;

#define ADCPPUIF0_ALL_TZHI_NOT_OCCUR     ((0x0UL) << ADCPPUIF0_ALL_TZHI_Pos)
#define ADCPPUIF0_ALL_TZHI_OCCUR         ((0x1UL) << ADCPPUIF0_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF0       XZRO
 *  @access     ADC->ADCPPUIF0.bit.XZRO
 *  @brief      Latched ADCPPU0 zero-cross status
 */
#define ADCPPUIF0_ALL_XZRO_Pos (2)
#define ADCPPUIF0_ALL_XZRO_Msk (0x1UL << ADCPPUIF0_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIF0_BIT_XZRO_NOT_OCCUR     = 0,  /*!< ADCPPU0 zero-cross does not happen   */
    ADCPPUIF0_BIT_XZRO_OCCUR         = 1,  /*!< ADCPPU0 zero-cross happened          */
} ADCPPUIF0_BIT_XZRO;

#define ADCPPUIF0_ALL_XZRO_NOT_OCCUR     ((0x0UL) << ADCPPUIF0_ALL_XZRO_Pos)
#define ADCPPUIF0_ALL_XZRO_OCCUR         ((0x1UL) << ADCPPUIF0_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF0       INT
 *  @access     ADC->ADCPPUIF0.bit.INT
 *  @brief      ADCPPU0 interrupt flag
 */
#define ADCPPUIF0_ALL_INT_Pos (3)
#define ADCPPUIF0_ALL_INT_Msk (0x1UL << ADCPPUIF0_ALL_INT_Pos)

typedef enum
{
    ADCPPUIF0_BIT_INT_NOT_OCCUR     = 0,  /*!< ADCPPU0 interrupt does not happen   */
    ADCPPUIF0_BIT_INT_OCCUR         = 1,  /*!< ADCPPU0 interrupt happened          */
} ADCPPUIF0_BIT_INT;

#define ADCPPUIF0_ALL_INT_NOT_OCCUR     ((0x0UL) << ADCPPUIF0_ALL_INT_Pos)
#define ADCPPUIF0_ALL_INT_OCCUR         ((0x1UL) << ADCPPUIF0_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF1       TZLO
 *  @access     ADC->ADCPPUIF1.bit.TZLO
 *  @brief      Latched ADCPPU1 too-low status
 */
#define ADCPPUIF1_ALL_TZLO_Pos (0)
#define ADCPPUIF1_ALL_TZLO_Msk (0x1UL << ADCPPUIF1_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIF1_BIT_TZLO_NOT_OCCUR     = 0,  /*!< ADCPPU1 too-low does not happen   */
    ADCPPUIF1_BIT_TZLO_OCCUR         = 1,  /*!< ADCPPU1 too-low happened          */
} ADCPPUIF1_BIT_TZLO;

#define ADCPPUIF1_ALL_TZLO_NOT_OCCUR     ((0x0UL) << ADCPPUIF1_ALL_TZLO_Pos)
#define ADCPPUIF1_ALL_TZLO_OCCUR         ((0x1UL) << ADCPPUIF1_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF1       TZHI
 *  @access     ADC->ADCPPUIF1.bit.TZHI
 *  @brief      Latched ADCPPU1 too-high status
 */
#define ADCPPUIF1_ALL_TZHI_Pos (1)
#define ADCPPUIF1_ALL_TZHI_Msk (0x1UL << ADCPPUIF1_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIF1_BIT_TZHI_NOT_OCCUR     = 0,  /*!< ADCPPU1 too-high does not happen   */
    ADCPPUIF1_BIT_TZHI_OCCUR         = 1,  /*!< ADCPPU1 too-high happened          */
} ADCPPUIF1_BIT_TZHI;

#define ADCPPUIF1_ALL_TZHI_NOT_OCCUR     ((0x0UL) << ADCPPUIF1_ALL_TZHI_Pos)
#define ADCPPUIF1_ALL_TZHI_OCCUR         ((0x1UL) << ADCPPUIF1_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF1       XZRO
 *  @access     ADC->ADCPPUIF1.bit.XZRO
 *  @brief      Latched ADCPPU1 zero-cross status
 */
#define ADCPPUIF1_ALL_XZRO_Pos (2)
#define ADCPPUIF1_ALL_XZRO_Msk (0x1UL << ADCPPUIF1_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIF1_BIT_XZRO_NOT_OCCUR     = 0,  /*!< ADCPPU1 zero-cross does not happen   */
    ADCPPUIF1_BIT_XZRO_OCCUR         = 1,  /*!< ADCPPU1 zero-cross happened          */
} ADCPPUIF1_BIT_XZRO;

#define ADCPPUIF1_ALL_XZRO_NOT_OCCUR     ((0x0UL) << ADCPPUIF1_ALL_XZRO_Pos)
#define ADCPPUIF1_ALL_XZRO_OCCUR         ((0x1UL) << ADCPPUIF1_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF1       INT
 *  @access     ADC->ADCPPUIF1.bit.INT
 *  @brief      ADCPPU1 interrupt flag
 */
#define ADCPPUIF1_ALL_INT_Pos (3)
#define ADCPPUIF1_ALL_INT_Msk (0x1UL << ADCPPUIF1_ALL_INT_Pos)

typedef enum
{
    ADCPPUIF1_BIT_INT_NOT_OCCUR     = 0,  /*!< ADCPPU1 interrupt does not happen   */
    ADCPPUIF1_BIT_INT_OCCUR         = 1,  /*!< ADCPPU1 interrupt happened          */
} ADCPPUIF1_BIT_INT;

#define ADCPPUIF1_ALL_INT_NOT_OCCUR     ((0x0UL) << ADCPPUIF1_ALL_INT_Pos)
#define ADCPPUIF1_ALL_INT_OCCUR         ((0x1UL) << ADCPPUIF1_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF2       TZLO
 *  @access     ADC->ADCPPUIF2.bit.TZLO
 *  @brief      Latched ADCPPU2 too-low status
 */
#define ADCPPUIF2_ALL_TZLO_Pos (0)
#define ADCPPUIF2_ALL_TZLO_Msk (0x1UL << ADCPPUIF2_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIF2_BIT_TZLO_NOT_OCCUR     = 0,  /*!< ADCPPU2 too-low does not happen   */
    ADCPPUIF2_BIT_TZLO_OCCUR         = 1,  /*!< ADCPPU2 too-low happened          */
} ADCPPUIF2_BIT_TZLO;

#define ADCPPUIF2_ALL_TZLO_NOT_OCCUR     ((0x0UL) << ADCPPUIF2_ALL_TZLO_Pos)
#define ADCPPUIF2_ALL_TZLO_OCCUR         ((0x1UL) << ADCPPUIF2_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF2       TZHI
 *  @access     ADC->ADCPPUIF2.bit.TZHI
 *  @brief      Latched ADCPPU2 too-high status
 */
#define ADCPPUIF2_ALL_TZHI_Pos (1)
#define ADCPPUIF2_ALL_TZHI_Msk (0x1UL << ADCPPUIF2_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIF2_BIT_TZHI_NOT_OCCUR     = 0,  /*!< ADCPPU2 too-high does not happen   */
    ADCPPUIF2_BIT_TZHI_OCCUR         = 1,  /*!< ADCPPU2 too-high happened          */
} ADCPPUIF2_BIT_TZHI;

#define ADCPPUIF2_ALL_TZHI_NOT_OCCUR     ((0x0UL) << ADCPPUIF2_ALL_TZHI_Pos)
#define ADCPPUIF2_ALL_TZHI_OCCUR         ((0x1UL) << ADCPPUIF2_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF2       XZRO
 *  @access     ADC->ADCPPUIF2.bit.XZRO
 *  @brief      Latched ADCPPU2 zero-cross status
 */
#define ADCPPUIF2_ALL_XZRO_Pos (2)
#define ADCPPUIF2_ALL_XZRO_Msk (0x1UL << ADCPPUIF2_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIF2_BIT_XZRO_NOT_OCCUR     = 0,  /*!< ADCPPU2 zero-cross does not happen   */
    ADCPPUIF2_BIT_XZRO_OCCUR         = 1,  /*!< ADCPPU2 zero-cross happened          */
} ADCPPUIF2_BIT_XZRO;

#define ADCPPUIF2_ALL_XZRO_NOT_OCCUR     ((0x0UL) << ADCPPUIF2_ALL_XZRO_Pos)
#define ADCPPUIF2_ALL_XZRO_OCCUR         ((0x1UL) << ADCPPUIF2_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF2       INT
 *  @access     ADC->ADCPPUIF2.bit.INT
 *  @brief      ADCPPU2 interrupt flag
 */
#define ADCPPUIF2_ALL_INT_Pos (3)
#define ADCPPUIF2_ALL_INT_Msk (0x1UL << ADCPPUIF2_ALL_INT_Pos)

typedef enum
{
    ADCPPUIF2_BIT_INT_NOT_OCCUR     = 0,  /*!< ADCPPU2 interrupt does not happen   */
    ADCPPUIF2_BIT_INT_OCCUR         = 1,  /*!< ADCPPU2 interrupt happened          */
} ADCPPUIF2_BIT_INT;

#define ADCPPUIF2_ALL_INT_NOT_OCCUR     ((0x0UL) << ADCPPUIF2_ALL_INT_Pos)
#define ADCPPUIF2_ALL_INT_OCCUR         ((0x1UL) << ADCPPUIF2_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF3       TZLO
 *  @access     ADC->ADCPPUIF3.bit.TZLO
 *  @brief      Latched ADCPPU3 too-low status
 */
#define ADCPPUIF3_ALL_TZLO_Pos (0)
#define ADCPPUIF3_ALL_TZLO_Msk (0x1UL << ADCPPUIF3_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIF3_BIT_TZLO_NOT_OCCUR     = 0,  /*!< ADCPPU3 too-low does not happen   */
    ADCPPUIF3_BIT_TZLO_OCCUR         = 1,  /*!< ADCPPU3 too-low happened          */
} ADCPPUIF3_BIT_TZLO;

#define ADCPPUIF3_ALL_TZLO_NOT_OCCUR     ((0x0UL) << ADCPPUIF3_ALL_TZLO_Pos)
#define ADCPPUIF3_ALL_TZLO_OCCUR         ((0x1UL) << ADCPPUIF3_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF3       TZHI
 *  @access     ADC->ADCPPUIF3.bit.TZHI
 *  @brief      Latched ADCPPU3 too-high status
 */
#define ADCPPUIF3_ALL_TZHI_Pos (1)
#define ADCPPUIF3_ALL_TZHI_Msk (0x1UL << ADCPPUIF3_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIF3_BIT_TZHI_NOT_OCCUR     = 0,  /*!< ADCPPU3 too-high does not happen   */
    ADCPPUIF3_BIT_TZHI_OCCUR         = 1,  /*!< ADCPPU3 too-high happened          */
} ADCPPUIF3_BIT_TZHI;

#define ADCPPUIF3_ALL_TZHI_NOT_OCCUR     ((0x0UL) << ADCPPUIF3_ALL_TZHI_Pos)
#define ADCPPUIF3_ALL_TZHI_OCCUR         ((0x1UL) << ADCPPUIF3_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF3       XZRO
 *  @access     ADC->ADCPPUIF3.bit.XZRO
 *  @brief      Latched ADCPPU3 zero-cross status
 */
#define ADCPPUIF3_ALL_XZRO_Pos (2)
#define ADCPPUIF3_ALL_XZRO_Msk (0x1UL << ADCPPUIF3_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIF3_BIT_XZRO_NOT_OCCUR     = 0,  /*!< ADCPPU3 zero-cross does not happen   */
    ADCPPUIF3_BIT_XZRO_OCCUR         = 1,  /*!< ADCPPU3 zero-cross happened          */
} ADCPPUIF3_BIT_XZRO;

#define ADCPPUIF3_ALL_XZRO_NOT_OCCUR     ((0x0UL) << ADCPPUIF3_ALL_XZRO_Pos)
#define ADCPPUIF3_ALL_XZRO_OCCUR         ((0x1UL) << ADCPPUIF3_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF3       INT
 *  @access     ADC->ADCPPUIF3.bit.INT
 *  @brief      ADCPPU3 interrupt flag
 */
#define ADCPPUIF3_ALL_INT_Pos (3)
#define ADCPPUIF3_ALL_INT_Msk (0x1UL << ADCPPUIF3_ALL_INT_Pos)

typedef enum
{
    ADCPPUIF3_BIT_INT_NOT_OCCUR     = 0,  /*!< ADCPPU3 interrupt does not happen   */
    ADCPPUIF3_BIT_INT_OCCUR         = 1,  /*!< ADCPPU3 interrupt happened          */
} ADCPPUIF3_BIT_INT;

#define ADCPPUIF3_ALL_INT_NOT_OCCUR     ((0x0UL) << ADCPPUIF3_ALL_INT_Pos)
#define ADCPPUIF3_ALL_INT_OCCUR         ((0x1UL) << ADCPPUIF3_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF4       TZLO
 *  @access     ADC->ADCPPUIF4.bit.TZLO
 *  @brief      Latched ADCPPU4 too-low status
 */
#define ADCPPUIF4_ALL_TZLO_Pos (0)
#define ADCPPUIF4_ALL_TZLO_Msk (0x1UL << ADCPPUIF4_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIF4_BIT_TZLO_NOT_OCCUR     = 0,  /*!< ADCPPU4 too-low does not happen   */
    ADCPPUIF4_BIT_TZLO_OCCUR         = 1,  /*!< ADCPPU4 too-low happened          */
} ADCPPUIF4_BIT_TZLO;

#define ADCPPUIF4_ALL_TZLO_NOT_OCCUR     ((0x0UL) << ADCPPUIF4_ALL_TZLO_Pos)
#define ADCPPUIF4_ALL_TZLO_OCCUR         ((0x1UL) << ADCPPUIF4_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF4       TZHI
 *  @access     ADC->ADCPPUIF4.bit.TZHI
 *  @brief      Latched ADCPPU4 too-high status
 */
#define ADCPPUIF4_ALL_TZHI_Pos (1)
#define ADCPPUIF4_ALL_TZHI_Msk (0x1UL << ADCPPUIF4_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIF4_BIT_TZHI_NOT_OCCUR     = 0,  /*!< ADCPPU4 too-high does not happen   */
    ADCPPUIF4_BIT_TZHI_OCCUR         = 1,  /*!< ADCPPU4 too-high happened          */
} ADCPPUIF4_BIT_TZHI;

#define ADCPPUIF4_ALL_TZHI_NOT_OCCUR     ((0x0UL) << ADCPPUIF4_ALL_TZHI_Pos)
#define ADCPPUIF4_ALL_TZHI_OCCUR         ((0x1UL) << ADCPPUIF4_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF4       XZRO
 *  @access     ADC->ADCPPUIF4.bit.XZRO
 *  @brief      Latched ADCPPU4 zero-cross status
 */
#define ADCPPUIF4_ALL_XZRO_Pos (2)
#define ADCPPUIF4_ALL_XZRO_Msk (0x1UL << ADCPPUIF4_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIF4_BIT_XZRO_NOT_OCCUR     = 0,  /*!< ADCPPU4 zero-cross does not happen   */
    ADCPPUIF4_BIT_XZRO_OCCUR         = 1,  /*!< ADCPPU4 zero-cross happened          */
} ADCPPUIF4_BIT_XZRO;

#define ADCPPUIF4_ALL_XZRO_NOT_OCCUR     ((0x0UL) << ADCPPUIF4_ALL_XZRO_Pos)
#define ADCPPUIF4_ALL_XZRO_OCCUR         ((0x1UL) << ADCPPUIF4_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF4       INT
 *  @access     ADC->ADCPPUIF4.bit.INT
 *  @brief      ADCPPU4 interrupt flag
 */
#define ADCPPUIF4_ALL_INT_Pos (3)
#define ADCPPUIF4_ALL_INT_Msk (0x1UL << ADCPPUIF4_ALL_INT_Pos)

typedef enum
{
    ADCPPUIF4_BIT_INT_NOT_OCCUR     = 0,  /*!< ADCPPU4 interrupt does not happen   */
    ADCPPUIF4_BIT_INT_OCCUR         = 1,  /*!< ADCPPU4 interrupt happened          */
} ADCPPUIF4_BIT_INT;

#define ADCPPUIF4_ALL_INT_NOT_OCCUR     ((0x0UL) << ADCPPUIF4_ALL_INT_Pos)
#define ADCPPUIF4_ALL_INT_OCCUR         ((0x1UL) << ADCPPUIF4_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF5       TZLO
 *  @access     ADC->ADCPPUIF5.bit.TZLO
 *  @brief      Latched ADCPPU5 too-low status
 */
#define ADCPPUIF5_ALL_TZLO_Pos (0)
#define ADCPPUIF5_ALL_TZLO_Msk (0x1UL << ADCPPUIF5_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIF5_BIT_TZLO_NOT_OCCUR     = 0,  /*!< ADCPPU5 too-low does not happen   */
    ADCPPUIF5_BIT_TZLO_OCCUR         = 1,  /*!< ADCPPU5 too-low happened          */
} ADCPPUIF5_BIT_TZLO;

#define ADCPPUIF5_ALL_TZLO_NOT_OCCUR     ((0x0UL) << ADCPPUIF5_ALL_TZLO_Pos)
#define ADCPPUIF5_ALL_TZLO_OCCUR         ((0x1UL) << ADCPPUIF5_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF5       TZHI
 *  @access     ADC->ADCPPUIF5.bit.TZHI
 *  @brief      Latched ADCPPU5 too-high status
 */
#define ADCPPUIF5_ALL_TZHI_Pos (1)
#define ADCPPUIF5_ALL_TZHI_Msk (0x1UL << ADCPPUIF5_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIF5_BIT_TZHI_NOT_OCCUR     = 0,  /*!< ADCPPU5 too-high does not happen   */
    ADCPPUIF5_BIT_TZHI_OCCUR         = 1,  /*!< ADCPPU5 too-high happened          */
} ADCPPUIF5_BIT_TZHI;

#define ADCPPUIF5_ALL_TZHI_NOT_OCCUR     ((0x0UL) << ADCPPUIF5_ALL_TZHI_Pos)
#define ADCPPUIF5_ALL_TZHI_OCCUR         ((0x1UL) << ADCPPUIF5_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF5       XZRO
 *  @access     ADC->ADCPPUIF5.bit.XZRO
 *  @brief      Latched ADCPPU5 zero-cross status
 */
#define ADCPPUIF5_ALL_XZRO_Pos (2)
#define ADCPPUIF5_ALL_XZRO_Msk (0x1UL << ADCPPUIF5_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIF5_BIT_XZRO_NOT_OCCUR     = 0,  /*!< ADCPPU5 zero-cross does not happen   */
    ADCPPUIF5_BIT_XZRO_OCCUR         = 1,  /*!< ADCPPU5 zero-cross happened          */
} ADCPPUIF5_BIT_XZRO;

#define ADCPPUIF5_ALL_XZRO_NOT_OCCUR     ((0x0UL) << ADCPPUIF5_ALL_XZRO_Pos)
#define ADCPPUIF5_ALL_XZRO_OCCUR         ((0x1UL) << ADCPPUIF5_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIF5       INT
 *  @access     ADC->ADCPPUIF5.bit.INT
 *  @brief      ADCPPU5 interrupt flag
 */
#define ADCPPUIF5_ALL_INT_Pos (3)
#define ADCPPUIF5_ALL_INT_Msk (0x1UL << ADCPPUIF5_ALL_INT_Pos)

typedef enum
{
    ADCPPUIF5_BIT_INT_NOT_OCCUR     = 0,  /*!< ADCPPU5 interrupt does not happen   */
    ADCPPUIF5_BIT_INT_OCCUR         = 1,  /*!< ADCPPU5 interrupt happened          */
} ADCPPUIF5_BIT_INT;

#define ADCPPUIF5_ALL_INT_NOT_OCCUR     ((0x0UL) << ADCPPUIF5_ALL_INT_Pos)
#define ADCPPUIF5_ALL_INT_OCCUR         ((0x1UL) << ADCPPUIF5_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC0       TZLO
 *  @access     ADC->ADCPPUIC0.bit.TZLO
 *  @brief      Latched ADCPPU0 too-low status clear
 */
#define ADCPPUIC0_ALL_TZLO_Pos (0)
#define ADCPPUIC0_ALL_TZLO_Msk (0x1UL << ADCPPUIC0_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIC0_BIT_TZLO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC0_BIT_TZLO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU0IF[TZLO]. This bit is self-cleared.   */
} ADCPPUIC0_BIT_TZLO;

#define ADCPPUIC0_ALL_TZLO_NO_EFFECT     ((0x0UL) << ADCPPUIC0_ALL_TZLO_Pos)
#define ADCPPUIC0_ALL_TZLO_CLEAR         ((0x1UL) << ADCPPUIC0_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC0       TZHI
 *  @access     ADC->ADCPPUIC0.bit.TZHI
 *  @brief      Latched ADCPPU0 too-high status clear
 */
#define ADCPPUIC0_ALL_TZHI_Pos (1)
#define ADCPPUIC0_ALL_TZHI_Msk (0x1UL << ADCPPUIC0_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIC0_BIT_TZHI_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC0_BIT_TZHI_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU0IF[TZHI]. This bit is self-cleared.   */
} ADCPPUIC0_BIT_TZHI;

#define ADCPPUIC0_ALL_TZHI_NO_EFFECT     ((0x0UL) << ADCPPUIC0_ALL_TZHI_Pos)
#define ADCPPUIC0_ALL_TZHI_CLEAR         ((0x1UL) << ADCPPUIC0_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC0       XZRO
 *  @access     ADC->ADCPPUIC0.bit.XZRO
 *  @brief      Latched ADCPPU0 zero-cross status clear
 */
#define ADCPPUIC0_ALL_XZRO_Pos (2)
#define ADCPPUIC0_ALL_XZRO_Msk (0x1UL << ADCPPUIC0_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIC0_BIT_XZRO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC0_BIT_XZRO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU0IF[XZRO]. This bit is self-cleared.   */
} ADCPPUIC0_BIT_XZRO;

#define ADCPPUIC0_ALL_XZRO_NO_EFFECT     ((0x0UL) << ADCPPUIC0_ALL_XZRO_Pos)
#define ADCPPUIC0_ALL_XZRO_CLEAR         ((0x1UL) << ADCPPUIC0_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC0       INT
 *  @access     ADC->ADCPPUIC0.bit.INT
 *  @brief      ADCPPU0 interrupt flag clear
 */
#define ADCPPUIC0_ALL_INT_Pos (3)
#define ADCPPUIC0_ALL_INT_Msk (0x1UL << ADCPPUIC0_ALL_INT_Pos)

typedef enum
{
    ADCPPUIC0_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                   */
    ADCPPUIC0_BIT_INT_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU0IF[INT]. This bit is self-cleared.   */
} ADCPPUIC0_BIT_INT;

#define ADCPPUIC0_ALL_INT_NO_EFFECT     ((0x0UL) << ADCPPUIC0_ALL_INT_Pos)
#define ADCPPUIC0_ALL_INT_CLEAR         ((0x1UL) << ADCPPUIC0_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC1       TZLO
 *  @access     ADC->ADCPPUIC1.bit.TZLO
 *  @brief      Latched ADCPPU1 too-low status clear
 */
#define ADCPPUIC1_ALL_TZLO_Pos (0)
#define ADCPPUIC1_ALL_TZLO_Msk (0x1UL << ADCPPUIC1_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIC1_BIT_TZLO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC1_BIT_TZLO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU1IF[TZLO]. This bit is self-cleared.   */
} ADCPPUIC1_BIT_TZLO;

#define ADCPPUIC1_ALL_TZLO_NO_EFFECT     ((0x0UL) << ADCPPUIC1_ALL_TZLO_Pos)
#define ADCPPUIC1_ALL_TZLO_CLEAR         ((0x1UL) << ADCPPUIC1_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC1       TZHI
 *  @access     ADC->ADCPPUIC1.bit.TZHI
 *  @brief      Latched ADCPPU1 too-high status clear
 */
#define ADCPPUIC1_ALL_TZHI_Pos (1)
#define ADCPPUIC1_ALL_TZHI_Msk (0x1UL << ADCPPUIC1_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIC1_BIT_TZHI_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC1_BIT_TZHI_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU1IF[TZHI]. This bit is self-cleared.   */
} ADCPPUIC1_BIT_TZHI;

#define ADCPPUIC1_ALL_TZHI_NO_EFFECT     ((0x0UL) << ADCPPUIC1_ALL_TZHI_Pos)
#define ADCPPUIC1_ALL_TZHI_CLEAR         ((0x1UL) << ADCPPUIC1_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC1       XZRO
 *  @access     ADC->ADCPPUIC1.bit.XZRO
 *  @brief      Latched ADCPPU1 zero-cross status clear
 */
#define ADCPPUIC1_ALL_XZRO_Pos (2)
#define ADCPPUIC1_ALL_XZRO_Msk (0x1UL << ADCPPUIC1_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIC1_BIT_XZRO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC1_BIT_XZRO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU1IF[XZRO]. This bit is self-cleared.   */
} ADCPPUIC1_BIT_XZRO;

#define ADCPPUIC1_ALL_XZRO_NO_EFFECT     ((0x0UL) << ADCPPUIC1_ALL_XZRO_Pos)
#define ADCPPUIC1_ALL_XZRO_CLEAR         ((0x1UL) << ADCPPUIC1_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC1       INT
 *  @access     ADC->ADCPPUIC1.bit.INT
 *  @brief      ADCPPU1 interrupt flag clear
 */
#define ADCPPUIC1_ALL_INT_Pos (3)
#define ADCPPUIC1_ALL_INT_Msk (0x1UL << ADCPPUIC1_ALL_INT_Pos)

typedef enum
{
    ADCPPUIC1_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                   */
    ADCPPUIC1_BIT_INT_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU1IF[INT]. This bit is self-cleared.   */
} ADCPPUIC1_BIT_INT;

#define ADCPPUIC1_ALL_INT_NO_EFFECT     ((0x0UL) << ADCPPUIC1_ALL_INT_Pos)
#define ADCPPUIC1_ALL_INT_CLEAR         ((0x1UL) << ADCPPUIC1_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC2       TZLO
 *  @access     ADC->ADCPPUIC2.bit.TZLO
 *  @brief      Latched ADCPPU2 too-low status clear
 */
#define ADCPPUIC2_ALL_TZLO_Pos (0)
#define ADCPPUIC2_ALL_TZLO_Msk (0x1UL << ADCPPUIC2_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIC2_BIT_TZLO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC2_BIT_TZLO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU2IF[TZLO]. This bit is self-cleared.   */
} ADCPPUIC2_BIT_TZLO;

#define ADCPPUIC2_ALL_TZLO_NO_EFFECT     ((0x0UL) << ADCPPUIC2_ALL_TZLO_Pos)
#define ADCPPUIC2_ALL_TZLO_CLEAR         ((0x1UL) << ADCPPUIC2_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC2       TZHI
 *  @access     ADC->ADCPPUIC2.bit.TZHI
 *  @brief      Latched ADCPPU2 too-high status clear
 */
#define ADCPPUIC2_ALL_TZHI_Pos (1)
#define ADCPPUIC2_ALL_TZHI_Msk (0x1UL << ADCPPUIC2_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIC2_BIT_TZHI_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC2_BIT_TZHI_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU2IF[TZHI]. This bit is self-cleared.   */
} ADCPPUIC2_BIT_TZHI;

#define ADCPPUIC2_ALL_TZHI_NO_EFFECT     ((0x0UL) << ADCPPUIC2_ALL_TZHI_Pos)
#define ADCPPUIC2_ALL_TZHI_CLEAR         ((0x1UL) << ADCPPUIC2_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC2       XZRO
 *  @access     ADC->ADCPPUIC2.bit.XZRO
 *  @brief      Latched ADCPPU2 zero-cross status clear
 */
#define ADCPPUIC2_ALL_XZRO_Pos (2)
#define ADCPPUIC2_ALL_XZRO_Msk (0x1UL << ADCPPUIC2_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIC2_BIT_XZRO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC2_BIT_XZRO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU2IF[XZRO]. This bit is self-cleared.   */
} ADCPPUIC2_BIT_XZRO;

#define ADCPPUIC2_ALL_XZRO_NO_EFFECT     ((0x0UL) << ADCPPUIC2_ALL_XZRO_Pos)
#define ADCPPUIC2_ALL_XZRO_CLEAR         ((0x1UL) << ADCPPUIC2_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC2       INT
 *  @access     ADC->ADCPPUIC2.bit.INT
 *  @brief      ADCPPU2 interrupt flag clear
 */
#define ADCPPUIC2_ALL_INT_Pos (3)
#define ADCPPUIC2_ALL_INT_Msk (0x1UL << ADCPPUIC2_ALL_INT_Pos)

typedef enum
{
    ADCPPUIC2_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                   */
    ADCPPUIC2_BIT_INT_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU2IF[INT]. This bit is self-cleared.   */
} ADCPPUIC2_BIT_INT;

#define ADCPPUIC2_ALL_INT_NO_EFFECT     ((0x0UL) << ADCPPUIC2_ALL_INT_Pos)
#define ADCPPUIC2_ALL_INT_CLEAR         ((0x1UL) << ADCPPUIC2_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC3       TZLO
 *  @access     ADC->ADCPPUIC3.bit.TZLO
 *  @brief      Latched ADCPPU3 too-low status clear
 */
#define ADCPPUIC3_ALL_TZLO_Pos (0)
#define ADCPPUIC3_ALL_TZLO_Msk (0x1UL << ADCPPUIC3_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIC3_BIT_TZLO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC3_BIT_TZLO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU3IF[TZLO]. This bit is self-cleared.   */
} ADCPPUIC3_BIT_TZLO;

#define ADCPPUIC3_ALL_TZLO_NO_EFFECT     ((0x0UL) << ADCPPUIC3_ALL_TZLO_Pos)
#define ADCPPUIC3_ALL_TZLO_CLEAR         ((0x1UL) << ADCPPUIC3_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC3       TZHI
 *  @access     ADC->ADCPPUIC3.bit.TZHI
 *  @brief      Latched ADCPPU3 too-high status clear
 */
#define ADCPPUIC3_ALL_TZHI_Pos (1)
#define ADCPPUIC3_ALL_TZHI_Msk (0x1UL << ADCPPUIC3_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIC3_BIT_TZHI_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC3_BIT_TZHI_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU3IF[TZHI]. This bit is self-cleared.   */
} ADCPPUIC3_BIT_TZHI;

#define ADCPPUIC3_ALL_TZHI_NO_EFFECT     ((0x0UL) << ADCPPUIC3_ALL_TZHI_Pos)
#define ADCPPUIC3_ALL_TZHI_CLEAR         ((0x1UL) << ADCPPUIC3_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC3       XZRO
 *  @access     ADC->ADCPPUIC3.bit.XZRO
 *  @brief      Latched ADCPPU3 zero-cross status clear
 */
#define ADCPPUIC3_ALL_XZRO_Pos (2)
#define ADCPPUIC3_ALL_XZRO_Msk (0x1UL << ADCPPUIC3_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIC3_BIT_XZRO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC3_BIT_XZRO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU3IF[XZRO]. This bit is self-cleared.   */
} ADCPPUIC3_BIT_XZRO;

#define ADCPPUIC3_ALL_XZRO_NO_EFFECT     ((0x0UL) << ADCPPUIC3_ALL_XZRO_Pos)
#define ADCPPUIC3_ALL_XZRO_CLEAR         ((0x1UL) << ADCPPUIC3_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC3       INT
 *  @access     ADC->ADCPPUIC3.bit.INT
 *  @brief      ADCPPU3 interrupt flag clear
 */
#define ADCPPUIC3_ALL_INT_Pos (3)
#define ADCPPUIC3_ALL_INT_Msk (0x1UL << ADCPPUIC3_ALL_INT_Pos)

typedef enum
{
    ADCPPUIC3_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                   */
    ADCPPUIC3_BIT_INT_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU3IF[INT]. This bit is self-cleared.   */
} ADCPPUIC3_BIT_INT;

#define ADCPPUIC3_ALL_INT_NO_EFFECT     ((0x0UL) << ADCPPUIC3_ALL_INT_Pos)
#define ADCPPUIC3_ALL_INT_CLEAR         ((0x1UL) << ADCPPUIC3_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC4       TZLO
 *  @access     ADC->ADCPPUIC4.bit.TZLO
 *  @brief      Latched ADCPPU4 too-low status clear
 */
#define ADCPPUIC4_ALL_TZLO_Pos (0)
#define ADCPPUIC4_ALL_TZLO_Msk (0x1UL << ADCPPUIC4_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIC4_BIT_TZLO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC4_BIT_TZLO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU4IF[TZLO]. This bit is self-cleared.   */
} ADCPPUIC4_BIT_TZLO;

#define ADCPPUIC4_ALL_TZLO_NO_EFFECT     ((0x0UL) << ADCPPUIC4_ALL_TZLO_Pos)
#define ADCPPUIC4_ALL_TZLO_CLEAR         ((0x1UL) << ADCPPUIC4_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC4       TZHI
 *  @access     ADC->ADCPPUIC4.bit.TZHI
 *  @brief      Latched ADCPPU4 too-high status clear
 */
#define ADCPPUIC4_ALL_TZHI_Pos (1)
#define ADCPPUIC4_ALL_TZHI_Msk (0x1UL << ADCPPUIC4_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIC4_BIT_TZHI_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC4_BIT_TZHI_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU4IF[TZHI]. This bit is self-cleared.   */
} ADCPPUIC4_BIT_TZHI;

#define ADCPPUIC4_ALL_TZHI_NO_EFFECT     ((0x0UL) << ADCPPUIC4_ALL_TZHI_Pos)
#define ADCPPUIC4_ALL_TZHI_CLEAR         ((0x1UL) << ADCPPUIC4_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC4       XZRO
 *  @access     ADC->ADCPPUIC4.bit.XZRO
 *  @brief      Latched ADCPPU4 zero-cross status clear
 */
#define ADCPPUIC4_ALL_XZRO_Pos (2)
#define ADCPPUIC4_ALL_XZRO_Msk (0x1UL << ADCPPUIC4_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIC4_BIT_XZRO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC4_BIT_XZRO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU4IF[XZRO]. This bit is self-cleared.   */
} ADCPPUIC4_BIT_XZRO;

#define ADCPPUIC4_ALL_XZRO_NO_EFFECT     ((0x0UL) << ADCPPUIC4_ALL_XZRO_Pos)
#define ADCPPUIC4_ALL_XZRO_CLEAR         ((0x1UL) << ADCPPUIC4_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC4       INT
 *  @access     ADC->ADCPPUIC4.bit.INT
 *  @brief      ADCPPU4 interrupt flag clear
 */
#define ADCPPUIC4_ALL_INT_Pos (3)
#define ADCPPUIC4_ALL_INT_Msk (0x1UL << ADCPPUIC4_ALL_INT_Pos)

typedef enum
{
    ADCPPUIC4_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                   */
    ADCPPUIC4_BIT_INT_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU4IF[INT]. This bit is self-cleared.   */
} ADCPPUIC4_BIT_INT;

#define ADCPPUIC4_ALL_INT_NO_EFFECT     ((0x0UL) << ADCPPUIC4_ALL_INT_Pos)
#define ADCPPUIC4_ALL_INT_CLEAR         ((0x1UL) << ADCPPUIC4_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC5       TZLO
 *  @access     ADC->ADCPPUIC5.bit.TZLO
 *  @brief      Latched ADCPPU5 too-low status clear
 */
#define ADCPPUIC5_ALL_TZLO_Pos (0)
#define ADCPPUIC5_ALL_TZLO_Msk (0x1UL << ADCPPUIC5_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIC5_BIT_TZLO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC5_BIT_TZLO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU5IF[TZLO]. This bit is self-cleared.   */
} ADCPPUIC5_BIT_TZLO;

#define ADCPPUIC5_ALL_TZLO_NO_EFFECT     ((0x0UL) << ADCPPUIC5_ALL_TZLO_Pos)
#define ADCPPUIC5_ALL_TZLO_CLEAR         ((0x1UL) << ADCPPUIC5_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC5       TZHI
 *  @access     ADC->ADCPPUIC5.bit.TZHI
 *  @brief      Latched ADCPPU5 too-high status clear
 */
#define ADCPPUIC5_ALL_TZHI_Pos (1)
#define ADCPPUIC5_ALL_TZHI_Msk (0x1UL << ADCPPUIC5_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIC5_BIT_TZHI_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC5_BIT_TZHI_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU5IF[TZHI]. This bit is self-cleared.   */
} ADCPPUIC5_BIT_TZHI;

#define ADCPPUIC5_ALL_TZHI_NO_EFFECT     ((0x0UL) << ADCPPUIC5_ALL_TZHI_Pos)
#define ADCPPUIC5_ALL_TZHI_CLEAR         ((0x1UL) << ADCPPUIC5_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC5       XZRO
 *  @access     ADC->ADCPPUIC5.bit.XZRO
 *  @brief      Latched ADCPPU5 zero-cross status clear
 */
#define ADCPPUIC5_ALL_XZRO_Pos (2)
#define ADCPPUIC5_ALL_XZRO_Msk (0x1UL << ADCPPUIC5_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIC5_BIT_XZRO_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                    */
    ADCPPUIC5_BIT_XZRO_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU5IF[XZRO]. This bit is self-cleared.   */
} ADCPPUIC5_BIT_XZRO;

#define ADCPPUIC5_ALL_XZRO_NO_EFFECT     ((0x0UL) << ADCPPUIC5_ALL_XZRO_Pos)
#define ADCPPUIC5_ALL_XZRO_CLEAR         ((0x1UL) << ADCPPUIC5_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIC5       INT
 *  @access     ADC->ADCPPUIC5.bit.INT
 *  @brief      ADCPPU5 interrupt flag clear
 */
#define ADCPPUIC5_ALL_INT_Pos (3)
#define ADCPPUIC5_ALL_INT_Msk (0x1UL << ADCPPUIC5_ALL_INT_Pos)

typedef enum
{
    ADCPPUIC5_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always readback 0                   */
    ADCPPUIC5_BIT_INT_CLEAR         = 1,  /*!< Write a 1 clears ADCPPU5IF[INT]. This bit is self-cleared.   */
} ADCPPUIC5_BIT_INT;

#define ADCPPUIC5_ALL_INT_NO_EFFECT     ((0x0UL) << ADCPPUIC5_ALL_INT_Pos)
#define ADCPPUIC5_ALL_INT_CLEAR         ((0x1UL) << ADCPPUIC5_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE0       TZLO
 *  @access     ADC->ADCPPUIE0.bit.TZLO
 *  @brief      Enable ADCPPU0 too-low as ADCPPU0 interrupt source
 */
#define ADCPPUIE0_ALL_TZLO_Pos (0)
#define ADCPPUIE0_ALL_TZLO_Msk (0x1UL << ADCPPUIE0_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIE0_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE0_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE0_BIT_TZLO;

#define ADCPPUIE0_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUIE0_ALL_TZLO_Pos)
#define ADCPPUIE0_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUIE0_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE0       TZHI
 *  @access     ADC->ADCPPUIE0.bit.TZHI
 *  @brief      Enable ADCPPU0 too-high as ADCPPU0 interrupt source
 */
#define ADCPPUIE0_ALL_TZHI_Pos (1)
#define ADCPPUIE0_ALL_TZHI_Msk (0x1UL << ADCPPUIE0_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIE0_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE0_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE0_BIT_TZHI;

#define ADCPPUIE0_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUIE0_ALL_TZHI_Pos)
#define ADCPPUIE0_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUIE0_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE0       XZRO
 *  @access     ADC->ADCPPUIE0.bit.XZRO
 *  @brief      Enable ADCPPU0 zero-cross as ADCPPU0 interrupt source
 */
#define ADCPPUIE0_ALL_XZRO_Pos (2)
#define ADCPPUIE0_ALL_XZRO_Msk (0x1UL << ADCPPUIE0_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIE0_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE0_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE0_BIT_XZRO;

#define ADCPPUIE0_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUIE0_ALL_XZRO_Pos)
#define ADCPPUIE0_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUIE0_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE1       TZLO
 *  @access     ADC->ADCPPUIE1.bit.TZLO
 *  @brief      Enable ADCPPU1 too-low as ADCPPU1 interrupt source
 */
#define ADCPPUIE1_ALL_TZLO_Pos (0)
#define ADCPPUIE1_ALL_TZLO_Msk (0x1UL << ADCPPUIE1_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIE1_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE1_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE1_BIT_TZLO;

#define ADCPPUIE1_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUIE1_ALL_TZLO_Pos)
#define ADCPPUIE1_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUIE1_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE1       TZHI
 *  @access     ADC->ADCPPUIE1.bit.TZHI
 *  @brief      Enable ADCPPU1 too-high as ADCPPU1 interrupt source
 */
#define ADCPPUIE1_ALL_TZHI_Pos (1)
#define ADCPPUIE1_ALL_TZHI_Msk (0x1UL << ADCPPUIE1_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIE1_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE1_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE1_BIT_TZHI;

#define ADCPPUIE1_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUIE1_ALL_TZHI_Pos)
#define ADCPPUIE1_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUIE1_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE1       XZRO
 *  @access     ADC->ADCPPUIE1.bit.XZRO
 *  @brief      Enable ADCPPU1 zero-cross as ADCPPU1 interrupt source
 */
#define ADCPPUIE1_ALL_XZRO_Pos (2)
#define ADCPPUIE1_ALL_XZRO_Msk (0x1UL << ADCPPUIE1_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIE1_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE1_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE1_BIT_XZRO;

#define ADCPPUIE1_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUIE1_ALL_XZRO_Pos)
#define ADCPPUIE1_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUIE1_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE2       TZLO
 *  @access     ADC->ADCPPUIE2.bit.TZLO
 *  @brief      Enable ADCPPU2 too-low as ADCPPU2 interrupt source
 */
#define ADCPPUIE2_ALL_TZLO_Pos (0)
#define ADCPPUIE2_ALL_TZLO_Msk (0x1UL << ADCPPUIE2_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIE2_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE2_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE2_BIT_TZLO;

#define ADCPPUIE2_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUIE2_ALL_TZLO_Pos)
#define ADCPPUIE2_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUIE2_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE2       TZHI
 *  @access     ADC->ADCPPUIE2.bit.TZHI
 *  @brief      Enable ADCPPU2 too-high as ADCPPU2 interrupt source
 */
#define ADCPPUIE2_ALL_TZHI_Pos (1)
#define ADCPPUIE2_ALL_TZHI_Msk (0x1UL << ADCPPUIE2_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIE2_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE2_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE2_BIT_TZHI;

#define ADCPPUIE2_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUIE2_ALL_TZHI_Pos)
#define ADCPPUIE2_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUIE2_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE2       XZRO
 *  @access     ADC->ADCPPUIE2.bit.XZRO
 *  @brief      Enable ADCPPU2 zero-cross as ADCPPU2 interrupt source
 */
#define ADCPPUIE2_ALL_XZRO_Pos (2)
#define ADCPPUIE2_ALL_XZRO_Msk (0x1UL << ADCPPUIE2_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIE2_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE2_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE2_BIT_XZRO;

#define ADCPPUIE2_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUIE2_ALL_XZRO_Pos)
#define ADCPPUIE2_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUIE2_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE3       TZLO
 *  @access     ADC->ADCPPUIE3.bit.TZLO
 *  @brief      Enable ADCPPU3 too-low as ADCPPU3 interrupt source
 */
#define ADCPPUIE3_ALL_TZLO_Pos (0)
#define ADCPPUIE3_ALL_TZLO_Msk (0x1UL << ADCPPUIE3_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIE3_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE3_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE3_BIT_TZLO;

#define ADCPPUIE3_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUIE3_ALL_TZLO_Pos)
#define ADCPPUIE3_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUIE3_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE3       TZHI
 *  @access     ADC->ADCPPUIE3.bit.TZHI
 *  @brief      Enable ADCPPU3 too-high as ADCPPU3 interrupt source
 */
#define ADCPPUIE3_ALL_TZHI_Pos (1)
#define ADCPPUIE3_ALL_TZHI_Msk (0x1UL << ADCPPUIE3_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIE3_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE3_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE3_BIT_TZHI;

#define ADCPPUIE3_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUIE3_ALL_TZHI_Pos)
#define ADCPPUIE3_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUIE3_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE3       XZRO
 *  @access     ADC->ADCPPUIE3.bit.XZRO
 *  @brief      Enable ADCPPU3 zero-cross as ADCPPU3 interrupt source
 */
#define ADCPPUIE3_ALL_XZRO_Pos (2)
#define ADCPPUIE3_ALL_XZRO_Msk (0x1UL << ADCPPUIE3_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIE3_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE3_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE3_BIT_XZRO;

#define ADCPPUIE3_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUIE3_ALL_XZRO_Pos)
#define ADCPPUIE3_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUIE3_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE4       TZLO
 *  @access     ADC->ADCPPUIE4.bit.TZLO
 *  @brief      Enable ADCPPU4 too-low as ADCPPU4 interrupt source
 */
#define ADCPPUIE4_ALL_TZLO_Pos (0)
#define ADCPPUIE4_ALL_TZLO_Msk (0x1UL << ADCPPUIE4_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIE4_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE4_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE4_BIT_TZLO;

#define ADCPPUIE4_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUIE4_ALL_TZLO_Pos)
#define ADCPPUIE4_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUIE4_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE4       TZHI
 *  @access     ADC->ADCPPUIE4.bit.TZHI
 *  @brief      Enable ADCPPU4 too-high as ADCPPU4 interrupt source
 */
#define ADCPPUIE4_ALL_TZHI_Pos (1)
#define ADCPPUIE4_ALL_TZHI_Msk (0x1UL << ADCPPUIE4_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIE4_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE4_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE4_BIT_TZHI;

#define ADCPPUIE4_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUIE4_ALL_TZHI_Pos)
#define ADCPPUIE4_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUIE4_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE4       XZRO
 *  @access     ADC->ADCPPUIE4.bit.XZRO
 *  @brief      Enable ADCPPU4 zero-cross as ADCPPU4 interrupt source
 */
#define ADCPPUIE4_ALL_XZRO_Pos (2)
#define ADCPPUIE4_ALL_XZRO_Msk (0x1UL << ADCPPUIE4_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIE4_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE4_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE4_BIT_XZRO;

#define ADCPPUIE4_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUIE4_ALL_XZRO_Pos)
#define ADCPPUIE4_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUIE4_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE5       TZLO
 *  @access     ADC->ADCPPUIE5.bit.TZLO
 *  @brief      Enable ADCPPU5 too-low as ADCPPU5 interrupt source
 */
#define ADCPPUIE5_ALL_TZLO_Pos (0)
#define ADCPPUIE5_ALL_TZLO_Msk (0x1UL << ADCPPUIE5_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUIE5_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE5_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE5_BIT_TZLO;

#define ADCPPUIE5_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUIE5_ALL_TZLO_Pos)
#define ADCPPUIE5_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUIE5_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE5       TZHI
 *  @access     ADC->ADCPPUIE5.bit.TZHI
 *  @brief      Enable ADCPPU5 too-high as ADCPPU5 interrupt source
 */
#define ADCPPUIE5_ALL_TZHI_Pos (1)
#define ADCPPUIE5_ALL_TZHI_Msk (0x1UL << ADCPPUIE5_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUIE5_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE5_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE5_BIT_TZHI;

#define ADCPPUIE5_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUIE5_ALL_TZHI_Pos)
#define ADCPPUIE5_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUIE5_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUIE5       XZRO
 *  @access     ADC->ADCPPUIE5.bit.XZRO
 *  @brief      Enable ADCPPU5 zero-cross as ADCPPU5 interrupt source
 */
#define ADCPPUIE5_ALL_XZRO_Pos (2)
#define ADCPPUIE5_ALL_XZRO_Msk (0x1UL << ADCPPUIE5_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUIE5_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUIE5_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUIE5_BIT_XZRO;

#define ADCPPUIE5_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUIE5_ALL_XZRO_Pos)
#define ADCPPUIE5_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUIE5_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE0      TZLO
 *  @access     ADC->ADCPPUTZE0.bit.TZLO
 *  @brief      Enable ADCPPU0 too-low as ADCPPU0 trip-zone event
 */
#define ADCPPUTZE0_ALL_TZLO_Pos (0)
#define ADCPPUTZE0_ALL_TZLO_Msk (0x1UL << ADCPPUTZE0_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUTZE0_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE0_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE0_BIT_TZLO;

#define ADCPPUTZE0_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUTZE0_ALL_TZLO_Pos)
#define ADCPPUTZE0_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUTZE0_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE0      TZHI
 *  @access     ADC->ADCPPUTZE0.bit.TZHI
 *  @brief      Enable ADCPPU0 too-high as ADCPPU0 trip-zone event
 */
#define ADCPPUTZE0_ALL_TZHI_Pos (1)
#define ADCPPUTZE0_ALL_TZHI_Msk (0x1UL << ADCPPUTZE0_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUTZE0_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE0_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE0_BIT_TZHI;

#define ADCPPUTZE0_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUTZE0_ALL_TZHI_Pos)
#define ADCPPUTZE0_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUTZE0_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE0      XZRO
 *  @access     ADC->ADCPPUTZE0.bit.XZRO
 *  @brief      Enable ADCPPU0 zero-cross as ADCPPU0 trip-zone event
 */
#define ADCPPUTZE0_ALL_XZRO_Pos (2)
#define ADCPPUTZE0_ALL_XZRO_Msk (0x1UL << ADCPPUTZE0_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUTZE0_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE0_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE0_BIT_XZRO;

#define ADCPPUTZE0_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUTZE0_ALL_XZRO_Pos)
#define ADCPPUTZE0_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUTZE0_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE1      TZLO
 *  @access     ADC->ADCPPUTZE1.bit.TZLO
 *  @brief      Enable ADCPPU1 too-low as ADCPPU1 trip-zone event
 */
#define ADCPPUTZE1_ALL_TZLO_Pos (0)
#define ADCPPUTZE1_ALL_TZLO_Msk (0x1UL << ADCPPUTZE1_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUTZE1_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE1_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE1_BIT_TZLO;

#define ADCPPUTZE1_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUTZE1_ALL_TZLO_Pos)
#define ADCPPUTZE1_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUTZE1_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE1      TZHI
 *  @access     ADC->ADCPPUTZE1.bit.TZHI
 *  @brief      Enable ADCPPU1 too-high as ADCPPU1 trip-zone event
 */
#define ADCPPUTZE1_ALL_TZHI_Pos (1)
#define ADCPPUTZE1_ALL_TZHI_Msk (0x1UL << ADCPPUTZE1_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUTZE1_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE1_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE1_BIT_TZHI;

#define ADCPPUTZE1_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUTZE1_ALL_TZHI_Pos)
#define ADCPPUTZE1_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUTZE1_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE1      XZRO
 *  @access     ADC->ADCPPUTZE1.bit.XZRO
 *  @brief      Enable ADCPPU1 zero-cross as ADCPPU1 trip-zone event
 */
#define ADCPPUTZE1_ALL_XZRO_Pos (2)
#define ADCPPUTZE1_ALL_XZRO_Msk (0x1UL << ADCPPUTZE1_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUTZE1_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE1_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE1_BIT_XZRO;

#define ADCPPUTZE1_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUTZE1_ALL_XZRO_Pos)
#define ADCPPUTZE1_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUTZE1_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE2      TZLO
 *  @access     ADC->ADCPPUTZE2.bit.TZLO
 *  @brief      Enable ADCPPU2 too-low as ADCPPU2 trip-zone event
 */
#define ADCPPUTZE2_ALL_TZLO_Pos (0)
#define ADCPPUTZE2_ALL_TZLO_Msk (0x1UL << ADCPPUTZE2_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUTZE2_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE2_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE2_BIT_TZLO;

#define ADCPPUTZE2_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUTZE2_ALL_TZLO_Pos)
#define ADCPPUTZE2_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUTZE2_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE2      TZHI
 *  @access     ADC->ADCPPUTZE2.bit.TZHI
 *  @brief      Enable ADCPPU2 too-high as ADCPPU2 trip-zone event
 */
#define ADCPPUTZE2_ALL_TZHI_Pos (1)
#define ADCPPUTZE2_ALL_TZHI_Msk (0x1UL << ADCPPUTZE2_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUTZE2_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE2_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE2_BIT_TZHI;

#define ADCPPUTZE2_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUTZE2_ALL_TZHI_Pos)
#define ADCPPUTZE2_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUTZE2_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE2      XZRO
 *  @access     ADC->ADCPPUTZE2.bit.XZRO
 *  @brief      Enable ADCPPU2 zero-cross as ADCPPU2 trip-zone event
 */
#define ADCPPUTZE2_ALL_XZRO_Pos (2)
#define ADCPPUTZE2_ALL_XZRO_Msk (0x1UL << ADCPPUTZE2_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUTZE2_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE2_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE2_BIT_XZRO;

#define ADCPPUTZE2_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUTZE2_ALL_XZRO_Pos)
#define ADCPPUTZE2_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUTZE2_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE3      TZLO
 *  @access     ADC->ADCPPUTZE3.bit.TZLO
 *  @brief      Enable ADCPPU3 too-low as ADCPPU3 trip-zone event
 */
#define ADCPPUTZE3_ALL_TZLO_Pos (0)
#define ADCPPUTZE3_ALL_TZLO_Msk (0x1UL << ADCPPUTZE3_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUTZE3_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE3_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE3_BIT_TZLO;

#define ADCPPUTZE3_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUTZE3_ALL_TZLO_Pos)
#define ADCPPUTZE3_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUTZE3_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE3      TZHI
 *  @access     ADC->ADCPPUTZE3.bit.TZHI
 *  @brief      Enable ADCPPU3 too-high as ADCPPU3 trip-zone event
 */
#define ADCPPUTZE3_ALL_TZHI_Pos (1)
#define ADCPPUTZE3_ALL_TZHI_Msk (0x1UL << ADCPPUTZE3_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUTZE3_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE3_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE3_BIT_TZHI;

#define ADCPPUTZE3_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUTZE3_ALL_TZHI_Pos)
#define ADCPPUTZE3_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUTZE3_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE3      XZRO
 *  @access     ADC->ADCPPUTZE3.bit.XZRO
 *  @brief      Enable ADCPPU3 zero-cross as ADCPPU3 trip-zone event
 */
#define ADCPPUTZE3_ALL_XZRO_Pos (2)
#define ADCPPUTZE3_ALL_XZRO_Msk (0x1UL << ADCPPUTZE3_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUTZE3_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE3_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE3_BIT_XZRO;

#define ADCPPUTZE3_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUTZE3_ALL_XZRO_Pos)
#define ADCPPUTZE3_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUTZE3_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE4      TZLO
 *  @access     ADC->ADCPPUTZE4.bit.TZLO
 *  @brief      Enable ADCPPU4 too-low as ADCPPU4 trip-zone event
 */
#define ADCPPUTZE4_ALL_TZLO_Pos (0)
#define ADCPPUTZE4_ALL_TZLO_Msk (0x1UL << ADCPPUTZE4_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUTZE4_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE4_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE4_BIT_TZLO;

#define ADCPPUTZE4_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUTZE4_ALL_TZLO_Pos)
#define ADCPPUTZE4_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUTZE4_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE4      TZHI
 *  @access     ADC->ADCPPUTZE4.bit.TZHI
 *  @brief      Enable ADCPPU4 too-high as ADCPPU4 trip-zone event
 */
#define ADCPPUTZE4_ALL_TZHI_Pos (1)
#define ADCPPUTZE4_ALL_TZHI_Msk (0x1UL << ADCPPUTZE4_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUTZE4_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE4_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE4_BIT_TZHI;

#define ADCPPUTZE4_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUTZE4_ALL_TZHI_Pos)
#define ADCPPUTZE4_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUTZE4_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE4      XZRO
 *  @access     ADC->ADCPPUTZE4.bit.XZRO
 *  @brief      Enable ADCPPU4 zero-cross as ADCPPU4 trip-zone event
 */
#define ADCPPUTZE4_ALL_XZRO_Pos (2)
#define ADCPPUTZE4_ALL_XZRO_Msk (0x1UL << ADCPPUTZE4_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUTZE4_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE4_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE4_BIT_XZRO;

#define ADCPPUTZE4_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUTZE4_ALL_XZRO_Pos)
#define ADCPPUTZE4_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUTZE4_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE5      TZLO
 *  @access     ADC->ADCPPUTZE5.bit.TZLO
 *  @brief      Enable ADCPPU5 too-low as ADCPPU5 trip-zone event
 */
#define ADCPPUTZE5_ALL_TZLO_Pos (0)
#define ADCPPUTZE5_ALL_TZLO_Msk (0x1UL << ADCPPUTZE5_ALL_TZLO_Pos)

typedef enum
{
    ADCPPUTZE5_BIT_TZLO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE5_BIT_TZLO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE5_BIT_TZLO;

#define ADCPPUTZE5_ALL_TZLO_DISABLE     ((0x0UL) << ADCPPUTZE5_ALL_TZLO_Pos)
#define ADCPPUTZE5_ALL_TZLO_ENABLE      ((0x1UL) << ADCPPUTZE5_ALL_TZLO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE5      TZHI
 *  @access     ADC->ADCPPUTZE5.bit.TZHI
 *  @brief      Enable ADCPPU5 too-high as ADCPPU5 trip-zone event
 */
#define ADCPPUTZE5_ALL_TZHI_Pos (1)
#define ADCPPUTZE5_ALL_TZHI_Msk (0x1UL << ADCPPUTZE5_ALL_TZHI_Pos)

typedef enum
{
    ADCPPUTZE5_BIT_TZHI_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE5_BIT_TZHI_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE5_BIT_TZHI;

#define ADCPPUTZE5_ALL_TZHI_DISABLE     ((0x0UL) << ADCPPUTZE5_ALL_TZHI_Pos)
#define ADCPPUTZE5_ALL_TZHI_ENABLE      ((0x1UL) << ADCPPUTZE5_ALL_TZHI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTZE5      XZRO
 *  @access     ADC->ADCPPUTZE5.bit.XZRO
 *  @brief      Enable ADCPPU5 zero-cross as ADCPPU5 trip-zone event
 */
#define ADCPPUTZE5_ALL_XZRO_Pos (2)
#define ADCPPUTZE5_ALL_XZRO_Msk (0x1UL << ADCPPUTZE5_ALL_XZRO_Pos)

typedef enum
{
    ADCPPUTZE5_BIT_XZRO_DISABLE     = 0,  /*!< Disable   */
    ADCPPUTZE5_BIT_XZRO_ENABLE      = 1,  /*!< Enable    */
} ADCPPUTZE5_BIT_XZRO;

#define ADCPPUTZE5_ALL_XZRO_DISABLE     ((0x0UL) << ADCPPUTZE5_ALL_XZRO_Pos)
#define ADCPPUTZE5_ALL_XZRO_ENABLE      ((0x1UL) << ADCPPUTZE5_ALL_XZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL0      EN
 *  @access     ADC->ADCPPUCTL0.bit.EN
 *  @brief      ADCPPU0 enable
 */
#define ADCPPUCTL0_ALL_EN_Pos (0)
#define ADCPPUCTL0_ALL_EN_Msk (0x1UL << ADCPPUCTL0_ALL_EN_Pos)

typedef enum
{
    ADCPPUCTL0_BIT_EN_DISABLE     = 0,  /*!< Disable ADCPPU0   */
    ADCPPUCTL0_BIT_EN_ENABLE      = 1,  /*!< Enable ADCPPU0    */
} ADCPPUCTL0_BIT_EN;

#define ADCPPUCTL0_ALL_EN_DISABLE     ((0x0UL) << ADCPPUCTL0_ALL_EN_Pos)
#define ADCPPUCTL0_ALL_EN_ENABLE      ((0x1UL) << ADCPPUCTL0_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL0      CBCEN
 *  @access     ADC->ADCPPUCTL0.bit.CBCEN
 *  @brief      ADCPPU0 cycle-by-cycle clear enable
 */
#define ADCPPUCTL0_ALL_CBCEN_Pos (1)
#define ADCPPUCTL0_ALL_CBCEN_Msk (0x1UL << ADCPPUCTL0_ALL_CBCEN_Pos)

typedef enum
{
    ADCPPUCTL0_BIT_CBCEN_DISABLE     = 0,  /*!< Disable ADCPPU0 cycle-by-cycle clear   */
    ADCPPUCTL0_BIT_CBCEN_ENABLE      = 1,  /*!< Enable ADCPPU0 cycle-by-cycle clear    */
} ADCPPUCTL0_BIT_CBCEN;

#define ADCPPUCTL0_ALL_CBCEN_DISABLE     ((0x0UL) << ADCPPUCTL0_ALL_CBCEN_Pos)
#define ADCPPUCTL0_ALL_CBCEN_ENABLE      ((0x1UL) << ADCPPUCTL0_ALL_CBCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL0      SOCSEL
 *  @access     ADC->ADCPPUCTL0.bit.SOCSEL
 *  @brief      Select the SOC signal to derive the ADCPPU0SOCDLY
 */
#define ADCPPUCTL0_ALL_SOCSEL_Pos (2)
#define ADCPPUCTL0_ALL_SOCSEL_Msk (0xFUL << ADCPPUCTL0_ALL_SOCSEL_Pos)

#define ADCPPUCTL0_BIT_SOCSEL

#define ADCPPUCTL0_ALL_SOCSEL_(x) ((x) << ADCPPUCTL0_ALL_SOCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL0      DATASEL
 *  @access     ADC->ADCPPUCTL0.bit.DATASEL
 *  @brief      Select the ADC result to compare with the reference
 */
#define ADCPPUCTL0_ALL_DATASEL_Pos (6)
#define ADCPPUCTL0_ALL_DATASEL_Msk (0xFUL << ADCPPUCTL0_ALL_DATASEL_Pos)

#define ADCPPUCTL0_BIT_DATASEL

#define ADCPPUCTL0_ALL_DATASEL_(x) ((x) << ADCPPUCTL0_ALL_DATASEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL0      POL
 *  @access     ADC->ADCPPUCTL0.bit.POL
 *  @brief      Polarity for comparison
 */
#define ADCPPUCTL0_ALL_POL_Pos (10)
#define ADCPPUCTL0_ALL_POL_Msk (0x1UL << ADCPPUCTL0_ALL_POL_Pos)

typedef enum
{
    ADCPPUCTL0_BIT_POL_REF_MINUS_CODE     = 0,  /*!< ADCPPU0 result is the reference minus the selected result   */
    ADCPPUCTL0_BIT_POL_CODE_MINUS_REF     = 1,  /*!< ADCPPU0 result is the selected result minus the reference   */
} ADCPPUCTL0_BIT_POL;

#define ADCPPUCTL0_ALL_POL_REF_MINUS_CODE     ((0x0UL) << ADCPPUCTL0_ALL_POL_Pos)
#define ADCPPUCTL0_ALL_POL_CODE_MINUS_REF     ((0x1UL) << ADCPPUCTL0_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL1      EN
 *  @access     ADC->ADCPPUCTL1.bit.EN
 *  @brief      ADCPPU1 enable
 */
#define ADCPPUCTL1_ALL_EN_Pos (0)
#define ADCPPUCTL1_ALL_EN_Msk (0x1UL << ADCPPUCTL1_ALL_EN_Pos)

typedef enum
{
    ADCPPUCTL1_BIT_EN_DISABLE     = 0,  /*!< Disable ADCPPU1   */
    ADCPPUCTL1_BIT_EN_ENABLE      = 1,  /*!< Enable ADCPPU1    */
} ADCPPUCTL1_BIT_EN;

#define ADCPPUCTL1_ALL_EN_DISABLE     ((0x0UL) << ADCPPUCTL1_ALL_EN_Pos)
#define ADCPPUCTL1_ALL_EN_ENABLE      ((0x1UL) << ADCPPUCTL1_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL1      CBCEN
 *  @access     ADC->ADCPPUCTL1.bit.CBCEN
 *  @brief      ADCPPU1 cycle-by-cycle clear enable
 */
#define ADCPPUCTL1_ALL_CBCEN_Pos (1)
#define ADCPPUCTL1_ALL_CBCEN_Msk (0x1UL << ADCPPUCTL1_ALL_CBCEN_Pos)

typedef enum
{
    ADCPPUCTL1_BIT_CBCEN_DISABLE     = 0,  /*!< Disable ADCPPU1 cycle-by-cycle clear   */
    ADCPPUCTL1_BIT_CBCEN_ENABLE      = 1,  /*!< Enable ADCPPU1 cycle-by-cycle clear    */
} ADCPPUCTL1_BIT_CBCEN;

#define ADCPPUCTL1_ALL_CBCEN_DISABLE     ((0x0UL) << ADCPPUCTL1_ALL_CBCEN_Pos)
#define ADCPPUCTL1_ALL_CBCEN_ENABLE      ((0x1UL) << ADCPPUCTL1_ALL_CBCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL1      SOCSEL
 *  @access     ADC->ADCPPUCTL1.bit.SOCSEL
 *  @brief      Select the SOC signal to derive the ADCPPU0SOCDLY
 */
#define ADCPPUCTL1_ALL_SOCSEL_Pos (2)
#define ADCPPUCTL1_ALL_SOCSEL_Msk (0xFUL << ADCPPUCTL1_ALL_SOCSEL_Pos)

#define ADCPPUCTL1_BIT_SOCSEL

#define ADCPPUCTL1_ALL_SOCSEL_(x) ((x) << ADCPPUCTL1_ALL_SOCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL1      DATASEL
 *  @access     ADC->ADCPPUCTL1.bit.DATASEL
 *  @brief      Select the ADC result to compare with the reference
 */
#define ADCPPUCTL1_ALL_DATASEL_Pos (6)
#define ADCPPUCTL1_ALL_DATASEL_Msk (0xFUL << ADCPPUCTL1_ALL_DATASEL_Pos)

#define ADCPPUCTL1_BIT_DATASEL

#define ADCPPUCTL1_ALL_DATASEL_(x) ((x) << ADCPPUCTL1_ALL_DATASEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL1      POL
 *  @access     ADC->ADCPPUCTL1.bit.POL
 *  @brief      Polarity for comparison
 */
#define ADCPPUCTL1_ALL_POL_Pos (10)
#define ADCPPUCTL1_ALL_POL_Msk (0x1UL << ADCPPUCTL1_ALL_POL_Pos)

typedef enum
{
    ADCPPUCTL1_BIT_POL_REF_MINUS_CODE     = 0,  /*!< ADCPPU1 result is the reference minus the selected result   */
    ADCPPUCTL1_BIT_POL_CODE_MINUS_REF     = 1,  /*!< ADCPPU1 result is the selected result minus the reference   */
} ADCPPUCTL1_BIT_POL;

#define ADCPPUCTL1_ALL_POL_REF_MINUS_CODE     ((0x0UL) << ADCPPUCTL1_ALL_POL_Pos)
#define ADCPPUCTL1_ALL_POL_CODE_MINUS_REF     ((0x1UL) << ADCPPUCTL1_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL2      EN
 *  @access     ADC->ADCPPUCTL2.bit.EN
 *  @brief      ADCPPU2 enable
 */
#define ADCPPUCTL2_ALL_EN_Pos (0)
#define ADCPPUCTL2_ALL_EN_Msk (0x1UL << ADCPPUCTL2_ALL_EN_Pos)

typedef enum
{
    ADCPPUCTL2_BIT_EN_DISABLE     = 0,  /*!< Disable ADCPPU2   */
    ADCPPUCTL2_BIT_EN_ENABLE      = 1,  /*!< Enable ADCPPU2    */
} ADCPPUCTL2_BIT_EN;

#define ADCPPUCTL2_ALL_EN_DISABLE     ((0x0UL) << ADCPPUCTL2_ALL_EN_Pos)
#define ADCPPUCTL2_ALL_EN_ENABLE      ((0x1UL) << ADCPPUCTL2_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL2      CBCEN
 *  @access     ADC->ADCPPUCTL2.bit.CBCEN
 *  @brief      ADCPPU2 cycle-by-cycle clear enable
 */
#define ADCPPUCTL2_ALL_CBCEN_Pos (1)
#define ADCPPUCTL2_ALL_CBCEN_Msk (0x1UL << ADCPPUCTL2_ALL_CBCEN_Pos)

typedef enum
{
    ADCPPUCTL2_BIT_CBCEN_DISABLE     = 0,  /*!< Disable ADCPPU2 cycle-by-cycle clear   */
    ADCPPUCTL2_BIT_CBCEN_ENABLE      = 1,  /*!< Enable ADCPPU2 cycle-by-cycle clear    */
} ADCPPUCTL2_BIT_CBCEN;

#define ADCPPUCTL2_ALL_CBCEN_DISABLE     ((0x0UL) << ADCPPUCTL2_ALL_CBCEN_Pos)
#define ADCPPUCTL2_ALL_CBCEN_ENABLE      ((0x1UL) << ADCPPUCTL2_ALL_CBCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL2      SOCSEL
 *  @access     ADC->ADCPPUCTL2.bit.SOCSEL
 *  @brief      Select the SOC signal to derive the ADCPPU0SOCDLY
 */
#define ADCPPUCTL2_ALL_SOCSEL_Pos (2)
#define ADCPPUCTL2_ALL_SOCSEL_Msk (0xFUL << ADCPPUCTL2_ALL_SOCSEL_Pos)

#define ADCPPUCTL2_BIT_SOCSEL

#define ADCPPUCTL2_ALL_SOCSEL_(x) ((x) << ADCPPUCTL2_ALL_SOCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL2      DATASEL
 *  @access     ADC->ADCPPUCTL2.bit.DATASEL
 *  @brief      Select the ADC result to compare with the reference
 */
#define ADCPPUCTL2_ALL_DATASEL_Pos (6)
#define ADCPPUCTL2_ALL_DATASEL_Msk (0xFUL << ADCPPUCTL2_ALL_DATASEL_Pos)

#define ADCPPUCTL2_BIT_DATASEL

#define ADCPPUCTL2_ALL_DATASEL_(x) ((x) << ADCPPUCTL2_ALL_DATASEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL2      POL
 *  @access     ADC->ADCPPUCTL2.bit.POL
 *  @brief      Polarity for comparison
 */
#define ADCPPUCTL2_ALL_POL_Pos (10)
#define ADCPPUCTL2_ALL_POL_Msk (0x1UL << ADCPPUCTL2_ALL_POL_Pos)

typedef enum
{
    ADCPPUCTL2_BIT_POL_REF_MINUS_CODE     = 0,  /*!< ADCPPU2 result is the reference minus the selected result   */
    ADCPPUCTL2_BIT_POL_CODE_MINUS_REF     = 1,  /*!< ADCPPU2 result is the selected result minus the reference   */
} ADCPPUCTL2_BIT_POL;

#define ADCPPUCTL2_ALL_POL_REF_MINUS_CODE     ((0x0UL) << ADCPPUCTL2_ALL_POL_Pos)
#define ADCPPUCTL2_ALL_POL_CODE_MINUS_REF     ((0x1UL) << ADCPPUCTL2_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL3      EN
 *  @access     ADC->ADCPPUCTL3.bit.EN
 *  @brief      ADCPPU3 enable
 */
#define ADCPPUCTL3_ALL_EN_Pos (0)
#define ADCPPUCTL3_ALL_EN_Msk (0x1UL << ADCPPUCTL3_ALL_EN_Pos)

typedef enum
{
    ADCPPUCTL3_BIT_EN_DISABLE     = 0,  /*!< Disable ADCPPU3   */
    ADCPPUCTL3_BIT_EN_ENABLE      = 1,  /*!< Enable ADCPPU3    */
} ADCPPUCTL3_BIT_EN;

#define ADCPPUCTL3_ALL_EN_DISABLE     ((0x0UL) << ADCPPUCTL3_ALL_EN_Pos)
#define ADCPPUCTL3_ALL_EN_ENABLE      ((0x1UL) << ADCPPUCTL3_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL3      CBCEN
 *  @access     ADC->ADCPPUCTL3.bit.CBCEN
 *  @brief      ADCPPU3 cycle-by-cycle clear enable
 */
#define ADCPPUCTL3_ALL_CBCEN_Pos (1)
#define ADCPPUCTL3_ALL_CBCEN_Msk (0x1UL << ADCPPUCTL3_ALL_CBCEN_Pos)

typedef enum
{
    ADCPPUCTL3_BIT_CBCEN_DISABLE     = 0,  /*!< Disable ADCPPU3 cycle-by-cycle clear   */
    ADCPPUCTL3_BIT_CBCEN_ENABLE      = 1,  /*!< Enable ADCPPU3 cycle-by-cycle clear    */
} ADCPPUCTL3_BIT_CBCEN;

#define ADCPPUCTL3_ALL_CBCEN_DISABLE     ((0x0UL) << ADCPPUCTL3_ALL_CBCEN_Pos)
#define ADCPPUCTL3_ALL_CBCEN_ENABLE      ((0x1UL) << ADCPPUCTL3_ALL_CBCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL3      SOCSEL
 *  @access     ADC->ADCPPUCTL3.bit.SOCSEL
 *  @brief      Select the SOC signal to derive the ADCPPU0SOCDLY
 */
#define ADCPPUCTL3_ALL_SOCSEL_Pos (2)
#define ADCPPUCTL3_ALL_SOCSEL_Msk (0xFUL << ADCPPUCTL3_ALL_SOCSEL_Pos)

#define ADCPPUCTL3_BIT_SOCSEL

#define ADCPPUCTL3_ALL_SOCSEL_(x) ((x) << ADCPPUCTL3_ALL_SOCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL3      DATASEL
 *  @access     ADC->ADCPPUCTL3.bit.DATASEL
 *  @brief      Select the ADC result to compare with the reference
 */
#define ADCPPUCTL3_ALL_DATASEL_Pos (6)
#define ADCPPUCTL3_ALL_DATASEL_Msk (0xFUL << ADCPPUCTL3_ALL_DATASEL_Pos)

#define ADCPPUCTL3_BIT_DATASEL

#define ADCPPUCTL3_ALL_DATASEL_(x) ((x) << ADCPPUCTL3_ALL_DATASEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL3      POL
 *  @access     ADC->ADCPPUCTL3.bit.POL
 *  @brief      Polarity for comparison
 */
#define ADCPPUCTL3_ALL_POL_Pos (10)
#define ADCPPUCTL3_ALL_POL_Msk (0x1UL << ADCPPUCTL3_ALL_POL_Pos)

typedef enum
{
    ADCPPUCTL3_BIT_POL_REF_MINUS_CODE     = 0,  /*!< ADCPPU3 result is the reference minus the selected result   */
    ADCPPUCTL3_BIT_POL_CODE_MINUS_REF     = 1,  /*!< ADCPPU3 result is the selected result minus the reference   */
} ADCPPUCTL3_BIT_POL;

#define ADCPPUCTL3_ALL_POL_REF_MINUS_CODE     ((0x0UL) << ADCPPUCTL3_ALL_POL_Pos)
#define ADCPPUCTL3_ALL_POL_CODE_MINUS_REF     ((0x1UL) << ADCPPUCTL3_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL4      EN
 *  @access     ADC->ADCPPUCTL4.bit.EN
 *  @brief      ADCPPU4 enable
 */
#define ADCPPUCTL4_ALL_EN_Pos (0)
#define ADCPPUCTL4_ALL_EN_Msk (0x1UL << ADCPPUCTL4_ALL_EN_Pos)

typedef enum
{
    ADCPPUCTL4_BIT_EN_DISABLE     = 0,  /*!< Disable ADCPPU4   */
    ADCPPUCTL4_BIT_EN_ENABLE      = 1,  /*!< Enable ADCPPU4    */
} ADCPPUCTL4_BIT_EN;

#define ADCPPUCTL4_ALL_EN_DISABLE     ((0x0UL) << ADCPPUCTL4_ALL_EN_Pos)
#define ADCPPUCTL4_ALL_EN_ENABLE      ((0x1UL) << ADCPPUCTL4_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL4      CBCEN
 *  @access     ADC->ADCPPUCTL4.bit.CBCEN
 *  @brief      ADCPPU4 cycle-by-cycle clear enable
 */
#define ADCPPUCTL4_ALL_CBCEN_Pos (1)
#define ADCPPUCTL4_ALL_CBCEN_Msk (0x1UL << ADCPPUCTL4_ALL_CBCEN_Pos)

typedef enum
{
    ADCPPUCTL4_BIT_CBCEN_DISABLE     = 0,  /*!< Disable ADCPPU4 cycle-by-cycle clear   */
    ADCPPUCTL4_BIT_CBCEN_ENABLE      = 1,  /*!< Enable ADCPPU4 cycle-by-cycle clear    */
} ADCPPUCTL4_BIT_CBCEN;

#define ADCPPUCTL4_ALL_CBCEN_DISABLE     ((0x0UL) << ADCPPUCTL4_ALL_CBCEN_Pos)
#define ADCPPUCTL4_ALL_CBCEN_ENABLE      ((0x1UL) << ADCPPUCTL4_ALL_CBCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL4      SOCSEL
 *  @access     ADC->ADCPPUCTL4.bit.SOCSEL
 *  @brief      Select the SOC signal to derive the ADCPPU0SOCDLY
 */
#define ADCPPUCTL4_ALL_SOCSEL_Pos (2)
#define ADCPPUCTL4_ALL_SOCSEL_Msk (0xFUL << ADCPPUCTL4_ALL_SOCSEL_Pos)

#define ADCPPUCTL4_BIT_SOCSEL

#define ADCPPUCTL4_ALL_SOCSEL_(x) ((x) << ADCPPUCTL4_ALL_SOCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL4      DATASEL
 *  @access     ADC->ADCPPUCTL4.bit.DATASEL
 *  @brief      Select the ADC result to compare with the reference
 */
#define ADCPPUCTL4_ALL_DATASEL_Pos (6)
#define ADCPPUCTL4_ALL_DATASEL_Msk (0xFUL << ADCPPUCTL4_ALL_DATASEL_Pos)

#define ADCPPUCTL4_BIT_DATASEL

#define ADCPPUCTL4_ALL_DATASEL_(x) ((x) << ADCPPUCTL4_ALL_DATASEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL4      POL
 *  @access     ADC->ADCPPUCTL4.bit.POL
 *  @brief      Polarity for comparison
 */
#define ADCPPUCTL4_ALL_POL_Pos (10)
#define ADCPPUCTL4_ALL_POL_Msk (0x1UL << ADCPPUCTL4_ALL_POL_Pos)

typedef enum
{
    ADCPPUCTL4_BIT_POL_REF_MINUS_CODE     = 0,  /*!< ADCPPU4 result is the reference minus the selected result   */
    ADCPPUCTL4_BIT_POL_CODE_MINUS_REF     = 1,  /*!< ADCPPU4 result is the selected result minus the reference   */
} ADCPPUCTL4_BIT_POL;

#define ADCPPUCTL4_ALL_POL_REF_MINUS_CODE     ((0x0UL) << ADCPPUCTL4_ALL_POL_Pos)
#define ADCPPUCTL4_ALL_POL_CODE_MINUS_REF     ((0x1UL) << ADCPPUCTL4_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL5      EN
 *  @access     ADC->ADCPPUCTL5.bit.EN
 *  @brief      ADCPPU5 enable
 */
#define ADCPPUCTL5_ALL_EN_Pos (0)
#define ADCPPUCTL5_ALL_EN_Msk (0x1UL << ADCPPUCTL5_ALL_EN_Pos)

typedef enum
{
    ADCPPUCTL5_BIT_EN_DISABLE     = 0,  /*!< Disable ADCPPU5   */
    ADCPPUCTL5_BIT_EN_ENABLE      = 1,  /*!< Enable ADCPPU5    */
} ADCPPUCTL5_BIT_EN;

#define ADCPPUCTL5_ALL_EN_DISABLE     ((0x0UL) << ADCPPUCTL5_ALL_EN_Pos)
#define ADCPPUCTL5_ALL_EN_ENABLE      ((0x1UL) << ADCPPUCTL5_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL5      CBCEN
 *  @access     ADC->ADCPPUCTL5.bit.CBCEN
 *  @brief      ADCPPU5 cycle-by-cycle clear enable
 */
#define ADCPPUCTL5_ALL_CBCEN_Pos (1)
#define ADCPPUCTL5_ALL_CBCEN_Msk (0x1UL << ADCPPUCTL5_ALL_CBCEN_Pos)

typedef enum
{
    ADCPPUCTL5_BIT_CBCEN_DISABLE     = 0,  /*!< Disable ADCPPU5 cycle-by-cycle clear   */
    ADCPPUCTL5_BIT_CBCEN_ENABLE      = 1,  /*!< Enable ADCPPU5 cycle-by-cycle clear    */
} ADCPPUCTL5_BIT_CBCEN;

#define ADCPPUCTL5_ALL_CBCEN_DISABLE     ((0x0UL) << ADCPPUCTL5_ALL_CBCEN_Pos)
#define ADCPPUCTL5_ALL_CBCEN_ENABLE      ((0x1UL) << ADCPPUCTL5_ALL_CBCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL5      SOCSEL
 *  @access     ADC->ADCPPUCTL5.bit.SOCSEL
 *  @brief      Select the SOC signal to derive the ADCPPU0SOCDLY
 */
#define ADCPPUCTL5_ALL_SOCSEL_Pos (2)
#define ADCPPUCTL5_ALL_SOCSEL_Msk (0xFUL << ADCPPUCTL5_ALL_SOCSEL_Pos)

#define ADCPPUCTL5_BIT_SOCSEL

#define ADCPPUCTL5_ALL_SOCSEL_(x) ((x) << ADCPPUCTL5_ALL_SOCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL5      DATASEL
 *  @access     ADC->ADCPPUCTL5.bit.DATASEL
 *  @brief      Select the ADC result to compare with the reference
 */
#define ADCPPUCTL5_ALL_DATASEL_Pos (6)
#define ADCPPUCTL5_ALL_DATASEL_Msk (0xFUL << ADCPPUCTL5_ALL_DATASEL_Pos)

#define ADCPPUCTL5_BIT_DATASEL

#define ADCPPUCTL5_ALL_DATASEL_(x) ((x) << ADCPPUCTL5_ALL_DATASEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUCTL5      POL
 *  @access     ADC->ADCPPUCTL5.bit.POL
 *  @brief      Polarity for comparison
 */
#define ADCPPUCTL5_ALL_POL_Pos (10)
#define ADCPPUCTL5_ALL_POL_Msk (0x1UL << ADCPPUCTL5_ALL_POL_Pos)

typedef enum
{
    ADCPPUCTL5_BIT_POL_REF_MINUS_CODE     = 0,  /*!< ADCPPU5 result is the reference minus the selected result   */
    ADCPPUCTL5_BIT_POL_CODE_MINUS_REF     = 1,  /*!< ADCPPU5 result is the selected result minus the reference   */
} ADCPPUCTL5_BIT_POL;

#define ADCPPUCTL5_ALL_POL_REF_MINUS_CODE     ((0x0UL) << ADCPPUCTL5_ALL_POL_Pos)
#define ADCPPUCTL5_ALL_POL_CODE_MINUS_REF     ((0x1UL) << ADCPPUCTL5_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUREF0      VAL
 *  @access     ADC->ADCPPUREF0.bit.VAL
 *  @brief      Reference with extended sign bit
 *              Should be within [-8192, 8191]
 */
#define ADCPPUREF0_ALL_VAL_Pos (0)
#define ADCPPUREF0_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUREF0_ALL_VAL_Pos)

#define ADCPPUREF0_BIT_VAL

#define ADCPPUREF0_ALL_VAL_(x) ((x) << ADCPPUREF0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUREF1      VAL
 *  @access     ADC->ADCPPUREF1.bit.VAL
 *  @brief      Reference with extended sign bit
 *              Should be within [-8192, 8191]
 */
#define ADCPPUREF1_ALL_VAL_Pos (0)
#define ADCPPUREF1_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUREF1_ALL_VAL_Pos)

#define ADCPPUREF1_BIT_VAL

#define ADCPPUREF1_ALL_VAL_(x) ((x) << ADCPPUREF1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUREF2      VAL
 *  @access     ADC->ADCPPUREF2.bit.VAL
 *  @brief      Reference with extended sign bit
 *              Should be within [-8192, 8191]
 */
#define ADCPPUREF2_ALL_VAL_Pos (0)
#define ADCPPUREF2_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUREF2_ALL_VAL_Pos)

#define ADCPPUREF2_BIT_VAL

#define ADCPPUREF2_ALL_VAL_(x) ((x) << ADCPPUREF2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUREF3      VAL
 *  @access     ADC->ADCPPUREF3.bit.VAL
 *  @brief      Reference with extended sign bit
 *              Should be within [-8192, 8191]
 */
#define ADCPPUREF3_ALL_VAL_Pos (0)
#define ADCPPUREF3_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUREF3_ALL_VAL_Pos)

#define ADCPPUREF3_BIT_VAL

#define ADCPPUREF3_ALL_VAL_(x) ((x) << ADCPPUREF3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUREF4      VAL
 *  @access     ADC->ADCPPUREF4.bit.VAL
 *  @brief      Reference with extended sign bit
 *              Should be within [-8192, 8191]
 */
#define ADCPPUREF4_ALL_VAL_Pos (0)
#define ADCPPUREF4_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUREF4_ALL_VAL_Pos)

#define ADCPPUREF4_BIT_VAL

#define ADCPPUREF4_ALL_VAL_(x) ((x) << ADCPPUREF4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUREF5      VAL
 *  @access     ADC->ADCPPUREF5.bit.VAL
 *  @brief      Reference with extended sign bit
 *              Should be within [-8192, 8191]
 */
#define ADCPPUREF5_ALL_VAL_Pos (0)
#define ADCPPUREF5_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUREF5_ALL_VAL_Pos)

#define ADCPPUREF5_BIT_VAL

#define ADCPPUREF5_ALL_VAL_(x) ((x) << ADCPPUREF5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHH0      VAL
 *  @access     ADC->ADCPPUTHH0.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHH0_ALL_VAL_Pos (0)
#define ADCPPUTHH0_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHH0_ALL_VAL_Pos)

#define ADCPPUTHH0_BIT_VAL

#define ADCPPUTHH0_ALL_VAL_(x) ((x) << ADCPPUTHH0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHH1      VAL
 *  @access     ADC->ADCPPUTHH1.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHH1_ALL_VAL_Pos (0)
#define ADCPPUTHH1_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHH1_ALL_VAL_Pos)

#define ADCPPUTHH1_BIT_VAL

#define ADCPPUTHH1_ALL_VAL_(x) ((x) << ADCPPUTHH1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHH2      VAL
 *  @access     ADC->ADCPPUTHH2.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHH2_ALL_VAL_Pos (0)
#define ADCPPUTHH2_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHH2_ALL_VAL_Pos)

#define ADCPPUTHH2_BIT_VAL

#define ADCPPUTHH2_ALL_VAL_(x) ((x) << ADCPPUTHH2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHH3      VAL
 *  @access     ADC->ADCPPUTHH3.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHH3_ALL_VAL_Pos (0)
#define ADCPPUTHH3_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHH3_ALL_VAL_Pos)

#define ADCPPUTHH3_BIT_VAL

#define ADCPPUTHH3_ALL_VAL_(x) ((x) << ADCPPUTHH3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHH4      VAL
 *  @access     ADC->ADCPPUTHH4.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHH4_ALL_VAL_Pos (0)
#define ADCPPUTHH4_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHH4_ALL_VAL_Pos)

#define ADCPPUTHH4_BIT_VAL

#define ADCPPUTHH4_ALL_VAL_(x) ((x) << ADCPPUTHH4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHH5      VAL
 *  @access     ADC->ADCPPUTHH5.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHH5_ALL_VAL_Pos (0)
#define ADCPPUTHH5_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHH5_ALL_VAL_Pos)

#define ADCPPUTHH5_BIT_VAL

#define ADCPPUTHH5_ALL_VAL_(x) ((x) << ADCPPUTHH5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHL0      VAL
 *  @access     ADC->ADCPPUTHL0.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHL0_ALL_VAL_Pos (0)
#define ADCPPUTHL0_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHL0_ALL_VAL_Pos)

#define ADCPPUTHL0_BIT_VAL

#define ADCPPUTHL0_ALL_VAL_(x) ((x) << ADCPPUTHL0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHL1      VAL
 *  @access     ADC->ADCPPUTHL1.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHL1_ALL_VAL_Pos (0)
#define ADCPPUTHL1_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHL1_ALL_VAL_Pos)

#define ADCPPUTHL1_BIT_VAL

#define ADCPPUTHL1_ALL_VAL_(x) ((x) << ADCPPUTHL1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHL2      VAL
 *  @access     ADC->ADCPPUTHL2.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHL2_ALL_VAL_Pos (0)
#define ADCPPUTHL2_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHL2_ALL_VAL_Pos)

#define ADCPPUTHL2_BIT_VAL

#define ADCPPUTHL2_ALL_VAL_(x) ((x) << ADCPPUTHL2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHL3      VAL
 *  @access     ADC->ADCPPUTHL3.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHL3_ALL_VAL_Pos (0)
#define ADCPPUTHL3_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHL3_ALL_VAL_Pos)

#define ADCPPUTHL3_BIT_VAL

#define ADCPPUTHL3_ALL_VAL_(x) ((x) << ADCPPUTHL3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHL4      VAL
 *  @access     ADC->ADCPPUTHL4.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHL4_ALL_VAL_Pos (0)
#define ADCPPUTHL4_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHL4_ALL_VAL_Pos)

#define ADCPPUTHL4_BIT_VAL

#define ADCPPUTHL4_ALL_VAL_(x) ((x) << ADCPPUTHL4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCPPUTHL5      VAL
 *  @access     ADC->ADCPPUTHL5.bit.VAL
 *  @brief      Signed trip-zone threshold within [-16384, 16383]
 */
#define ADCPPUTHL5_ALL_VAL_Pos (0)
#define ADCPPUTHL5_ALL_VAL_Msk (0xFFFFFFFFUL << ADCPPUTHL5_ALL_VAL_Pos)

#define ADCPPUTHL5_BIT_VAL

#define ADCPPUTHL5_ALL_VAL_(x) ((x) << ADCPPUTHL5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             TSENSCTL        EN
 *  @access     ADC->TSENSCTL.bit.EN
 *  @brief      Temperature sensor enable
 */
#define TSENSCTL_ALL_EN_Pos (0)
#define TSENSCTL_ALL_EN_Msk (0x1UL << TSENSCTL_ALL_EN_Pos)

typedef enum
{
    TSENSCTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    TSENSCTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} TSENSCTL_BIT_EN;

#define TSENSCTL_ALL_EN_DISABLE     ((0x0UL) << TSENSCTL_ALL_EN_Pos)
#define TSENSCTL_ALL_EN_ENABLE      ((0x1UL) << TSENSCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             TSENSCTL        OUTINV
 *  @access     ADC->TSENSCTL.bit.OUTINV
 *  @brief      Invert T-Sensor output 0 and output 1
 */
#define TSENSCTL_ALL_OUTINV_Pos (1)
#define TSENSCTL_ALL_OUTINV_Msk (0x1UL << TSENSCTL_ALL_OUTINV_Pos)

typedef enum
{
    TSENSCTL_BIT_OUTINV_DISABLE     = 0,  /*!< Normal connect                          */
    TSENSCTL_BIT_OUTINV_ENABLE      = 1,  /*!< Invert T-Sensor output 0 and output 1   */
} TSENSCTL_BIT_OUTINV;

#define TSENSCTL_ALL_OUTINV_DISABLE     ((0x0UL) << TSENSCTL_ALL_OUTINV_Pos)
#define TSENSCTL_ALL_OUTINV_ENABLE      ((0x1UL) << TSENSCTL_ALL_OUTINV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             TSENSCTL        SWAPBJT
 *  @access     ADC->TSENSCTL.bit.SWAPBJT
 *  @brief      Swap BJT
 */
#define TSENSCTL_ALL_SWAPBJT_Pos (2)
#define TSENSCTL_ALL_SWAPBJT_Msk (0x1UL << TSENSCTL_ALL_SWAPBJT_Pos)

typedef enum
{
    TSENSCTL_BIT_SWAPBJT_NOT_SWAP     = 0,  /*!< Not swap bi-polar   */
    TSENSCTL_BIT_SWAPBJT_SWAP         = 1,  /*!< Swap bi-polar       */
} TSENSCTL_BIT_SWAPBJT;

#define TSENSCTL_ALL_SWAPBJT_NOT_SWAP     ((0x0UL) << TSENSCTL_ALL_SWAPBJT_Pos)
#define TSENSCTL_ALL_SWAPBJT_SWAP         ((0x1UL) << TSENSCTL_ALL_SWAPBJT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             TSENSCTL        DEMSEL
 *  @access     ADC->TSENSCTL.bit.DEMSEL
 *  @brief      Current branch select for dynamic element match
 */
#define TSENSCTL_ALL_DEMSEL_Pos (3)
#define TSENSCTL_ALL_DEMSEL_Msk (0xFUL << TSENSCTL_ALL_DEMSEL_Pos)

#define TSENSCTL_BIT_DEMSEL

#define TSENSCTL_ALL_DEMSEL_(x) ((x) << TSENSCTL_ALL_DEMSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ADC             ADCREGKEY       KEY
 *  @access     ADC->ADCREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected ADC registers
 */
#define ADCREGKEY_ALL_KEY_Pos (0)
#define ADCREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << ADCREGKEY_ALL_KEY_Pos)

#define ADCREGKEY_BIT_KEY

#define ADCREGKEY_ALL_KEY_(x) ((x) << ADCREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     PWM
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       TBPRD
 *  @access     PWM->SHADOWSTS.bit.TBPRD
 *  @brief      TBPRD shadow status
 */
#define SHADOWSTS_ALL_TBPRD_Pos (0)
#define SHADOWSTS_ALL_TBPRD_Msk (0x1UL << SHADOWSTS_ALL_TBPRD_Pos)

typedef enum
{
    SHADOWSTS_BIT_TBPRD_EMPTY     = 0,  /*!< A load from TBPRD to TBPRDA clears this bit                        */
    SHADOWSTS_BIT_TBPRD_FULL      = 1,  /*!< Write to TBPRD set this bit and overwrite current value in TBPRD   */
} SHADOWSTS_BIT_TBPRD;

#define SHADOWSTS_ALL_TBPRD_EMPTY     ((0x0UL) << SHADOWSTS_ALL_TBPRD_Pos)
#define SHADOWSTS_ALL_TBPRD_FULL      ((0x1UL) << SHADOWSTS_ALL_TBPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       CMPA
 *  @access     PWM->SHADOWSTS.bit.CMPA
 *  @brief      CMPA shadow status
 */
#define SHADOWSTS_ALL_CMPA_Pos (1)
#define SHADOWSTS_ALL_CMPA_Msk (0x1UL << SHADOWSTS_ALL_CMPA_Pos)

typedef enum
{
    SHADOWSTS_BIT_CMPA_EMPTY     = 0,  /*!< A load from CMPA to CMPAA clears this bit                        */
    SHADOWSTS_BIT_CMPA_FULL      = 1,  /*!< Write to CMPA set this bit and overwrite current value in CMPA   */
} SHADOWSTS_BIT_CMPA;

#define SHADOWSTS_ALL_CMPA_EMPTY     ((0x0UL) << SHADOWSTS_ALL_CMPA_Pos)
#define SHADOWSTS_ALL_CMPA_FULL      ((0x1UL) << SHADOWSTS_ALL_CMPA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       CMPB
 *  @access     PWM->SHADOWSTS.bit.CMPB
 *  @brief      CMPB shadow status
 */
#define SHADOWSTS_ALL_CMPB_Pos (2)
#define SHADOWSTS_ALL_CMPB_Msk (0x1UL << SHADOWSTS_ALL_CMPB_Pos)

typedef enum
{
    SHADOWSTS_BIT_CMPB_EMPTY     = 0,  /*!< A load from CMPB to CMPBA clears this bit                        */
    SHADOWSTS_BIT_CMPB_FULL      = 1,  /*!< Write to CMPB set this bit and overwrite current value in CMPB   */
} SHADOWSTS_BIT_CMPB;

#define SHADOWSTS_ALL_CMPB_EMPTY     ((0x0UL) << SHADOWSTS_ALL_CMPB_Pos)
#define SHADOWSTS_ALL_CMPB_FULL      ((0x1UL) << SHADOWSTS_ALL_CMPB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       CMPC
 *  @access     PWM->SHADOWSTS.bit.CMPC
 *  @brief      CMPC shadow status
 */
#define SHADOWSTS_ALL_CMPC_Pos (3)
#define SHADOWSTS_ALL_CMPC_Msk (0x1UL << SHADOWSTS_ALL_CMPC_Pos)

typedef enum
{
    SHADOWSTS_BIT_CMPC_EMPTY     = 0,  /*!< A load from CMPC to CMPCA clears this bit                        */
    SHADOWSTS_BIT_CMPC_FULL      = 1,  /*!< Write to CMPC set this bit and overwrite current value in CMPC   */
} SHADOWSTS_BIT_CMPC;

#define SHADOWSTS_ALL_CMPC_EMPTY     ((0x0UL) << SHADOWSTS_ALL_CMPC_Pos)
#define SHADOWSTS_ALL_CMPC_FULL      ((0x1UL) << SHADOWSTS_ALL_CMPC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       CMPD
 *  @access     PWM->SHADOWSTS.bit.CMPD
 *  @brief      CMPD shadow status
 */
#define SHADOWSTS_ALL_CMPD_Pos (4)
#define SHADOWSTS_ALL_CMPD_Msk (0x1UL << SHADOWSTS_ALL_CMPD_Pos)

typedef enum
{
    SHADOWSTS_BIT_CMPD_EMPTY     = 0,  /*!< A load from CMPD to CMPDA clears this bit                        */
    SHADOWSTS_BIT_CMPD_FULL      = 1,  /*!< Write to CMPD set this bit and overwrite current value in CMPD   */
} SHADOWSTS_BIT_CMPD;

#define SHADOWSTS_ALL_CMPD_EMPTY     ((0x0UL) << SHADOWSTS_ALL_CMPD_Pos)
#define SHADOWSTS_ALL_CMPD_FULL      ((0x1UL) << SHADOWSTS_ALL_CMPD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       AQCTLA
 *  @access     PWM->SHADOWSTS.bit.AQCTLA
 *  @brief      AQCTLA shadow status
 */
#define SHADOWSTS_ALL_AQCTLA_Pos (5)
#define SHADOWSTS_ALL_AQCTLA_Msk (0x1UL << SHADOWSTS_ALL_AQCTLA_Pos)

typedef enum
{
    SHADOWSTS_BIT_AQCTLA_EMPTY     = 0,  /*!< A load from AQCTLA to AQCTLAA clears this bit                        */
    SHADOWSTS_BIT_AQCTLA_FULL      = 1,  /*!< Write to AQCTLA set this bit and overwrite current value in AQCTLA   */
} SHADOWSTS_BIT_AQCTLA;

#define SHADOWSTS_ALL_AQCTLA_EMPTY     ((0x0UL) << SHADOWSTS_ALL_AQCTLA_Pos)
#define SHADOWSTS_ALL_AQCTLA_FULL      ((0x1UL) << SHADOWSTS_ALL_AQCTLA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       AQCTLB
 *  @access     PWM->SHADOWSTS.bit.AQCTLB
 *  @brief      AQCTLB shadow status
 */
#define SHADOWSTS_ALL_AQCTLB_Pos (6)
#define SHADOWSTS_ALL_AQCTLB_Msk (0x1UL << SHADOWSTS_ALL_AQCTLB_Pos)

typedef enum
{
    SHADOWSTS_BIT_AQCTLB_EMPTY     = 0,  /*!< A load from AQCTLB to AQCTLBA clears this bit                        */
    SHADOWSTS_BIT_AQCTLB_FULL      = 1,  /*!< Write to AQCTLB set this bit and overwrite current value in AQCTLB   */
} SHADOWSTS_BIT_AQCTLB;

#define SHADOWSTS_ALL_AQCTLB_EMPTY     ((0x0UL) << SHADOWSTS_ALL_AQCTLB_Pos)
#define SHADOWSTS_ALL_AQCTLB_FULL      ((0x1UL) << SHADOWSTS_ALL_AQCTLB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       AQCSFRC
 *  @access     PWM->SHADOWSTS.bit.AQCSFRC
 *  @brief      AQCSFRC shadow status
 */
#define SHADOWSTS_ALL_AQCSFRC_Pos (7)
#define SHADOWSTS_ALL_AQCSFRC_Msk (0x1UL << SHADOWSTS_ALL_AQCSFRC_Pos)

typedef enum
{
    SHADOWSTS_BIT_AQCSFRC_EMPTY     = 0,  /*!< A load from AQCSFRC to AQCSFRCA clears this bit                        */
    SHADOWSTS_BIT_AQCSFRC_FULL      = 1,  /*!< Write to AQCSFRC set this bit and overwrite current value in AQCSFRC   */
} SHADOWSTS_BIT_AQCSFRC;

#define SHADOWSTS_ALL_AQCSFRC_EMPTY     ((0x0UL) << SHADOWSTS_ALL_AQCSFRC_Pos)
#define SHADOWSTS_ALL_AQCSFRC_FULL      ((0x1UL) << SHADOWSTS_ALL_AQCSFRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       DBCTL
 *  @access     PWM->SHADOWSTS.bit.DBCTL
 *  @brief      DBCTL shadow status
 */
#define SHADOWSTS_ALL_DBCTL_Pos (8)
#define SHADOWSTS_ALL_DBCTL_Msk (0x1UL << SHADOWSTS_ALL_DBCTL_Pos)

typedef enum
{
    SHADOWSTS_BIT_DBCTL_EMPTY     = 0,  /*!< A load from DBCTL to DBCTLA clears this bit                        */
    SHADOWSTS_BIT_DBCTL_FULL      = 1,  /*!< Write to DBCTL set this bit and overwrite current value in DBCTL   */
} SHADOWSTS_BIT_DBCTL;

#define SHADOWSTS_ALL_DBCTL_EMPTY     ((0x0UL) << SHADOWSTS_ALL_DBCTL_Pos)
#define SHADOWSTS_ALL_DBCTL_FULL      ((0x1UL) << SHADOWSTS_ALL_DBCTL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       DBRED
 *  @access     PWM->SHADOWSTS.bit.DBRED
 *  @brief      DBRED shadow status
 */
#define SHADOWSTS_ALL_DBRED_Pos (9)
#define SHADOWSTS_ALL_DBRED_Msk (0x1UL << SHADOWSTS_ALL_DBRED_Pos)

typedef enum
{
    SHADOWSTS_BIT_DBRED_EMPTY     = 0,  /*!< A load from DBRED to DBREDA clears this bit                        */
    SHADOWSTS_BIT_DBRED_FULL      = 1,  /*!< Write to DBRED set this bit and overwrite current value in DBRED   */
} SHADOWSTS_BIT_DBRED;

#define SHADOWSTS_ALL_DBRED_EMPTY     ((0x0UL) << SHADOWSTS_ALL_DBRED_Pos)
#define SHADOWSTS_ALL_DBRED_FULL      ((0x1UL) << SHADOWSTS_ALL_DBRED_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             SHADOWSTS       DBFED
 *  @access     PWM->SHADOWSTS.bit.DBFED
 *  @brief      DBFED shadow status
 */
#define SHADOWSTS_ALL_DBFED_Pos (10)
#define SHADOWSTS_ALL_DBFED_Msk (0x1UL << SHADOWSTS_ALL_DBFED_Pos)

typedef enum
{
    SHADOWSTS_BIT_DBFED_EMPTY     = 0,  /*!< A load from DBFED to DBFEDA clears this bit                        */
    SHADOWSTS_BIT_DBFED_FULL      = 1,  /*!< Write to DBFED set this bit and overwrite current value in DBFED   */
} SHADOWSTS_BIT_DBFED;

#define SHADOWSTS_ALL_DBFED_EMPTY     ((0x0UL) << SHADOWSTS_ALL_DBFED_Pos)
#define SHADOWSTS_ALL_DBFED_FULL      ((0x1UL) << SHADOWSTS_ALL_DBFED_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDCTL0         GLDEN
 *  @access     PWM->GLDCTL0.bit.GLDEN
 *  @brief      Global shadow to active load enable
 */
#define GLDCTL0_ALL_GLDEN_Pos (0)
#define GLDCTL0_ALL_GLDEN_Msk (0x1UL << GLDCTL0_ALL_GLDEN_Pos)

typedef enum
{
    GLDCTL0_BIT_GLDEN_DISABLE     = 0,  /*!< Shadow to active load is defined per register regardless of GLDSEL.  
                                             i.e. CMPA load is always controlled by CMPCTL[CMPALOAD]               */
    GLDCTL0_BIT_GLDEN_ENABLE      = 1,  /*!< Shadow to active load is globally controlled                          */
} GLDCTL0_BIT_GLDEN;

#define GLDCTL0_ALL_GLDEN_DISABLE     ((0x0UL) << GLDCTL0_ALL_GLDEN_Pos)
#define GLDCTL0_ALL_GLDEN_ENABLE      ((0x1UL) << GLDCTL0_ALL_GLDEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDCTL0         GLDLOAD
 *  @access     PWM->GLDCTL0.bit.GLDLOAD
 *  @brief      Global shadow to active load mode
 */
#define GLDCTL0_ALL_GLDLOAD_Pos (1)
#define GLDCTL0_ALL_GLDLOAD_Msk (0x7UL << GLDCTL0_ALL_GLDLOAD_Pos)

typedef enum
{
    GLDCTL0_BIT_GLDLOAD_LOAD_ON_ZERO                 = 0,  /*!< Load from shadow to active on TBCNT=0                                     */
    GLDCTL0_BIT_GLDLOAD_LOAD_ON_PERIOD               = 1,  /*!< Load from shadow to active on TBCNT=TBPRD                                 */
    GLDCTL0_BIT_GLDLOAD_LOAD_ON_ZERO_PERIOD          = 2,  /*!< Load from shadow to active on TBCNT=0 or TBCNT=TBPRD                      */
    GLDCTL0_BIT_GLDLOAD_LOAD_ON_SYNC                 = 3,  /*!< Load from shadow to active on SYNC event                                  */
    GLDCTL0_BIT_GLDLOAD_LOAD_ON_SYNC_ZERO            = 4,  /*!< Load from shadow to active on SYNC event or TBCNT=0                       */
    GLDCTL0_BIT_GLDLOAD_LOAD_ON_SYNC_PERIOD          = 5,  /*!< Load from shadow to active on SYNC event or TBCNT=TBPRD                   */
    GLDCTL0_BIT_GLDLOAD_LOAD_ON_SYNC_ZERO_PERIOD     = 6,  /*!< Load from shadow to active on SYNC event, TBCNT=0 or TBCNT=TBPRD          */
    GLDCTL0_BIT_GLDLOAD_LOAD_ON_FORCE                = 7,  /*!< Load from shadow to active on software by writing 1 to GLDCTL1[FRCLOAD]   */
} GLDCTL0_BIT_GLDLOAD;

#define GLDCTL0_ALL_GLDLOAD_LOAD_ON_ZERO                 ((0x0UL) << GLDCTL0_ALL_GLDLOAD_Pos)
#define GLDCTL0_ALL_GLDLOAD_LOAD_ON_PERIOD               ((0x1UL) << GLDCTL0_ALL_GLDLOAD_Pos)
#define GLDCTL0_ALL_GLDLOAD_LOAD_ON_ZERO_PERIOD          ((0x2UL) << GLDCTL0_ALL_GLDLOAD_Pos)
#define GLDCTL0_ALL_GLDLOAD_LOAD_ON_SYNC                 ((0x3UL) << GLDCTL0_ALL_GLDLOAD_Pos)
#define GLDCTL0_ALL_GLDLOAD_LOAD_ON_SYNC_ZERO            ((0x4UL) << GLDCTL0_ALL_GLDLOAD_Pos)
#define GLDCTL0_ALL_GLDLOAD_LOAD_ON_SYNC_PERIOD          ((0x5UL) << GLDCTL0_ALL_GLDLOAD_Pos)
#define GLDCTL0_ALL_GLDLOAD_LOAD_ON_SYNC_ZERO_PERIOD     ((0x6UL) << GLDCTL0_ALL_GLDLOAD_Pos)
#define GLDCTL0_ALL_GLDLOAD_LOAD_ON_FORCE                ((0x7UL) << GLDCTL0_ALL_GLDLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDCTL0         GLDPRD
 *  @access     PWM->GLDCTL0.bit.GLDPRD
 *  @brief      Global shadow to active load strobe period
 *              No global load pulse will be generated if GLDPRD=0. Otherwise, the global load pulse
 *              is generated upon GLDCNT = GLDPRD.
 *              It has no effect if OSTMODE=1
 */
#define GLDCTL0_ALL_GLDPRD_Pos (4)
#define GLDCTL0_ALL_GLDPRD_Msk (0xFUL << GLDCTL0_ALL_GLDPRD_Pos)

#define GLDCTL0_BIT_GLDPRD

#define GLDCTL0_ALL_GLDPRD_(x) ((x) << GLDCTL0_ALL_GLDPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDCTL0         GLDCNT
 *  @access     PWM->GLDCTL0.bit.GLDCNT
 *  @brief      Global shadow to active load strobe counter
 *              It indicates how many selected global load events have occurred
 */
#define GLDCTL0_ALL_GLDCNT_Pos (8)
#define GLDCTL0_ALL_GLDCNT_Msk (0xFUL << GLDCTL0_ALL_GLDCNT_Pos)

#define GLDCTL0_BIT_GLDCNT

#define GLDCTL0_ALL_GLDCNT_(x) ((x) << GLDCTL0_ALL_GLDCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDCTL0         OSTMODE
 *  @access     PWM->GLDCTL0.bit.OSTMODE
 *  @brief      One-shot global load mode
 */
#define GLDCTL0_ALL_OSTMODE_Pos (12)
#define GLDCTL0_ALL_OSTMODE_Msk (0x1UL << GLDCTL0_ALL_OSTMODE_Pos)

typedef enum
{
    GLDCTL0_BIT_OSTMODE_CONTINUOUS_MODE     = 0,  /*!< Global strobe is continuously controlled by GLDPRD and GLDCNT       */
    GLDCTL0_BIT_OSTMODE_ONE_SHOT_MODE       = 1,  /*!< Global strobe is blocked until GLDCTL1[OSTLOAD] is written with 1   */
} GLDCTL0_BIT_OSTMODE;

#define GLDCTL0_ALL_OSTMODE_CONTINUOUS_MODE     ((0x0UL) << GLDCTL0_ALL_OSTMODE_Pos)
#define GLDCTL0_ALL_OSTMODE_ONE_SHOT_MODE       ((0x1UL) << GLDCTL0_ALL_OSTMODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDCTL1         OSTLOAD
 *  @access     PWM->GLDCTL1.bit.OSTLOAD
 *  @brief      Start the one-shot load pending
 */
#define GLDCTL1_ALL_OSTLOAD_Pos (0)
#define GLDCTL1_ALL_OSTLOAD_Msk (0x1UL << GLDCTL1_ALL_OSTLOAD_Pos)

typedef enum
{
    GLDCTL1_BIT_OSTLOAD_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Read a 0 indicates there is no pending one-shot load          */
    GLDCTL1_BIT_OSTLOAD_PENDING       = 1,  /*!< Write a 1 initialize a one-shot load pending. Upon event defined by GLDCTL[GLDLOAD],  
                                                 the global load happens and this bit is self-cleared to 0.                             */
} GLDCTL1_BIT_OSTLOAD;

#define GLDCTL1_ALL_OSTLOAD_NO_EFFECT     ((0x0UL) << GLDCTL1_ALL_OSTLOAD_Pos)
#define GLDCTL1_ALL_OSTLOAD_PENDING       ((0x1UL) << GLDCTL1_ALL_OSTLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDCTL1         FRCLOAD
 *  @access     PWM->GLDCTL1.bit.FRCLOAD
 *  @brief      Global force shadow to active load
 */
#define GLDCTL1_ALL_FRCLOAD_Pos (1)
#define GLDCTL1_ALL_FRCLOAD_Msk (0x1UL << GLDCTL1_ALL_FRCLOAD_Pos)

typedef enum
{
    GLDCTL1_BIT_FRCLOAD_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0               */
    GLDCTL1_BIT_FRCLOAD_FORCE         = 1,  /*!< Write a 1 generates global load event to the event counter   */
} GLDCTL1_BIT_FRCLOAD;

#define GLDCTL1_ALL_FRCLOAD_NO_EFFECT     ((0x0UL) << GLDCTL1_ALL_FRCLOAD_Pos)
#define GLDCTL1_ALL_FRCLOAD_FORCE         ((0x1UL) << GLDCTL1_ALL_FRCLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          TBPRD
 *  @access     PWM->GLDSEL.bit.TBPRD
 *  @brief      TBPRD global shadow to active load select
 */
#define GLDSEL_ALL_TBPRD_Pos (0)
#define GLDSEL_ALL_TBPRD_Msk (0x1UL << GLDSEL_ALL_TBPRD_Pos)

typedef enum
{
    GLDSEL_BIT_TBPRD_LOCAL      = 0,  /*!< Shadow to active load is controlled by TBCTL[TBPRDLOAD]   */
    GLDSEL_BIT_TBPRD_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL             */
} GLDSEL_BIT_TBPRD;

#define GLDSEL_ALL_TBPRD_LOCAL      ((0x0UL) << GLDSEL_ALL_TBPRD_Pos)
#define GLDSEL_ALL_TBPRD_GLOBAL     ((0x1UL) << GLDSEL_ALL_TBPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          CMPA
 *  @access     PWM->GLDSEL.bit.CMPA
 *  @brief      CMPA global shadow to active load select
 */
#define GLDSEL_ALL_CMPA_Pos (1)
#define GLDSEL_ALL_CMPA_Msk (0x1UL << GLDSEL_ALL_CMPA_Pos)

typedef enum
{
    GLDSEL_BIT_CMPA_LOCAL      = 0,  /*!< Shadow to active load is controlled by CMPCTL[CMPALOAD]   */
    GLDSEL_BIT_CMPA_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL             */
} GLDSEL_BIT_CMPA;

#define GLDSEL_ALL_CMPA_LOCAL      ((0x0UL) << GLDSEL_ALL_CMPA_Pos)
#define GLDSEL_ALL_CMPA_GLOBAL     ((0x1UL) << GLDSEL_ALL_CMPA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          CMPB
 *  @access     PWM->GLDSEL.bit.CMPB
 *  @brief      CMPB global shadow to active load select
 */
#define GLDSEL_ALL_CMPB_Pos (2)
#define GLDSEL_ALL_CMPB_Msk (0x1UL << GLDSEL_ALL_CMPB_Pos)

typedef enum
{
    GLDSEL_BIT_CMPB_LOCAL      = 0,  /*!< Shadow to active load is controlled by CMPCTL[CMPBLOAD]   */
    GLDSEL_BIT_CMPB_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL             */
} GLDSEL_BIT_CMPB;

#define GLDSEL_ALL_CMPB_LOCAL      ((0x0UL) << GLDSEL_ALL_CMPB_Pos)
#define GLDSEL_ALL_CMPB_GLOBAL     ((0x1UL) << GLDSEL_ALL_CMPB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          CMPC
 *  @access     PWM->GLDSEL.bit.CMPC
 *  @brief      CMPC global shadow to active load select
 */
#define GLDSEL_ALL_CMPC_Pos (3)
#define GLDSEL_ALL_CMPC_Msk (0x1UL << GLDSEL_ALL_CMPC_Pos)

typedef enum
{
    GLDSEL_BIT_CMPC_LOCAL      = 0,  /*!< Shadow to active load is controlled by CMPCTL[CMPCLOAD]   */
    GLDSEL_BIT_CMPC_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL             */
} GLDSEL_BIT_CMPC;

#define GLDSEL_ALL_CMPC_LOCAL      ((0x0UL) << GLDSEL_ALL_CMPC_Pos)
#define GLDSEL_ALL_CMPC_GLOBAL     ((0x1UL) << GLDSEL_ALL_CMPC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          CMPD
 *  @access     PWM->GLDSEL.bit.CMPD
 *  @brief      CMPD global shadow to active load select
 */
#define GLDSEL_ALL_CMPD_Pos (4)
#define GLDSEL_ALL_CMPD_Msk (0x1UL << GLDSEL_ALL_CMPD_Pos)

typedef enum
{
    GLDSEL_BIT_CMPD_LOCAL      = 0,  /*!< Shadow to active load is controlled by CMPCTL[CMPDLOAD]   */
    GLDSEL_BIT_CMPD_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL             */
} GLDSEL_BIT_CMPD;

#define GLDSEL_ALL_CMPD_LOCAL      ((0x0UL) << GLDSEL_ALL_CMPD_Pos)
#define GLDSEL_ALL_CMPD_GLOBAL     ((0x1UL) << GLDSEL_ALL_CMPD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          AQCTLA
 *  @access     PWM->GLDSEL.bit.AQCTLA
 *  @brief      AQCTLA global shadow to active load select
 */
#define GLDSEL_ALL_AQCTLA_Pos (5)
#define GLDSEL_ALL_AQCTLA_Msk (0x1UL << GLDSEL_ALL_AQCTLA_Pos)

typedef enum
{
    GLDSEL_BIT_AQCTLA_LOCAL      = 0,  /*!< Shadow to active load is controlled by AQCTL[AQCTLALOAD]   */
    GLDSEL_BIT_AQCTLA_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL              */
} GLDSEL_BIT_AQCTLA;

#define GLDSEL_ALL_AQCTLA_LOCAL      ((0x0UL) << GLDSEL_ALL_AQCTLA_Pos)
#define GLDSEL_ALL_AQCTLA_GLOBAL     ((0x1UL) << GLDSEL_ALL_AQCTLA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          AQCTLB
 *  @access     PWM->GLDSEL.bit.AQCTLB
 *  @brief      AQCTLB global shadow to active load select
 */
#define GLDSEL_ALL_AQCTLB_Pos (6)
#define GLDSEL_ALL_AQCTLB_Msk (0x1UL << GLDSEL_ALL_AQCTLB_Pos)

typedef enum
{
    GLDSEL_BIT_AQCTLB_LOCAL      = 0,  /*!< Shadow to active load is controlled by AQCTL[AQCTLBLOAD]   */
    GLDSEL_BIT_AQCTLB_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL              */
} GLDSEL_BIT_AQCTLB;

#define GLDSEL_ALL_AQCTLB_LOCAL      ((0x0UL) << GLDSEL_ALL_AQCTLB_Pos)
#define GLDSEL_ALL_AQCTLB_GLOBAL     ((0x1UL) << GLDSEL_ALL_AQCTLB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          AQCSFRC
 *  @access     PWM->GLDSEL.bit.AQCSFRC
 *  @brief      AQCSFRC global shadow to active load select
 */
#define GLDSEL_ALL_AQCSFRC_Pos (7)
#define GLDSEL_ALL_AQCSFRC_Msk (0x1UL << GLDSEL_ALL_AQCSFRC_Pos)

typedef enum
{
    GLDSEL_BIT_AQCSFRC_LOCAL      = 0,  /*!< Shadow to active load is controlled by AQCTL[AQCSFRCLOAD]   */
    GLDSEL_BIT_AQCSFRC_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL               */
} GLDSEL_BIT_AQCSFRC;

#define GLDSEL_ALL_AQCSFRC_LOCAL      ((0x0UL) << GLDSEL_ALL_AQCSFRC_Pos)
#define GLDSEL_ALL_AQCSFRC_GLOBAL     ((0x1UL) << GLDSEL_ALL_AQCSFRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          DBCTL
 *  @access     PWM->GLDSEL.bit.DBCTL
 *  @brief      DBCTL global shadow to active load select
 */
#define GLDSEL_ALL_DBCTL_Pos (8)
#define GLDSEL_ALL_DBCTL_Msk (0x1UL << GLDSEL_ALL_DBCTL_Pos)

typedef enum
{
    GLDSEL_BIT_DBCTL_LOCAL      = 0,  /*!< Shadow to active load is controlled by DBCTL[DBCTLLOAD]   */
    GLDSEL_BIT_DBCTL_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL             */
} GLDSEL_BIT_DBCTL;

#define GLDSEL_ALL_DBCTL_LOCAL      ((0x0UL) << GLDSEL_ALL_DBCTL_Pos)
#define GLDSEL_ALL_DBCTL_GLOBAL     ((0x1UL) << GLDSEL_ALL_DBCTL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          DBRED
 *  @access     PWM->GLDSEL.bit.DBRED
 *  @brief      DBRED global shadow to active load select
 */
#define GLDSEL_ALL_DBRED_Pos (9)
#define GLDSEL_ALL_DBRED_Msk (0x1UL << GLDSEL_ALL_DBRED_Pos)

typedef enum
{
    GLDSEL_BIT_DBRED_LOCAL      = 0,  /*!< Shadow to active load is controlled by DBCTL[DBREDLOAD]   */
    GLDSEL_BIT_DBRED_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL             */
} GLDSEL_BIT_DBRED;

#define GLDSEL_ALL_DBRED_LOCAL      ((0x0UL) << GLDSEL_ALL_DBRED_Pos)
#define GLDSEL_ALL_DBRED_GLOBAL     ((0x1UL) << GLDSEL_ALL_DBRED_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             GLDSEL          DBFED
 *  @access     PWM->GLDSEL.bit.DBFED
 *  @brief      DBFED global shadow to active load select
 */
#define GLDSEL_ALL_DBFED_Pos (10)
#define GLDSEL_ALL_DBFED_Msk (0x1UL << GLDSEL_ALL_DBFED_Pos)

typedef enum
{
    GLDSEL_BIT_DBFED_LOCAL      = 0,  /*!< Shadow to active load is controlled by DBCTL[DBFEDLOAD]   */
    GLDSEL_BIT_DBFED_GLOBAL     = 1,  /*!< Shadow to active load is controlled by GLDCTL             */
} GLDSEL_BIT_DBFED;

#define GLDSEL_ALL_DBFED_LOCAL      ((0x0UL) << GLDSEL_ALL_DBFED_Pos)
#define GLDSEL_ALL_DBFED_GLOBAL     ((0x1UL) << GLDSEL_ALL_DBFED_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMLINK         TBPRD
 *  @access     PWM->PWMLINK.bit.TBPRD
 *  @brief      Write to the TBPRD of PWM selected by PWMLINK[TBPRD] results in simultaneous write
 *              to TBPRD of current PWM module
 */
#define PWMLINK_ALL_TBPRD_Pos (0)
#define PWMLINK_ALL_TBPRD_Msk (0xFUL << PWMLINK_ALL_TBPRD_Pos)

typedef enum
{
    PWMLINK_BIT_TBPRD_LINK_PWM0     = 0,  /*!< Select PWM0       */
    PWMLINK_BIT_TBPRD_LINK_PWM1     = 1,  /*!< Select PWM1       */
    PWMLINK_BIT_TBPRD_LINK_PWM2     = 2,  /*!< Select PWM2       */
    PWMLINK_BIT_TBPRD_LINK_PWM3     = 3,  /*!< Select PWM3       */
    PWMLINK_BIT_TBPRD_LINK_PWM4     = 4,  /*!< Select PWM4       */
    PWMLINK_BIT_TBPRD_LINK_PWM5     = 5,  /*!< Select PWM5       */
    PWMLINK_BIT_TBPRD_LINK_NONE     = 15,  /*!< No PWM selected   */
} PWMLINK_BIT_TBPRD;

#define PWMLINK_ALL_TBPRD_LINK_PWM0     ((0x00UL) << PWMLINK_ALL_TBPRD_Pos)
#define PWMLINK_ALL_TBPRD_LINK_PWM1     ((0x01UL) << PWMLINK_ALL_TBPRD_Pos)
#define PWMLINK_ALL_TBPRD_LINK_PWM2     ((0x02UL) << PWMLINK_ALL_TBPRD_Pos)
#define PWMLINK_ALL_TBPRD_LINK_PWM3     ((0x03UL) << PWMLINK_ALL_TBPRD_Pos)
#define PWMLINK_ALL_TBPRD_LINK_PWM4     ((0x04UL) << PWMLINK_ALL_TBPRD_Pos)
#define PWMLINK_ALL_TBPRD_LINK_PWM5     ((0x05UL) << PWMLINK_ALL_TBPRD_Pos)
#define PWMLINK_ALL_TBPRD_LINK_NONE     ((0x0FUL) << PWMLINK_ALL_TBPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMLINK         CMPA
 *  @access     PWM->PWMLINK.bit.CMPA
 *  @brief      Write to the CMPA of PWM selected by PWMLINK[CMPA] results in simultaneous write
 *              to CMPA of current PWM module
 */
#define PWMLINK_ALL_CMPA_Pos (4)
#define PWMLINK_ALL_CMPA_Msk (0xFUL << PWMLINK_ALL_CMPA_Pos)

typedef enum
{
    PWMLINK_BIT_CMPA_LINK_PWM0     = 0,  /*!< Select PWM0       */
    PWMLINK_BIT_CMPA_LINK_PWM1     = 1,  /*!< Select PWM1       */
    PWMLINK_BIT_CMPA_LINK_PWM2     = 2,  /*!< Select PWM2       */
    PWMLINK_BIT_CMPA_LINK_PWM3     = 3,  /*!< Select PWM3       */
    PWMLINK_BIT_CMPA_LINK_PWM4     = 4,  /*!< Select PWM4       */
    PWMLINK_BIT_CMPA_LINK_PWM5     = 5,  /*!< Select PWM5       */
    PWMLINK_BIT_CMPA_LINK_NONE     = 15,  /*!< No PWM selected   */
} PWMLINK_BIT_CMPA;

#define PWMLINK_ALL_CMPA_LINK_PWM0     ((0x00UL) << PWMLINK_ALL_CMPA_Pos)
#define PWMLINK_ALL_CMPA_LINK_PWM1     ((0x01UL) << PWMLINK_ALL_CMPA_Pos)
#define PWMLINK_ALL_CMPA_LINK_PWM2     ((0x02UL) << PWMLINK_ALL_CMPA_Pos)
#define PWMLINK_ALL_CMPA_LINK_PWM3     ((0x03UL) << PWMLINK_ALL_CMPA_Pos)
#define PWMLINK_ALL_CMPA_LINK_PWM4     ((0x04UL) << PWMLINK_ALL_CMPA_Pos)
#define PWMLINK_ALL_CMPA_LINK_PWM5     ((0x05UL) << PWMLINK_ALL_CMPA_Pos)
#define PWMLINK_ALL_CMPA_LINK_NONE     ((0x0FUL) << PWMLINK_ALL_CMPA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMLINK         CMPB
 *  @access     PWM->PWMLINK.bit.CMPB
 *  @brief      Write to the CMPB of PWM selected by PWMLINK[CMPB] results in simultaneous write
 *              to CMPB of current PWM module
 */
#define PWMLINK_ALL_CMPB_Pos (8)
#define PWMLINK_ALL_CMPB_Msk (0xFUL << PWMLINK_ALL_CMPB_Pos)

typedef enum
{
    PWMLINK_BIT_CMPB_LINK_PWM0     = 0,  /*!< Select PWM0       */
    PWMLINK_BIT_CMPB_LINK_PWM1     = 1,  /*!< Select PWM1       */
    PWMLINK_BIT_CMPB_LINK_PWM2     = 2,  /*!< Select PWM2       */
    PWMLINK_BIT_CMPB_LINK_PWM3     = 3,  /*!< Select PWM3       */
    PWMLINK_BIT_CMPB_LINK_PWM4     = 4,  /*!< Select PWM4       */
    PWMLINK_BIT_CMPB_LINK_PWM5     = 5,  /*!< Select PWM5       */
    PWMLINK_BIT_CMPB_LINK_NONE     = 15,  /*!< No PWM selected   */
} PWMLINK_BIT_CMPB;

#define PWMLINK_ALL_CMPB_LINK_PWM0     ((0x00UL) << PWMLINK_ALL_CMPB_Pos)
#define PWMLINK_ALL_CMPB_LINK_PWM1     ((0x01UL) << PWMLINK_ALL_CMPB_Pos)
#define PWMLINK_ALL_CMPB_LINK_PWM2     ((0x02UL) << PWMLINK_ALL_CMPB_Pos)
#define PWMLINK_ALL_CMPB_LINK_PWM3     ((0x03UL) << PWMLINK_ALL_CMPB_Pos)
#define PWMLINK_ALL_CMPB_LINK_PWM4     ((0x04UL) << PWMLINK_ALL_CMPB_Pos)
#define PWMLINK_ALL_CMPB_LINK_PWM5     ((0x05UL) << PWMLINK_ALL_CMPB_Pos)
#define PWMLINK_ALL_CMPB_LINK_NONE     ((0x0FUL) << PWMLINK_ALL_CMPB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMLINK         CMPC
 *  @access     PWM->PWMLINK.bit.CMPC
 *  @brief      Write to the CMPC of PWM selected by PWMLINK[CMPC] results in simultaneous write
 *              to CMPC of current PWM module
 */
#define PWMLINK_ALL_CMPC_Pos (12)
#define PWMLINK_ALL_CMPC_Msk (0xFUL << PWMLINK_ALL_CMPC_Pos)

typedef enum
{
    PWMLINK_BIT_CMPC_LINK_PWM0     = 0,  /*!< Select PWM0       */
    PWMLINK_BIT_CMPC_LINK_PWM1     = 1,  /*!< Select PWM1       */
    PWMLINK_BIT_CMPC_LINK_PWM2     = 2,  /*!< Select PWM2       */
    PWMLINK_BIT_CMPC_LINK_PWM3     = 3,  /*!< Select PWM3       */
    PWMLINK_BIT_CMPC_LINK_PWM4     = 4,  /*!< Select PWM4       */
    PWMLINK_BIT_CMPC_LINK_PWM5     = 5,  /*!< Select PWM5       */
    PWMLINK_BIT_CMPC_LINK_NONE     = 15,  /*!< No PWM selected   */
} PWMLINK_BIT_CMPC;

#define PWMLINK_ALL_CMPC_LINK_PWM0     ((0x00UL) << PWMLINK_ALL_CMPC_Pos)
#define PWMLINK_ALL_CMPC_LINK_PWM1     ((0x01UL) << PWMLINK_ALL_CMPC_Pos)
#define PWMLINK_ALL_CMPC_LINK_PWM2     ((0x02UL) << PWMLINK_ALL_CMPC_Pos)
#define PWMLINK_ALL_CMPC_LINK_PWM3     ((0x03UL) << PWMLINK_ALL_CMPC_Pos)
#define PWMLINK_ALL_CMPC_LINK_PWM4     ((0x04UL) << PWMLINK_ALL_CMPC_Pos)
#define PWMLINK_ALL_CMPC_LINK_PWM5     ((0x05UL) << PWMLINK_ALL_CMPC_Pos)
#define PWMLINK_ALL_CMPC_LINK_NONE     ((0x0FUL) << PWMLINK_ALL_CMPC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMLINK         CMPD
 *  @access     PWM->PWMLINK.bit.CMPD
 *  @brief      Write to the CMPD of PWM selected by PWMLINK[CMPD] results in simultaneous write
 *              to CMPD of current PWM module
 */
#define PWMLINK_ALL_CMPD_Pos (16)
#define PWMLINK_ALL_CMPD_Msk (0xFUL << PWMLINK_ALL_CMPD_Pos)

typedef enum
{
    PWMLINK_BIT_CMPD_LINK_PWM0     = 0,  /*!< Select PWM0       */
    PWMLINK_BIT_CMPD_LINK_PWM1     = 1,  /*!< Select PWM1       */
    PWMLINK_BIT_CMPD_LINK_PWM2     = 2,  /*!< Select PWM2       */
    PWMLINK_BIT_CMPD_LINK_PWM3     = 3,  /*!< Select PWM3       */
    PWMLINK_BIT_CMPD_LINK_PWM4     = 4,  /*!< Select PWM4       */
    PWMLINK_BIT_CMPD_LINK_PWM5     = 5,  /*!< Select PWM5       */
    PWMLINK_BIT_CMPD_LINK_NONE     = 15,  /*!< No PWM selected   */
} PWMLINK_BIT_CMPD;

#define PWMLINK_ALL_CMPD_LINK_PWM0     ((0x00UL) << PWMLINK_ALL_CMPD_Pos)
#define PWMLINK_ALL_CMPD_LINK_PWM1     ((0x01UL) << PWMLINK_ALL_CMPD_Pos)
#define PWMLINK_ALL_CMPD_LINK_PWM2     ((0x02UL) << PWMLINK_ALL_CMPD_Pos)
#define PWMLINK_ALL_CMPD_LINK_PWM3     ((0x03UL) << PWMLINK_ALL_CMPD_Pos)
#define PWMLINK_ALL_CMPD_LINK_PWM4     ((0x04UL) << PWMLINK_ALL_CMPD_Pos)
#define PWMLINK_ALL_CMPD_LINK_PWM5     ((0x05UL) << PWMLINK_ALL_CMPD_Pos)
#define PWMLINK_ALL_CMPD_LINK_NONE     ((0x0FUL) << PWMLINK_ALL_CMPD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMLINK         DBRED
 *  @access     PWM->PWMLINK.bit.DBRED
 *  @brief      Write to the DBRED of PWM selected by PWMLINK[DBRED] results in simultaneous write
 *              to DBRED of current PWM module
 */
#define PWMLINK_ALL_DBRED_Pos (20)
#define PWMLINK_ALL_DBRED_Msk (0xFUL << PWMLINK_ALL_DBRED_Pos)

typedef enum
{
    PWMLINK_BIT_DBRED_LINK_PWM0     = 0,  /*!< Select PWM0       */
    PWMLINK_BIT_DBRED_LINK_PWM1     = 1,  /*!< Select PWM1       */
    PWMLINK_BIT_DBRED_LINK_PWM2     = 2,  /*!< Select PWM2       */
    PWMLINK_BIT_DBRED_LINK_PWM3     = 3,  /*!< Select PWM3       */
    PWMLINK_BIT_DBRED_LINK_PWM4     = 4,  /*!< Select PWM4       */
    PWMLINK_BIT_DBRED_LINK_PWM5     = 5,  /*!< Select PWM5       */
    PWMLINK_BIT_DBRED_LINK_NONE     = 15,  /*!< No PWM selected   */
} PWMLINK_BIT_DBRED;

#define PWMLINK_ALL_DBRED_LINK_PWM0     ((0x00UL) << PWMLINK_ALL_DBRED_Pos)
#define PWMLINK_ALL_DBRED_LINK_PWM1     ((0x01UL) << PWMLINK_ALL_DBRED_Pos)
#define PWMLINK_ALL_DBRED_LINK_PWM2     ((0x02UL) << PWMLINK_ALL_DBRED_Pos)
#define PWMLINK_ALL_DBRED_LINK_PWM3     ((0x03UL) << PWMLINK_ALL_DBRED_Pos)
#define PWMLINK_ALL_DBRED_LINK_PWM4     ((0x04UL) << PWMLINK_ALL_DBRED_Pos)
#define PWMLINK_ALL_DBRED_LINK_PWM5     ((0x05UL) << PWMLINK_ALL_DBRED_Pos)
#define PWMLINK_ALL_DBRED_LINK_NONE     ((0x0FUL) << PWMLINK_ALL_DBRED_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMLINK         DBFED
 *  @access     PWM->PWMLINK.bit.DBFED
 *  @brief      Write to the DBFED of PWM selected by PWMLINK[DBFED] results in simultaneous write
 *              to DBFED of current PWM module
 */
#define PWMLINK_ALL_DBFED_Pos (24)
#define PWMLINK_ALL_DBFED_Msk (0xFUL << PWMLINK_ALL_DBFED_Pos)

typedef enum
{
    PWMLINK_BIT_DBFED_LINK_PWM0     = 0,  /*!< Select PWM0       */
    PWMLINK_BIT_DBFED_LINK_PWM1     = 1,  /*!< Select PWM1       */
    PWMLINK_BIT_DBFED_LINK_PWM2     = 2,  /*!< Select PWM2       */
    PWMLINK_BIT_DBFED_LINK_PWM3     = 3,  /*!< Select PWM3       */
    PWMLINK_BIT_DBFED_LINK_PWM4     = 4,  /*!< Select PWM4       */
    PWMLINK_BIT_DBFED_LINK_PWM5     = 5,  /*!< Select PWM5       */
    PWMLINK_BIT_DBFED_LINK_NONE     = 15,  /*!< No PWM selected   */
} PWMLINK_BIT_DBFED;

#define PWMLINK_ALL_DBFED_LINK_PWM0     ((0x00UL) << PWMLINK_ALL_DBFED_Pos)
#define PWMLINK_ALL_DBFED_LINK_PWM1     ((0x01UL) << PWMLINK_ALL_DBFED_Pos)
#define PWMLINK_ALL_DBFED_LINK_PWM2     ((0x02UL) << PWMLINK_ALL_DBFED_Pos)
#define PWMLINK_ALL_DBFED_LINK_PWM3     ((0x03UL) << PWMLINK_ALL_DBFED_Pos)
#define PWMLINK_ALL_DBFED_LINK_PWM4     ((0x04UL) << PWMLINK_ALL_DBFED_Pos)
#define PWMLINK_ALL_DBFED_LINK_PWM5     ((0x05UL) << PWMLINK_ALL_DBFED_Pos)
#define PWMLINK_ALL_DBFED_LINK_NONE     ((0x0FUL) << PWMLINK_ALL_DBFED_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMLINK         GLDCTL1
 *  @access     PWM->PWMLINK.bit.GLDCTL1
 *  @brief      Write to the GLDCTL1 of PWM selected by PWMLINK[GLDCTL1] results in simultaneous
 *              write to GLDCTL1 of current PWM module
 */
#define PWMLINK_ALL_GLDCTL1_Pos (28)
#define PWMLINK_ALL_GLDCTL1_Msk (0xFUL << PWMLINK_ALL_GLDCTL1_Pos)

typedef enum
{
    PWMLINK_BIT_GLDCTL1_LINK_PWM0     = 0,  /*!< Select PWM0       */
    PWMLINK_BIT_GLDCTL1_LINK_PWM1     = 1,  /*!< Select PWM1       */
    PWMLINK_BIT_GLDCTL1_LINK_PWM2     = 2,  /*!< Select PWM2       */
    PWMLINK_BIT_GLDCTL1_LINK_PWM3     = 3,  /*!< Select PWM3       */
    PWMLINK_BIT_GLDCTL1_LINK_PWM4     = 4,  /*!< Select PWM4       */
    PWMLINK_BIT_GLDCTL1_LINK_PWM5     = 5,  /*!< Select PWM5       */
    PWMLINK_BIT_GLDCTL1_LINK_NONE     = 15,  /*!< No PWM selected   */
} PWMLINK_BIT_GLDCTL1;

#define PWMLINK_ALL_GLDCTL1_LINK_PWM0     ((0x00UL) << PWMLINK_ALL_GLDCTL1_Pos)
#define PWMLINK_ALL_GLDCTL1_LINK_PWM1     ((0x01UL) << PWMLINK_ALL_GLDCTL1_Pos)
#define PWMLINK_ALL_GLDCTL1_LINK_PWM2     ((0x02UL) << PWMLINK_ALL_GLDCTL1_Pos)
#define PWMLINK_ALL_GLDCTL1_LINK_PWM3     ((0x03UL) << PWMLINK_ALL_GLDCTL1_Pos)
#define PWMLINK_ALL_GLDCTL1_LINK_PWM4     ((0x04UL) << PWMLINK_ALL_GLDCTL1_Pos)
#define PWMLINK_ALL_GLDCTL1_LINK_PWM5     ((0x05UL) << PWMLINK_ALL_GLDCTL1_Pos)
#define PWMLINK_ALL_GLDCTL1_LINK_NONE     ((0x0FUL) << PWMLINK_ALL_GLDCTL1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           CNTRUN
 *  @access     PWM->TBCTL.bit.CNTRUN
 *  @brief      Counter run/stop control
 */
#define TBCTL_ALL_CNTRUN_Pos (0)
#define TBCTL_ALL_CNTRUN_Msk (0x1UL << TBCTL_ALL_CNTRUN_Pos)

typedef enum
{
    TBCTL_BIT_CNTRUN_COUNT_STOP     = 0,  /*!< Counter stop           */
    TBCTL_BIT_CNTRUN_COUNT_RUN      = 1,  /*!< Counter free-running   */
} TBCTL_BIT_CNTRUN;

#define TBCTL_ALL_CNTRUN_COUNT_STOP     ((0x0UL) << TBCTL_ALL_CNTRUN_Pos)
#define TBCTL_ALL_CNTRUN_COUNT_RUN      ((0x1UL) << TBCTL_ALL_CNTRUN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           CNTMODE
 *  @access     PWM->TBCTL.bit.CNTMODE
 *  @brief      Counter mode
 */
#define TBCTL_ALL_CNTMODE_Pos (1)
#define TBCTL_ALL_CNTMODE_Msk (0x3UL << TBCTL_ALL_CNTMODE_Pos)

typedef enum
{
    TBCTL_BIT_CNTMODE_COUNT_DOWN        = 0,  /*!< Down-count                           */
    TBCTL_BIT_CNTMODE_COUNT_UP          = 1,  /*!< Up-count                             */
    TBCTL_BIT_CNTMODE_COUNT_UP_DOWN     = 2,  /*!< Up-down-count                        */
    TBCTL_BIT_CNTMODE_COUNT_FREEZE      = 3,  /*!< Stop and freeze (default on reset)   */
} TBCTL_BIT_CNTMODE;

#define TBCTL_ALL_CNTMODE_COUNT_DOWN        ((0x0UL) << TBCTL_ALL_CNTMODE_Pos)
#define TBCTL_ALL_CNTMODE_COUNT_UP          ((0x1UL) << TBCTL_ALL_CNTMODE_Pos)
#define TBCTL_ALL_CNTMODE_COUNT_UP_DOWN     ((0x2UL) << TBCTL_ALL_CNTMODE_Pos)
#define TBCTL_ALL_CNTMODE_COUNT_FREEZE      ((0x3UL) << TBCTL_ALL_CNTMODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           PHSEN
 *  @access     PWM->TBCTL.bit.PHSEN
 *  @brief      Phase register enable
 */
#define TBCTL_ALL_PHSEN_Pos (3)
#define TBCTL_ALL_PHSEN_Msk (0x1UL << TBCTL_ALL_PHSEN_Pos)

typedef enum
{
    TBCTL_BIT_PHSEN_DISABLE     = 0,  /*!< Do not load time-base counter (TBCNT) from time-base phase register (TBPHS)                      */
    TBCTL_BIT_PHSEN_ENABLE      = 1,  /*!< Load TBCNT from TBPHS when synchronization event occurs (SYNCI input, software synchronization  
                                           or digital compare sync event)                                                                   */
} TBCTL_BIT_PHSEN;

#define TBCTL_ALL_PHSEN_DISABLE     ((0x0UL) << TBCTL_ALL_PHSEN_Pos)
#define TBCTL_ALL_PHSEN_ENABLE      ((0x1UL) << TBCTL_ALL_PHSEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           PHSDIR
 *  @access     PWM->TBCTL.bit.PHSDIR
 *  @brief      Phase direction
 *              It is valid only when TBCNT is in up-down-count mode (CNTMODE=10)
 */
#define TBCTL_ALL_PHSDIR_Pos (4)
#define TBCTL_ALL_PHSDIR_Msk (0x1UL << TBCTL_ALL_PHSDIR_Pos)

typedef enum
{
    TBCTL_BIT_PHSDIR_COUNT_DOWN_AFTER_SYNC     = 0,  /*!< Count down after synchronization event   */
    TBCTL_BIT_PHSDIR_COUNT_UP_AFTER_SYNC       = 1,  /*!< Count up after synchronization event     */
} TBCTL_BIT_PHSDIR;

#define TBCTL_ALL_PHSDIR_COUNT_DOWN_AFTER_SYNC     ((0x0UL) << TBCTL_ALL_PHSDIR_Pos)
#define TBCTL_ALL_PHSDIR_COUNT_UP_AFTER_SYNC       ((0x1UL) << TBCTL_ALL_PHSDIR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           TBPRDLOAD
 *  @access     PWM->TBCTL.bit.TBPRDLOAD
 *  @brief      TBPRD active value load mode
 *              It has no effect when TBCTL[TBPRDLOCK]=1
 */
#define TBCTL_ALL_TBPRDLOAD_Pos (5)
#define TBCTL_ALL_TBPRDLOAD_Msk (0x3UL << TBCTL_ALL_TBPRDLOAD_Pos)

typedef enum
{
    TBCTL_BIT_TBPRDLOAD_LOAD_ON_ZERO          = 0,  /*!< Load TBPRD into TBPRDA on TBCNT=0                                */
    TBCTL_BIT_TBPRDLOAD_LOAD_ON_SYNC          = 1,  /*!< Load TBPRD into TBPRDA on SYNC event                             */
    TBCTL_BIT_TBPRDLOAD_LOAD_ON_SYNC_ZERO     = 2,  /*!< Load TBPRD into TBPRDA on SYNC event or TBCNT=0                  */
    TBCTL_BIT_TBPRDLOAD_LOAD_IMMEDIATE        = 3,  /*!< Write TBPRD will immediately change the active value in TBPRDA   */
} TBCTL_BIT_TBPRDLOAD;

#define TBCTL_ALL_TBPRDLOAD_LOAD_ON_ZERO          ((0x0UL) << TBCTL_ALL_TBPRDLOAD_Pos)
#define TBCTL_ALL_TBPRDLOAD_LOAD_ON_SYNC          ((0x1UL) << TBCTL_ALL_TBPRDLOAD_Pos)
#define TBCTL_ALL_TBPRDLOAD_LOAD_ON_SYNC_ZERO     ((0x2UL) << TBCTL_ALL_TBPRDLOAD_Pos)
#define TBCTL_ALL_TBPRDLOAD_LOAD_IMMEDIATE        ((0x3UL) << TBCTL_ALL_TBPRDLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           TBPRDLOCK
 *  @access     PWM->TBCTL.bit.TBPRDLOCK
 *  @brief      TBPRD active value lock
 */
#define TBCTL_ALL_TBPRDLOCK_Pos (7)
#define TBCTL_ALL_TBPRDLOCK_Msk (0x1UL << TBCTL_ALL_TBPRDLOCK_Pos)

typedef enum
{
    TBCTL_BIT_TBPRDLOCK_UNLOCK     = 0,  /*!< Active value in TBPRDA is updated according to TBCTL[TBPRDLOAD]   */
    TBCTL_BIT_TBPRDLOCK_LOCK       = 1,  /*!< Active value in TBPRDA will not change                            */
} TBCTL_BIT_TBPRDLOCK;

#define TBCTL_ALL_TBPRDLOCK_UNLOCK     ((0x0UL) << TBCTL_ALL_TBPRDLOCK_Pos)
#define TBCTL_ALL_TBPRDLOCK_LOCK       ((0x1UL) << TBCTL_ALL_TBPRDLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           SYNCOSEL
 *  @access     PWM->TBCTL.bit.SYNCOSEL
 *  @brief      Synchronization output select
 */
#define TBCTL_ALL_SYNCOSEL_Pos (8)
#define TBCTL_ALL_SYNCOSEL_Msk (0x7UL << TBCTL_ALL_SYNCOSEL_Pos)

typedef enum
{
    TBCTL_BIT_SYNCOSEL_SYNCI_AND_FRCSYNC     = 0,  /*!< SYNCI and the software forced sync   */
    TBCTL_BIT_SYNCOSEL_TBCNT_EQU_ZERO        = 1,  /*!< TBCNT=0 event                        */
    TBCTL_BIT_SYNCOSEL_TBCNT_EQU_TBPRD       = 2,  /*!< TBCNT=TBPRD event                    */
    TBCTL_BIT_SYNCOSEL_TBCNT_EQU_CMPA        = 3,  /*!< TBCNT=CMPA event                     */
    TBCTL_BIT_SYNCOSEL_TBCNT_EQU_CMPB        = 4,  /*!< TBCNT=CMPB event                     */
    TBCTL_BIT_SYNCOSEL_TBCNT_EQU_CMPC        = 5,  /*!< TBCNT=CMPC event                     */
    TBCTL_BIT_SYNCOSEL_TBCNT_EQU_CMPD        = 6,  /*!< TBCNT=CMPD event                     */
    TBCTL_BIT_SYNCOSEL_DISABLE               = 7,  /*!< Disable SYNCO                        */
} TBCTL_BIT_SYNCOSEL;

#define TBCTL_ALL_SYNCOSEL_SYNCI_AND_FRCSYNC     ((0x0UL) << TBCTL_ALL_SYNCOSEL_Pos)
#define TBCTL_ALL_SYNCOSEL_TBCNT_EQU_ZERO        ((0x1UL) << TBCTL_ALL_SYNCOSEL_Pos)
#define TBCTL_ALL_SYNCOSEL_TBCNT_EQU_TBPRD       ((0x2UL) << TBCTL_ALL_SYNCOSEL_Pos)
#define TBCTL_ALL_SYNCOSEL_TBCNT_EQU_CMPA        ((0x3UL) << TBCTL_ALL_SYNCOSEL_Pos)
#define TBCTL_ALL_SYNCOSEL_TBCNT_EQU_CMPB        ((0x4UL) << TBCTL_ALL_SYNCOSEL_Pos)
#define TBCTL_ALL_SYNCOSEL_TBCNT_EQU_CMPC        ((0x5UL) << TBCTL_ALL_SYNCOSEL_Pos)
#define TBCTL_ALL_SYNCOSEL_TBCNT_EQU_CMPD        ((0x6UL) << TBCTL_ALL_SYNCOSEL_Pos)
#define TBCTL_ALL_SYNCOSEL_DISABLE               ((0x7UL) << TBCTL_ALL_SYNCOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           FRCSYNC
 *  @access     PWM->TBCTL.bit.FRCSYNC
 *  @brief      Software forced synchronization
 *              This event is ORed with SYNCI input and is valid only when SYNCOSEL=000
 */
#define TBCTL_ALL_FRCSYNC_Pos (11)
#define TBCTL_ALL_FRCSYNC_Msk (0x1UL << TBCTL_ALL_FRCSYNC_Pos)

typedef enum
{
    TBCTL_BIT_FRCSYNC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and reads always return a 0                                */
    TBCTL_BIT_FRCSYNC_ENABLE        = 1,  /*!< Write a 1 forces a one-time synchronization pulse. This bit is self-cleared to 0  
                                               and not affected by PWMREGKEY protection                                           */
} TBCTL_BIT_FRCSYNC;

#define TBCTL_ALL_FRCSYNC_NO_EFFECT     ((0x0UL) << TBCTL_ALL_FRCSYNC_Pos)
#define TBCTL_ALL_FRCSYNC_ENABLE        ((0x1UL) << TBCTL_ALL_FRCSYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           TBDIVLIN
 *  @access     PWM->TBCTL.bit.TBDIVLIN
 *  @brief      Lineary part of TBCLK dividing ratio from PWM clock input. Overall dividing ratio
 *              is 2^TBDIVBIN * (TBDIVLIN+1)
 */
#define TBCTL_ALL_TBDIVLIN_Pos (12)
#define TBCTL_ALL_TBDIVLIN_Msk (0x7UL << TBCTL_ALL_TBDIVLIN_Pos)

typedef enum
{
    TBCTL_BIT_TBDIVLIN_1     = 0,  /*!< Divide by 1 (default on reset)   */
    TBCTL_BIT_TBDIVLIN_2     = 1,  /*!< Divide by 2                      */
    TBCTL_BIT_TBDIVLIN_3     = 2,  /*!< Divide by 3                      */
    TBCTL_BIT_TBDIVLIN_4     = 3,  /*!< Divide by 4                      */
    TBCTL_BIT_TBDIVLIN_5     = 4,  /*!< Divide by 5                      */
    TBCTL_BIT_TBDIVLIN_6     = 5,  /*!< Divide by 6                      */
    TBCTL_BIT_TBDIVLIN_7     = 6,  /*!< Divide by 7                      */
    TBCTL_BIT_TBDIVLIN_8     = 7,  /*!< Divide by 8                      */
} TBCTL_BIT_TBDIVLIN;

#define TBCTL_ALL_TBDIVLIN_1     ((0x0UL) << TBCTL_ALL_TBDIVLIN_Pos)
#define TBCTL_ALL_TBDIVLIN_2     ((0x1UL) << TBCTL_ALL_TBDIVLIN_Pos)
#define TBCTL_ALL_TBDIVLIN_3     ((0x2UL) << TBCTL_ALL_TBDIVLIN_Pos)
#define TBCTL_ALL_TBDIVLIN_4     ((0x3UL) << TBCTL_ALL_TBDIVLIN_Pos)
#define TBCTL_ALL_TBDIVLIN_5     ((0x4UL) << TBCTL_ALL_TBDIVLIN_Pos)
#define TBCTL_ALL_TBDIVLIN_6     ((0x5UL) << TBCTL_ALL_TBDIVLIN_Pos)
#define TBCTL_ALL_TBDIVLIN_7     ((0x6UL) << TBCTL_ALL_TBDIVLIN_Pos)
#define TBCTL_ALL_TBDIVLIN_8     ((0x7UL) << TBCTL_ALL_TBDIVLIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           TBDIVBIN
 *  @access     PWM->TBCTL.bit.TBDIVBIN
 *  @brief      Binary part of TBCLK dividing ratio from PWM clock input. Overall dividing ratio
 *              is 2^TBDIVBIN * (TBDIVLIN+1)
 */
#define TBCTL_ALL_TBDIVBIN_Pos (15)
#define TBCTL_ALL_TBDIVBIN_Msk (0x7UL << TBCTL_ALL_TBDIVBIN_Pos)

typedef enum
{
    TBCTL_BIT_TBDIVBIN_1       = 0,  /*!< Divide by 1 (default on reset)   */
    TBCTL_BIT_TBDIVBIN_2       = 1,  /*!< Divide by 2                      */
    TBCTL_BIT_TBDIVBIN_4       = 2,  /*!< Divide by 4                      */
    TBCTL_BIT_TBDIVBIN_8       = 3,  /*!< Divide by 8                      */
    TBCTL_BIT_TBDIVBIN_16      = 4,  /*!< Divide by 16                     */
    TBCTL_BIT_TBDIVBIN_32      = 5,  /*!< Divide by 32                     */
    TBCTL_BIT_TBDIVBIN_64      = 6,  /*!< Divide by 64                     */
    TBCTL_BIT_TBDIVBIN_128     = 7,  /*!< Divide by 128                    */
} TBCTL_BIT_TBDIVBIN;

#define TBCTL_ALL_TBDIVBIN_1       ((0x0UL) << TBCTL_ALL_TBDIVBIN_Pos)
#define TBCTL_ALL_TBDIVBIN_2       ((0x1UL) << TBCTL_ALL_TBDIVBIN_Pos)
#define TBCTL_ALL_TBDIVBIN_4       ((0x2UL) << TBCTL_ALL_TBDIVBIN_Pos)
#define TBCTL_ALL_TBDIVBIN_8       ((0x3UL) << TBCTL_ALL_TBDIVBIN_Pos)
#define TBCTL_ALL_TBDIVBIN_16      ((0x4UL) << TBCTL_ALL_TBDIVBIN_Pos)
#define TBCTL_ALL_TBDIVBIN_32      ((0x5UL) << TBCTL_ALL_TBDIVBIN_Pos)
#define TBCTL_ALL_TBDIVBIN_64      ((0x6UL) << TBCTL_ALL_TBDIVBIN_Pos)
#define TBCTL_ALL_TBDIVBIN_128     ((0x7UL) << TBCTL_ALL_TBDIVBIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCTL           DBGRUN
 *  @access     PWM->TBCTL.bit.DBGRUN
 *  @brief      PWM counter behaviour when CPU is halted
 *              Note: Debug operation and CPU fault exceptions both can cause CPU halted.
 */
#define TBCTL_ALL_DBGRUN_Pos (18)
#define TBCTL_ALL_DBGRUN_Msk (0x3UL << TBCTL_ALL_DBGRUN_Pos)

typedef enum
{
    TBCTL_BIT_DBGRUN_STOP_AFTER_COUNTING     = 0,  /*!< Stop after the next time-base counter increment or decrement                         */
    TBCTL_BIT_DBGRUN_STOP_AFTER_CYCLE        = 1,  /*!< Stop when TBCNT completes a whole cycle (TBCNT=TBPRD for up-count mode and TBCNT=0  
                                                        for other modes)                                                                     */
    TBCTL_BIT_DBGRUN_KEEP_RUN                = 2,  /*!< Counter keep running when CPU is halted                                              */
} TBCTL_BIT_DBGRUN;

#define TBCTL_ALL_DBGRUN_STOP_AFTER_COUNTING     ((0x0UL) << TBCTL_ALL_DBGRUN_Pos)
#define TBCTL_ALL_DBGRUN_STOP_AFTER_CYCLE        ((0x1UL) << TBCTL_ALL_DBGRUN_Pos)
#define TBCTL_ALL_DBGRUN_KEEP_RUN                ((0x2UL) << TBCTL_ALL_DBGRUN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBPRD           VAL
 *  @access     PWM->TBPRD.bit.VAL
 *  @brief      Time-base counter period
 */
#define TBPRD_ALL_VAL_Pos (0)
#define TBPRD_ALL_VAL_Msk (0xFFFFUL << TBPRD_ALL_VAL_Pos)

#define TBPRD_BIT_VAL

#define TBPRD_ALL_VAL_(x) ((x) << TBPRD_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBPRDA          VAL
 *  @access     PWM->TBPRDA.bit.VAL
 *  @brief      Time-base counter active period
 *              When TBCTL[PRDLOAD]=0x3, write to TBPRD directly affects this register.
 *              Otherwise, the value is loaded from TBPRD upon the events defined in TBCTL[PRDLOAD].
 */
#define TBPRDA_ALL_VAL_Pos (0)
#define TBPRDA_ALL_VAL_Msk (0xFFFFUL << TBPRDA_ALL_VAL_Pos)

#define TBPRDA_BIT_VAL

#define TBPRDA_ALL_VAL_(x) ((x) << TBPRDA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBPHS           VAL
 *  @access     PWM->TBPHS.bit.VAL
 *  @brief      Time-base counter phase when synchronization event occurs
 *              TBCTL[PHSEN]=0: The synchronization event is ignored and TBCNT keeps its value.
 *              TBCTL[PHSEN]=1: Time-base counter (TBCNT) will be loaded with TBPHS when synchronization
 *              event occurs.
 */
#define TBPHS_ALL_VAL_Pos (0)
#define TBPHS_ALL_VAL_Msk (0xFFFFUL << TBPHS_ALL_VAL_Pos)

#define TBPHS_BIT_VAL

#define TBPHS_ALL_VAL_(x) ((x) << TBPHS_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBCNT           VAL
 *  @access     PWM->TBCNT.bit.VAL
 *  @brief      Current value of the time-base counter
 */
#define TBCNT_ALL_VAL_Pos (0)
#define TBCNT_ALL_VAL_Msk (0xFFFFUL << TBCNT_ALL_VAL_Pos)

#define TBCNT_BIT_VAL

#define TBCNT_ALL_VAL_(x) ((x) << TBCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           SYNCI
 *  @access     PWM->TBSTS.bit.SYNCI
 *  @brief      Input synchronization latched status
 */
#define TBSTS_ALL_SYNCI_Pos (0)
#define TBSTS_ALL_SYNCI_Msk (0x1UL << TBSTS_ALL_SYNCI_Pos)

typedef enum
{
    TBSTS_BIT_SYNCI_NO_EVENT        = 0,  /*!< No input synchronization event has occurred   */
    TBSTS_BIT_SYNCI_EVENT_OCCUR     = 1,  /*!< An input synchronization event has occurred   */
} TBSTS_BIT_SYNCI;

#define TBSTS_ALL_SYNCI_NO_EVENT        ((0x0UL) << TBSTS_ALL_SYNCI_Pos)
#define TBSTS_ALL_SYNCI_EVENT_OCCUR     ((0x1UL) << TBSTS_ALL_SYNCI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           CNTMAX
 *  @access     PWM->TBSTS.bit.CNTMAX
 *  @brief      Time-base counter reaching max latched status
 */
#define TBSTS_ALL_CNTMAX_Pos (1)
#define TBSTS_ALL_CNTMAX_Msk (0x1UL << TBSTS_ALL_CNTMAX_Pos)

typedef enum
{
    TBSTS_BIT_CNTMAX_NOT_REACHED     = 0,  /*!< TBCNT never reaches 0xFFFFFFFF   */
    TBSTS_BIT_CNTMAX_REACHED         = 1,  /*!< TBCNT reached 0xFFFFFFFF         */
} TBSTS_BIT_CNTMAX;

#define TBSTS_ALL_CNTMAX_NOT_REACHED     ((0x0UL) << TBSTS_ALL_CNTMAX_Pos)
#define TBSTS_ALL_CNTMAX_REACHED         ((0x1UL) << TBSTS_ALL_CNTMAX_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           CNTZRO
 *  @access     PWM->TBSTS.bit.CNTZRO
 *  @brief      Time-base counter reaching zero latched status
 */
#define TBSTS_ALL_CNTZRO_Pos (2)
#define TBSTS_ALL_CNTZRO_Msk (0x1UL << TBSTS_ALL_CNTZRO_Pos)

typedef enum
{
    TBSTS_BIT_CNTZRO_NOT_REACHED     = 0,  /*!< TBCNT never reaches 0x0   */
    TBSTS_BIT_CNTZRO_REACHED         = 1,  /*!< TBCNT reached 0x0         */
} TBSTS_BIT_CNTZRO;

#define TBSTS_ALL_CNTZRO_NOT_REACHED     ((0x0UL) << TBSTS_ALL_CNTZRO_Pos)
#define TBSTS_ALL_CNTZRO_REACHED         ((0x1UL) << TBSTS_ALL_CNTZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           CNTPRD
 *  @access     PWM->TBSTS.bit.CNTPRD
 *  @brief      Time-base counter reaching period latched status
 */
#define TBSTS_ALL_CNTPRD_Pos (3)
#define TBSTS_ALL_CNTPRD_Msk (0x1UL << TBSTS_ALL_CNTPRD_Pos)

typedef enum
{
    TBSTS_BIT_CNTPRD_NOT_REACHED     = 0,  /*!< TBCNT never reaches TBPRD   */
    TBSTS_BIT_CNTPRD_REACHED         = 1,  /*!< TBCNT reached TBPRD         */
} TBSTS_BIT_CNTPRD;

#define TBSTS_ALL_CNTPRD_NOT_REACHED     ((0x0UL) << TBSTS_ALL_CNTPRD_Pos)
#define TBSTS_ALL_CNTPRD_REACHED         ((0x1UL) << TBSTS_ALL_CNTPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           CNTCMPA
 *  @access     PWM->TBSTS.bit.CNTCMPA
 *  @brief      Time-base counter reaching CMPA latched status
 */
#define TBSTS_ALL_CNTCMPA_Pos (4)
#define TBSTS_ALL_CNTCMPA_Msk (0x1UL << TBSTS_ALL_CNTCMPA_Pos)

typedef enum
{
    TBSTS_BIT_CNTCMPA_NOT_REACHED     = 0,  /*!< TBCNTnever reaches CMPA   */
    TBSTS_BIT_CNTCMPA_REACHED         = 1,  /*!< TBCNT reached CMPA        */
} TBSTS_BIT_CNTCMPA;

#define TBSTS_ALL_CNTCMPA_NOT_REACHED     ((0x0UL) << TBSTS_ALL_CNTCMPA_Pos)
#define TBSTS_ALL_CNTCMPA_REACHED         ((0x1UL) << TBSTS_ALL_CNTCMPA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           CNTCMPB
 *  @access     PWM->TBSTS.bit.CNTCMPB
 *  @brief      Time-base counter reaching CMPB latched status
 */
#define TBSTS_ALL_CNTCMPB_Pos (5)
#define TBSTS_ALL_CNTCMPB_Msk (0x1UL << TBSTS_ALL_CNTCMPB_Pos)

typedef enum
{
    TBSTS_BIT_CNTCMPB_NOT_REACHED     = 0,  /*!< TBCNT never reaches CMPB   */
    TBSTS_BIT_CNTCMPB_REACHED         = 1,  /*!< TBCNT reached CMPB         */
} TBSTS_BIT_CNTCMPB;

#define TBSTS_ALL_CNTCMPB_NOT_REACHED     ((0x0UL) << TBSTS_ALL_CNTCMPB_Pos)
#define TBSTS_ALL_CNTCMPB_REACHED         ((0x1UL) << TBSTS_ALL_CNTCMPB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           CNTCMPC
 *  @access     PWM->TBSTS.bit.CNTCMPC
 *  @brief      Time-base counter reaching CMPC latched status
 */
#define TBSTS_ALL_CNTCMPC_Pos (6)
#define TBSTS_ALL_CNTCMPC_Msk (0x1UL << TBSTS_ALL_CNTCMPC_Pos)

typedef enum
{
    TBSTS_BIT_CNTCMPC_NOT_REACHED     = 0,  /*!< TBCNT never reaches CMPC   */
    TBSTS_BIT_CNTCMPC_REACHED         = 1,  /*!< TBCNT reached CMPC         */
} TBSTS_BIT_CNTCMPC;

#define TBSTS_ALL_CNTCMPC_NOT_REACHED     ((0x0UL) << TBSTS_ALL_CNTCMPC_Pos)
#define TBSTS_ALL_CNTCMPC_REACHED         ((0x1UL) << TBSTS_ALL_CNTCMPC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           CNTCMPD
 *  @access     PWM->TBSTS.bit.CNTCMPD
 *  @brief      Time-base counter reaching CMPD latched status
 */
#define TBSTS_ALL_CNTCMPD_Pos (7)
#define TBSTS_ALL_CNTCMPD_Msk (0x1UL << TBSTS_ALL_CNTCMPD_Pos)

typedef enum
{
    TBSTS_BIT_CNTCMPD_NOT_REACHED     = 0,  /*!< TBCNT never reaches CMPD   */
    TBSTS_BIT_CNTCMPD_REACHED         = 1,  /*!< TBCNT reached CMPD         */
} TBSTS_BIT_CNTCMPD;

#define TBSTS_ALL_CNTCMPD_NOT_REACHED     ((0x0UL) << TBSTS_ALL_CNTCMPD_Pos)
#define TBSTS_ALL_CNTCMPD_REACHED         ((0x1UL) << TBSTS_ALL_CNTCMPD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTS           CNTDIR
 *  @access     PWM->TBSTS.bit.CNTDIR
 *  @brief      Time-base counter direction status
 */
#define TBSTS_ALL_CNTDIR_Pos (8)
#define TBSTS_ALL_CNTDIR_Msk (0x1UL << TBSTS_ALL_CNTDIR_Pos)

typedef enum
{
    TBSTS_BIT_CNTDIR_COUNTING_DOWN     = 0,  /*!< Time-base counter is currently counting down   */
    TBSTS_BIT_CNTDIR_COUNTING_UP       = 1,  /*!< Time-base counter is currently counting up     */
} TBSTS_BIT_CNTDIR;

#define TBSTS_ALL_CNTDIR_COUNTING_DOWN     ((0x0UL) << TBSTS_ALL_CNTDIR_Pos)
#define TBSTS_ALL_CNTDIR_COUNTING_UP       ((0x1UL) << TBSTS_ALL_CNTDIR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTSCLR        SYNCI
 *  @access     PWM->TBSTSCLR.bit.SYNCI
 *  @brief      Input synchronization latched status clear
 */
#define TBSTSCLR_ALL_SYNCI_Pos (0)
#define TBSTSCLR_ALL_SYNCI_Msk (0x1UL << TBSTSCLR_ALL_SYNCI_Pos)

typedef enum
{
    TBSTSCLR_BIT_SYNCI_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect. Always readback 0.                          */
    TBSTSCLR_BIT_SYNCI_CLEAR         = 1,  /*!< Writing a 1 will clear the latched status. This bit is self-cleared.   */
} TBSTSCLR_BIT_SYNCI;

#define TBSTSCLR_ALL_SYNCI_NO_EFFECT     ((0x0UL) << TBSTSCLR_ALL_SYNCI_Pos)
#define TBSTSCLR_ALL_SYNCI_CLEAR         ((0x1UL) << TBSTSCLR_ALL_SYNCI_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTSCLR        CNTMAX
 *  @access     PWM->TBSTSCLR.bit.CNTMAX
 *  @brief      Time-base counter reaching max latched status clear
 */
#define TBSTSCLR_ALL_CNTMAX_Pos (1)
#define TBSTSCLR_ALL_CNTMAX_Msk (0x1UL << TBSTSCLR_ALL_CNTMAX_Pos)

typedef enum
{
    TBSTSCLR_BIT_CNTMAX_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect. Always readback 0.                          */
    TBSTSCLR_BIT_CNTMAX_CLEAR         = 1,  /*!< Writing a 1 will clear the latched status. This bit is self-cleared.   */
} TBSTSCLR_BIT_CNTMAX;

#define TBSTSCLR_ALL_CNTMAX_NO_EFFECT     ((0x0UL) << TBSTSCLR_ALL_CNTMAX_Pos)
#define TBSTSCLR_ALL_CNTMAX_CLEAR         ((0x1UL) << TBSTSCLR_ALL_CNTMAX_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTSCLR        CNTZRO
 *  @access     PWM->TBSTSCLR.bit.CNTZRO
 *  @brief      Time-base counter reaching zero latched status clear
 */
#define TBSTSCLR_ALL_CNTZRO_Pos (2)
#define TBSTSCLR_ALL_CNTZRO_Msk (0x1UL << TBSTSCLR_ALL_CNTZRO_Pos)

typedef enum
{
    TBSTSCLR_BIT_CNTZRO_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect. Always readback 0.                          */
    TBSTSCLR_BIT_CNTZRO_CLEAR         = 1,  /*!< Writing a 1 will clear the latched status. This bit is self-cleared.   */
} TBSTSCLR_BIT_CNTZRO;

#define TBSTSCLR_ALL_CNTZRO_NO_EFFECT     ((0x0UL) << TBSTSCLR_ALL_CNTZRO_Pos)
#define TBSTSCLR_ALL_CNTZRO_CLEAR         ((0x1UL) << TBSTSCLR_ALL_CNTZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTSCLR        CNTPRD
 *  @access     PWM->TBSTSCLR.bit.CNTPRD
 *  @brief      Time-base counter reaching period latched status clear
 */
#define TBSTSCLR_ALL_CNTPRD_Pos (3)
#define TBSTSCLR_ALL_CNTPRD_Msk (0x1UL << TBSTSCLR_ALL_CNTPRD_Pos)

typedef enum
{
    TBSTSCLR_BIT_CNTPRD_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect. Always readback 0.                          */
    TBSTSCLR_BIT_CNTPRD_CLEAR         = 1,  /*!< Writing a 1 will clear the latched status. This bit is self-cleared.   */
} TBSTSCLR_BIT_CNTPRD;

#define TBSTSCLR_ALL_CNTPRD_NO_EFFECT     ((0x0UL) << TBSTSCLR_ALL_CNTPRD_Pos)
#define TBSTSCLR_ALL_CNTPRD_CLEAR         ((0x1UL) << TBSTSCLR_ALL_CNTPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTSCLR        CNTCMPA
 *  @access     PWM->TBSTSCLR.bit.CNTCMPA
 *  @brief      Time-base counter reaching CMPA latched status clear
 */
#define TBSTSCLR_ALL_CNTCMPA_Pos (4)
#define TBSTSCLR_ALL_CNTCMPA_Msk (0x1UL << TBSTSCLR_ALL_CNTCMPA_Pos)

typedef enum
{
    TBSTSCLR_BIT_CNTCMPA_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect. Always readback 0.                          */
    TBSTSCLR_BIT_CNTCMPA_CLEAR         = 1,  /*!< Writing a 1 will clear the latched status. This bit is self-cleared.   */
} TBSTSCLR_BIT_CNTCMPA;

#define TBSTSCLR_ALL_CNTCMPA_NO_EFFECT     ((0x0UL) << TBSTSCLR_ALL_CNTCMPA_Pos)
#define TBSTSCLR_ALL_CNTCMPA_CLEAR         ((0x1UL) << TBSTSCLR_ALL_CNTCMPA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTSCLR        CNTCMPB
 *  @access     PWM->TBSTSCLR.bit.CNTCMPB
 *  @brief      Time-base counter reaching CMPB latched status clear
 */
#define TBSTSCLR_ALL_CNTCMPB_Pos (5)
#define TBSTSCLR_ALL_CNTCMPB_Msk (0x1UL << TBSTSCLR_ALL_CNTCMPB_Pos)

typedef enum
{
    TBSTSCLR_BIT_CNTCMPB_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect. Always readback 0.                          */
    TBSTSCLR_BIT_CNTCMPB_CLEAR         = 1,  /*!< Writing a 1 will clear the latched status. This bit is self-cleared.   */
} TBSTSCLR_BIT_CNTCMPB;

#define TBSTSCLR_ALL_CNTCMPB_NO_EFFECT     ((0x0UL) << TBSTSCLR_ALL_CNTCMPB_Pos)
#define TBSTSCLR_ALL_CNTCMPB_CLEAR         ((0x1UL) << TBSTSCLR_ALL_CNTCMPB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTSCLR        CNTCMPC
 *  @access     PWM->TBSTSCLR.bit.CNTCMPC
 *  @brief      Time-base counter reaching CMPC latched status clear
 */
#define TBSTSCLR_ALL_CNTCMPC_Pos (6)
#define TBSTSCLR_ALL_CNTCMPC_Msk (0x1UL << TBSTSCLR_ALL_CNTCMPC_Pos)

typedef enum
{
    TBSTSCLR_BIT_CNTCMPC_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect. Always readback 0.                          */
    TBSTSCLR_BIT_CNTCMPC_CLEAR         = 1,  /*!< Writing a 1 will clear the latched status. This bit is self-cleared.   */
} TBSTSCLR_BIT_CNTCMPC;

#define TBSTSCLR_ALL_CNTCMPC_NO_EFFECT     ((0x0UL) << TBSTSCLR_ALL_CNTCMPC_Pos)
#define TBSTSCLR_ALL_CNTCMPC_CLEAR         ((0x1UL) << TBSTSCLR_ALL_CNTCMPC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TBSTSCLR        CNTCMPD
 *  @access     PWM->TBSTSCLR.bit.CNTCMPD
 *  @brief      Time-base counter reaching CMPD latched status clear
 */
#define TBSTSCLR_ALL_CNTCMPD_Pos (7)
#define TBSTSCLR_ALL_CNTCMPD_Msk (0x1UL << TBSTSCLR_ALL_CNTCMPD_Pos)

typedef enum
{
    TBSTSCLR_BIT_CNTCMPD_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect. Always readback 0.                          */
    TBSTSCLR_BIT_CNTCMPD_CLEAR         = 1,  /*!< Writing a 1 will clear the latched status. This bit is self-cleared.   */
} TBSTSCLR_BIT_CNTCMPD;

#define TBSTSCLR_ALL_CNTCMPD_NO_EFFECT     ((0x0UL) << TBSTSCLR_ALL_CNTCMPD_Pos)
#define TBSTSCLR_ALL_CNTCMPD_CLEAR         ((0x1UL) << TBSTSCLR_ALL_CNTCMPD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCTL          CMPALOAD
 *  @access     PWM->CMPCTL.bit.CMPALOAD
 *  @brief      CMPA active value load mode
 *              It has no effect when CMPATL[CMPALOCK]=1
 */
#define CMPCTL_ALL_CMPALOAD_Pos (0)
#define CMPCTL_ALL_CMPALOAD_Msk (0x7UL << CMPCTL_ALL_CMPALOAD_Pos)

typedef enum
{
    CMPCTL_BIT_CMPALOAD_LOAD_ON_ZERO                 = 0,  /*!< Load CMPA into CMPAA on TBCNT=0                                */
    CMPCTL_BIT_CMPALOAD_LOAD_ON_PERIOD               = 1,  /*!< Load CMPA into CMPAA on TBCNT=TBPRD                            */
    CMPCTL_BIT_CMPALOAD_LOAD_ON_ZERO_PERIOD          = 2,  /*!< Load CMPA into CMPAA on TBCNT=0 or TBCNT=TBPRD                 */
    CMPCTL_BIT_CMPALOAD_LOAD_ON_SYNC                 = 3,  /*!< Load CMPA into CMPAA on SYNC event                             */
    CMPCTL_BIT_CMPALOAD_LOAD_ON_SYNC_ZERO            = 4,  /*!< Load CMPA into CMPAA on SYNC event or TBCNT=0                  */
    CMPCTL_BIT_CMPALOAD_LOAD_ON_SYNC_PERIOD          = 5,  /*!< Load CMPA into CMPAA on SYNC event or TBCNT=TBPRD              */
    CMPCTL_BIT_CMPALOAD_LOAD_ON_SYNC_ZERO_PERIOD     = 6,  /*!< Load CMPA into CMPAA on SYNC event, TBCNT=0 or TBCNT=TBPRD     */
    CMPCTL_BIT_CMPALOAD_LOAD_IMMEDIATE               = 7,  /*!< Write CMPA will immediately change the active value in CMPAA   */
} CMPCTL_BIT_CMPALOAD;

#define CMPCTL_ALL_CMPALOAD_LOAD_ON_ZERO                 ((0x0UL) << CMPCTL_ALL_CMPALOAD_Pos)
#define CMPCTL_ALL_CMPALOAD_LOAD_ON_PERIOD               ((0x1UL) << CMPCTL_ALL_CMPALOAD_Pos)
#define CMPCTL_ALL_CMPALOAD_LOAD_ON_ZERO_PERIOD          ((0x2UL) << CMPCTL_ALL_CMPALOAD_Pos)
#define CMPCTL_ALL_CMPALOAD_LOAD_ON_SYNC                 ((0x3UL) << CMPCTL_ALL_CMPALOAD_Pos)
#define CMPCTL_ALL_CMPALOAD_LOAD_ON_SYNC_ZERO            ((0x4UL) << CMPCTL_ALL_CMPALOAD_Pos)
#define CMPCTL_ALL_CMPALOAD_LOAD_ON_SYNC_PERIOD          ((0x5UL) << CMPCTL_ALL_CMPALOAD_Pos)
#define CMPCTL_ALL_CMPALOAD_LOAD_ON_SYNC_ZERO_PERIOD     ((0x6UL) << CMPCTL_ALL_CMPALOAD_Pos)
#define CMPCTL_ALL_CMPALOAD_LOAD_IMMEDIATE               ((0x7UL) << CMPCTL_ALL_CMPALOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCTL          CMPALOCK
 *  @access     PWM->CMPCTL.bit.CMPALOCK
 *  @brief      CMPA active value lock
 */
#define CMPCTL_ALL_CMPALOCK_Pos (3)
#define CMPCTL_ALL_CMPALOCK_Msk (0x1UL << CMPCTL_ALL_CMPALOCK_Pos)

typedef enum
{
    CMPCTL_BIT_CMPALOCK_UNLOCK     = 0,  /*!< Active value in CMPAA is updated according to CMPATL[CMPALOAD]   */
    CMPCTL_BIT_CMPALOCK_LOCK       = 1,  /*!< Active value in CMPAA will not change                            */
} CMPCTL_BIT_CMPALOCK;

#define CMPCTL_ALL_CMPALOCK_UNLOCK     ((0x0UL) << CMPCTL_ALL_CMPALOCK_Pos)
#define CMPCTL_ALL_CMPALOCK_LOCK       ((0x1UL) << CMPCTL_ALL_CMPALOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCTL          CMPBLOAD
 *  @access     PWM->CMPCTL.bit.CMPBLOAD
 *  @brief      CMPB active value load mode
 *              It has no effect when CMPBTL[CMPBLOCK]=1
 */
#define CMPCTL_ALL_CMPBLOAD_Pos (4)
#define CMPCTL_ALL_CMPBLOAD_Msk (0x7UL << CMPCTL_ALL_CMPBLOAD_Pos)

typedef enum
{
    CMPCTL_BIT_CMPBLOAD_LOAD_ON_ZERO                 = 0,  /*!< Load CMPB into CMPBA on TBCNT=0                                */
    CMPCTL_BIT_CMPBLOAD_LOAD_ON_PERIOD               = 1,  /*!< Load CMPB into CMPBA on TBCNT=TBPRD                            */
    CMPCTL_BIT_CMPBLOAD_LOAD_ON_ZERO_PERIOD          = 2,  /*!< Load CMPB into CMPBA on TBCNT=0 or TBCNT=TBPRD                 */
    CMPCTL_BIT_CMPBLOAD_LOAD_ON_SYNC                 = 3,  /*!< Load CMPB into CMPBA on SYNC event                             */
    CMPCTL_BIT_CMPBLOAD_LOAD_ON_SYNC_ZERO            = 4,  /*!< Load CMPB into CMPBA on SYNC event or TBCNT=0                  */
    CMPCTL_BIT_CMPBLOAD_LOAD_ON_SYNC_PERIOD          = 5,  /*!< Load CMPB into CMPBA on SYNC event or TBCNT=TBPRD              */
    CMPCTL_BIT_CMPBLOAD_LOAD_ON_SYNC_ZERO_PERIOD     = 6,  /*!< Load CMPB into CMPBA on SYNC event, TBCNT=0 or TBCNT=TBPRD     */
    CMPCTL_BIT_CMPBLOAD_LOAD_IMMEDIATE               = 7,  /*!< Write CMPB will immediately change the active value in CMPBA   */
} CMPCTL_BIT_CMPBLOAD;

#define CMPCTL_ALL_CMPBLOAD_LOAD_ON_ZERO                 ((0x0UL) << CMPCTL_ALL_CMPBLOAD_Pos)
#define CMPCTL_ALL_CMPBLOAD_LOAD_ON_PERIOD               ((0x1UL) << CMPCTL_ALL_CMPBLOAD_Pos)
#define CMPCTL_ALL_CMPBLOAD_LOAD_ON_ZERO_PERIOD          ((0x2UL) << CMPCTL_ALL_CMPBLOAD_Pos)
#define CMPCTL_ALL_CMPBLOAD_LOAD_ON_SYNC                 ((0x3UL) << CMPCTL_ALL_CMPBLOAD_Pos)
#define CMPCTL_ALL_CMPBLOAD_LOAD_ON_SYNC_ZERO            ((0x4UL) << CMPCTL_ALL_CMPBLOAD_Pos)
#define CMPCTL_ALL_CMPBLOAD_LOAD_ON_SYNC_PERIOD          ((0x5UL) << CMPCTL_ALL_CMPBLOAD_Pos)
#define CMPCTL_ALL_CMPBLOAD_LOAD_ON_SYNC_ZERO_PERIOD     ((0x6UL) << CMPCTL_ALL_CMPBLOAD_Pos)
#define CMPCTL_ALL_CMPBLOAD_LOAD_IMMEDIATE               ((0x7UL) << CMPCTL_ALL_CMPBLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCTL          CMPBLOCK
 *  @access     PWM->CMPCTL.bit.CMPBLOCK
 *  @brief      CMPB active value lock
 */
#define CMPCTL_ALL_CMPBLOCK_Pos (7)
#define CMPCTL_ALL_CMPBLOCK_Msk (0x1UL << CMPCTL_ALL_CMPBLOCK_Pos)

typedef enum
{
    CMPCTL_BIT_CMPBLOCK_UNLOCK     = 0,  /*!< Active value in CMPBA is updated according to CMPBTL[CMPBLOAD]   */
    CMPCTL_BIT_CMPBLOCK_LOCK       = 1,  /*!< Active value in CMPBA will not change                            */
} CMPCTL_BIT_CMPBLOCK;

#define CMPCTL_ALL_CMPBLOCK_UNLOCK     ((0x0UL) << CMPCTL_ALL_CMPBLOCK_Pos)
#define CMPCTL_ALL_CMPBLOCK_LOCK       ((0x1UL) << CMPCTL_ALL_CMPBLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCTL          CMPCLOAD
 *  @access     PWM->CMPCTL.bit.CMPCLOAD
 *  @brief      CMPC active value load mode
 *              It has no effect when CMPCTL[CMPCLOCK]=1
 */
#define CMPCTL_ALL_CMPCLOAD_Pos (8)
#define CMPCTL_ALL_CMPCLOAD_Msk (0x7UL << CMPCTL_ALL_CMPCLOAD_Pos)

typedef enum
{
    CMPCTL_BIT_CMPCLOAD_LOAD_ON_ZERO                 = 0,  /*!< Load CMPC into CMPCA on TBCNT=0                                */
    CMPCTL_BIT_CMPCLOAD_LOAD_ON_PERIOD               = 1,  /*!< Load CMPC into CMPCA on TBCNT=TBPRD                            */
    CMPCTL_BIT_CMPCLOAD_LOAD_ON_ZERO_PERIOD          = 2,  /*!< Load CMPC into CMPCA on TBCNT=0 or TBCNT=TBPRD                 */
    CMPCTL_BIT_CMPCLOAD_LOAD_ON_SYNC                 = 3,  /*!< Load CMPC into CMPCA on SYNC event                             */
    CMPCTL_BIT_CMPCLOAD_LOAD_ON_SYNC_ZERO            = 4,  /*!< Load CMPC into CMPCA on SYNC event or TBCNT=0                  */
    CMPCTL_BIT_CMPCLOAD_LOAD_ON_SYNC_PERIOD          = 5,  /*!< Load CMPC into CMPCA on SYNC event or TBCNT=TBPRD              */
    CMPCTL_BIT_CMPCLOAD_LOAD_ON_SYNC_ZERO_PERIOD     = 6,  /*!< Load CMPC into CMPCA on SYNC event, TBCNT=0 or TBCNT=TBPRD     */
    CMPCTL_BIT_CMPCLOAD_LOAD_IMMEDIATE               = 7,  /*!< Write CMPC will immediately change the active value in CMPCA   */
} CMPCTL_BIT_CMPCLOAD;

#define CMPCTL_ALL_CMPCLOAD_LOAD_ON_ZERO                 ((0x0UL) << CMPCTL_ALL_CMPCLOAD_Pos)
#define CMPCTL_ALL_CMPCLOAD_LOAD_ON_PERIOD               ((0x1UL) << CMPCTL_ALL_CMPCLOAD_Pos)
#define CMPCTL_ALL_CMPCLOAD_LOAD_ON_ZERO_PERIOD          ((0x2UL) << CMPCTL_ALL_CMPCLOAD_Pos)
#define CMPCTL_ALL_CMPCLOAD_LOAD_ON_SYNC                 ((0x3UL) << CMPCTL_ALL_CMPCLOAD_Pos)
#define CMPCTL_ALL_CMPCLOAD_LOAD_ON_SYNC_ZERO            ((0x4UL) << CMPCTL_ALL_CMPCLOAD_Pos)
#define CMPCTL_ALL_CMPCLOAD_LOAD_ON_SYNC_PERIOD          ((0x5UL) << CMPCTL_ALL_CMPCLOAD_Pos)
#define CMPCTL_ALL_CMPCLOAD_LOAD_ON_SYNC_ZERO_PERIOD     ((0x6UL) << CMPCTL_ALL_CMPCLOAD_Pos)
#define CMPCTL_ALL_CMPCLOAD_LOAD_IMMEDIATE               ((0x7UL) << CMPCTL_ALL_CMPCLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCTL          CMPCLOCK
 *  @access     PWM->CMPCTL.bit.CMPCLOCK
 *  @brief      CMPC active value lock
 */
#define CMPCTL_ALL_CMPCLOCK_Pos (11)
#define CMPCTL_ALL_CMPCLOCK_Msk (0x1UL << CMPCTL_ALL_CMPCLOCK_Pos)

typedef enum
{
    CMPCTL_BIT_CMPCLOCK_UNLOCK     = 0,  /*!< Active value in CMPCA is updated according to CMPCTL[CMPCLOAD]   */
    CMPCTL_BIT_CMPCLOCK_LOCK       = 1,  /*!< Active value in CMPCA will not change                            */
} CMPCTL_BIT_CMPCLOCK;

#define CMPCTL_ALL_CMPCLOCK_UNLOCK     ((0x0UL) << CMPCTL_ALL_CMPCLOCK_Pos)
#define CMPCTL_ALL_CMPCLOCK_LOCK       ((0x1UL) << CMPCTL_ALL_CMPCLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCTL          CMPDLOAD
 *  @access     PWM->CMPCTL.bit.CMPDLOAD
 *  @brief      CMPD active value load mode
 *              It has no effect when CMPCTL[CMPDLOCK]=1
 */
#define CMPCTL_ALL_CMPDLOAD_Pos (12)
#define CMPCTL_ALL_CMPDLOAD_Msk (0x7UL << CMPCTL_ALL_CMPDLOAD_Pos)

typedef enum
{
    CMPCTL_BIT_CMPDLOAD_LOAD_ON_ZERO                 = 0,  /*!< Load CMPD into CMPDA on TBCNT=0                                */
    CMPCTL_BIT_CMPDLOAD_LOAD_ON_PERIOD               = 1,  /*!< Load CMPD into CMPDA on TBCNT=TBPRD                            */
    CMPCTL_BIT_CMPDLOAD_LOAD_ON_ZERO_PERIOD          = 2,  /*!< Load CMPD into CMPDA on TBCNT=0 or TBCNT=TBPRD                 */
    CMPCTL_BIT_CMPDLOAD_LOAD_ON_SYNC                 = 3,  /*!< Load CMPD into CMPDA on SYNC event                             */
    CMPCTL_BIT_CMPDLOAD_LOAD_ON_SYNC_ZERO            = 4,  /*!< Load CMPD into CMPDA on SYNC event or TBCNT=0                  */
    CMPCTL_BIT_CMPDLOAD_LOAD_ON_SYNC_PERIOD          = 5,  /*!< Load CMPD into CMPDA on SYNC event or TBCNT=TBPRD              */
    CMPCTL_BIT_CMPDLOAD_LOAD_ON_SYNC_ZERO_PERIOD     = 6,  /*!< Load CMPD into CMPDA on SYNC event, TBCNT=0 or TBCNT=TBPRD     */
    CMPCTL_BIT_CMPDLOAD_LOAD_IMMEDIATE               = 7,  /*!< Write CMPD will immediately change the active value in CMPDA   */
} CMPCTL_BIT_CMPDLOAD;

#define CMPCTL_ALL_CMPDLOAD_LOAD_ON_ZERO                 ((0x0UL) << CMPCTL_ALL_CMPDLOAD_Pos)
#define CMPCTL_ALL_CMPDLOAD_LOAD_ON_PERIOD               ((0x1UL) << CMPCTL_ALL_CMPDLOAD_Pos)
#define CMPCTL_ALL_CMPDLOAD_LOAD_ON_ZERO_PERIOD          ((0x2UL) << CMPCTL_ALL_CMPDLOAD_Pos)
#define CMPCTL_ALL_CMPDLOAD_LOAD_ON_SYNC                 ((0x3UL) << CMPCTL_ALL_CMPDLOAD_Pos)
#define CMPCTL_ALL_CMPDLOAD_LOAD_ON_SYNC_ZERO            ((0x4UL) << CMPCTL_ALL_CMPDLOAD_Pos)
#define CMPCTL_ALL_CMPDLOAD_LOAD_ON_SYNC_PERIOD          ((0x5UL) << CMPCTL_ALL_CMPDLOAD_Pos)
#define CMPCTL_ALL_CMPDLOAD_LOAD_ON_SYNC_ZERO_PERIOD     ((0x6UL) << CMPCTL_ALL_CMPDLOAD_Pos)
#define CMPCTL_ALL_CMPDLOAD_LOAD_IMMEDIATE               ((0x7UL) << CMPCTL_ALL_CMPDLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCTL          CMPDLOCK
 *  @access     PWM->CMPCTL.bit.CMPDLOCK
 *  @brief      CMPD active value lock
 */
#define CMPCTL_ALL_CMPDLOCK_Pos (15)
#define CMPCTL_ALL_CMPDLOCK_Msk (0x1UL << CMPCTL_ALL_CMPDLOCK_Pos)

typedef enum
{
    CMPCTL_BIT_CMPDLOCK_UNLOCK     = 0,  /*!< Active value in CMPDA is updated according to CMPCTL[CMPDLOAD]   */
    CMPCTL_BIT_CMPDLOCK_LOCK       = 1,  /*!< Active value in CMPDA will not change                            */
} CMPCTL_BIT_CMPDLOCK;

#define CMPCTL_ALL_CMPDLOCK_UNLOCK     ((0x0UL) << CMPCTL_ALL_CMPDLOCK_Pos)
#define CMPCTL_ALL_CMPDLOCK_LOCK       ((0x1UL) << CMPCTL_ALL_CMPDLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPA            VAL
 *  @access     PWM->CMPA.bit.VAL
 *  @brief      Comparator A threshold
 */
#define CMPA_ALL_VAL_Pos (0)
#define CMPA_ALL_VAL_Msk (0xFFFFUL << CMPA_ALL_VAL_Pos)

#define CMPA_BIT_VAL

#define CMPA_ALL_VAL_(x) ((x) << CMPA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPAA           VAL
 *  @access     PWM->CMPAA.bit.VAL
 *  @brief      Comparator A threshold active value
 *              A TBCNT=CMPA event will be generated while TBCNT is equal to the threshold value
 */
#define CMPAA_ALL_VAL_Pos (0)
#define CMPAA_ALL_VAL_Msk (0xFFFFUL << CMPAA_ALL_VAL_Pos)

#define CMPAA_BIT_VAL

#define CMPAA_ALL_VAL_(x) ((x) << CMPAA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPB            VAL
 *  @access     PWM->CMPB.bit.VAL
 *  @brief      Comparator B threshold
 */
#define CMPB_ALL_VAL_Pos (0)
#define CMPB_ALL_VAL_Msk (0xFFFFUL << CMPB_ALL_VAL_Pos)

#define CMPB_BIT_VAL

#define CMPB_ALL_VAL_(x) ((x) << CMPB_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPBA           VAL
 *  @access     PWM->CMPBA.bit.VAL
 *  @brief      Comparator B threshold active value
 *              A TBCNT=CMPB event will be generated while TBCNT is equal to the threshold value
 */
#define CMPBA_ALL_VAL_Pos (0)
#define CMPBA_ALL_VAL_Msk (0xFFFFUL << CMPBA_ALL_VAL_Pos)

#define CMPBA_BIT_VAL

#define CMPBA_ALL_VAL_(x) ((x) << CMPBA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPC            VAL
 *  @access     PWM->CMPC.bit.VAL
 *  @brief      Comparator C threshold
 */
#define CMPC_ALL_VAL_Pos (0)
#define CMPC_ALL_VAL_Msk (0xFFFFUL << CMPC_ALL_VAL_Pos)

#define CMPC_BIT_VAL

#define CMPC_ALL_VAL_(x) ((x) << CMPC_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPCA           VAL
 *  @access     PWM->CMPCA.bit.VAL
 *  @brief      Comparator C threshold active value
 *              A TBCNT=CMPC event will be generated while TBCNT is equal to the threshold value
 */
#define CMPCA_ALL_VAL_Pos (0)
#define CMPCA_ALL_VAL_Msk (0xFFFFUL << CMPCA_ALL_VAL_Pos)

#define CMPCA_BIT_VAL

#define CMPCA_ALL_VAL_(x) ((x) << CMPCA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPD            VAL
 *  @access     PWM->CMPD.bit.VAL
 *  @brief      Comparator D threshold
 */
#define CMPD_ALL_VAL_Pos (0)
#define CMPD_ALL_VAL_Msk (0xFFFFUL << CMPD_ALL_VAL_Pos)

#define CMPD_BIT_VAL

#define CMPD_ALL_VAL_(x) ((x) << CMPD_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             CMPDA           VAL
 *  @access     PWM->CMPDA.bit.VAL
 *  @brief      Comparator D threshold active value
 *              A TBCNT=CMPD event will be generated while TBCNT is equal to the threshold value
 */
#define CMPDA_ALL_VAL_Pos (0)
#define CMPDA_ALL_VAL_Msk (0xFFFFUL << CMPDA_ALL_VAL_Pos)

#define CMPDA_BIT_VAL

#define CMPDA_ALL_VAL_(x) ((x) << CMPDA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTL           AQCTLALOAD
 *  @access     PWM->AQCTL.bit.AQCTLALOAD
 *  @brief      AQCTLA active value load mode
 *              It has no effect when AQCTL[AQCTLALOCK]=1
 */
#define AQCTL_ALL_AQCTLALOAD_Pos (0)
#define AQCTL_ALL_AQCTLALOAD_Msk (0x7UL << AQCTL_ALL_AQCTLALOAD_Pos)

typedef enum
{
    AQCTL_BIT_AQCTLALOAD_LOAD_ON_ZERO                 = 0,  /*!< Load AQCTLA into AQCTLAA on TBCNT=0                              */
    AQCTL_BIT_AQCTLALOAD_LOAD_ON_PERIOD               = 1,  /*!< Load AQCTLA into AQCTLAA on TBCNT=TBPRD                          */
    AQCTL_BIT_AQCTLALOAD_LOAD_ON_ZERO_PERIOD          = 2,  /*!< Load AQCTLA into AQCTLAA on TBCNT=0 or TBCNT=TBPRD               */
    AQCTL_BIT_AQCTLALOAD_LOAD_ON_SYNC                 = 3,  /*!< Load AQCTLA into AQCTLAA on SYNC event                           */
    AQCTL_BIT_AQCTLALOAD_LOAD_ON_SYNC_ZERO            = 4,  /*!< Load AQCTLA into AQCTLAA on SYNC event or TBCNT=0                */
    AQCTL_BIT_AQCTLALOAD_LOAD_ON_SYNC_PERIOD          = 5,  /*!< Load AQCTLA into AQCTLAA on SYNC event or TBCNT=TBPRD            */
    AQCTL_BIT_AQCTLALOAD_LOAD_ON_SYNC_ZERO_PERIOD     = 6,  /*!< Load AQCTLA into AQCTLAA on SYNC event, TBCNT=0 or TBCNT=TBPRD   */
    AQCTL_BIT_AQCTLALOAD_LOAD_IMMEDIATE               = 7,  /*!< Write AQCTLA immediately change the active value in AQCTLAA      */
} AQCTL_BIT_AQCTLALOAD;

#define AQCTL_ALL_AQCTLALOAD_LOAD_ON_ZERO                 ((0x0UL) << AQCTL_ALL_AQCTLALOAD_Pos)
#define AQCTL_ALL_AQCTLALOAD_LOAD_ON_PERIOD               ((0x1UL) << AQCTL_ALL_AQCTLALOAD_Pos)
#define AQCTL_ALL_AQCTLALOAD_LOAD_ON_ZERO_PERIOD          ((0x2UL) << AQCTL_ALL_AQCTLALOAD_Pos)
#define AQCTL_ALL_AQCTLALOAD_LOAD_ON_SYNC                 ((0x3UL) << AQCTL_ALL_AQCTLALOAD_Pos)
#define AQCTL_ALL_AQCTLALOAD_LOAD_ON_SYNC_ZERO            ((0x4UL) << AQCTL_ALL_AQCTLALOAD_Pos)
#define AQCTL_ALL_AQCTLALOAD_LOAD_ON_SYNC_PERIOD          ((0x5UL) << AQCTL_ALL_AQCTLALOAD_Pos)
#define AQCTL_ALL_AQCTLALOAD_LOAD_ON_SYNC_ZERO_PERIOD     ((0x6UL) << AQCTL_ALL_AQCTLALOAD_Pos)
#define AQCTL_ALL_AQCTLALOAD_LOAD_IMMEDIATE               ((0x7UL) << AQCTL_ALL_AQCTLALOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTL           AQCTLALOCK
 *  @access     PWM->AQCTL.bit.AQCTLALOCK
 *  @brief      AQCTLA active value lock
 */
#define AQCTL_ALL_AQCTLALOCK_Pos (3)
#define AQCTL_ALL_AQCTLALOCK_Msk (0x1UL << AQCTL_ALL_AQCTLALOCK_Pos)

typedef enum
{
    AQCTL_BIT_AQCTLALOCK_UNLOCK     = 0,  /*!< Active value in AQCTLAA is updated according to AQCTL[AQCTLALOAD]   */
    AQCTL_BIT_AQCTLALOCK_LOCK       = 1,  /*!< Active value in AQCTLAA will not change                             */
} AQCTL_BIT_AQCTLALOCK;

#define AQCTL_ALL_AQCTLALOCK_UNLOCK     ((0x0UL) << AQCTL_ALL_AQCTLALOCK_Pos)
#define AQCTL_ALL_AQCTLALOCK_LOCK       ((0x1UL) << AQCTL_ALL_AQCTLALOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTL           AQCTLBLOAD
 *  @access     PWM->AQCTL.bit.AQCTLBLOAD
 *  @brief      AQCTLB active value load mode
 *              It has no effect when AQCTL[AQCTLBLOCK]=1
 */
#define AQCTL_ALL_AQCTLBLOAD_Pos (4)
#define AQCTL_ALL_AQCTLBLOAD_Msk (0x7UL << AQCTL_ALL_AQCTLBLOAD_Pos)

typedef enum
{
    AQCTL_BIT_AQCTLBLOAD_LOAD_ON_ZERO                 = 0,  /*!< Load AQCTLB into AQCTLBA on TBCNT=0                              */
    AQCTL_BIT_AQCTLBLOAD_LOAD_ON_PERIOD               = 1,  /*!< Load AQCTLB into AQCTLBA on TBCNT=TBPRD                          */
    AQCTL_BIT_AQCTLBLOAD_LOAD_ON_ZERO_PERIOD          = 2,  /*!< Load AQCTLB into AQCTLBA on TBCNT=0 or TBCNT=TBPRD               */
    AQCTL_BIT_AQCTLBLOAD_LOAD_ON_SYNC                 = 3,  /*!< Load AQCTLB into AQCTLBA on SYNC event                           */
    AQCTL_BIT_AQCTLBLOAD_LOAD_ON_SYNC_ZERO            = 4,  /*!< Load AQCTLB into AQCTLBA on SYNC event or TBCNT=0                */
    AQCTL_BIT_AQCTLBLOAD_LOAD_ON_SYNC_PERIOD          = 5,  /*!< Load AQCTLB into AQCTLBA on SYNC event or TBCNT=TBPRD            */
    AQCTL_BIT_AQCTLBLOAD_LOAD_ON_SYNC_ZERO_PERIOD     = 6,  /*!< Load AQCTLB into AQCTLBA on SYNC event, TBCNT=0 or TBCNT=TBPRD   */
    AQCTL_BIT_AQCTLBLOAD_LOAD_IMMEDIATE               = 7,  /*!< Write AQCTLB immediately change the active value in AQCTLBA      */
} AQCTL_BIT_AQCTLBLOAD;

#define AQCTL_ALL_AQCTLBLOAD_LOAD_ON_ZERO                 ((0x0UL) << AQCTL_ALL_AQCTLBLOAD_Pos)
#define AQCTL_ALL_AQCTLBLOAD_LOAD_ON_PERIOD               ((0x1UL) << AQCTL_ALL_AQCTLBLOAD_Pos)
#define AQCTL_ALL_AQCTLBLOAD_LOAD_ON_ZERO_PERIOD          ((0x2UL) << AQCTL_ALL_AQCTLBLOAD_Pos)
#define AQCTL_ALL_AQCTLBLOAD_LOAD_ON_SYNC                 ((0x3UL) << AQCTL_ALL_AQCTLBLOAD_Pos)
#define AQCTL_ALL_AQCTLBLOAD_LOAD_ON_SYNC_ZERO            ((0x4UL) << AQCTL_ALL_AQCTLBLOAD_Pos)
#define AQCTL_ALL_AQCTLBLOAD_LOAD_ON_SYNC_PERIOD          ((0x5UL) << AQCTL_ALL_AQCTLBLOAD_Pos)
#define AQCTL_ALL_AQCTLBLOAD_LOAD_ON_SYNC_ZERO_PERIOD     ((0x6UL) << AQCTL_ALL_AQCTLBLOAD_Pos)
#define AQCTL_ALL_AQCTLBLOAD_LOAD_IMMEDIATE               ((0x7UL) << AQCTL_ALL_AQCTLBLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTL           AQCTLBLOCK
 *  @access     PWM->AQCTL.bit.AQCTLBLOCK
 *  @brief      AQCTLB active value lock
 */
#define AQCTL_ALL_AQCTLBLOCK_Pos (7)
#define AQCTL_ALL_AQCTLBLOCK_Msk (0x1UL << AQCTL_ALL_AQCTLBLOCK_Pos)

typedef enum
{
    AQCTL_BIT_AQCTLBLOCK_UNLOCK     = 0,  /*!< Active value in AQCTLBA is updated according to AQCTL[AQCTLBLOAD]   */
    AQCTL_BIT_AQCTLBLOCK_LOCK       = 1,  /*!< Active value in AQCTLBA will not change                             */
} AQCTL_BIT_AQCTLBLOCK;

#define AQCTL_ALL_AQCTLBLOCK_UNLOCK     ((0x0UL) << AQCTL_ALL_AQCTLBLOCK_Pos)
#define AQCTL_ALL_AQCTLBLOCK_LOCK       ((0x1UL) << AQCTL_ALL_AQCTLBLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTL           T0SEL
 *  @access     PWM->AQCTL.bit.T0SEL
 *  @brief      T0 event source select
 */
#define AQCTL_ALL_T0SEL_Pos (8)
#define AQCTL_ALL_T0SEL_Msk (0xFUL << AQCTL_ALL_T0SEL_Pos)

typedef enum
{
    AQCTL_BIT_T0SEL_DCAEVT0     = 0,  /*!< DCAEVT0   */
    AQCTL_BIT_T0SEL_DCAEVT1     = 1,  /*!< DCAEVT1   */
    AQCTL_BIT_T0SEL_DCBEVT0     = 2,  /*!< DCBEVT0   */
    AQCTL_BIT_T0SEL_DCBEVT1     = 3,  /*!< DCBEVT1   */
    AQCTL_BIT_T0SEL_TZ0         = 4,  /*!< TZ0       */
    AQCTL_BIT_T0SEL_TZ1         = 5,  /*!< TZ1       */
    AQCTL_BIT_T0SEL_TZ2         = 6,  /*!< TZ2       */
    AQCTL_BIT_T0SEL_TZ3         = 7,  /*!< TZ3       */
    AQCTL_BIT_T0SEL_TZ4         = 8,  /*!< TZ4       */
    AQCTL_BIT_T0SEL_SYNCI       = 9,  /*!< SYNCI     */
} AQCTL_BIT_T0SEL;

#define AQCTL_ALL_T0SEL_DCAEVT0     ((0x00UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_DCAEVT1     ((0x01UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_DCBEVT0     ((0x02UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_DCBEVT1     ((0x03UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_TZ0         ((0x04UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_TZ1         ((0x05UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_TZ2         ((0x06UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_TZ3         ((0x07UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_TZ4         ((0x08UL) << AQCTL_ALL_T0SEL_Pos)
#define AQCTL_ALL_T0SEL_SYNCI       ((0x09UL) << AQCTL_ALL_T0SEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTL           T1SEL
 *  @access     PWM->AQCTL.bit.T1SEL
 *  @brief      T1 event source select
 */
#define AQCTL_ALL_T1SEL_Pos (12)
#define AQCTL_ALL_T1SEL_Msk (0xFUL << AQCTL_ALL_T1SEL_Pos)

typedef enum
{
    AQCTL_BIT_T1SEL_DCAEVT0     = 0,  /*!< DCAEVT0   */
    AQCTL_BIT_T1SEL_DCAEVT1     = 1,  /*!< DCAEVT1   */
    AQCTL_BIT_T1SEL_DCBEVT0     = 2,  /*!< DCBEVT0   */
    AQCTL_BIT_T1SEL_DCBEVT1     = 3,  /*!< DCBEVT1   */
    AQCTL_BIT_T1SEL_TZ0         = 4,  /*!< TZ0       */
    AQCTL_BIT_T1SEL_TZ1         = 5,  /*!< TZ1       */
    AQCTL_BIT_T1SEL_TZ2         = 6,  /*!< TZ2       */
    AQCTL_BIT_T1SEL_TZ3         = 7,  /*!< TZ3       */
    AQCTL_BIT_T1SEL_TZ4         = 8,  /*!< TZ4       */
    AQCTL_BIT_T1SEL_SYNCI       = 9,  /*!< SYNCI     */
} AQCTL_BIT_T1SEL;

#define AQCTL_ALL_T1SEL_DCAEVT0     ((0x00UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_DCAEVT1     ((0x01UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_DCBEVT0     ((0x02UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_DCBEVT1     ((0x03UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_TZ0         ((0x04UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_TZ1         ((0x05UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_TZ2         ((0x06UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_TZ3         ((0x07UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_TZ4         ((0x08UL) << AQCTL_ALL_T1SEL_Pos)
#define AQCTL_ALL_T1SEL_SYNCI       ((0x09UL) << AQCTL_ALL_T1SEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          ZRO
 *  @access     PWM->AQCTLA.bit.ZRO
 *  @brief      Action on output A when TBCNT=Zero
 */
#define AQCTLA_ALL_ZRO_Pos (0)
#define AQCTLA_ALL_ZRO_Msk (0x3UL << AQCTLA_ALL_ZRO_Pos)

typedef enum
{
    AQCTLA_BIT_ZRO_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_ZRO_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_ZRO_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_ZRO_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_ZRO;

#define AQCTLA_ALL_ZRO_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_ZRO_Pos)
#define AQCTLA_ALL_ZRO_SET_LOW        ((0x1UL) << AQCTLA_ALL_ZRO_Pos)
#define AQCTLA_ALL_ZRO_SET_HIGH       ((0x2UL) << AQCTLA_ALL_ZRO_Pos)
#define AQCTLA_ALL_ZRO_TOGGLE         ((0x3UL) << AQCTLA_ALL_ZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          PRD
 *  @access     PWM->AQCTLA.bit.PRD
 *  @brief      Action on output A when TBCNT=TBPRD
 */
#define AQCTLA_ALL_PRD_Pos (2)
#define AQCTLA_ALL_PRD_Msk (0x3UL << AQCTLA_ALL_PRD_Pos)

typedef enum
{
    AQCTLA_BIT_PRD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_PRD_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_PRD_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_PRD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_PRD;

#define AQCTLA_ALL_PRD_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_PRD_Pos)
#define AQCTLA_ALL_PRD_SET_LOW        ((0x1UL) << AQCTLA_ALL_PRD_Pos)
#define AQCTLA_ALL_PRD_SET_HIGH       ((0x2UL) << AQCTLA_ALL_PRD_Pos)
#define AQCTLA_ALL_PRD_TOGGLE         ((0x3UL) << AQCTLA_ALL_PRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          CAU
 *  @access     PWM->AQCTLA.bit.CAU
 *  @brief      Action on output A when TBCNT=CMPA and TBCNT is counting up
 */
#define AQCTLA_ALL_CAU_Pos (4)
#define AQCTLA_ALL_CAU_Msk (0x3UL << AQCTLA_ALL_CAU_Pos)

typedef enum
{
    AQCTLA_BIT_CAU_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_CAU_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_CAU_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_CAU_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_CAU;

#define AQCTLA_ALL_CAU_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_CAU_Pos)
#define AQCTLA_ALL_CAU_SET_LOW        ((0x1UL) << AQCTLA_ALL_CAU_Pos)
#define AQCTLA_ALL_CAU_SET_HIGH       ((0x2UL) << AQCTLA_ALL_CAU_Pos)
#define AQCTLA_ALL_CAU_TOGGLE         ((0x3UL) << AQCTLA_ALL_CAU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          CAD
 *  @access     PWM->AQCTLA.bit.CAD
 *  @brief      Action on output A when TBCNT=CMPA and TBCNT is counting down
 */
#define AQCTLA_ALL_CAD_Pos (6)
#define AQCTLA_ALL_CAD_Msk (0x3UL << AQCTLA_ALL_CAD_Pos)

typedef enum
{
    AQCTLA_BIT_CAD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_CAD_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_CAD_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_CAD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_CAD;

#define AQCTLA_ALL_CAD_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_CAD_Pos)
#define AQCTLA_ALL_CAD_SET_LOW        ((0x1UL) << AQCTLA_ALL_CAD_Pos)
#define AQCTLA_ALL_CAD_SET_HIGH       ((0x2UL) << AQCTLA_ALL_CAD_Pos)
#define AQCTLA_ALL_CAD_TOGGLE         ((0x3UL) << AQCTLA_ALL_CAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          CBU
 *  @access     PWM->AQCTLA.bit.CBU
 *  @brief      Action on output A when TBCNT=CMPB and TBCNT is counting up
 */
#define AQCTLA_ALL_CBU_Pos (8)
#define AQCTLA_ALL_CBU_Msk (0x3UL << AQCTLA_ALL_CBU_Pos)

typedef enum
{
    AQCTLA_BIT_CBU_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_CBU_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_CBU_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_CBU_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_CBU;

#define AQCTLA_ALL_CBU_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_CBU_Pos)
#define AQCTLA_ALL_CBU_SET_LOW        ((0x1UL) << AQCTLA_ALL_CBU_Pos)
#define AQCTLA_ALL_CBU_SET_HIGH       ((0x2UL) << AQCTLA_ALL_CBU_Pos)
#define AQCTLA_ALL_CBU_TOGGLE         ((0x3UL) << AQCTLA_ALL_CBU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          CBD
 *  @access     PWM->AQCTLA.bit.CBD
 *  @brief      Action on output A when TBCNT=CMPB and TBCNT is counting down
 */
#define AQCTLA_ALL_CBD_Pos (10)
#define AQCTLA_ALL_CBD_Msk (0x3UL << AQCTLA_ALL_CBD_Pos)

typedef enum
{
    AQCTLA_BIT_CBD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_CBD_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_CBD_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_CBD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_CBD;

#define AQCTLA_ALL_CBD_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_CBD_Pos)
#define AQCTLA_ALL_CBD_SET_LOW        ((0x1UL) << AQCTLA_ALL_CBD_Pos)
#define AQCTLA_ALL_CBD_SET_HIGH       ((0x2UL) << AQCTLA_ALL_CBD_Pos)
#define AQCTLA_ALL_CBD_TOGGLE         ((0x3UL) << AQCTLA_ALL_CBD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          T0U
 *  @access     PWM->AQCTLA.bit.T0U
 *  @brief      Action on output A when T0 event and TBCNT is counting up
 */
#define AQCTLA_ALL_T0U_Pos (12)
#define AQCTLA_ALL_T0U_Msk (0x3UL << AQCTLA_ALL_T0U_Pos)

typedef enum
{
    AQCTLA_BIT_T0U_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_T0U_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_T0U_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_T0U_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_T0U;

#define AQCTLA_ALL_T0U_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_T0U_Pos)
#define AQCTLA_ALL_T0U_SET_LOW        ((0x1UL) << AQCTLA_ALL_T0U_Pos)
#define AQCTLA_ALL_T0U_SET_HIGH       ((0x2UL) << AQCTLA_ALL_T0U_Pos)
#define AQCTLA_ALL_T0U_TOGGLE         ((0x3UL) << AQCTLA_ALL_T0U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          T0D
 *  @access     PWM->AQCTLA.bit.T0D
 *  @brief      Action on output A when T0 event and TBCNT is counting down
 */
#define AQCTLA_ALL_T0D_Pos (14)
#define AQCTLA_ALL_T0D_Msk (0x3UL << AQCTLA_ALL_T0D_Pos)

typedef enum
{
    AQCTLA_BIT_T0D_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_T0D_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_T0D_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_T0D_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_T0D;

#define AQCTLA_ALL_T0D_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_T0D_Pos)
#define AQCTLA_ALL_T0D_SET_LOW        ((0x1UL) << AQCTLA_ALL_T0D_Pos)
#define AQCTLA_ALL_T0D_SET_HIGH       ((0x2UL) << AQCTLA_ALL_T0D_Pos)
#define AQCTLA_ALL_T0D_TOGGLE         ((0x3UL) << AQCTLA_ALL_T0D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          T1U
 *  @access     PWM->AQCTLA.bit.T1U
 *  @brief      Action on output A when T1 event and TBCNT is counting up
 */
#define AQCTLA_ALL_T1U_Pos (16)
#define AQCTLA_ALL_T1U_Msk (0x3UL << AQCTLA_ALL_T1U_Pos)

typedef enum
{
    AQCTLA_BIT_T1U_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_T1U_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_T1U_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_T1U_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_T1U;

#define AQCTLA_ALL_T1U_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_T1U_Pos)
#define AQCTLA_ALL_T1U_SET_LOW        ((0x1UL) << AQCTLA_ALL_T1U_Pos)
#define AQCTLA_ALL_T1U_SET_HIGH       ((0x2UL) << AQCTLA_ALL_T1U_Pos)
#define AQCTLA_ALL_T1U_TOGGLE         ((0x3UL) << AQCTLA_ALL_T1U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLA          T1D
 *  @access     PWM->AQCTLA.bit.T1D
 *  @brief      Action on output A when T1 event and TBCNT is counting down
 */
#define AQCTLA_ALL_T1D_Pos (18)
#define AQCTLA_ALL_T1D_Msk (0x3UL << AQCTLA_ALL_T1D_Pos)

typedef enum
{
    AQCTLA_BIT_T1D_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLA_BIT_T1D_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLA_BIT_T1D_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLA_BIT_T1D_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLA_BIT_T1D;

#define AQCTLA_ALL_T1D_DO_NOTHING     ((0x0UL) << AQCTLA_ALL_T1D_Pos)
#define AQCTLA_ALL_T1D_SET_LOW        ((0x1UL) << AQCTLA_ALL_T1D_Pos)
#define AQCTLA_ALL_T1D_SET_HIGH       ((0x2UL) << AQCTLA_ALL_T1D_Pos)
#define AQCTLA_ALL_T1D_TOGGLE         ((0x3UL) << AQCTLA_ALL_T1D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         ZRO
 *  @access     PWM->AQCTLAA.bit.ZRO
 *  @brief      Action on output A when TBCNT=Zero
 */
#define AQCTLAA_ALL_ZRO_Pos (0)
#define AQCTLAA_ALL_ZRO_Msk (0x3UL << AQCTLAA_ALL_ZRO_Pos)

typedef enum
{
    AQCTLAA_BIT_ZRO_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_ZRO_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_ZRO_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_ZRO_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_ZRO;

#define AQCTLAA_ALL_ZRO_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_ZRO_Pos)
#define AQCTLAA_ALL_ZRO_SET_LOW        ((0x1UL) << AQCTLAA_ALL_ZRO_Pos)
#define AQCTLAA_ALL_ZRO_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_ZRO_Pos)
#define AQCTLAA_ALL_ZRO_TOGGLE         ((0x3UL) << AQCTLAA_ALL_ZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         PRD
 *  @access     PWM->AQCTLAA.bit.PRD
 *  @brief      Action on output A when TBCNT=TBPRD
 */
#define AQCTLAA_ALL_PRD_Pos (2)
#define AQCTLAA_ALL_PRD_Msk (0x3UL << AQCTLAA_ALL_PRD_Pos)

typedef enum
{
    AQCTLAA_BIT_PRD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_PRD_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_PRD_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_PRD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_PRD;

#define AQCTLAA_ALL_PRD_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_PRD_Pos)
#define AQCTLAA_ALL_PRD_SET_LOW        ((0x1UL) << AQCTLAA_ALL_PRD_Pos)
#define AQCTLAA_ALL_PRD_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_PRD_Pos)
#define AQCTLAA_ALL_PRD_TOGGLE         ((0x3UL) << AQCTLAA_ALL_PRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         CAU
 *  @access     PWM->AQCTLAA.bit.CAU
 *  @brief      Action on output A when TBCNT=CMPA and TBCNT is counting up
 */
#define AQCTLAA_ALL_CAU_Pos (4)
#define AQCTLAA_ALL_CAU_Msk (0x3UL << AQCTLAA_ALL_CAU_Pos)

typedef enum
{
    AQCTLAA_BIT_CAU_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_CAU_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_CAU_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_CAU_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_CAU;

#define AQCTLAA_ALL_CAU_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_CAU_Pos)
#define AQCTLAA_ALL_CAU_SET_LOW        ((0x1UL) << AQCTLAA_ALL_CAU_Pos)
#define AQCTLAA_ALL_CAU_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_CAU_Pos)
#define AQCTLAA_ALL_CAU_TOGGLE         ((0x3UL) << AQCTLAA_ALL_CAU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         CAD
 *  @access     PWM->AQCTLAA.bit.CAD
 *  @brief      Action on output A when TBCNT=CMPA and TBCNT is counting down
 */
#define AQCTLAA_ALL_CAD_Pos (6)
#define AQCTLAA_ALL_CAD_Msk (0x3UL << AQCTLAA_ALL_CAD_Pos)

typedef enum
{
    AQCTLAA_BIT_CAD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_CAD_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_CAD_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_CAD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_CAD;

#define AQCTLAA_ALL_CAD_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_CAD_Pos)
#define AQCTLAA_ALL_CAD_SET_LOW        ((0x1UL) << AQCTLAA_ALL_CAD_Pos)
#define AQCTLAA_ALL_CAD_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_CAD_Pos)
#define AQCTLAA_ALL_CAD_TOGGLE         ((0x3UL) << AQCTLAA_ALL_CAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         CBU
 *  @access     PWM->AQCTLAA.bit.CBU
 *  @brief      Action on output A when TBCNT=CMPB and TBCNT is counting up
 */
#define AQCTLAA_ALL_CBU_Pos (8)
#define AQCTLAA_ALL_CBU_Msk (0x3UL << AQCTLAA_ALL_CBU_Pos)

typedef enum
{
    AQCTLAA_BIT_CBU_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_CBU_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_CBU_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_CBU_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_CBU;

#define AQCTLAA_ALL_CBU_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_CBU_Pos)
#define AQCTLAA_ALL_CBU_SET_LOW        ((0x1UL) << AQCTLAA_ALL_CBU_Pos)
#define AQCTLAA_ALL_CBU_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_CBU_Pos)
#define AQCTLAA_ALL_CBU_TOGGLE         ((0x3UL) << AQCTLAA_ALL_CBU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         CBD
 *  @access     PWM->AQCTLAA.bit.CBD
 *  @brief      Action on output A when TBCNT=CMPB and TBCNT is counting down
 */
#define AQCTLAA_ALL_CBD_Pos (10)
#define AQCTLAA_ALL_CBD_Msk (0x3UL << AQCTLAA_ALL_CBD_Pos)

typedef enum
{
    AQCTLAA_BIT_CBD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_CBD_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_CBD_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_CBD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_CBD;

#define AQCTLAA_ALL_CBD_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_CBD_Pos)
#define AQCTLAA_ALL_CBD_SET_LOW        ((0x1UL) << AQCTLAA_ALL_CBD_Pos)
#define AQCTLAA_ALL_CBD_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_CBD_Pos)
#define AQCTLAA_ALL_CBD_TOGGLE         ((0x3UL) << AQCTLAA_ALL_CBD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         T0U
 *  @access     PWM->AQCTLAA.bit.T0U
 *  @brief      Action on output A when T0 event and TBCNT is counting up
 */
#define AQCTLAA_ALL_T0U_Pos (12)
#define AQCTLAA_ALL_T0U_Msk (0x3UL << AQCTLAA_ALL_T0U_Pos)

typedef enum
{
    AQCTLAA_BIT_T0U_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_T0U_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_T0U_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_T0U_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_T0U;

#define AQCTLAA_ALL_T0U_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_T0U_Pos)
#define AQCTLAA_ALL_T0U_SET_LOW        ((0x1UL) << AQCTLAA_ALL_T0U_Pos)
#define AQCTLAA_ALL_T0U_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_T0U_Pos)
#define AQCTLAA_ALL_T0U_TOGGLE         ((0x3UL) << AQCTLAA_ALL_T0U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         T0D
 *  @access     PWM->AQCTLAA.bit.T0D
 *  @brief      Action on output A when T0 event and TBCNT is counting down
 */
#define AQCTLAA_ALL_T0D_Pos (14)
#define AQCTLAA_ALL_T0D_Msk (0x3UL << AQCTLAA_ALL_T0D_Pos)

typedef enum
{
    AQCTLAA_BIT_T0D_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_T0D_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_T0D_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_T0D_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_T0D;

#define AQCTLAA_ALL_T0D_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_T0D_Pos)
#define AQCTLAA_ALL_T0D_SET_LOW        ((0x1UL) << AQCTLAA_ALL_T0D_Pos)
#define AQCTLAA_ALL_T0D_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_T0D_Pos)
#define AQCTLAA_ALL_T0D_TOGGLE         ((0x3UL) << AQCTLAA_ALL_T0D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         T1U
 *  @access     PWM->AQCTLAA.bit.T1U
 *  @brief      Action on output A when T1 event and TBCNT is counting up
 */
#define AQCTLAA_ALL_T1U_Pos (16)
#define AQCTLAA_ALL_T1U_Msk (0x3UL << AQCTLAA_ALL_T1U_Pos)

typedef enum
{
    AQCTLAA_BIT_T1U_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_T1U_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_T1U_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_T1U_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_T1U;

#define AQCTLAA_ALL_T1U_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_T1U_Pos)
#define AQCTLAA_ALL_T1U_SET_LOW        ((0x1UL) << AQCTLAA_ALL_T1U_Pos)
#define AQCTLAA_ALL_T1U_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_T1U_Pos)
#define AQCTLAA_ALL_T1U_TOGGLE         ((0x3UL) << AQCTLAA_ALL_T1U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLAA         T1D
 *  @access     PWM->AQCTLAA.bit.T1D
 *  @brief      Action on output A when T1 event and TBCNT is counting down
 */
#define AQCTLAA_ALL_T1D_Pos (18)
#define AQCTLAA_ALL_T1D_Msk (0x3UL << AQCTLAA_ALL_T1D_Pos)

typedef enum
{
    AQCTLAA_BIT_T1D_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLAA_BIT_T1D_SET_LOW        = 1,  /*!< Clear (force PWM output A to low)             */
    AQCTLAA_BIT_T1D_SET_HIGH       = 2,  /*!< Set (force PWM output A to high)              */
    AQCTLAA_BIT_T1D_TOGGLE         = 3,  /*!< Toggle (invert current PWM output A status)   */
} AQCTLAA_BIT_T1D;

#define AQCTLAA_ALL_T1D_DO_NOTHING     ((0x0UL) << AQCTLAA_ALL_T1D_Pos)
#define AQCTLAA_ALL_T1D_SET_LOW        ((0x1UL) << AQCTLAA_ALL_T1D_Pos)
#define AQCTLAA_ALL_T1D_SET_HIGH       ((0x2UL) << AQCTLAA_ALL_T1D_Pos)
#define AQCTLAA_ALL_T1D_TOGGLE         ((0x3UL) << AQCTLAA_ALL_T1D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          ZRO
 *  @access     PWM->AQCTLB.bit.ZRO
 *  @brief      Action on output B when TBCNT=Zero
 */
#define AQCTLB_ALL_ZRO_Pos (0)
#define AQCTLB_ALL_ZRO_Msk (0x3UL << AQCTLB_ALL_ZRO_Pos)

typedef enum
{
    AQCTLB_BIT_ZRO_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_ZRO_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_ZRO_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_ZRO_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_ZRO;

#define AQCTLB_ALL_ZRO_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_ZRO_Pos)
#define AQCTLB_ALL_ZRO_SET_LOW        ((0x1UL) << AQCTLB_ALL_ZRO_Pos)
#define AQCTLB_ALL_ZRO_SET_HIGH       ((0x2UL) << AQCTLB_ALL_ZRO_Pos)
#define AQCTLB_ALL_ZRO_TOGGLE         ((0x3UL) << AQCTLB_ALL_ZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          PRD
 *  @access     PWM->AQCTLB.bit.PRD
 *  @brief      Action on output B when TBCNT=TBPRD
 */
#define AQCTLB_ALL_PRD_Pos (2)
#define AQCTLB_ALL_PRD_Msk (0x3UL << AQCTLB_ALL_PRD_Pos)

typedef enum
{
    AQCTLB_BIT_PRD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_PRD_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_PRD_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_PRD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_PRD;

#define AQCTLB_ALL_PRD_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_PRD_Pos)
#define AQCTLB_ALL_PRD_SET_LOW        ((0x1UL) << AQCTLB_ALL_PRD_Pos)
#define AQCTLB_ALL_PRD_SET_HIGH       ((0x2UL) << AQCTLB_ALL_PRD_Pos)
#define AQCTLB_ALL_PRD_TOGGLE         ((0x3UL) << AQCTLB_ALL_PRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          CAU
 *  @access     PWM->AQCTLB.bit.CAU
 *  @brief      Action on output B when TBCNT=CMPA and TBCNT is counting up
 */
#define AQCTLB_ALL_CAU_Pos (4)
#define AQCTLB_ALL_CAU_Msk (0x3UL << AQCTLB_ALL_CAU_Pos)

typedef enum
{
    AQCTLB_BIT_CAU_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_CAU_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_CAU_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_CAU_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_CAU;

#define AQCTLB_ALL_CAU_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_CAU_Pos)
#define AQCTLB_ALL_CAU_SET_LOW        ((0x1UL) << AQCTLB_ALL_CAU_Pos)
#define AQCTLB_ALL_CAU_SET_HIGH       ((0x2UL) << AQCTLB_ALL_CAU_Pos)
#define AQCTLB_ALL_CAU_TOGGLE         ((0x3UL) << AQCTLB_ALL_CAU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          CAD
 *  @access     PWM->AQCTLB.bit.CAD
 *  @brief      Action on output B when TBCNT=CMPA and TBCNT is counting down
 */
#define AQCTLB_ALL_CAD_Pos (6)
#define AQCTLB_ALL_CAD_Msk (0x3UL << AQCTLB_ALL_CAD_Pos)

typedef enum
{
    AQCTLB_BIT_CAD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_CAD_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_CAD_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_CAD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_CAD;

#define AQCTLB_ALL_CAD_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_CAD_Pos)
#define AQCTLB_ALL_CAD_SET_LOW        ((0x1UL) << AQCTLB_ALL_CAD_Pos)
#define AQCTLB_ALL_CAD_SET_HIGH       ((0x2UL) << AQCTLB_ALL_CAD_Pos)
#define AQCTLB_ALL_CAD_TOGGLE         ((0x3UL) << AQCTLB_ALL_CAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          CBU
 *  @access     PWM->AQCTLB.bit.CBU
 *  @brief      Action on output B when TBCNT=CMPB and TBCNT is counting up
 */
#define AQCTLB_ALL_CBU_Pos (8)
#define AQCTLB_ALL_CBU_Msk (0x3UL << AQCTLB_ALL_CBU_Pos)

typedef enum
{
    AQCTLB_BIT_CBU_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_CBU_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_CBU_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_CBU_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_CBU;

#define AQCTLB_ALL_CBU_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_CBU_Pos)
#define AQCTLB_ALL_CBU_SET_LOW        ((0x1UL) << AQCTLB_ALL_CBU_Pos)
#define AQCTLB_ALL_CBU_SET_HIGH       ((0x2UL) << AQCTLB_ALL_CBU_Pos)
#define AQCTLB_ALL_CBU_TOGGLE         ((0x3UL) << AQCTLB_ALL_CBU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          CBD
 *  @access     PWM->AQCTLB.bit.CBD
 *  @brief      Action on output B when TBCNT=CMPA and TBCNT is counting down
 */
#define AQCTLB_ALL_CBD_Pos (10)
#define AQCTLB_ALL_CBD_Msk (0x3UL << AQCTLB_ALL_CBD_Pos)

typedef enum
{
    AQCTLB_BIT_CBD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_CBD_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_CBD_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_CBD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_CBD;

#define AQCTLB_ALL_CBD_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_CBD_Pos)
#define AQCTLB_ALL_CBD_SET_LOW        ((0x1UL) << AQCTLB_ALL_CBD_Pos)
#define AQCTLB_ALL_CBD_SET_HIGH       ((0x2UL) << AQCTLB_ALL_CBD_Pos)
#define AQCTLB_ALL_CBD_TOGGLE         ((0x3UL) << AQCTLB_ALL_CBD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          T0U
 *  @access     PWM->AQCTLB.bit.T0U
 *  @brief      Action on output B when T0 event and TBCNT is counting up
 */
#define AQCTLB_ALL_T0U_Pos (12)
#define AQCTLB_ALL_T0U_Msk (0x3UL << AQCTLB_ALL_T0U_Pos)

typedef enum
{
    AQCTLB_BIT_T0U_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_T0U_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_T0U_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_T0U_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_T0U;

#define AQCTLB_ALL_T0U_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_T0U_Pos)
#define AQCTLB_ALL_T0U_SET_LOW        ((0x1UL) << AQCTLB_ALL_T0U_Pos)
#define AQCTLB_ALL_T0U_SET_HIGH       ((0x2UL) << AQCTLB_ALL_T0U_Pos)
#define AQCTLB_ALL_T0U_TOGGLE         ((0x3UL) << AQCTLB_ALL_T0U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          T0D
 *  @access     PWM->AQCTLB.bit.T0D
 *  @brief      Action on output B when T0 event and TBCNT is counting down
 */
#define AQCTLB_ALL_T0D_Pos (14)
#define AQCTLB_ALL_T0D_Msk (0x3UL << AQCTLB_ALL_T0D_Pos)

typedef enum
{
    AQCTLB_BIT_T0D_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_T0D_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_T0D_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_T0D_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_T0D;

#define AQCTLB_ALL_T0D_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_T0D_Pos)
#define AQCTLB_ALL_T0D_SET_LOW        ((0x1UL) << AQCTLB_ALL_T0D_Pos)
#define AQCTLB_ALL_T0D_SET_HIGH       ((0x2UL) << AQCTLB_ALL_T0D_Pos)
#define AQCTLB_ALL_T0D_TOGGLE         ((0x3UL) << AQCTLB_ALL_T0D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          T1U
 *  @access     PWM->AQCTLB.bit.T1U
 *  @brief      Action on output B when T1 event and TBCNT is counting up
 */
#define AQCTLB_ALL_T1U_Pos (16)
#define AQCTLB_ALL_T1U_Msk (0x3UL << AQCTLB_ALL_T1U_Pos)

typedef enum
{
    AQCTLB_BIT_T1U_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_T1U_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_T1U_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_T1U_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_T1U;

#define AQCTLB_ALL_T1U_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_T1U_Pos)
#define AQCTLB_ALL_T1U_SET_LOW        ((0x1UL) << AQCTLB_ALL_T1U_Pos)
#define AQCTLB_ALL_T1U_SET_HIGH       ((0x2UL) << AQCTLB_ALL_T1U_Pos)
#define AQCTLB_ALL_T1U_TOGGLE         ((0x3UL) << AQCTLB_ALL_T1U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLB          T1D
 *  @access     PWM->AQCTLB.bit.T1D
 *  @brief      Action on output B when T1 event and TBCNT is counting down
 */
#define AQCTLB_ALL_T1D_Pos (18)
#define AQCTLB_ALL_T1D_Msk (0x3UL << AQCTLB_ALL_T1D_Pos)

typedef enum
{
    AQCTLB_BIT_T1D_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLB_BIT_T1D_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLB_BIT_T1D_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLB_BIT_T1D_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLB_BIT_T1D;

#define AQCTLB_ALL_T1D_DO_NOTHING     ((0x0UL) << AQCTLB_ALL_T1D_Pos)
#define AQCTLB_ALL_T1D_SET_LOW        ((0x1UL) << AQCTLB_ALL_T1D_Pos)
#define AQCTLB_ALL_T1D_SET_HIGH       ((0x2UL) << AQCTLB_ALL_T1D_Pos)
#define AQCTLB_ALL_T1D_TOGGLE         ((0x3UL) << AQCTLB_ALL_T1D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         ZRO
 *  @access     PWM->AQCTLBA.bit.ZRO
 *  @brief      Action on output B when TBCNT=Zero
 */
#define AQCTLBA_ALL_ZRO_Pos (0)
#define AQCTLBA_ALL_ZRO_Msk (0x3UL << AQCTLBA_ALL_ZRO_Pos)

typedef enum
{
    AQCTLBA_BIT_ZRO_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_ZRO_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_ZRO_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_ZRO_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_ZRO;

#define AQCTLBA_ALL_ZRO_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_ZRO_Pos)
#define AQCTLBA_ALL_ZRO_SET_LOW        ((0x1UL) << AQCTLBA_ALL_ZRO_Pos)
#define AQCTLBA_ALL_ZRO_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_ZRO_Pos)
#define AQCTLBA_ALL_ZRO_TOGGLE         ((0x3UL) << AQCTLBA_ALL_ZRO_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         PRD
 *  @access     PWM->AQCTLBA.bit.PRD
 *  @brief      Action on output B when TBCNT=TBPRD
 */
#define AQCTLBA_ALL_PRD_Pos (2)
#define AQCTLBA_ALL_PRD_Msk (0x3UL << AQCTLBA_ALL_PRD_Pos)

typedef enum
{
    AQCTLBA_BIT_PRD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_PRD_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_PRD_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_PRD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_PRD;

#define AQCTLBA_ALL_PRD_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_PRD_Pos)
#define AQCTLBA_ALL_PRD_SET_LOW        ((0x1UL) << AQCTLBA_ALL_PRD_Pos)
#define AQCTLBA_ALL_PRD_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_PRD_Pos)
#define AQCTLBA_ALL_PRD_TOGGLE         ((0x3UL) << AQCTLBA_ALL_PRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         CAU
 *  @access     PWM->AQCTLBA.bit.CAU
 *  @brief      Action on output B when TBCNT=CMPA and TBCNT is counting up
 */
#define AQCTLBA_ALL_CAU_Pos (4)
#define AQCTLBA_ALL_CAU_Msk (0x3UL << AQCTLBA_ALL_CAU_Pos)

typedef enum
{
    AQCTLBA_BIT_CAU_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_CAU_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_CAU_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_CAU_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_CAU;

#define AQCTLBA_ALL_CAU_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_CAU_Pos)
#define AQCTLBA_ALL_CAU_SET_LOW        ((0x1UL) << AQCTLBA_ALL_CAU_Pos)
#define AQCTLBA_ALL_CAU_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_CAU_Pos)
#define AQCTLBA_ALL_CAU_TOGGLE         ((0x3UL) << AQCTLBA_ALL_CAU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         CAD
 *  @access     PWM->AQCTLBA.bit.CAD
 *  @brief      Action on output B when TBCNT=CMPA and TBCNT is counting down
 */
#define AQCTLBA_ALL_CAD_Pos (6)
#define AQCTLBA_ALL_CAD_Msk (0x3UL << AQCTLBA_ALL_CAD_Pos)

typedef enum
{
    AQCTLBA_BIT_CAD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_CAD_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_CAD_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_CAD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_CAD;

#define AQCTLBA_ALL_CAD_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_CAD_Pos)
#define AQCTLBA_ALL_CAD_SET_LOW        ((0x1UL) << AQCTLBA_ALL_CAD_Pos)
#define AQCTLBA_ALL_CAD_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_CAD_Pos)
#define AQCTLBA_ALL_CAD_TOGGLE         ((0x3UL) << AQCTLBA_ALL_CAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         CBU
 *  @access     PWM->AQCTLBA.bit.CBU
 *  @brief      Action on output B when TBCNT=CMPB and TBCNT is counting up
 */
#define AQCTLBA_ALL_CBU_Pos (8)
#define AQCTLBA_ALL_CBU_Msk (0x3UL << AQCTLBA_ALL_CBU_Pos)

typedef enum
{
    AQCTLBA_BIT_CBU_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_CBU_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_CBU_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_CBU_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_CBU;

#define AQCTLBA_ALL_CBU_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_CBU_Pos)
#define AQCTLBA_ALL_CBU_SET_LOW        ((0x1UL) << AQCTLBA_ALL_CBU_Pos)
#define AQCTLBA_ALL_CBU_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_CBU_Pos)
#define AQCTLBA_ALL_CBU_TOGGLE         ((0x3UL) << AQCTLBA_ALL_CBU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         CBD
 *  @access     PWM->AQCTLBA.bit.CBD
 *  @brief      Action on output B when TBCNT=CMPA and TBCNT is counting down
 */
#define AQCTLBA_ALL_CBD_Pos (10)
#define AQCTLBA_ALL_CBD_Msk (0x3UL << AQCTLBA_ALL_CBD_Pos)

typedef enum
{
    AQCTLBA_BIT_CBD_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_CBD_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_CBD_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_CBD_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_CBD;

#define AQCTLBA_ALL_CBD_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_CBD_Pos)
#define AQCTLBA_ALL_CBD_SET_LOW        ((0x1UL) << AQCTLBA_ALL_CBD_Pos)
#define AQCTLBA_ALL_CBD_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_CBD_Pos)
#define AQCTLBA_ALL_CBD_TOGGLE         ((0x3UL) << AQCTLBA_ALL_CBD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         T0U
 *  @access     PWM->AQCTLBA.bit.T0U
 *  @brief      Action on output B when T0 event and TBCNT is counting up
 */
#define AQCTLBA_ALL_T0U_Pos (12)
#define AQCTLBA_ALL_T0U_Msk (0x3UL << AQCTLBA_ALL_T0U_Pos)

typedef enum
{
    AQCTLBA_BIT_T0U_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_T0U_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_T0U_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_T0U_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_T0U;

#define AQCTLBA_ALL_T0U_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_T0U_Pos)
#define AQCTLBA_ALL_T0U_SET_LOW        ((0x1UL) << AQCTLBA_ALL_T0U_Pos)
#define AQCTLBA_ALL_T0U_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_T0U_Pos)
#define AQCTLBA_ALL_T0U_TOGGLE         ((0x3UL) << AQCTLBA_ALL_T0U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         T0D
 *  @access     PWM->AQCTLBA.bit.T0D
 *  @brief      Action on output B when T0 event and TBCNT is counting down
 */
#define AQCTLBA_ALL_T0D_Pos (14)
#define AQCTLBA_ALL_T0D_Msk (0x3UL << AQCTLBA_ALL_T0D_Pos)

typedef enum
{
    AQCTLBA_BIT_T0D_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_T0D_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_T0D_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_T0D_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_T0D;

#define AQCTLBA_ALL_T0D_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_T0D_Pos)
#define AQCTLBA_ALL_T0D_SET_LOW        ((0x1UL) << AQCTLBA_ALL_T0D_Pos)
#define AQCTLBA_ALL_T0D_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_T0D_Pos)
#define AQCTLBA_ALL_T0D_TOGGLE         ((0x3UL) << AQCTLBA_ALL_T0D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         T1U
 *  @access     PWM->AQCTLBA.bit.T1U
 *  @brief      Action on output B when T1 event and TBCNT is counting up
 */
#define AQCTLBA_ALL_T1U_Pos (16)
#define AQCTLBA_ALL_T1U_Msk (0x3UL << AQCTLBA_ALL_T1U_Pos)

typedef enum
{
    AQCTLBA_BIT_T1U_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_T1U_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_T1U_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_T1U_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_T1U;

#define AQCTLBA_ALL_T1U_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_T1U_Pos)
#define AQCTLBA_ALL_T1U_SET_LOW        ((0x1UL) << AQCTLBA_ALL_T1U_Pos)
#define AQCTLBA_ALL_T1U_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_T1U_Pos)
#define AQCTLBA_ALL_T1U_TOGGLE         ((0x3UL) << AQCTLBA_ALL_T1U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCTLBA         T1D
 *  @access     PWM->AQCTLBA.bit.T1D
 *  @brief      Action on output B when T1 event and TBCNT is counting down
 */
#define AQCTLBA_ALL_T1D_Pos (18)
#define AQCTLBA_ALL_T1D_Msk (0x3UL << AQCTLBA_ALL_T1D_Pos)

typedef enum
{
    AQCTLBA_BIT_T1D_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                  */
    AQCTLBA_BIT_T1D_SET_LOW        = 1,  /*!< Clear (force PWM output B to low)             */
    AQCTLBA_BIT_T1D_SET_HIGH       = 2,  /*!< Set (force PWM output B to high)              */
    AQCTLBA_BIT_T1D_TOGGLE         = 3,  /*!< Toggle (invert current PWM output B status)   */
} AQCTLBA_BIT_T1D;

#define AQCTLBA_ALL_T1D_DO_NOTHING     ((0x0UL) << AQCTLBA_ALL_T1D_Pos)
#define AQCTLBA_ALL_T1D_SET_LOW        ((0x1UL) << AQCTLBA_ALL_T1D_Pos)
#define AQCTLBA_ALL_T1D_SET_HIGH       ((0x2UL) << AQCTLBA_ALL_T1D_Pos)
#define AQCTLBA_ALL_T1D_TOGGLE         ((0x3UL) << AQCTLBA_ALL_T1D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQSFRC          ACTSFA
 *  @access     PWM->AQSFRC.bit.ACTSFA
 *  @brief      Action when one-time software force A is invoked
 */
#define AQSFRC_ALL_ACTSFA_Pos (0)
#define AQSFRC_ALL_ACTSFA_Msk (0x3UL << AQSFRC_ALL_ACTSFA_Pos)

typedef enum
{
    AQSFRC_BIT_ACTSFA_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                     */
    AQSFRC_BIT_ACTSFA_SET_LOW        = 1,  /*!< Clear (force PWM output A to low                 */
    AQSFRC_BIT_ACTSFA_SET_HIGH       = 2,  /*!< Set (force PWM output A to high                  */
    AQSFRC_BIT_ACTSFA_TOGGLE         = 3,  /*!< Toggle (invert current PWM AQ output A status)   */
} AQSFRC_BIT_ACTSFA;

#define AQSFRC_ALL_ACTSFA_DO_NOTHING     ((0x0UL) << AQSFRC_ALL_ACTSFA_Pos)
#define AQSFRC_ALL_ACTSFA_SET_LOW        ((0x1UL) << AQSFRC_ALL_ACTSFA_Pos)
#define AQSFRC_ALL_ACTSFA_SET_HIGH       ((0x2UL) << AQSFRC_ALL_ACTSFA_Pos)
#define AQSFRC_ALL_ACTSFA_TOGGLE         ((0x3UL) << AQSFRC_ALL_ACTSFA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQSFRC          OTSFA
 *  @access     PWM->AQSFRC.bit.OTSFA
 *  @brief      One-time software forced event on output A
 *              This bit is auto cleared once a write to it is complete
 */
#define AQSFRC_ALL_OTSFA_Pos (2)
#define AQSFRC_ALL_OTSFA_Msk (0x1UL << AQSFRC_ALL_OTSFA_Pos)

typedef enum
{
    AQSFRC_BIT_OTSFA_NO_EFFECT          = 0,  /*!< Write a 0 has no effect. Always reads back a 0                                */
    AQSFRC_BIT_OTSFA_FORCE_ONE_TIME     = 1,  /*!< Write a 1 initialize a one-cycle force pulse. This bit is self-cleared to 0   */
} AQSFRC_BIT_OTSFA;

#define AQSFRC_ALL_OTSFA_NO_EFFECT          ((0x0UL) << AQSFRC_ALL_OTSFA_Pos)
#define AQSFRC_ALL_OTSFA_FORCE_ONE_TIME     ((0x1UL) << AQSFRC_ALL_OTSFA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQSFRC          ACTSFB
 *  @access     PWM->AQSFRC.bit.ACTSFB
 *  @brief      Action when one-time software force B is invoked
 */
#define AQSFRC_ALL_ACTSFB_Pos (3)
#define AQSFRC_ALL_ACTSFB_Msk (0x3UL << AQSFRC_ALL_ACTSFB_Pos)

typedef enum
{
    AQSFRC_BIT_ACTSFB_DO_NOTHING     = 0,  /*!< Do nothing (action disabled)                     */
    AQSFRC_BIT_ACTSFB_SET_LOW        = 1,  /*!< Clear (force PWM output B to low                 */
    AQSFRC_BIT_ACTSFB_SET_HIGH       = 2,  /*!< Set (force PWM output B to high                  */
    AQSFRC_BIT_ACTSFB_TOGGLE         = 3,  /*!< Toggle (invert current PWM AQ output B status)   */
} AQSFRC_BIT_ACTSFB;

#define AQSFRC_ALL_ACTSFB_DO_NOTHING     ((0x0UL) << AQSFRC_ALL_ACTSFB_Pos)
#define AQSFRC_ALL_ACTSFB_SET_LOW        ((0x1UL) << AQSFRC_ALL_ACTSFB_Pos)
#define AQSFRC_ALL_ACTSFB_SET_HIGH       ((0x2UL) << AQSFRC_ALL_ACTSFB_Pos)
#define AQSFRC_ALL_ACTSFB_TOGGLE         ((0x3UL) << AQSFRC_ALL_ACTSFB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQSFRC          OTSFB
 *  @access     PWM->AQSFRC.bit.OTSFB
 *  @brief      One-time software forced event on output B
 *              This bit is auto cleared once a write to it is complete
 */
#define AQSFRC_ALL_OTSFB_Pos (5)
#define AQSFRC_ALL_OTSFB_Msk (0x1UL << AQSFRC_ALL_OTSFB_Pos)

typedef enum
{
    AQSFRC_BIT_OTSFB_NO_EFFECT          = 0,  /*!< Write a 0 has no effect. Always reads back a 0                                */
    AQSFRC_BIT_OTSFB_FORCE_ONE_TIME     = 1,  /*!< Write a 1 initialize a one-cycle force pulse. This bit is self-cleared to 0   */
} AQSFRC_BIT_OTSFB;

#define AQSFRC_ALL_OTSFB_NO_EFFECT          ((0x0UL) << AQSFRC_ALL_OTSFB_Pos)
#define AQSFRC_ALL_OTSFB_FORCE_ONE_TIME     ((0x1UL) << AQSFRC_ALL_OTSFB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQSFRC          CSFLOAD
 *  @access     PWM->AQSFRC.bit.CSFLOAD
 *  @brief      Options to load continuous software force register (AQCSFRC) active value from shadow
 *              register
 */
#define AQSFRC_ALL_CSFLOAD_Pos (6)
#define AQSFRC_ALL_CSFLOAD_Msk (0x3UL << AQSFRC_ALL_CSFLOAD_Pos)

typedef enum
{
    AQSFRC_BIT_CSFLOAD_LOAD_ON_ZERO            = 0,  /*!< Load from AQCSFRC into AQCSFRCA on TBCNT=0                      */
    AQSFRC_BIT_CSFLOAD_LOAD_ON_PERIOD          = 1,  /*!< Load from AQCSFRC into AQCSFRCA on TBCNT=TBPRD                  */
    AQSFRC_BIT_CSFLOAD_LOAD_ON_ZERO_PERIOD     = 2,  /*!< Load from AQCSFRC into AQCSFRCA on TBCNT=Zero or TBCNT=TBPRD    */
    AQSFRC_BIT_CSFLOAD_LOAD_IMMEDIATE          = 3,  /*!< Write AQCSFRC immediately change the active value in AQCSFRCA   */
} AQSFRC_BIT_CSFLOAD;

#define AQSFRC_ALL_CSFLOAD_LOAD_ON_ZERO            ((0x0UL) << AQSFRC_ALL_CSFLOAD_Pos)
#define AQSFRC_ALL_CSFLOAD_LOAD_ON_PERIOD          ((0x1UL) << AQSFRC_ALL_CSFLOAD_Pos)
#define AQSFRC_ALL_CSFLOAD_LOAD_ON_ZERO_PERIOD     ((0x2UL) << AQSFRC_ALL_CSFLOAD_Pos)
#define AQSFRC_ALL_CSFLOAD_LOAD_IMMEDIATE          ((0x3UL) << AQSFRC_ALL_CSFLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCSFRC         CSFA
 *  @access     PWM->AQCSFRC.bit.CSFA
 *  @brief      Continuous software force on output A
 */
#define AQCSFRC_ALL_CSFA_Pos (0)
#define AQCSFRC_ALL_CSFA_Msk (0x3UL << AQCSFRC_ALL_CSFA_Pos)

typedef enum
{
    AQCSFRC_BIT_CSFA_DISABLE                   = 0,  /*!< Forcing disabled                      */
    AQCSFRC_BIT_CSFA_FORCE_CONTINUOUS_LOW      = 1,  /*!< Force a continuous low on output A    */
    AQCSFRC_BIT_CSFA_FORCE_CONTINUOUS_HIGH     = 2,  /*!< Force a continuous high on output A   */
    AQCSFRC_BIT_CSFA_NO_EFFECT                 = 3,  /*!< Invalid option                        */
} AQCSFRC_BIT_CSFA;

#define AQCSFRC_ALL_CSFA_DISABLE                   ((0x0UL) << AQCSFRC_ALL_CSFA_Pos)
#define AQCSFRC_ALL_CSFA_FORCE_CONTINUOUS_LOW      ((0x1UL) << AQCSFRC_ALL_CSFA_Pos)
#define AQCSFRC_ALL_CSFA_FORCE_CONTINUOUS_HIGH     ((0x2UL) << AQCSFRC_ALL_CSFA_Pos)
#define AQCSFRC_ALL_CSFA_NO_EFFECT                 ((0x3UL) << AQCSFRC_ALL_CSFA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCSFRC         CSFB
 *  @access     PWM->AQCSFRC.bit.CSFB
 *  @brief      Continuous software force on output B
 */
#define AQCSFRC_ALL_CSFB_Pos (2)
#define AQCSFRC_ALL_CSFB_Msk (0x3UL << AQCSFRC_ALL_CSFB_Pos)

typedef enum
{
    AQCSFRC_BIT_CSFB_DISABLE                   = 0,  /*!< Forcing disabled                      */
    AQCSFRC_BIT_CSFB_FORCE_CONTINUOUS_LOW      = 1,  /*!< Force a continuous low on output B    */
    AQCSFRC_BIT_CSFB_FORCE_CONTINUOUS_HIGH     = 2,  /*!< Force a continuous high on output B   */
    AQCSFRC_BIT_CSFB_NO_EFFECT                 = 3,  /*!< Invalid option                        */
} AQCSFRC_BIT_CSFB;

#define AQCSFRC_ALL_CSFB_DISABLE                   ((0x0UL) << AQCSFRC_ALL_CSFB_Pos)
#define AQCSFRC_ALL_CSFB_FORCE_CONTINUOUS_LOW      ((0x1UL) << AQCSFRC_ALL_CSFB_Pos)
#define AQCSFRC_ALL_CSFB_FORCE_CONTINUOUS_HIGH     ((0x2UL) << AQCSFRC_ALL_CSFB_Pos)
#define AQCSFRC_ALL_CSFB_NO_EFFECT                 ((0x3UL) << AQCSFRC_ALL_CSFB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCSFRCA        CSFA
 *  @access     PWM->AQCSFRCA.bit.CSFA
 *  @brief      Continuous software force on output A
 */
#define AQCSFRCA_ALL_CSFA_Pos (0)
#define AQCSFRCA_ALL_CSFA_Msk (0x3UL << AQCSFRCA_ALL_CSFA_Pos)

typedef enum
{
    AQCSFRCA_BIT_CSFA_DISABLE                   = 0,  /*!< Forcing disabled                      */
    AQCSFRCA_BIT_CSFA_FORCE_CONTINUOUS_LOW      = 1,  /*!< Force a continuous low on output A    */
    AQCSFRCA_BIT_CSFA_FORCE_CONTINUOUS_HIGH     = 2,  /*!< Force a continuous high on output A   */
    AQCSFRCA_BIT_CSFA_NO_EFFECT                 = 3,  /*!< Invalid option                        */
} AQCSFRCA_BIT_CSFA;

#define AQCSFRCA_ALL_CSFA_DISABLE                   ((0x0UL) << AQCSFRCA_ALL_CSFA_Pos)
#define AQCSFRCA_ALL_CSFA_FORCE_CONTINUOUS_LOW      ((0x1UL) << AQCSFRCA_ALL_CSFA_Pos)
#define AQCSFRCA_ALL_CSFA_FORCE_CONTINUOUS_HIGH     ((0x2UL) << AQCSFRCA_ALL_CSFA_Pos)
#define AQCSFRCA_ALL_CSFA_NO_EFFECT                 ((0x3UL) << AQCSFRCA_ALL_CSFA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             AQCSFRCA        CSFB
 *  @access     PWM->AQCSFRCA.bit.CSFB
 *  @brief      Continuous software force on output B
 */
#define AQCSFRCA_ALL_CSFB_Pos (2)
#define AQCSFRCA_ALL_CSFB_Msk (0x3UL << AQCSFRCA_ALL_CSFB_Pos)

typedef enum
{
    AQCSFRCA_BIT_CSFB_DISABLE                   = 0,  /*!< Forcing disabled                      */
    AQCSFRCA_BIT_CSFB_FORCE_CONTINUOUS_LOW      = 1,  /*!< Force a continuous low on output B    */
    AQCSFRCA_BIT_CSFB_FORCE_CONTINUOUS_HIGH     = 2,  /*!< Force a continuous high on output B   */
    AQCSFRCA_BIT_CSFB_NO_EFFECT                 = 3,  /*!< Invalid option                        */
} AQCSFRCA_BIT_CSFB;

#define AQCSFRCA_ALL_CSFB_DISABLE                   ((0x0UL) << AQCSFRCA_ALL_CSFB_Pos)
#define AQCSFRCA_ALL_CSFB_FORCE_CONTINUOUS_LOW      ((0x1UL) << AQCSFRCA_ALL_CSFB_Pos)
#define AQCSFRCA_ALL_CSFB_FORCE_CONTINUOUS_HIGH     ((0x2UL) << AQCSFRCA_ALL_CSFB_Pos)
#define AQCSFRCA_ALL_CSFB_NO_EFFECT                 ((0x3UL) << AQCSFRCA_ALL_CSFB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           REDEN
 *  @access     PWM->DBCTL.bit.REDEN
 *  @brief      Rising-edge delay enable
 */
#define DBCTL_ALL_REDEN_Pos (0)
#define DBCTL_ALL_REDEN_Msk (0x1UL << DBCTL_ALL_REDEN_Pos)

typedef enum
{
    DBCTL_BIT_REDEN_DISABLE     = 0,  /*!< Rising-edge delay is bypassed and the input from action-qualifier goes to the submodule  
                                           directly                                                                                  */
    DBCTL_BIT_REDEN_ENABLE      = 1,  /*!< Rising-edge delay is enabled and applied at output A                                      */
} DBCTL_BIT_REDEN;

#define DBCTL_ALL_REDEN_DISABLE     ((0x0UL) << DBCTL_ALL_REDEN_Pos)
#define DBCTL_ALL_REDEN_ENABLE      ((0x1UL) << DBCTL_ALL_REDEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           FEDEN
 *  @access     PWM->DBCTL.bit.FEDEN
 *  @brief      Falling-edge delay enable
 */
#define DBCTL_ALL_FEDEN_Pos (1)
#define DBCTL_ALL_FEDEN_Msk (0x1UL << DBCTL_ALL_FEDEN_Pos)

typedef enum
{
    DBCTL_BIT_FEDEN_DISABLE     = 0,  /*!< Falling-edge delay is bypassed and the input from action-qualifier goes to the submodule  
                                           directly                                                                                   */
    DBCTL_BIT_FEDEN_ENABLE      = 1,  /*!< Falling-edge delay is enabled and applied at output B                                      */
} DBCTL_BIT_FEDEN;

#define DBCTL_ALL_FEDEN_DISABLE     ((0x0UL) << DBCTL_ALL_FEDEN_Pos)
#define DBCTL_ALL_FEDEN_ENABLE      ((0x1UL) << DBCTL_ALL_FEDEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           REDSRC
 *  @access     PWM->DBCTL.bit.REDSRC
 *  @brief      Rising-edge delay source
 */
#define DBCTL_ALL_REDSRC_Pos (2)
#define DBCTL_ALL_REDSRC_Msk (0x1UL << DBCTL_ALL_REDSRC_Pos)

typedef enum
{
    DBCTL_BIT_REDSRC_FROM_A     = 0,  /*!< Input A is the source for rising-edge delay   */
    DBCTL_BIT_REDSRC_FROM_B     = 1,  /*!< Input B is the source for rising-edge delay   */
} DBCTL_BIT_REDSRC;

#define DBCTL_ALL_REDSRC_FROM_A     ((0x0UL) << DBCTL_ALL_REDSRC_Pos)
#define DBCTL_ALL_REDSRC_FROM_B     ((0x1UL) << DBCTL_ALL_REDSRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           FEDSRC
 *  @access     PWM->DBCTL.bit.FEDSRC
 *  @brief      Falling-edge delay source
 */
#define DBCTL_ALL_FEDSRC_Pos (3)
#define DBCTL_ALL_FEDSRC_Msk (0x1UL << DBCTL_ALL_FEDSRC_Pos)

typedef enum
{
    DBCTL_BIT_FEDSRC_FROM_A     = 0,  /*!< Input A is the source for falling-edge delay   */
    DBCTL_BIT_FEDSRC_FROM_B     = 1,  /*!< Input B is the source for falling-edge delay   */
} DBCTL_BIT_FEDSRC;

#define DBCTL_ALL_FEDSRC_FROM_A     ((0x0UL) << DBCTL_ALL_FEDSRC_Pos)
#define DBCTL_ALL_FEDSRC_FROM_B     ((0x1UL) << DBCTL_ALL_FEDSRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           REDPOL
 *  @access     PWM->DBCTL.bit.REDPOL
 *  @brief      Rising-edge delay output polarity
 */
#define DBCTL_ALL_REDPOL_Pos (4)
#define DBCTL_ALL_REDPOL_Msk (0x1UL << DBCTL_ALL_REDPOL_Pos)

typedef enum
{
    DBCTL_BIT_REDPOL_ACTIVE_LOW      = 0,  /*!< Rising-edge delay output is inverted to have active-low polarity   */
    DBCTL_BIT_REDPOL_ACTIVE_HIGH     = 1,  /*!< Rising-edge delay output keeps the original active-high polarity   */
} DBCTL_BIT_REDPOL;

#define DBCTL_ALL_REDPOL_ACTIVE_LOW      ((0x0UL) << DBCTL_ALL_REDPOL_Pos)
#define DBCTL_ALL_REDPOL_ACTIVE_HIGH     ((0x1UL) << DBCTL_ALL_REDPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           FEDPOL
 *  @access     PWM->DBCTL.bit.FEDPOL
 *  @brief      Falling-edge delay output polarity
 */
#define DBCTL_ALL_FEDPOL_Pos (5)
#define DBCTL_ALL_FEDPOL_Msk (0x1UL << DBCTL_ALL_FEDPOL_Pos)

typedef enum
{
    DBCTL_BIT_FEDPOL_ACTIVE_LOW      = 0,  /*!< Falling-edge delay output is inverted to have active-low polarity   */
    DBCTL_BIT_FEDPOL_ACTIVE_HIGH     = 1,  /*!< Falling-edge delay output keeps the original active-high polarity   */
} DBCTL_BIT_FEDPOL;

#define DBCTL_ALL_FEDPOL_ACTIVE_LOW      ((0x0UL) << DBCTL_ALL_FEDPOL_Pos)
#define DBCTL_ALL_FEDPOL_ACTIVE_HIGH     ((0x1UL) << DBCTL_ALL_FEDPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           OUTASRC
 *  @access     PWM->DBCTL.bit.OUTASRC
 *  @brief      Output A source
 */
#define DBCTL_ALL_OUTASRC_Pos (6)
#define DBCTL_ALL_OUTASRC_Msk (0x1UL << DBCTL_ALL_OUTASRC_Pos)

typedef enum
{
    DBCTL_BIT_OUTASRC_FALLING_EDGE     = 0,  /*!< Falling-edge delay path is selected as output A   */
    DBCTL_BIT_OUTASRC_RISING_EDGE      = 1,  /*!< Rising-edge delay path is selected as output A    */
} DBCTL_BIT_OUTASRC;

#define DBCTL_ALL_OUTASRC_FALLING_EDGE     ((0x0UL) << DBCTL_ALL_OUTASRC_Pos)
#define DBCTL_ALL_OUTASRC_RISING_EDGE      ((0x1UL) << DBCTL_ALL_OUTASRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           OUTBSRC
 *  @access     PWM->DBCTL.bit.OUTBSRC
 *  @brief      Output B source
 */
#define DBCTL_ALL_OUTBSRC_Pos (7)
#define DBCTL_ALL_OUTBSRC_Msk (0x1UL << DBCTL_ALL_OUTBSRC_Pos)

typedef enum
{
    DBCTL_BIT_OUTBSRC_FALLING_EDGE     = 0,  /*!< Falling-edge delay path is selected as output B   */
    DBCTL_BIT_OUTBSRC_RISING_EDGE      = 1,  /*!< Rising-edge delay path is selected as output B    */
} DBCTL_BIT_OUTBSRC;

#define DBCTL_ALL_OUTBSRC_FALLING_EDGE     ((0x0UL) << DBCTL_ALL_OUTBSRC_Pos)
#define DBCTL_ALL_OUTBSRC_RISING_EDGE      ((0x1UL) << DBCTL_ALL_OUTBSRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           DUALEDGE
 *  @access     PWM->DBCTL.bit.DUALEDGE
 *  @brief      Dual-edge delay mode
 */
#define DBCTL_ALL_DUALEDGE_Pos (8)
#define DBCTL_ALL_DUALEDGE_Msk (0x1UL << DBCTL_ALL_DUALEDGE_Pos)

typedef enum
{
    DBCTL_BIT_DUALEDGE_DISABLE     = 0,  /*!< Rising-edge delay and falling-edge delay are two separate paths             */
    DBCTL_BIT_DUALEDGE_ENABLE      = 1,  /*!< Rising-edge delay path output serves as input for Falling-edge delay path   */
} DBCTL_BIT_DUALEDGE;

#define DBCTL_ALL_DUALEDGE_DISABLE     ((0x0UL) << DBCTL_ALL_DUALEDGE_Pos)
#define DBCTL_ALL_DUALEDGE_ENABLE      ((0x1UL) << DBCTL_ALL_DUALEDGE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           HALFCYCLE
 *  @access     PWM->DBCTL.bit.HALFCYCLE
 *  @brief      Half cycle clocking enable
 */
#define DBCTL_ALL_HALFCYCLE_Pos (9)
#define DBCTL_ALL_HALFCYCLE_Msk (0x1UL << DBCTL_ALL_HALFCYCLE_Pos)

typedef enum
{
    DBCTL_BIT_HALFCYCLE_DISABLE     = 0,  /*!< Full cycle clocking enabled. The dead-band counter is clocked at TBCLK.      */
    DBCTL_BIT_HALFCYCLE_ENABLE      = 1,  /*!< Half cycle clocking enabled. The dead-band counter is clocked at 2x TBCLK.   */
} DBCTL_BIT_HALFCYCLE;

#define DBCTL_ALL_HALFCYCLE_DISABLE     ((0x0UL) << DBCTL_ALL_HALFCYCLE_Pos)
#define DBCTL_ALL_HALFCYCLE_ENABLE      ((0x1UL) << DBCTL_ALL_HALFCYCLE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           DBCTLLOAD
 *  @access     PWM->DBCTL.bit.DBCTLLOAD
 *  @brief      DBCTL[9:0] active value load mode
 *              It has no effect when DBCTL[DBCTLLOCK]=1
 */
#define DBCTL_ALL_DBCTLLOAD_Pos (10)
#define DBCTL_ALL_DBCTLLOAD_Msk (0x3UL << DBCTL_ALL_DBCTLLOAD_Pos)

typedef enum
{
    DBCTL_BIT_DBCTLLOAD_LOAD_ON_ZERO            = 0,  /*!< Load DBCTL[9:0] into DBCTLA on TBCNT=0                                */
    DBCTL_BIT_DBCTLLOAD_LOAD_ON_PERIOD          = 1,  /*!< Load DBCTL[9:0] into DBCTLA on TBCNT=TBPRD                            */
    DBCTL_BIT_DBCTLLOAD_LOAD_ON_ZERO_PERIOD     = 2,  /*!< Load DBCTL[9:0] into DBCTLA on TBCNT=0 or TBCNT=TBPRD                 */
    DBCTL_BIT_DBCTLLOAD_LOAD_IMMEDIATE          = 3,  /*!< Write DBCTL[9:0] will immediately change the active value in DBCTLA   */
} DBCTL_BIT_DBCTLLOAD;

#define DBCTL_ALL_DBCTLLOAD_LOAD_ON_ZERO            ((0x0UL) << DBCTL_ALL_DBCTLLOAD_Pos)
#define DBCTL_ALL_DBCTLLOAD_LOAD_ON_PERIOD          ((0x1UL) << DBCTL_ALL_DBCTLLOAD_Pos)
#define DBCTL_ALL_DBCTLLOAD_LOAD_ON_ZERO_PERIOD     ((0x2UL) << DBCTL_ALL_DBCTLLOAD_Pos)
#define DBCTL_ALL_DBCTLLOAD_LOAD_IMMEDIATE          ((0x3UL) << DBCTL_ALL_DBCTLLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           DBCTLLOCK
 *  @access     PWM->DBCTL.bit.DBCTLLOCK
 *  @brief      DBCTL[9:0] active value lock
 */
#define DBCTL_ALL_DBCTLLOCK_Pos (12)
#define DBCTL_ALL_DBCTLLOCK_Msk (0x1UL << DBCTL_ALL_DBCTLLOCK_Pos)

typedef enum
{
    DBCTL_BIT_DBCTLLOCK_UNLOCK     = 0,  /*!< Active value in DBCTLA is updated according to DBCTL[DBCTLLOAD]   */
    DBCTL_BIT_DBCTLLOCK_LOCK       = 1,  /*!< Active value in DBCTLA will not change                            */
} DBCTL_BIT_DBCTLLOCK;

#define DBCTL_ALL_DBCTLLOCK_UNLOCK     ((0x0UL) << DBCTL_ALL_DBCTLLOCK_Pos)
#define DBCTL_ALL_DBCTLLOCK_LOCK       ((0x1UL) << DBCTL_ALL_DBCTLLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           DBREDLOAD
 *  @access     PWM->DBCTL.bit.DBREDLOAD
 *  @brief      DBRED active value load mode
 *              It has no effect when DBCTL[DBFEDLOCK]=1
 */
#define DBCTL_ALL_DBREDLOAD_Pos (13)
#define DBCTL_ALL_DBREDLOAD_Msk (0x3UL << DBCTL_ALL_DBREDLOAD_Pos)

typedef enum
{
    DBCTL_BIT_DBREDLOAD_LOAD_ON_ZERO            = 0,  /*!< Load DBRED into DBREDA on TBCNT=0                                */
    DBCTL_BIT_DBREDLOAD_LOAD_ON_PERIOD          = 1,  /*!< Load DBRED into DBREDA on TBCNT=TBPRD                            */
    DBCTL_BIT_DBREDLOAD_LOAD_ON_ZERO_PERIOD     = 2,  /*!< Load DBRED into DBREDA on TBCNT=0 or TBCNT=TBPRD                 */
    DBCTL_BIT_DBREDLOAD_LOAD_IMMEDIATE          = 3,  /*!< Write DBRED will immediately change the active value in DBREDA   */
} DBCTL_BIT_DBREDLOAD;

#define DBCTL_ALL_DBREDLOAD_LOAD_ON_ZERO            ((0x0UL) << DBCTL_ALL_DBREDLOAD_Pos)
#define DBCTL_ALL_DBREDLOAD_LOAD_ON_PERIOD          ((0x1UL) << DBCTL_ALL_DBREDLOAD_Pos)
#define DBCTL_ALL_DBREDLOAD_LOAD_ON_ZERO_PERIOD     ((0x2UL) << DBCTL_ALL_DBREDLOAD_Pos)
#define DBCTL_ALL_DBREDLOAD_LOAD_IMMEDIATE          ((0x3UL) << DBCTL_ALL_DBREDLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           DBREDLOCK
 *  @access     PWM->DBCTL.bit.DBREDLOCK
 *  @brief      DBRED active value lock
 */
#define DBCTL_ALL_DBREDLOCK_Pos (15)
#define DBCTL_ALL_DBREDLOCK_Msk (0x1UL << DBCTL_ALL_DBREDLOCK_Pos)

typedef enum
{
    DBCTL_BIT_DBREDLOCK_UNLOCK     = 0,  /*!< Active value in DBREDA is updated according to DBCTL[DBREDLOAD]   */
    DBCTL_BIT_DBREDLOCK_LOCK       = 1,  /*!< Active value in DBREDA will not change                            */
} DBCTL_BIT_DBREDLOCK;

#define DBCTL_ALL_DBREDLOCK_UNLOCK     ((0x0UL) << DBCTL_ALL_DBREDLOCK_Pos)
#define DBCTL_ALL_DBREDLOCK_LOCK       ((0x1UL) << DBCTL_ALL_DBREDLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           DBFEDLOAD
 *  @access     PWM->DBCTL.bit.DBFEDLOAD
 *  @brief      DBFED active value load mode
 *              It has no effect when DBCTL[DBFEDLOCK]=1
 */
#define DBCTL_ALL_DBFEDLOAD_Pos (16)
#define DBCTL_ALL_DBFEDLOAD_Msk (0x3UL << DBCTL_ALL_DBFEDLOAD_Pos)

typedef enum
{
    DBCTL_BIT_DBFEDLOAD_LOAD_ON_ZERO            = 0,  /*!< Load DBFED into DBFEDA on TBCNT=0                           */
    DBCTL_BIT_DBFEDLOAD_LOAD_ON_PERIOD          = 1,  /*!< Load DBFED into DBFEDA on TBCNT=TBPRD                       */
    DBCTL_BIT_DBFEDLOAD_LOAD_ON_ZERO_PERIOD     = 2,  /*!< Load DBFED into DBFEDA on TBCNT=0 or TBCNT=TBPRD            */
    DBCTL_BIT_DBFEDLOAD_LOAD_IMMEDIATE          = 3,  /*!< Write DBFED immediately change the active value in DBFEDA   */
} DBCTL_BIT_DBFEDLOAD;

#define DBCTL_ALL_DBFEDLOAD_LOAD_ON_ZERO            ((0x0UL) << DBCTL_ALL_DBFEDLOAD_Pos)
#define DBCTL_ALL_DBFEDLOAD_LOAD_ON_PERIOD          ((0x1UL) << DBCTL_ALL_DBFEDLOAD_Pos)
#define DBCTL_ALL_DBFEDLOAD_LOAD_ON_ZERO_PERIOD     ((0x2UL) << DBCTL_ALL_DBFEDLOAD_Pos)
#define DBCTL_ALL_DBFEDLOAD_LOAD_IMMEDIATE          ((0x3UL) << DBCTL_ALL_DBFEDLOAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTL           DBFEDLOCK
 *  @access     PWM->DBCTL.bit.DBFEDLOCK
 *  @brief      DBFED active value lock
 */
#define DBCTL_ALL_DBFEDLOCK_Pos (18)
#define DBCTL_ALL_DBFEDLOCK_Msk (0x1UL << DBCTL_ALL_DBFEDLOCK_Pos)

typedef enum
{
    DBCTL_BIT_DBFEDLOCK_UNLOCK     = 0,  /*!< Active value in DBFEDA is updated according to DBCTL[DBFEDLOAD]   */
    DBCTL_BIT_DBFEDLOCK_LOCK       = 1,  /*!< Active value in DBFEDA will not change                            */
} DBCTL_BIT_DBFEDLOCK;

#define DBCTL_ALL_DBFEDLOCK_UNLOCK     ((0x0UL) << DBCTL_ALL_DBFEDLOCK_Pos)
#define DBCTL_ALL_DBFEDLOCK_LOCK       ((0x1UL) << DBCTL_ALL_DBFEDLOCK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          REDEN
 *  @access     PWM->DBCTLA.bit.REDEN
 *  @brief      Rising-edge delay enable
 */
#define DBCTLA_ALL_REDEN_Pos (0)
#define DBCTLA_ALL_REDEN_Msk (0x1UL << DBCTLA_ALL_REDEN_Pos)

typedef enum
{
    DBCTLA_BIT_REDEN_DISABLE     = 0,  /*!< Rising-edge delay is bypassed and the input from action-qualifier goes to the submodule  
                                            directly                                                                                  */
    DBCTLA_BIT_REDEN_ENABLE      = 1,  /*!< Rising-edge delay is enabled and applied at output A                                      */
} DBCTLA_BIT_REDEN;

#define DBCTLA_ALL_REDEN_DISABLE     ((0x0UL) << DBCTLA_ALL_REDEN_Pos)
#define DBCTLA_ALL_REDEN_ENABLE      ((0x1UL) << DBCTLA_ALL_REDEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          FEDEN
 *  @access     PWM->DBCTLA.bit.FEDEN
 *  @brief      Falling-edge delay enable
 */
#define DBCTLA_ALL_FEDEN_Pos (1)
#define DBCTLA_ALL_FEDEN_Msk (0x1UL << DBCTLA_ALL_FEDEN_Pos)

typedef enum
{
    DBCTLA_BIT_FEDEN_DISABLE     = 0,  /*!< Falling-edge delay is bypassed and the input from action-qualifier goes to the submodule  
                                            directly                                                                                   */
    DBCTLA_BIT_FEDEN_ENABLE      = 1,  /*!< Falling-edge delay is enabled and applied at output B                                      */
} DBCTLA_BIT_FEDEN;

#define DBCTLA_ALL_FEDEN_DISABLE     ((0x0UL) << DBCTLA_ALL_FEDEN_Pos)
#define DBCTLA_ALL_FEDEN_ENABLE      ((0x1UL) << DBCTLA_ALL_FEDEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          REDSRC
 *  @access     PWM->DBCTLA.bit.REDSRC
 *  @brief      Rising-edge delay source
 */
#define DBCTLA_ALL_REDSRC_Pos (2)
#define DBCTLA_ALL_REDSRC_Msk (0x1UL << DBCTLA_ALL_REDSRC_Pos)

typedef enum
{
    DBCTLA_BIT_REDSRC_FROM_A     = 0,  /*!< Input A is the source for rising-edge delay   */
    DBCTLA_BIT_REDSRC_FROM_B     = 1,  /*!< Input B is the source for rising-edge delay   */
} DBCTLA_BIT_REDSRC;

#define DBCTLA_ALL_REDSRC_FROM_A     ((0x0UL) << DBCTLA_ALL_REDSRC_Pos)
#define DBCTLA_ALL_REDSRC_FROM_B     ((0x1UL) << DBCTLA_ALL_REDSRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          FEDSRC
 *  @access     PWM->DBCTLA.bit.FEDSRC
 *  @brief      Falling-edge delay source
 */
#define DBCTLA_ALL_FEDSRC_Pos (3)
#define DBCTLA_ALL_FEDSRC_Msk (0x1UL << DBCTLA_ALL_FEDSRC_Pos)

typedef enum
{
    DBCTLA_BIT_FEDSRC_FROM_A     = 0,  /*!< Input A is the source for falling-edge delay   */
    DBCTLA_BIT_FEDSRC_FROM_B     = 1,  /*!< Input B is the source for falling-edge delay   */
} DBCTLA_BIT_FEDSRC;

#define DBCTLA_ALL_FEDSRC_FROM_A     ((0x0UL) << DBCTLA_ALL_FEDSRC_Pos)
#define DBCTLA_ALL_FEDSRC_FROM_B     ((0x1UL) << DBCTLA_ALL_FEDSRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          REDPOL
 *  @access     PWM->DBCTLA.bit.REDPOL
 *  @brief      Rising-edge delay output polarity
 */
#define DBCTLA_ALL_REDPOL_Pos (4)
#define DBCTLA_ALL_REDPOL_Msk (0x1UL << DBCTLA_ALL_REDPOL_Pos)

typedef enum
{
    DBCTLA_BIT_REDPOL_ACTIVE_LOW      = 0,  /*!< Rising-edge delay output is inverted to have active-low polarity   */
    DBCTLA_BIT_REDPOL_ACTIVE_HIGH     = 1,  /*!< Rising-edge delay output keeps the original active-high polarity   */
} DBCTLA_BIT_REDPOL;

#define DBCTLA_ALL_REDPOL_ACTIVE_LOW      ((0x0UL) << DBCTLA_ALL_REDPOL_Pos)
#define DBCTLA_ALL_REDPOL_ACTIVE_HIGH     ((0x1UL) << DBCTLA_ALL_REDPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          FEDPOL
 *  @access     PWM->DBCTLA.bit.FEDPOL
 *  @brief      Falling-edge delay output polarity
 */
#define DBCTLA_ALL_FEDPOL_Pos (5)
#define DBCTLA_ALL_FEDPOL_Msk (0x1UL << DBCTLA_ALL_FEDPOL_Pos)

typedef enum
{
    DBCTLA_BIT_FEDPOL_ACTIVE_LOW      = 0,  /*!< Falling-edge delay output is inverted to have active-low polarity   */
    DBCTLA_BIT_FEDPOL_ACTIVE_HIGH     = 1,  /*!< Falling-edge delay output keeps the original active-high polarity   */
} DBCTLA_BIT_FEDPOL;

#define DBCTLA_ALL_FEDPOL_ACTIVE_LOW      ((0x0UL) << DBCTLA_ALL_FEDPOL_Pos)
#define DBCTLA_ALL_FEDPOL_ACTIVE_HIGH     ((0x1UL) << DBCTLA_ALL_FEDPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          OUTASRC
 *  @access     PWM->DBCTLA.bit.OUTASRC
 *  @brief      Output A source
 */
#define DBCTLA_ALL_OUTASRC_Pos (6)
#define DBCTLA_ALL_OUTASRC_Msk (0x1UL << DBCTLA_ALL_OUTASRC_Pos)

typedef enum
{
    DBCTLA_BIT_OUTASRC_FALLING_EDGE     = 0,  /*!< Falling-edge delay path is selected as output A   */
    DBCTLA_BIT_OUTASRC_RISING_EDGE      = 1,  /*!< Rising-edge delay path is selected as output A    */
} DBCTLA_BIT_OUTASRC;

#define DBCTLA_ALL_OUTASRC_FALLING_EDGE     ((0x0UL) << DBCTLA_ALL_OUTASRC_Pos)
#define DBCTLA_ALL_OUTASRC_RISING_EDGE      ((0x1UL) << DBCTLA_ALL_OUTASRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          OUTBSRC
 *  @access     PWM->DBCTLA.bit.OUTBSRC
 *  @brief      Output B source
 */
#define DBCTLA_ALL_OUTBSRC_Pos (7)
#define DBCTLA_ALL_OUTBSRC_Msk (0x1UL << DBCTLA_ALL_OUTBSRC_Pos)

typedef enum
{
    DBCTLA_BIT_OUTBSRC_FALLING_EDGE     = 0,  /*!< Falling-edge delay path is selected as output B   */
    DBCTLA_BIT_OUTBSRC_RISING_EDGE      = 1,  /*!< Rising-edge delay path is selected as output B    */
} DBCTLA_BIT_OUTBSRC;

#define DBCTLA_ALL_OUTBSRC_FALLING_EDGE     ((0x0UL) << DBCTLA_ALL_OUTBSRC_Pos)
#define DBCTLA_ALL_OUTBSRC_RISING_EDGE      ((0x1UL) << DBCTLA_ALL_OUTBSRC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          DUALEDGE
 *  @access     PWM->DBCTLA.bit.DUALEDGE
 *  @brief      Dual-edge delay mode
 */
#define DBCTLA_ALL_DUALEDGE_Pos (8)
#define DBCTLA_ALL_DUALEDGE_Msk (0x1UL << DBCTLA_ALL_DUALEDGE_Pos)

typedef enum
{
    DBCTLA_BIT_DUALEDGE_DISABLE     = 0,  /*!< Rising-edge delay and falling-edge delay are two separate paths             */
    DBCTLA_BIT_DUALEDGE_ENABLE      = 1,  /*!< Rising-edge delay path output serves as input for Falling-edge delay path   */
} DBCTLA_BIT_DUALEDGE;

#define DBCTLA_ALL_DUALEDGE_DISABLE     ((0x0UL) << DBCTLA_ALL_DUALEDGE_Pos)
#define DBCTLA_ALL_DUALEDGE_ENABLE      ((0x1UL) << DBCTLA_ALL_DUALEDGE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBCTLA          HALFCYCLE
 *  @access     PWM->DBCTLA.bit.HALFCYCLE
 *  @brief      Half cycle clocking enable
 */
#define DBCTLA_ALL_HALFCYCLE_Pos (9)
#define DBCTLA_ALL_HALFCYCLE_Msk (0x1UL << DBCTLA_ALL_HALFCYCLE_Pos)

typedef enum
{
    DBCTLA_BIT_HALFCYCLE_DISABLE     = 0,  /*!< Full cycle clocking enabled. The dead-band counter is clocked at TBCLK.      */
    DBCTLA_BIT_HALFCYCLE_ENABLE      = 1,  /*!< Half cycle clocking enabled. The dead-band counter is clocked at 2x TBCLK.   */
} DBCTLA_BIT_HALFCYCLE;

#define DBCTLA_ALL_HALFCYCLE_DISABLE     ((0x0UL) << DBCTLA_ALL_HALFCYCLE_Pos)
#define DBCTLA_ALL_HALFCYCLE_ENABLE      ((0x1UL) << DBCTLA_ALL_HALFCYCLE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBRED           VAL
 *  @access     PWM->DBRED.bit.VAL
 *  @brief      Rising-edge delay
 */
#define DBRED_ALL_VAL_Pos (0)
#define DBRED_ALL_VAL_Msk (0xFFFFUL << DBRED_ALL_VAL_Pos)

#define DBRED_BIT_VAL

#define DBRED_ALL_VAL_(x) ((x) << DBRED_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBREDA          VAL
 *  @access     PWM->DBREDA.bit.VAL
 *  @brief      Rising-edge delay
 */
#define DBREDA_ALL_VAL_Pos (0)
#define DBREDA_ALL_VAL_Msk (0xFFFFUL << DBREDA_ALL_VAL_Pos)

#define DBREDA_BIT_VAL

#define DBREDA_ALL_VAL_(x) ((x) << DBREDA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBFED           VAL
 *  @access     PWM->DBFED.bit.VAL
 *  @brief      Falling-edge delay
 */
#define DBFED_ALL_VAL_Pos (0)
#define DBFED_ALL_VAL_Msk (0xFFFFUL << DBFED_ALL_VAL_Pos)

#define DBFED_BIT_VAL

#define DBFED_ALL_VAL_(x) ((x) << DBFED_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DBFEDA          VAL
 *  @access     PWM->DBFEDA.bit.VAL
 *  @brief      Falling-edge delay
 */
#define DBFEDA_ALL_VAL_Pos (0)
#define DBFEDA_ALL_VAL_Msk (0xFFFFUL << DBFEDA_ALL_VAL_Pos)

#define DBFEDA_BIT_VAL

#define DBFEDA_ALL_VAL_(x) ((x) << DBFEDA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           OSTOUT
 *  @access     PWM->TZSEL.bit.OSTOUT
 *  @brief      One-shot trip-zone output select
 */
#define TZSEL_ALL_OSTOUT_Pos (0)
#define TZSEL_ALL_OSTOUT_Msk (0x3UL << TZSEL_ALL_OSTOUT_Pos)

typedef enum
{
    TZSEL_BIT_OSTOUT_DISABLE            = 0,  /*!< Disable one-shot trip-zone                                                  */
    TZSEL_BIT_OSTOUT_ASYNC              = 1,  /*!< Select only the asynchronous path. i.e. The original event OR gate output   */
    TZSEL_BIT_OSTOUT_LATCH              = 2,  /*!< Select only the latched path                                                */
    TZSEL_BIT_OSTOUT_ASYNC_OR_LATCH     = 3,  /*!< Select both the asynchronous path and the latched path (ORed)               */
} TZSEL_BIT_OSTOUT;

#define TZSEL_ALL_OSTOUT_DISABLE            ((0x0UL) << TZSEL_ALL_OSTOUT_Pos)
#define TZSEL_ALL_OSTOUT_ASYNC              ((0x1UL) << TZSEL_ALL_OSTOUT_Pos)
#define TZSEL_ALL_OSTOUT_LATCH              ((0x2UL) << TZSEL_ALL_OSTOUT_Pos)
#define TZSEL_ALL_OSTOUT_ASYNC_OR_LATCH     ((0x3UL) << TZSEL_ALL_OSTOUT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ0OST
 *  @access     PWM->TZSEL.bit.TZ0OST
 *  @brief      TZ0 as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_TZ0OST_Pos (2)
#define TZSEL_ALL_TZ0OST_Msk (0x1UL << TZSEL_ALL_TZ0OST_Pos)

typedef enum
{
    TZSEL_BIT_TZ0OST_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ0OST_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ0OST;

#define TZSEL_ALL_TZ0OST_DISABLE     ((0x0UL) << TZSEL_ALL_TZ0OST_Pos)
#define TZSEL_ALL_TZ0OST_ENABLE      ((0x1UL) << TZSEL_ALL_TZ0OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ1OST
 *  @access     PWM->TZSEL.bit.TZ1OST
 *  @brief      TZ1 as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_TZ1OST_Pos (3)
#define TZSEL_ALL_TZ1OST_Msk (0x1UL << TZSEL_ALL_TZ1OST_Pos)

typedef enum
{
    TZSEL_BIT_TZ1OST_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ1OST_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ1OST;

#define TZSEL_ALL_TZ1OST_DISABLE     ((0x0UL) << TZSEL_ALL_TZ1OST_Pos)
#define TZSEL_ALL_TZ1OST_ENABLE      ((0x1UL) << TZSEL_ALL_TZ1OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ2OST
 *  @access     PWM->TZSEL.bit.TZ2OST
 *  @brief      TZ2 as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_TZ2OST_Pos (4)
#define TZSEL_ALL_TZ2OST_Msk (0x1UL << TZSEL_ALL_TZ2OST_Pos)

typedef enum
{
    TZSEL_BIT_TZ2OST_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ2OST_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ2OST;

#define TZSEL_ALL_TZ2OST_DISABLE     ((0x0UL) << TZSEL_ALL_TZ2OST_Pos)
#define TZSEL_ALL_TZ2OST_ENABLE      ((0x1UL) << TZSEL_ALL_TZ2OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ3OST
 *  @access     PWM->TZSEL.bit.TZ3OST
 *  @brief      TZ3 as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_TZ3OST_Pos (5)
#define TZSEL_ALL_TZ3OST_Msk (0x1UL << TZSEL_ALL_TZ3OST_Pos)

typedef enum
{
    TZSEL_BIT_TZ3OST_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ3OST_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ3OST;

#define TZSEL_ALL_TZ3OST_DISABLE     ((0x0UL) << TZSEL_ALL_TZ3OST_Pos)
#define TZSEL_ALL_TZ3OST_ENABLE      ((0x1UL) << TZSEL_ALL_TZ3OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ4OST
 *  @access     PWM->TZSEL.bit.TZ4OST
 *  @brief      TZ4 as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_TZ4OST_Pos (6)
#define TZSEL_ALL_TZ4OST_Msk (0x1UL << TZSEL_ALL_TZ4OST_Pos)

typedef enum
{
    TZSEL_BIT_TZ4OST_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ4OST_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ4OST;

#define TZSEL_ALL_TZ4OST_DISABLE     ((0x0UL) << TZSEL_ALL_TZ4OST_Pos)
#define TZSEL_ALL_TZ4OST_ENABLE      ((0x1UL) << TZSEL_ALL_TZ4OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           CLKERROST
 *  @access     PWM->TZSEL.bit.CLKERROST
 *  @brief      Clock error as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_CLKERROST_Pos (7)
#define TZSEL_ALL_CLKERROST_Msk (0x1UL << TZSEL_ALL_CLKERROST_Pos)

typedef enum
{
    TZSEL_BIT_CLKERROST_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_CLKERROST_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_CLKERROST;

#define TZSEL_ALL_CLKERROST_DISABLE     ((0x0UL) << TZSEL_ALL_CLKERROST_Pos)
#define TZSEL_ALL_CLKERROST_ENABLE      ((0x1UL) << TZSEL_ALL_CLKERROST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           DCAEVT0
 *  @access     PWM->TZSEL.bit.DCAEVT0
 *  @brief      Digital compare A event 0 as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_DCAEVT0_Pos (8)
#define TZSEL_ALL_DCAEVT0_Msk (0x1UL << TZSEL_ALL_DCAEVT0_Pos)

typedef enum
{
    TZSEL_BIT_DCAEVT0_ONESHOT_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_DCAEVT0_ONESHOT_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_DCAEVT0;

#define TZSEL_ALL_DCAEVT0_ONESHOT_DISABLE     ((0x0UL) << TZSEL_ALL_DCAEVT0_Pos)
#define TZSEL_ALL_DCAEVT0_ONESHOT_ENABLE      ((0x1UL) << TZSEL_ALL_DCAEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           DCBEVT0
 *  @access     PWM->TZSEL.bit.DCBEVT0
 *  @brief      Digital compare B event 0 as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_DCBEVT0_Pos (9)
#define TZSEL_ALL_DCBEVT0_Msk (0x1UL << TZSEL_ALL_DCBEVT0_Pos)

typedef enum
{
    TZSEL_BIT_DCBEVT0_ONESHOT_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_DCBEVT0_ONESHOT_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_DCBEVT0;

#define TZSEL_ALL_DCBEVT0_ONESHOT_DISABLE     ((0x0UL) << TZSEL_ALL_DCBEVT0_Pos)
#define TZSEL_ALL_DCBEVT0_ONESHOT_ENABLE      ((0x1UL) << TZSEL_ALL_DCBEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           DBGOST
 *  @access     PWM->TZSEL.bit.DBGOST
 *  @brief      JTAG debug as a one-shot trip source (ORed)
 */
#define TZSEL_ALL_DBGOST_Pos (10)
#define TZSEL_ALL_DBGOST_Msk (0x1UL << TZSEL_ALL_DBGOST_Pos)

typedef enum
{
    TZSEL_BIT_DBGOST_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_DBGOST_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_DBGOST;

#define TZSEL_ALL_DBGOST_DISABLE     ((0x0UL) << TZSEL_ALL_DBGOST_Pos)
#define TZSEL_ALL_DBGOST_ENABLE      ((0x1UL) << TZSEL_ALL_DBGOST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           CBCOUT
 *  @access     PWM->TZSEL.bit.CBCOUT
 *  @brief      Cycle-by-cycle trip-zone output select
 */
#define TZSEL_ALL_CBCOUT_Pos (16)
#define TZSEL_ALL_CBCOUT_Msk (0x3UL << TZSEL_ALL_CBCOUT_Pos)

typedef enum
{
    TZSEL_BIT_CBCOUT_DISABLE            = 0,  /*!< Disable cycle-by-cycle trip-zone                                            */
    TZSEL_BIT_CBCOUT_ASYNC              = 1,  /*!< Select only the asynchronous path. i.e. The original event OR gate output   */
    TZSEL_BIT_CBCOUT_LATCH              = 2,  /*!< Select only the latched path                                                */
    TZSEL_BIT_CBCOUT_ASYNC_OR_LATCH     = 3,  /*!< Select both the asynchronous path and the latched path (ORed)               */
} TZSEL_BIT_CBCOUT;

#define TZSEL_ALL_CBCOUT_DISABLE            ((0x0UL) << TZSEL_ALL_CBCOUT_Pos)
#define TZSEL_ALL_CBCOUT_ASYNC              ((0x1UL) << TZSEL_ALL_CBCOUT_Pos)
#define TZSEL_ALL_CBCOUT_LATCH              ((0x2UL) << TZSEL_ALL_CBCOUT_Pos)
#define TZSEL_ALL_CBCOUT_ASYNC_OR_LATCH     ((0x3UL) << TZSEL_ALL_CBCOUT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ0CBC
 *  @access     PWM->TZSEL.bit.TZ0CBC
 *  @brief      TZ0 as a cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_TZ0CBC_Pos (18)
#define TZSEL_ALL_TZ0CBC_Msk (0x1UL << TZSEL_ALL_TZ0CBC_Pos)

typedef enum
{
    TZSEL_BIT_TZ0CBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ0CBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ0CBC;

#define TZSEL_ALL_TZ0CBC_DISABLE     ((0x0UL) << TZSEL_ALL_TZ0CBC_Pos)
#define TZSEL_ALL_TZ0CBC_ENABLE      ((0x1UL) << TZSEL_ALL_TZ0CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ1CBC
 *  @access     PWM->TZSEL.bit.TZ1CBC
 *  @brief      TZ1 as a cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_TZ1CBC_Pos (19)
#define TZSEL_ALL_TZ1CBC_Msk (0x1UL << TZSEL_ALL_TZ1CBC_Pos)

typedef enum
{
    TZSEL_BIT_TZ1CBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ1CBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ1CBC;

#define TZSEL_ALL_TZ1CBC_DISABLE     ((0x0UL) << TZSEL_ALL_TZ1CBC_Pos)
#define TZSEL_ALL_TZ1CBC_ENABLE      ((0x1UL) << TZSEL_ALL_TZ1CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ2CBC
 *  @access     PWM->TZSEL.bit.TZ2CBC
 *  @brief      TZ2 as a cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_TZ2CBC_Pos (20)
#define TZSEL_ALL_TZ2CBC_Msk (0x1UL << TZSEL_ALL_TZ2CBC_Pos)

typedef enum
{
    TZSEL_BIT_TZ2CBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ2CBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ2CBC;

#define TZSEL_ALL_TZ2CBC_DISABLE     ((0x0UL) << TZSEL_ALL_TZ2CBC_Pos)
#define TZSEL_ALL_TZ2CBC_ENABLE      ((0x1UL) << TZSEL_ALL_TZ2CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ3CBC
 *  @access     PWM->TZSEL.bit.TZ3CBC
 *  @brief      TZ3 as a cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_TZ3CBC_Pos (21)
#define TZSEL_ALL_TZ3CBC_Msk (0x1UL << TZSEL_ALL_TZ3CBC_Pos)

typedef enum
{
    TZSEL_BIT_TZ3CBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ3CBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ3CBC;

#define TZSEL_ALL_TZ3CBC_DISABLE     ((0x0UL) << TZSEL_ALL_TZ3CBC_Pos)
#define TZSEL_ALL_TZ3CBC_ENABLE      ((0x1UL) << TZSEL_ALL_TZ3CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           TZ4CBC
 *  @access     PWM->TZSEL.bit.TZ4CBC
 *  @brief      TZ4 as a cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_TZ4CBC_Pos (22)
#define TZSEL_ALL_TZ4CBC_Msk (0x1UL << TZSEL_ALL_TZ4CBC_Pos)

typedef enum
{
    TZSEL_BIT_TZ4CBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_TZ4CBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_TZ4CBC;

#define TZSEL_ALL_TZ4CBC_DISABLE     ((0x0UL) << TZSEL_ALL_TZ4CBC_Pos)
#define TZSEL_ALL_TZ4CBC_ENABLE      ((0x1UL) << TZSEL_ALL_TZ4CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           CLKERRCBC
 *  @access     PWM->TZSEL.bit.CLKERRCBC
 *  @brief      Clock error as a cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_CLKERRCBC_Pos (23)
#define TZSEL_ALL_CLKERRCBC_Msk (0x1UL << TZSEL_ALL_CLKERRCBC_Pos)

typedef enum
{
    TZSEL_BIT_CLKERRCBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_CLKERRCBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_CLKERRCBC;

#define TZSEL_ALL_CLKERRCBC_DISABLE     ((0x0UL) << TZSEL_ALL_CLKERRCBC_Pos)
#define TZSEL_ALL_CLKERRCBC_ENABLE      ((0x1UL) << TZSEL_ALL_CLKERRCBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           DCAEVT1
 *  @access     PWM->TZSEL.bit.DCAEVT1
 *  @brief      Digital compare A event 1 as a cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_DCAEVT1_Pos (24)
#define TZSEL_ALL_DCAEVT1_Msk (0x1UL << TZSEL_ALL_DCAEVT1_Pos)

typedef enum
{
    TZSEL_BIT_DCAEVT1_CBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_DCAEVT1_CBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_DCAEVT1;

#define TZSEL_ALL_DCAEVT1_CBC_DISABLE     ((0x0UL) << TZSEL_ALL_DCAEVT1_Pos)
#define TZSEL_ALL_DCAEVT1_CBC_ENABLE      ((0x1UL) << TZSEL_ALL_DCAEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           DCBEVT1
 *  @access     PWM->TZSEL.bit.DCBEVT1
 *  @brief      Digital compare B event 1 as a cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_DCBEVT1_Pos (25)
#define TZSEL_ALL_DCBEVT1_Msk (0x1UL << TZSEL_ALL_DCBEVT1_Pos)

typedef enum
{
    TZSEL_BIT_DCBEVT1_CBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_DCBEVT1_CBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_DCBEVT1;

#define TZSEL_ALL_DCBEVT1_CBC_DISABLE     ((0x0UL) << TZSEL_ALL_DCBEVT1_Pos)
#define TZSEL_ALL_DCBEVT1_CBC_ENABLE      ((0x1UL) << TZSEL_ALL_DCBEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSEL           DBGCBC
 *  @access     PWM->TZSEL.bit.DBGCBC
 *  @brief      JTAG debug as cycle-by-cycle trip source (ORed)
 */
#define TZSEL_ALL_DBGCBC_Pos (26)
#define TZSEL_ALL_DBGCBC_Msk (0x1UL << TZSEL_ALL_DBGCBC_Pos)

typedef enum
{
    TZSEL_BIT_DBGCBC_DISABLE     = 0,  /*!< Disable   */
    TZSEL_BIT_DBGCBC_ENABLE      = 1,  /*!< Enable    */
} TZSEL_BIT_DBGCBC;

#define TZSEL_ALL_DBGCBC_DISABLE     ((0x0UL) << TZSEL_ALL_DBGCBC_Pos)
#define TZSEL_ALL_DBGCBC_ENABLE      ((0x1UL) << TZSEL_ALL_DBGCBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ0OST
 *  @access     PWM->TZSTS.bit.TZ0OST
 *  @brief      Latched TZ0 one-shot trip event status
 */
#define TZSTS_ALL_TZ0OST_Pos (0)
#define TZSTS_ALL_TZ0OST_Msk (0x1UL << TZSTS_ALL_TZ0OST_Pos)

typedef enum
{
    TZSTS_BIT_TZ0OST_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ0OST_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ0OST;

#define TZSTS_ALL_TZ0OST_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ0OST_Pos)
#define TZSTS_ALL_TZ0OST_OCCUR         ((0x1UL) << TZSTS_ALL_TZ0OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ1OST
 *  @access     PWM->TZSTS.bit.TZ1OST
 *  @brief      Latched TZ1 one-shot trip event status
 */
#define TZSTS_ALL_TZ1OST_Pos (1)
#define TZSTS_ALL_TZ1OST_Msk (0x1UL << TZSTS_ALL_TZ1OST_Pos)

typedef enum
{
    TZSTS_BIT_TZ1OST_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ1OST_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ1OST;

#define TZSTS_ALL_TZ1OST_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ1OST_Pos)
#define TZSTS_ALL_TZ1OST_OCCUR         ((0x1UL) << TZSTS_ALL_TZ1OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ2OST
 *  @access     PWM->TZSTS.bit.TZ2OST
 *  @brief      Latched TZ2 one-shot trip event status
 */
#define TZSTS_ALL_TZ2OST_Pos (2)
#define TZSTS_ALL_TZ2OST_Msk (0x1UL << TZSTS_ALL_TZ2OST_Pos)

typedef enum
{
    TZSTS_BIT_TZ2OST_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ2OST_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ2OST;

#define TZSTS_ALL_TZ2OST_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ2OST_Pos)
#define TZSTS_ALL_TZ2OST_OCCUR         ((0x1UL) << TZSTS_ALL_TZ2OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ3OST
 *  @access     PWM->TZSTS.bit.TZ3OST
 *  @brief      Latched TZ3 one-shot trip event status
 */
#define TZSTS_ALL_TZ3OST_Pos (3)
#define TZSTS_ALL_TZ3OST_Msk (0x1UL << TZSTS_ALL_TZ3OST_Pos)

typedef enum
{
    TZSTS_BIT_TZ3OST_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ3OST_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ3OST;

#define TZSTS_ALL_TZ3OST_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ3OST_Pos)
#define TZSTS_ALL_TZ3OST_OCCUR         ((0x1UL) << TZSTS_ALL_TZ3OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ4OST
 *  @access     PWM->TZSTS.bit.TZ4OST
 *  @brief      Latched TZ4 one-shot trip event status
 */
#define TZSTS_ALL_TZ4OST_Pos (4)
#define TZSTS_ALL_TZ4OST_Msk (0x1UL << TZSTS_ALL_TZ4OST_Pos)

typedef enum
{
    TZSTS_BIT_TZ4OST_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ4OST_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ4OST;

#define TZSTS_ALL_TZ4OST_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ4OST_Pos)
#define TZSTS_ALL_TZ4OST_OCCUR         ((0x1UL) << TZSTS_ALL_TZ4OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           CLKERROST
 *  @access     PWM->TZSTS.bit.CLKERROST
 *  @brief      Latched clock error one-shot trip event status
 */
#define TZSTS_ALL_CLKERROST_Pos (5)
#define TZSTS_ALL_CLKERROST_Msk (0x1UL << TZSTS_ALL_CLKERROST_Pos)

typedef enum
{
    TZSTS_BIT_CLKERROST_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_CLKERROST_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_CLKERROST;

#define TZSTS_ALL_CLKERROST_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_CLKERROST_Pos)
#define TZSTS_ALL_CLKERROST_OCCUR         ((0x1UL) << TZSTS_ALL_CLKERROST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           DCAEVT0
 *  @access     PWM->TZSTS.bit.DCAEVT0
 *  @brief      Latched digital compare A event 0 one-shot trip status
 */
#define TZSTS_ALL_DCAEVT0_Pos (6)
#define TZSTS_ALL_DCAEVT0_Msk (0x1UL << TZSTS_ALL_DCAEVT0_Pos)

typedef enum
{
    TZSTS_BIT_DCAEVT0_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_DCAEVT0_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_DCAEVT0;

#define TZSTS_ALL_DCAEVT0_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_DCAEVT0_Pos)
#define TZSTS_ALL_DCAEVT0_OCCUR         ((0x1UL) << TZSTS_ALL_DCAEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           DCBEVT0
 *  @access     PWM->TZSTS.bit.DCBEVT0
 *  @brief      Latched digital compare B event 0 one-shot trip status
 */
#define TZSTS_ALL_DCBEVT0_Pos (7)
#define TZSTS_ALL_DCBEVT0_Msk (0x1UL << TZSTS_ALL_DCBEVT0_Pos)

typedef enum
{
    TZSTS_BIT_DCBEVT0_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_DCBEVT0_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_DCBEVT0;

#define TZSTS_ALL_DCBEVT0_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_DCBEVT0_Pos)
#define TZSTS_ALL_DCBEVT0_OCCUR         ((0x1UL) << TZSTS_ALL_DCBEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           DBGOST
 *  @access     PWM->TZSTS.bit.DBGOST
 *  @brief      Latched JTAG debug one-shot trip event status
 */
#define TZSTS_ALL_DBGOST_Pos (8)
#define TZSTS_ALL_DBGOST_Msk (0x1UL << TZSTS_ALL_DBGOST_Pos)

typedef enum
{
    TZSTS_BIT_DBGOST_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_DBGOST_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_DBGOST;

#define TZSTS_ALL_DBGOST_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_DBGOST_Pos)
#define TZSTS_ALL_DBGOST_OCCUR         ((0x1UL) << TZSTS_ALL_DBGOST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ0CBC
 *  @access     PWM->TZSTS.bit.TZ0CBC
 *  @brief      Latched TZ0 cycle-by-cycle trip event status
 */
#define TZSTS_ALL_TZ0CBC_Pos (9)
#define TZSTS_ALL_TZ0CBC_Msk (0x1UL << TZSTS_ALL_TZ0CBC_Pos)

typedef enum
{
    TZSTS_BIT_TZ0CBC_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ0CBC_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ0CBC;

#define TZSTS_ALL_TZ0CBC_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ0CBC_Pos)
#define TZSTS_ALL_TZ0CBC_OCCUR         ((0x1UL) << TZSTS_ALL_TZ0CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ1CBC
 *  @access     PWM->TZSTS.bit.TZ1CBC
 *  @brief      Latched TZ1 cycle-by-cycle trip event status
 */
#define TZSTS_ALL_TZ1CBC_Pos (10)
#define TZSTS_ALL_TZ1CBC_Msk (0x1UL << TZSTS_ALL_TZ1CBC_Pos)

typedef enum
{
    TZSTS_BIT_TZ1CBC_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ1CBC_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ1CBC;

#define TZSTS_ALL_TZ1CBC_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ1CBC_Pos)
#define TZSTS_ALL_TZ1CBC_OCCUR         ((0x1UL) << TZSTS_ALL_TZ1CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ2CBC
 *  @access     PWM->TZSTS.bit.TZ2CBC
 *  @brief      Latched TZ2 cycle-by-cycle trip event status
 */
#define TZSTS_ALL_TZ2CBC_Pos (11)
#define TZSTS_ALL_TZ2CBC_Msk (0x1UL << TZSTS_ALL_TZ2CBC_Pos)

typedef enum
{
    TZSTS_BIT_TZ2CBC_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ2CBC_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ2CBC;

#define TZSTS_ALL_TZ2CBC_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ2CBC_Pos)
#define TZSTS_ALL_TZ2CBC_OCCUR         ((0x1UL) << TZSTS_ALL_TZ2CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ3CBC
 *  @access     PWM->TZSTS.bit.TZ3CBC
 *  @brief      Latched TZ3 cycle-by-cycle trip event status
 */
#define TZSTS_ALL_TZ3CBC_Pos (12)
#define TZSTS_ALL_TZ3CBC_Msk (0x1UL << TZSTS_ALL_TZ3CBC_Pos)

typedef enum
{
    TZSTS_BIT_TZ3CBC_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ3CBC_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ3CBC;

#define TZSTS_ALL_TZ3CBC_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ3CBC_Pos)
#define TZSTS_ALL_TZ3CBC_OCCUR         ((0x1UL) << TZSTS_ALL_TZ3CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           TZ4CBC
 *  @access     PWM->TZSTS.bit.TZ4CBC
 *  @brief      Latched TZ4 cycle-by-cycle trip event status
 */
#define TZSTS_ALL_TZ4CBC_Pos (13)
#define TZSTS_ALL_TZ4CBC_Msk (0x1UL << TZSTS_ALL_TZ4CBC_Pos)

typedef enum
{
    TZSTS_BIT_TZ4CBC_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_TZ4CBC_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_TZ4CBC;

#define TZSTS_ALL_TZ4CBC_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_TZ4CBC_Pos)
#define TZSTS_ALL_TZ4CBC_OCCUR         ((0x1UL) << TZSTS_ALL_TZ4CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           CLKERRCBC
 *  @access     PWM->TZSTS.bit.CLKERRCBC
 *  @brief      Latched clock error cycle-by-cycle trip event status
 */
#define TZSTS_ALL_CLKERRCBC_Pos (14)
#define TZSTS_ALL_CLKERRCBC_Msk (0x1UL << TZSTS_ALL_CLKERRCBC_Pos)

typedef enum
{
    TZSTS_BIT_CLKERRCBC_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_CLKERRCBC_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_CLKERRCBC;

#define TZSTS_ALL_CLKERRCBC_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_CLKERRCBC_Pos)
#define TZSTS_ALL_CLKERRCBC_OCCUR         ((0x1UL) << TZSTS_ALL_CLKERRCBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           DCAEVT1
 *  @access     PWM->TZSTS.bit.DCAEVT1
 *  @brief      Latched digital compare A event 1 cycle-by-cycle trip status
 */
#define TZSTS_ALL_DCAEVT1_Pos (15)
#define TZSTS_ALL_DCAEVT1_Msk (0x1UL << TZSTS_ALL_DCAEVT1_Pos)

typedef enum
{
    TZSTS_BIT_DCAEVT1_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_DCAEVT1_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_DCAEVT1;

#define TZSTS_ALL_DCAEVT1_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_DCAEVT1_Pos)
#define TZSTS_ALL_DCAEVT1_OCCUR         ((0x1UL) << TZSTS_ALL_DCAEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           DCBEVT1
 *  @access     PWM->TZSTS.bit.DCBEVT1
 *  @brief      Latched digital compare B event 1 cycle-by-cycle trip status
 */
#define TZSTS_ALL_DCBEVT1_Pos (16)
#define TZSTS_ALL_DCBEVT1_Msk (0x1UL << TZSTS_ALL_DCBEVT1_Pos)

typedef enum
{
    TZSTS_BIT_DCBEVT1_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_DCBEVT1_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_DCBEVT1;

#define TZSTS_ALL_DCBEVT1_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_DCBEVT1_Pos)
#define TZSTS_ALL_DCBEVT1_OCCUR         ((0x1UL) << TZSTS_ALL_DCBEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTS           DBGCBC
 *  @access     PWM->TZSTS.bit.DBGCBC
 *  @brief      Latched JTAG debug cycle-by-cycle trip event status
 */
#define TZSTS_ALL_DBGCBC_Pos (17)
#define TZSTS_ALL_DBGCBC_Msk (0x1UL << TZSTS_ALL_DBGCBC_Pos)

typedef enum
{
    TZSTS_BIT_DBGCBC_NOT_OCCUR     = 0,  /*!< No event has occurred   */
    TZSTS_BIT_DBGCBC_OCCUR         = 1,  /*!< Event occurred          */
} TZSTS_BIT_DBGCBC;

#define TZSTS_ALL_DBGCBC_NOT_OCCUR     ((0x0UL) << TZSTS_ALL_DBGCBC_Pos)
#define TZSTS_ALL_DBGCBC_OCCUR         ((0x1UL) << TZSTS_ALL_DBGCBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ0OST
 *  @access     PWM->TZSTSCLR.bit.TZ0OST
 *  @brief      Latched TZ0 one-shot trip event status clear
 */
#define TZSTSCLR_ALL_TZ0OST_Pos (0)
#define TZSTSCLR_ALL_TZ0OST_Msk (0x1UL << TZSTSCLR_ALL_TZ0OST_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ0OST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ0OST_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ0OST;

#define TZSTSCLR_ALL_TZ0OST_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ0OST_Pos)
#define TZSTSCLR_ALL_TZ0OST_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ0OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ1OST
 *  @access     PWM->TZSTSCLR.bit.TZ1OST
 *  @brief      Latched TZ1 one-shot trip event status clear
 */
#define TZSTSCLR_ALL_TZ1OST_Pos (1)
#define TZSTSCLR_ALL_TZ1OST_Msk (0x1UL << TZSTSCLR_ALL_TZ1OST_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ1OST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ1OST_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ1OST;

#define TZSTSCLR_ALL_TZ1OST_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ1OST_Pos)
#define TZSTSCLR_ALL_TZ1OST_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ1OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ2OST
 *  @access     PWM->TZSTSCLR.bit.TZ2OST
 *  @brief      Latched TZ2 one-shot trip event status clear
 */
#define TZSTSCLR_ALL_TZ2OST_Pos (2)
#define TZSTSCLR_ALL_TZ2OST_Msk (0x1UL << TZSTSCLR_ALL_TZ2OST_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ2OST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ2OST_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ2OST;

#define TZSTSCLR_ALL_TZ2OST_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ2OST_Pos)
#define TZSTSCLR_ALL_TZ2OST_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ2OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ3OST
 *  @access     PWM->TZSTSCLR.bit.TZ3OST
 *  @brief      Latched TZ3 one-shot trip event status clear
 */
#define TZSTSCLR_ALL_TZ3OST_Pos (3)
#define TZSTSCLR_ALL_TZ3OST_Msk (0x1UL << TZSTSCLR_ALL_TZ3OST_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ3OST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ3OST_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ3OST;

#define TZSTSCLR_ALL_TZ3OST_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ3OST_Pos)
#define TZSTSCLR_ALL_TZ3OST_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ3OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ4OST
 *  @access     PWM->TZSTSCLR.bit.TZ4OST
 *  @brief      Latched TZ4 one-shot trip event status clear
 */
#define TZSTSCLR_ALL_TZ4OST_Pos (4)
#define TZSTSCLR_ALL_TZ4OST_Msk (0x1UL << TZSTSCLR_ALL_TZ4OST_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ4OST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ4OST_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ4OST;

#define TZSTSCLR_ALL_TZ4OST_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ4OST_Pos)
#define TZSTSCLR_ALL_TZ4OST_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ4OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        CLKERROST
 *  @access     PWM->TZSTSCLR.bit.CLKERROST
 *  @brief      Latched clock error one-shot trip event status clear
 */
#define TZSTSCLR_ALL_CLKERROST_Pos (5)
#define TZSTSCLR_ALL_CLKERROST_Msk (0x1UL << TZSTSCLR_ALL_CLKERROST_Pos)

typedef enum
{
    TZSTSCLR_BIT_CLKERROST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_CLKERROST_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_CLKERROST;

#define TZSTSCLR_ALL_CLKERROST_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_CLKERROST_Pos)
#define TZSTSCLR_ALL_CLKERROST_CLEAR         ((0x1UL) << TZSTSCLR_ALL_CLKERROST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        DCAEVT0
 *  @access     PWM->TZSTSCLR.bit.DCAEVT0
 *  @brief      Latched digital output A event 0 one-shot trip status clear
 */
#define TZSTSCLR_ALL_DCAEVT0_Pos (6)
#define TZSTSCLR_ALL_DCAEVT0_Msk (0x1UL << TZSTSCLR_ALL_DCAEVT0_Pos)

typedef enum
{
    TZSTSCLR_BIT_DCAEVT0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_DCAEVT0_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_DCAEVT0;

#define TZSTSCLR_ALL_DCAEVT0_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_DCAEVT0_Pos)
#define TZSTSCLR_ALL_DCAEVT0_CLEAR         ((0x1UL) << TZSTSCLR_ALL_DCAEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        DCBEVT0
 *  @access     PWM->TZSTSCLR.bit.DCBEVT0
 *  @brief      Latched digital output B event 0 one-shot trip status clear
 */
#define TZSTSCLR_ALL_DCBEVT0_Pos (7)
#define TZSTSCLR_ALL_DCBEVT0_Msk (0x1UL << TZSTSCLR_ALL_DCBEVT0_Pos)

typedef enum
{
    TZSTSCLR_BIT_DCBEVT0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_DCBEVT0_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_DCBEVT0;

#define TZSTSCLR_ALL_DCBEVT0_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_DCBEVT0_Pos)
#define TZSTSCLR_ALL_DCBEVT0_CLEAR         ((0x1UL) << TZSTSCLR_ALL_DCBEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        DBGOST
 *  @access     PWM->TZSTSCLR.bit.DBGOST
 *  @brief      Latched JTAG debug one-shot trip event status clear
 */
#define TZSTSCLR_ALL_DBGOST_Pos (8)
#define TZSTSCLR_ALL_DBGOST_Msk (0x1UL << TZSTSCLR_ALL_DBGOST_Pos)

typedef enum
{
    TZSTSCLR_BIT_DBGOST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_DBGOST_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_DBGOST;

#define TZSTSCLR_ALL_DBGOST_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_DBGOST_Pos)
#define TZSTSCLR_ALL_DBGOST_CLEAR         ((0x1UL) << TZSTSCLR_ALL_DBGOST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ0CBC
 *  @access     PWM->TZSTSCLR.bit.TZ0CBC
 *  @brief      Latched TZ0 cycle-by-cycle trip event status clear
 */
#define TZSTSCLR_ALL_TZ0CBC_Pos (9)
#define TZSTSCLR_ALL_TZ0CBC_Msk (0x1UL << TZSTSCLR_ALL_TZ0CBC_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ0CBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ0CBC_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ0CBC;

#define TZSTSCLR_ALL_TZ0CBC_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ0CBC_Pos)
#define TZSTSCLR_ALL_TZ0CBC_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ0CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ1CBC
 *  @access     PWM->TZSTSCLR.bit.TZ1CBC
 *  @brief      Latched TZ1 cycle-by-cycle trip event status clear
 */
#define TZSTSCLR_ALL_TZ1CBC_Pos (10)
#define TZSTSCLR_ALL_TZ1CBC_Msk (0x1UL << TZSTSCLR_ALL_TZ1CBC_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ1CBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ1CBC_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ1CBC;

#define TZSTSCLR_ALL_TZ1CBC_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ1CBC_Pos)
#define TZSTSCLR_ALL_TZ1CBC_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ1CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ2CBC
 *  @access     PWM->TZSTSCLR.bit.TZ2CBC
 *  @brief      Latched TZ2 cycle-by-cycle trip event status clear
 */
#define TZSTSCLR_ALL_TZ2CBC_Pos (11)
#define TZSTSCLR_ALL_TZ2CBC_Msk (0x1UL << TZSTSCLR_ALL_TZ2CBC_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ2CBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ2CBC_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ2CBC;

#define TZSTSCLR_ALL_TZ2CBC_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ2CBC_Pos)
#define TZSTSCLR_ALL_TZ2CBC_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ2CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ3CBC
 *  @access     PWM->TZSTSCLR.bit.TZ3CBC
 *  @brief      Latched TZ3 cycle-by-cycle trip event status clear
 */
#define TZSTSCLR_ALL_TZ3CBC_Pos (12)
#define TZSTSCLR_ALL_TZ3CBC_Msk (0x1UL << TZSTSCLR_ALL_TZ3CBC_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ3CBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ3CBC_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ3CBC;

#define TZSTSCLR_ALL_TZ3CBC_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ3CBC_Pos)
#define TZSTSCLR_ALL_TZ3CBC_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ3CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        TZ4CBC
 *  @access     PWM->TZSTSCLR.bit.TZ4CBC
 *  @brief      Latched TZ4 cycle-by-cycle trip event status clear
 */
#define TZSTSCLR_ALL_TZ4CBC_Pos (13)
#define TZSTSCLR_ALL_TZ4CBC_Msk (0x1UL << TZSTSCLR_ALL_TZ4CBC_Pos)

typedef enum
{
    TZSTSCLR_BIT_TZ4CBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_TZ4CBC_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_TZ4CBC;

#define TZSTSCLR_ALL_TZ4CBC_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_TZ4CBC_Pos)
#define TZSTSCLR_ALL_TZ4CBC_CLEAR         ((0x1UL) << TZSTSCLR_ALL_TZ4CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        CLKERRCBC
 *  @access     PWM->TZSTSCLR.bit.CLKERRCBC
 *  @brief      Latched clock error cycle-by-cycle trip event status clear
 */
#define TZSTSCLR_ALL_CLKERRCBC_Pos (14)
#define TZSTSCLR_ALL_CLKERRCBC_Msk (0x1UL << TZSTSCLR_ALL_CLKERRCBC_Pos)

typedef enum
{
    TZSTSCLR_BIT_CLKERRCBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_CLKERRCBC_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_CLKERRCBC;

#define TZSTSCLR_ALL_CLKERRCBC_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_CLKERRCBC_Pos)
#define TZSTSCLR_ALL_CLKERRCBC_CLEAR         ((0x1UL) << TZSTSCLR_ALL_CLKERRCBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        DCAEVT1
 *  @access     PWM->TZSTSCLR.bit.DCAEVT1
 *  @brief      Latched digital compare A event 1 cycle-by-cycle trip status clear
 */
#define TZSTSCLR_ALL_DCAEVT1_Pos (15)
#define TZSTSCLR_ALL_DCAEVT1_Msk (0x1UL << TZSTSCLR_ALL_DCAEVT1_Pos)

typedef enum
{
    TZSTSCLR_BIT_DCAEVT1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_DCAEVT1_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_DCAEVT1;

#define TZSTSCLR_ALL_DCAEVT1_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_DCAEVT1_Pos)
#define TZSTSCLR_ALL_DCAEVT1_CLEAR         ((0x1UL) << TZSTSCLR_ALL_DCAEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        DCBEVT1
 *  @access     PWM->TZSTSCLR.bit.DCBEVT1
 *  @brief      Latched digital compare B event 1 cycle-by-cycle trip status clear
 */
#define TZSTSCLR_ALL_DCBEVT1_Pos (16)
#define TZSTSCLR_ALL_DCBEVT1_Msk (0x1UL << TZSTSCLR_ALL_DCBEVT1_Pos)

typedef enum
{
    TZSTSCLR_BIT_DCBEVT1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_DCBEVT1_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_DCBEVT1;

#define TZSTSCLR_ALL_DCBEVT1_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_DCBEVT1_Pos)
#define TZSTSCLR_ALL_DCBEVT1_CLEAR         ((0x1UL) << TZSTSCLR_ALL_DCBEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZSTSCLR        DBGCBC
 *  @access     PWM->TZSTSCLR.bit.DBGCBC
 *  @brief      Latched JTAG debug cycle-by-cycle trip event status clear
 */
#define TZSTSCLR_ALL_DBGCBC_Pos (17)
#define TZSTSCLR_ALL_DBGCBC_Msk (0x1UL << TZSTSCLR_ALL_DBGCBC_Pos)

typedef enum
{
    TZSTSCLR_BIT_DBGCBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always reads back a 0                       */
    TZSTSCLR_BIT_DBGCBC_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} TZSTSCLR_BIT_DBGCBC;

#define TZSTSCLR_ALL_DBGCBC_NO_EFFECT     ((0x0UL) << TZSTSCLR_ALL_DBGCBC_Pos)
#define TZSTSCLR_ALL_DBGCBC_CLEAR         ((0x1UL) << TZSTSCLR_ALL_DBGCBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZDCSEL         DCAEVT0
 *  @access     PWM->TZDCSEL.bit.DCAEVT0
 *  @brief      Digital compare A event 0 option
 */
#define TZDCSEL_ALL_DCAEVT0_Pos (0)
#define TZDCSEL_ALL_DCAEVT0_Msk (0x7UL << TZDCSEL_ALL_DCAEVT0_Pos)

typedef enum
{
    TZDCSEL_BIT_DCAEVT0_DISABLE                 = 0,  /*!< Event disabled               */
    TZDCSEL_BIT_DCAEVT0_DCAH_X_DCAL_LOW         = 1,  /*!< DCAL=low, DCAH=don't care    */
    TZDCSEL_BIT_DCAEVT0_DCAH_X_DCAL_HIGH        = 2,  /*!< DCAL=high, DCAH=don't care   */
    TZDCSEL_BIT_DCAEVT0_DCAH_LOW_DCAL_X         = 3,  /*!< DCAL=don't care, DCAH=low    */
    TZDCSEL_BIT_DCAEVT0_DCAH_HIGH_DCAL_X        = 4,  /*!< DCAL=don't care, DCAH=high   */
    TZDCSEL_BIT_DCAEVT0_DCAH_HIGH_DCAL_LOW      = 5,  /*!< DCAL=low, DCAH=high          */
    TZDCSEL_BIT_DCAEVT0_DCAH_LOW_DCAL_HIGH      = 6,  /*!< DCAL=high, DCAH=low          */
    TZDCSEL_BIT_DCAEVT0_DCAH_HIGH_DCAL_HIGH     = 7,  /*!< DCAL=high, DCAH=high         */
} TZDCSEL_BIT_DCAEVT0;

#define TZDCSEL_ALL_DCAEVT0_DISABLE                 ((0x0UL) << TZDCSEL_ALL_DCAEVT0_Pos)
#define TZDCSEL_ALL_DCAEVT0_DCAH_X_DCAL_LOW         ((0x1UL) << TZDCSEL_ALL_DCAEVT0_Pos)
#define TZDCSEL_ALL_DCAEVT0_DCAH_X_DCAL_HIGH        ((0x2UL) << TZDCSEL_ALL_DCAEVT0_Pos)
#define TZDCSEL_ALL_DCAEVT0_DCAH_LOW_DCAL_X         ((0x3UL) << TZDCSEL_ALL_DCAEVT0_Pos)
#define TZDCSEL_ALL_DCAEVT0_DCAH_HIGH_DCAL_X        ((0x4UL) << TZDCSEL_ALL_DCAEVT0_Pos)
#define TZDCSEL_ALL_DCAEVT0_DCAH_HIGH_DCAL_LOW      ((0x5UL) << TZDCSEL_ALL_DCAEVT0_Pos)
#define TZDCSEL_ALL_DCAEVT0_DCAH_LOW_DCAL_HIGH      ((0x6UL) << TZDCSEL_ALL_DCAEVT0_Pos)
#define TZDCSEL_ALL_DCAEVT0_DCAH_HIGH_DCAL_HIGH     ((0x7UL) << TZDCSEL_ALL_DCAEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZDCSEL         DCAEVT1
 *  @access     PWM->TZDCSEL.bit.DCAEVT1
 *  @brief      Digital compare A event 1 option
 */
#define TZDCSEL_ALL_DCAEVT1_Pos (3)
#define TZDCSEL_ALL_DCAEVT1_Msk (0x7UL << TZDCSEL_ALL_DCAEVT1_Pos)

typedef enum
{
    TZDCSEL_BIT_DCAEVT1_DISABLE                 = 0,  /*!< Event disabled               */
    TZDCSEL_BIT_DCAEVT1_DCAH_X_DCAL_LOW         = 1,  /*!< DCAL=low, DCAH=don't care    */
    TZDCSEL_BIT_DCAEVT1_DCAH_X_DCAL_HIGH        = 2,  /*!< DCAL=high, DCAH=don't care   */
    TZDCSEL_BIT_DCAEVT1_DCAH_LOW_DCAL_X         = 3,  /*!< DCAL=don't care, DCAH=low    */
    TZDCSEL_BIT_DCAEVT1_DCAH_HIGH_DCAL_X        = 4,  /*!< DCAL=don't care, DCAH=high   */
    TZDCSEL_BIT_DCAEVT1_DCAH_HIGH_DCAL_LOW      = 5,  /*!< DCAL=low, DCAH=high          */
    TZDCSEL_BIT_DCAEVT1_DCAH_LOW_DCAL_HIGH      = 6,  /*!< DCAL=high, DCAH=low          */
    TZDCSEL_BIT_DCAEVT1_DCAH_HIGH_DCAL_HIGH     = 7,  /*!< DCAL=high, DCAH=high         */
} TZDCSEL_BIT_DCAEVT1;

#define TZDCSEL_ALL_DCAEVT1_DISABLE                 ((0x0UL) << TZDCSEL_ALL_DCAEVT1_Pos)
#define TZDCSEL_ALL_DCAEVT1_DCAH_X_DCAL_LOW         ((0x1UL) << TZDCSEL_ALL_DCAEVT1_Pos)
#define TZDCSEL_ALL_DCAEVT1_DCAH_X_DCAL_HIGH        ((0x2UL) << TZDCSEL_ALL_DCAEVT1_Pos)
#define TZDCSEL_ALL_DCAEVT1_DCAH_LOW_DCAL_X         ((0x3UL) << TZDCSEL_ALL_DCAEVT1_Pos)
#define TZDCSEL_ALL_DCAEVT1_DCAH_HIGH_DCAL_X        ((0x4UL) << TZDCSEL_ALL_DCAEVT1_Pos)
#define TZDCSEL_ALL_DCAEVT1_DCAH_HIGH_DCAL_LOW      ((0x5UL) << TZDCSEL_ALL_DCAEVT1_Pos)
#define TZDCSEL_ALL_DCAEVT1_DCAH_LOW_DCAL_HIGH      ((0x6UL) << TZDCSEL_ALL_DCAEVT1_Pos)
#define TZDCSEL_ALL_DCAEVT1_DCAH_HIGH_DCAL_HIGH     ((0x7UL) << TZDCSEL_ALL_DCAEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZDCSEL         DCBEVT0
 *  @access     PWM->TZDCSEL.bit.DCBEVT0
 *  @brief      Digital compare B event 0 option
 */
#define TZDCSEL_ALL_DCBEVT0_Pos (6)
#define TZDCSEL_ALL_DCBEVT0_Msk (0x7UL << TZDCSEL_ALL_DCBEVT0_Pos)

typedef enum
{
    TZDCSEL_BIT_DCBEVT0_DISABLE                 = 0,  /*!< Event disabled               */
    TZDCSEL_BIT_DCBEVT0_DCBH_X_DCBL_LOW         = 1,  /*!< DCBL=low, DCBH=don't care    */
    TZDCSEL_BIT_DCBEVT0_DCBH_X_DCBL_HIGH        = 2,  /*!< DCBL=high, DCBH=don't care   */
    TZDCSEL_BIT_DCBEVT0_DCBH_LOW_DCBL_X         = 3,  /*!< DCBL=don't care, DCBH=low    */
    TZDCSEL_BIT_DCBEVT0_DCBH_HIGH_DCBL_X        = 4,  /*!< DCBL=don't care, DCBH=high   */
    TZDCSEL_BIT_DCBEVT0_DCBH_HIGH_DCBL_LOW      = 5,  /*!< DCBL=low, DCBH=high          */
    TZDCSEL_BIT_DCBEVT0_DCBH_LOW_DCBL_HIGH      = 6,  /*!< DCBL=high, DCBH=low          */
    TZDCSEL_BIT_DCBEVT0_DCBH_HIGH_DCBL_HIGH     = 7,  /*!< DCBL=high, DCBH=high         */
} TZDCSEL_BIT_DCBEVT0;

#define TZDCSEL_ALL_DCBEVT0_DISABLE                 ((0x0UL) << TZDCSEL_ALL_DCBEVT0_Pos)
#define TZDCSEL_ALL_DCBEVT0_DCBH_X_DCBL_LOW         ((0x1UL) << TZDCSEL_ALL_DCBEVT0_Pos)
#define TZDCSEL_ALL_DCBEVT0_DCBH_X_DCBL_HIGH        ((0x2UL) << TZDCSEL_ALL_DCBEVT0_Pos)
#define TZDCSEL_ALL_DCBEVT0_DCBH_LOW_DCBL_X         ((0x3UL) << TZDCSEL_ALL_DCBEVT0_Pos)
#define TZDCSEL_ALL_DCBEVT0_DCBH_HIGH_DCBL_X        ((0x4UL) << TZDCSEL_ALL_DCBEVT0_Pos)
#define TZDCSEL_ALL_DCBEVT0_DCBH_HIGH_DCBL_LOW      ((0x5UL) << TZDCSEL_ALL_DCBEVT0_Pos)
#define TZDCSEL_ALL_DCBEVT0_DCBH_LOW_DCBL_HIGH      ((0x6UL) << TZDCSEL_ALL_DCBEVT0_Pos)
#define TZDCSEL_ALL_DCBEVT0_DCBH_HIGH_DCBL_HIGH     ((0x7UL) << TZDCSEL_ALL_DCBEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZDCSEL         DCBEVT1
 *  @access     PWM->TZDCSEL.bit.DCBEVT1
 *  @brief      Digital compare B event 1 option
 */
#define TZDCSEL_ALL_DCBEVT1_Pos (9)
#define TZDCSEL_ALL_DCBEVT1_Msk (0x7UL << TZDCSEL_ALL_DCBEVT1_Pos)

typedef enum
{
    TZDCSEL_BIT_DCBEVT1_DISABLE                 = 0,  /*!< Event disabled               */
    TZDCSEL_BIT_DCBEVT1_DCBH_X_DCBL_LOW         = 1,  /*!< DCBL=low, DCBH=don't care    */
    TZDCSEL_BIT_DCBEVT1_DCBH_X_DCBL_HIGH        = 2,  /*!< DCBL=high, DCBH=don't care   */
    TZDCSEL_BIT_DCBEVT1_DCBH_LOW_DCBL_X         = 3,  /*!< DCBL=don't care, DCBH=low    */
    TZDCSEL_BIT_DCBEVT1_DCBH_HIGH_DCBL_X        = 4,  /*!< DCBL=don't care, DCBH=high   */
    TZDCSEL_BIT_DCBEVT1_DCBH_HIGH_DCBL_LOW      = 5,  /*!< DCBL=low, DCBH=high          */
    TZDCSEL_BIT_DCBEVT1_DCBH_LOW_DCBL_HIGH      = 6,  /*!< DCBL=high, DCBH=low          */
    TZDCSEL_BIT_DCBEVT1_DCBH_HIGH_DCBL_HIGH     = 7,  /*!< DCBL=high, DCBH=high         */
} TZDCSEL_BIT_DCBEVT1;

#define TZDCSEL_ALL_DCBEVT1_DISABLE                 ((0x0UL) << TZDCSEL_ALL_DCBEVT1_Pos)
#define TZDCSEL_ALL_DCBEVT1_DCBH_X_DCBL_LOW         ((0x1UL) << TZDCSEL_ALL_DCBEVT1_Pos)
#define TZDCSEL_ALL_DCBEVT1_DCBH_X_DCBL_HIGH        ((0x2UL) << TZDCSEL_ALL_DCBEVT1_Pos)
#define TZDCSEL_ALL_DCBEVT1_DCBH_LOW_DCBL_X         ((0x3UL) << TZDCSEL_ALL_DCBEVT1_Pos)
#define TZDCSEL_ALL_DCBEVT1_DCBH_HIGH_DCBL_X        ((0x4UL) << TZDCSEL_ALL_DCBEVT1_Pos)
#define TZDCSEL_ALL_DCBEVT1_DCBH_HIGH_DCBL_LOW      ((0x5UL) << TZDCSEL_ALL_DCBEVT1_Pos)
#define TZDCSEL_ALL_DCBEVT1_DCBH_LOW_DCBL_HIGH      ((0x6UL) << TZDCSEL_ALL_DCBEVT1_Pos)
#define TZDCSEL_ALL_DCBEVT1_DCBH_HIGH_DCBL_HIGH     ((0x7UL) << TZDCSEL_ALL_DCBEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZACTL          TZAU
 *  @access     PWM->TZACTL.bit.TZAU
 *  @brief      Action on output A when a trip event occurs and TBCNT is counting up
 */
#define TZACTL_ALL_TZAU_Pos (0)
#define TZACTL_ALL_TZAU_Msk (0x7UL << TZACTL_ALL_TZAU_Pos)

typedef enum
{
    TZACTL_BIT_TZAU_TRI_STATE      = 0,  /*!< Set output A to high-impedance                                  */
    TZACTL_BIT_TZAU_SET_LOW        = 1,  /*!< Force output A to low state                                     */
    TZACTL_BIT_TZAU_SET_HIGH       = 2,  /*!< Force output A to high state                                    */
    TZACTL_BIT_TZAU_TOGGLE         = 3,  /*!< Force output A to invert current state (high->low, low->high)   */
    TZACTL_BIT_TZAU_DO_NOTHING     = 7,  /*!< Do nothing for output A                                         */
} TZACTL_BIT_TZAU;

#define TZACTL_ALL_TZAU_TRI_STATE      ((0x0UL) << TZACTL_ALL_TZAU_Pos)
#define TZACTL_ALL_TZAU_SET_LOW        ((0x1UL) << TZACTL_ALL_TZAU_Pos)
#define TZACTL_ALL_TZAU_SET_HIGH       ((0x2UL) << TZACTL_ALL_TZAU_Pos)
#define TZACTL_ALL_TZAU_TOGGLE         ((0x3UL) << TZACTL_ALL_TZAU_Pos)
#define TZACTL_ALL_TZAU_DO_NOTHING     ((0x7UL) << TZACTL_ALL_TZAU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZACTL          TZAD
 *  @access     PWM->TZACTL.bit.TZAD
 *  @brief      Action on output A when a trip event occurs and TBCNT is counting down
 */
#define TZACTL_ALL_TZAD_Pos (3)
#define TZACTL_ALL_TZAD_Msk (0x7UL << TZACTL_ALL_TZAD_Pos)

typedef enum
{
    TZACTL_BIT_TZAD_TRI_STATE      = 0,  /*!< Set output A to high-impedance                                  */
    TZACTL_BIT_TZAD_SET_LOW        = 1,  /*!< Force output A to low state                                     */
    TZACTL_BIT_TZAD_SET_HIGH       = 2,  /*!< Force output A to high state                                    */
    TZACTL_BIT_TZAD_TOGGLE         = 3,  /*!< Force output A to invert current state (high->low, low->high)   */
    TZACTL_BIT_TZAD_DO_NOTHING     = 7,  /*!< Do nothing for output A                                         */
} TZACTL_BIT_TZAD;

#define TZACTL_ALL_TZAD_TRI_STATE      ((0x0UL) << TZACTL_ALL_TZAD_Pos)
#define TZACTL_ALL_TZAD_SET_LOW        ((0x1UL) << TZACTL_ALL_TZAD_Pos)
#define TZACTL_ALL_TZAD_SET_HIGH       ((0x2UL) << TZACTL_ALL_TZAD_Pos)
#define TZACTL_ALL_TZAD_TOGGLE         ((0x3UL) << TZACTL_ALL_TZAD_Pos)
#define TZACTL_ALL_TZAD_DO_NOTHING     ((0x7UL) << TZACTL_ALL_TZAD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZACTL          DCAEVT0U
 *  @access     PWM->TZACTL.bit.DCAEVT0U
 *  @brief      Action on output A when a digital compare A event 0 occurs and TBCNT is counting
 *              up
 */
#define TZACTL_ALL_DCAEVT0U_Pos (6)
#define TZACTL_ALL_DCAEVT0U_Msk (0x7UL << TZACTL_ALL_DCAEVT0U_Pos)

typedef enum
{
    TZACTL_BIT_DCAEVT0U_TRI_STATE      = 0,  /*!< Set output A to high-impedance                                  */
    TZACTL_BIT_DCAEVT0U_SET_LOW        = 1,  /*!< Force output A to low state                                     */
    TZACTL_BIT_DCAEVT0U_SET_HIGH       = 2,  /*!< Force output A to high state                                    */
    TZACTL_BIT_DCAEVT0U_TOGGLE         = 3,  /*!< Force output A to invert current state (high->low, low->high)   */
    TZACTL_BIT_DCAEVT0U_DO_NOTHING     = 7,  /*!< Do nothing for output A                                         */
} TZACTL_BIT_DCAEVT0U;

#define TZACTL_ALL_DCAEVT0U_TRI_STATE      ((0x0UL) << TZACTL_ALL_DCAEVT0U_Pos)
#define TZACTL_ALL_DCAEVT0U_SET_LOW        ((0x1UL) << TZACTL_ALL_DCAEVT0U_Pos)
#define TZACTL_ALL_DCAEVT0U_SET_HIGH       ((0x2UL) << TZACTL_ALL_DCAEVT0U_Pos)
#define TZACTL_ALL_DCAEVT0U_TOGGLE         ((0x3UL) << TZACTL_ALL_DCAEVT0U_Pos)
#define TZACTL_ALL_DCAEVT0U_DO_NOTHING     ((0x7UL) << TZACTL_ALL_DCAEVT0U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZACTL          DCAEVT0D
 *  @access     PWM->TZACTL.bit.DCAEVT0D
 *  @brief      Action on output A when a digital compare A event 0 occurs and TBCNT is counting
 *              down
 */
#define TZACTL_ALL_DCAEVT0D_Pos (9)
#define TZACTL_ALL_DCAEVT0D_Msk (0x7UL << TZACTL_ALL_DCAEVT0D_Pos)

typedef enum
{
    TZACTL_BIT_DCAEVT0D_TRI_STATE      = 0,  /*!< Set output A to high-impedance                                  */
    TZACTL_BIT_DCAEVT0D_SET_LOW        = 1,  /*!< Force output A to low state                                     */
    TZACTL_BIT_DCAEVT0D_SET_HIGH       = 2,  /*!< Force output A to high state                                    */
    TZACTL_BIT_DCAEVT0D_TOGGLE         = 3,  /*!< Force output A to invert current state (high->low, low->high)   */
    TZACTL_BIT_DCAEVT0D_DO_NOTHING     = 7,  /*!< Do nothing for output A                                         */
} TZACTL_BIT_DCAEVT0D;

#define TZACTL_ALL_DCAEVT0D_TRI_STATE      ((0x0UL) << TZACTL_ALL_DCAEVT0D_Pos)
#define TZACTL_ALL_DCAEVT0D_SET_LOW        ((0x1UL) << TZACTL_ALL_DCAEVT0D_Pos)
#define TZACTL_ALL_DCAEVT0D_SET_HIGH       ((0x2UL) << TZACTL_ALL_DCAEVT0D_Pos)
#define TZACTL_ALL_DCAEVT0D_TOGGLE         ((0x3UL) << TZACTL_ALL_DCAEVT0D_Pos)
#define TZACTL_ALL_DCAEVT0D_DO_NOTHING     ((0x7UL) << TZACTL_ALL_DCAEVT0D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZACTL          DCAEVT1U
 *  @access     PWM->TZACTL.bit.DCAEVT1U
 *  @brief      Action on output A when a digital compare A event 1 occurs and TBCNT is counting
 *              up
 */
#define TZACTL_ALL_DCAEVT1U_Pos (12)
#define TZACTL_ALL_DCAEVT1U_Msk (0x7UL << TZACTL_ALL_DCAEVT1U_Pos)

typedef enum
{
    TZACTL_BIT_DCAEVT1U_TRI_STATE      = 0,  /*!< Set output A to high-impedance                                  */
    TZACTL_BIT_DCAEVT1U_SET_LOW        = 1,  /*!< Force output A to low state                                     */
    TZACTL_BIT_DCAEVT1U_SET_HIGH       = 2,  /*!< Force output A to high state                                    */
    TZACTL_BIT_DCAEVT1U_TOGGLE         = 3,  /*!< Force output A to invert current state (high->low, low->high)   */
    TZACTL_BIT_DCAEVT1U_DO_NOTHING     = 7,  /*!< Do nothing for output A                                         */
} TZACTL_BIT_DCAEVT1U;

#define TZACTL_ALL_DCAEVT1U_TRI_STATE      ((0x0UL) << TZACTL_ALL_DCAEVT1U_Pos)
#define TZACTL_ALL_DCAEVT1U_SET_LOW        ((0x1UL) << TZACTL_ALL_DCAEVT1U_Pos)
#define TZACTL_ALL_DCAEVT1U_SET_HIGH       ((0x2UL) << TZACTL_ALL_DCAEVT1U_Pos)
#define TZACTL_ALL_DCAEVT1U_TOGGLE         ((0x3UL) << TZACTL_ALL_DCAEVT1U_Pos)
#define TZACTL_ALL_DCAEVT1U_DO_NOTHING     ((0x7UL) << TZACTL_ALL_DCAEVT1U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZACTL          DCAEVT1D
 *  @access     PWM->TZACTL.bit.DCAEVT1D
 *  @brief      Action on output A when a digital compare A event 1 occurs and TBCNT is counting
 *              down
 */
#define TZACTL_ALL_DCAEVT1D_Pos (15)
#define TZACTL_ALL_DCAEVT1D_Msk (0x7UL << TZACTL_ALL_DCAEVT1D_Pos)

typedef enum
{
    TZACTL_BIT_DCAEVT1D_TRI_STATE      = 0,  /*!< Set output A to high-impedance                                  */
    TZACTL_BIT_DCAEVT1D_SET_LOW        = 1,  /*!< Force output A to low state                                     */
    TZACTL_BIT_DCAEVT1D_SET_HIGH       = 2,  /*!< Force output A to high state                                    */
    TZACTL_BIT_DCAEVT1D_TOGGLE         = 3,  /*!< Force output A to invert current state (high->low, low->high)   */
    TZACTL_BIT_DCAEVT1D_DO_NOTHING     = 7,  /*!< Do nothing for output A                                         */
} TZACTL_BIT_DCAEVT1D;

#define TZACTL_ALL_DCAEVT1D_TRI_STATE      ((0x0UL) << TZACTL_ALL_DCAEVT1D_Pos)
#define TZACTL_ALL_DCAEVT1D_SET_LOW        ((0x1UL) << TZACTL_ALL_DCAEVT1D_Pos)
#define TZACTL_ALL_DCAEVT1D_SET_HIGH       ((0x2UL) << TZACTL_ALL_DCAEVT1D_Pos)
#define TZACTL_ALL_DCAEVT1D_TOGGLE         ((0x3UL) << TZACTL_ALL_DCAEVT1D_Pos)
#define TZACTL_ALL_DCAEVT1D_DO_NOTHING     ((0x7UL) << TZACTL_ALL_DCAEVT1D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZBCTL          TZBU
 *  @access     PWM->TZBCTL.bit.TZBU
 *  @brief      Action on output B when a trip event occurs and TBCNT is counting up
 */
#define TZBCTL_ALL_TZBU_Pos (0)
#define TZBCTL_ALL_TZBU_Msk (0x7UL << TZBCTL_ALL_TZBU_Pos)

typedef enum
{
    TZBCTL_BIT_TZBU_TRI_STATE      = 0,  /*!< Set output B to high-impedance                                  */
    TZBCTL_BIT_TZBU_SET_LOW        = 1,  /*!< Force output B to low state                                     */
    TZBCTL_BIT_TZBU_SET_HIGH       = 2,  /*!< Force output B to high state                                    */
    TZBCTL_BIT_TZBU_TOGGLE         = 3,  /*!< Force output B to invert current state (high->low, low->high)   */
    TZBCTL_BIT_TZBU_DO_NOTHING     = 7,  /*!< Do nothing for output B                                         */
} TZBCTL_BIT_TZBU;

#define TZBCTL_ALL_TZBU_TRI_STATE      ((0x0UL) << TZBCTL_ALL_TZBU_Pos)
#define TZBCTL_ALL_TZBU_SET_LOW        ((0x1UL) << TZBCTL_ALL_TZBU_Pos)
#define TZBCTL_ALL_TZBU_SET_HIGH       ((0x2UL) << TZBCTL_ALL_TZBU_Pos)
#define TZBCTL_ALL_TZBU_TOGGLE         ((0x3UL) << TZBCTL_ALL_TZBU_Pos)
#define TZBCTL_ALL_TZBU_DO_NOTHING     ((0x7UL) << TZBCTL_ALL_TZBU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZBCTL          TZBD
 *  @access     PWM->TZBCTL.bit.TZBD
 *  @brief      Action on output B when a trip event occurs and TBCNT is counting down
 */
#define TZBCTL_ALL_TZBD_Pos (3)
#define TZBCTL_ALL_TZBD_Msk (0x7UL << TZBCTL_ALL_TZBD_Pos)

typedef enum
{
    TZBCTL_BIT_TZBD_TRI_STATE      = 0,  /*!< Set output B to high-impedance                                  */
    TZBCTL_BIT_TZBD_SET_LOW        = 1,  /*!< Force output B to low state                                     */
    TZBCTL_BIT_TZBD_SET_HIGH       = 2,  /*!< Force output B to high state                                    */
    TZBCTL_BIT_TZBD_TOGGLE         = 3,  /*!< Force output B to invert current state (high->low, low->high)   */
    TZBCTL_BIT_TZBD_DO_NOTHING     = 7,  /*!< Do nothing for output B                                         */
} TZBCTL_BIT_TZBD;

#define TZBCTL_ALL_TZBD_TRI_STATE      ((0x0UL) << TZBCTL_ALL_TZBD_Pos)
#define TZBCTL_ALL_TZBD_SET_LOW        ((0x1UL) << TZBCTL_ALL_TZBD_Pos)
#define TZBCTL_ALL_TZBD_SET_HIGH       ((0x2UL) << TZBCTL_ALL_TZBD_Pos)
#define TZBCTL_ALL_TZBD_TOGGLE         ((0x3UL) << TZBCTL_ALL_TZBD_Pos)
#define TZBCTL_ALL_TZBD_DO_NOTHING     ((0x7UL) << TZBCTL_ALL_TZBD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZBCTL          DCBEVT0U
 *  @access     PWM->TZBCTL.bit.DCBEVT0U
 *  @brief      Action on output B when a digital compare B event 0 occurs and TBCNT is counting
 *              up
 */
#define TZBCTL_ALL_DCBEVT0U_Pos (6)
#define TZBCTL_ALL_DCBEVT0U_Msk (0x7UL << TZBCTL_ALL_DCBEVT0U_Pos)

typedef enum
{
    TZBCTL_BIT_DCBEVT0U_TRI_STATE      = 0,  /*!< Set output B to high-impedance                                  */
    TZBCTL_BIT_DCBEVT0U_SET_LOW        = 1,  /*!< Force output B to low state                                     */
    TZBCTL_BIT_DCBEVT0U_SET_HIGH       = 2,  /*!< Force output B to high state                                    */
    TZBCTL_BIT_DCBEVT0U_TOGGLE         = 3,  /*!< Force output B to invert current state (high->low, low->high)   */
    TZBCTL_BIT_DCBEVT0U_DO_NOTHING     = 7,  /*!< Do nothing for output B                                         */
} TZBCTL_BIT_DCBEVT0U;

#define TZBCTL_ALL_DCBEVT0U_TRI_STATE      ((0x0UL) << TZBCTL_ALL_DCBEVT0U_Pos)
#define TZBCTL_ALL_DCBEVT0U_SET_LOW        ((0x1UL) << TZBCTL_ALL_DCBEVT0U_Pos)
#define TZBCTL_ALL_DCBEVT0U_SET_HIGH       ((0x2UL) << TZBCTL_ALL_DCBEVT0U_Pos)
#define TZBCTL_ALL_DCBEVT0U_TOGGLE         ((0x3UL) << TZBCTL_ALL_DCBEVT0U_Pos)
#define TZBCTL_ALL_DCBEVT0U_DO_NOTHING     ((0x7UL) << TZBCTL_ALL_DCBEVT0U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZBCTL          DCBEVT0D
 *  @access     PWM->TZBCTL.bit.DCBEVT0D
 *  @brief      Action on output B when a digital compare B event 0 occurs and TBCNT is counting
 *              down
 */
#define TZBCTL_ALL_DCBEVT0D_Pos (9)
#define TZBCTL_ALL_DCBEVT0D_Msk (0x7UL << TZBCTL_ALL_DCBEVT0D_Pos)

typedef enum
{
    TZBCTL_BIT_DCBEVT0D_TRI_STATE      = 0,  /*!< Set output B to high-impedance                                  */
    TZBCTL_BIT_DCBEVT0D_SET_LOW        = 1,  /*!< Force output B to low state                                     */
    TZBCTL_BIT_DCBEVT0D_SET_HIGH       = 2,  /*!< Force output B to high state                                    */
    TZBCTL_BIT_DCBEVT0D_TOGGLE         = 3,  /*!< Force output B to invert current state (high->low, low->high)   */
    TZBCTL_BIT_DCBEVT0D_DO_NOTHING     = 7,  /*!< Do nothing for output B                                         */
} TZBCTL_BIT_DCBEVT0D;

#define TZBCTL_ALL_DCBEVT0D_TRI_STATE      ((0x0UL) << TZBCTL_ALL_DCBEVT0D_Pos)
#define TZBCTL_ALL_DCBEVT0D_SET_LOW        ((0x1UL) << TZBCTL_ALL_DCBEVT0D_Pos)
#define TZBCTL_ALL_DCBEVT0D_SET_HIGH       ((0x2UL) << TZBCTL_ALL_DCBEVT0D_Pos)
#define TZBCTL_ALL_DCBEVT0D_TOGGLE         ((0x3UL) << TZBCTL_ALL_DCBEVT0D_Pos)
#define TZBCTL_ALL_DCBEVT0D_DO_NOTHING     ((0x7UL) << TZBCTL_ALL_DCBEVT0D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZBCTL          DCBEVT1U
 *  @access     PWM->TZBCTL.bit.DCBEVT1U
 *  @brief      Action on output B when a digital compare B event 1 occurs and TBCNT is counting
 *              up
 */
#define TZBCTL_ALL_DCBEVT1U_Pos (12)
#define TZBCTL_ALL_DCBEVT1U_Msk (0x7UL << TZBCTL_ALL_DCBEVT1U_Pos)

typedef enum
{
    TZBCTL_BIT_DCBEVT1U_TRI_STATE      = 0,  /*!< Set output B to high-impedance                                  */
    TZBCTL_BIT_DCBEVT1U_SET_LOW        = 1,  /*!< Force output B to low state                                     */
    TZBCTL_BIT_DCBEVT1U_SET_HIGH       = 2,  /*!< Force output B to high state                                    */
    TZBCTL_BIT_DCBEVT1U_TOGGLE         = 3,  /*!< Force output B to invert current state (high->low, low->high)   */
    TZBCTL_BIT_DCBEVT1U_DO_NOTHING     = 7,  /*!< Do nothing for output B                                         */
} TZBCTL_BIT_DCBEVT1U;

#define TZBCTL_ALL_DCBEVT1U_TRI_STATE      ((0x0UL) << TZBCTL_ALL_DCBEVT1U_Pos)
#define TZBCTL_ALL_DCBEVT1U_SET_LOW        ((0x1UL) << TZBCTL_ALL_DCBEVT1U_Pos)
#define TZBCTL_ALL_DCBEVT1U_SET_HIGH       ((0x2UL) << TZBCTL_ALL_DCBEVT1U_Pos)
#define TZBCTL_ALL_DCBEVT1U_TOGGLE         ((0x3UL) << TZBCTL_ALL_DCBEVT1U_Pos)
#define TZBCTL_ALL_DCBEVT1U_DO_NOTHING     ((0x7UL) << TZBCTL_ALL_DCBEVT1U_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZBCTL          DCBEVT1D
 *  @access     PWM->TZBCTL.bit.DCBEVT1D
 *  @brief      Action on output B when a digital compare B event 1 occurs and TBCNT is counting
 *              down
 */
#define TZBCTL_ALL_DCBEVT1D_Pos (15)
#define TZBCTL_ALL_DCBEVT1D_Msk (0x7UL << TZBCTL_ALL_DCBEVT1D_Pos)

typedef enum
{
    TZBCTL_BIT_DCBEVT1D_TRI_STATE      = 0,  /*!< Set output B to high-impedance                                  */
    TZBCTL_BIT_DCBEVT1D_SET_LOW        = 1,  /*!< Force output B to high state                                    */
    TZBCTL_BIT_DCBEVT1D_SET_HIGH       = 2,  /*!< Force output B to low state                                     */
    TZBCTL_BIT_DCBEVT1D_TOGGLE         = 3,  /*!< Force output B to invert current state (high->low, low->high)   */
    TZBCTL_BIT_DCBEVT1D_DO_NOTHING     = 7,  /*!< Do nothing for output B                                         */
} TZBCTL_BIT_DCBEVT1D;

#define TZBCTL_ALL_DCBEVT1D_TRI_STATE      ((0x0UL) << TZBCTL_ALL_DCBEVT1D_Pos)
#define TZBCTL_ALL_DCBEVT1D_SET_LOW        ((0x1UL) << TZBCTL_ALL_DCBEVT1D_Pos)
#define TZBCTL_ALL_DCBEVT1D_SET_HIGH       ((0x2UL) << TZBCTL_ALL_DCBEVT1D_Pos)
#define TZBCTL_ALL_DCBEVT1D_TOGGLE         ((0x3UL) << TZBCTL_ALL_DCBEVT1D_Pos)
#define TZBCTL_ALL_DCBEVT1D_DO_NOTHING     ((0x7UL) << TZBCTL_ALL_DCBEVT1D_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIF            OST
 *  @access     PWM->TZIF.bit.OST
 *  @brief      Latched one-shot trip event status flag
 */
#define TZIF_ALL_OST_Pos (0)
#define TZIF_ALL_OST_Msk (0x1UL << TZIF_ALL_OST_Pos)

typedef enum
{
    TZIF_BIT_OST_NOT_OCCUR     = 0,  /*!< No one-shot trip event has occurred                                        */
    TZIF_BIT_OST_OCCUR         = 1,  /*!< A one-shot trip event occurred. It is cleared by writing 1 to TZCLR.OST.   */
} TZIF_BIT_OST;

#define TZIF_ALL_OST_NOT_OCCUR     ((0x0UL) << TZIF_ALL_OST_Pos)
#define TZIF_ALL_OST_OCCUR         ((0x1UL) << TZIF_ALL_OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIF            CBC
 *  @access     PWM->TZIF.bit.CBC
 *  @brief      Latched cycle-by-cycle trip event status flag
 */
#define TZIF_ALL_CBC_Pos (1)
#define TZIF_ALL_CBC_Msk (0x1UL << TZIF_ALL_CBC_Pos)

typedef enum
{
    TZIF_BIT_CBC_NOT_OCCUR     = 0,  /*!< No cycle-by-cycle trip event has occurred                                               */
    TZIF_BIT_CBC_OCCUR         = 1,  /*!< A cycle-by-cycle trip event occurred. It will remain set until it is manually cleared  
                                          by wring 1 to TZCLR.CBC. If the cycle-by-cycle trip event is still present when the    
                                          CBC bit is cleared, it will be immediately set again.                                   */
} TZIF_BIT_CBC;

#define TZIF_ALL_CBC_NOT_OCCUR     ((0x0UL) << TZIF_ALL_CBC_Pos)
#define TZIF_ALL_CBC_OCCUR         ((0x1UL) << TZIF_ALL_CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIF            DCAEVT0
 *  @access     PWM->TZIF.bit.DCAEVT0
 *  @brief      Latched digital compare A event 0 status flag
 */
#define TZIF_ALL_DCAEVT0_Pos (2)
#define TZIF_ALL_DCAEVT0_Msk (0x1UL << TZIF_ALL_DCAEVT0_Pos)

typedef enum
{
    TZIF_BIT_DCAEVT0_NOT_OCCUR     = 0,  /*!< DCAEVT0 did not occur                                               */
    TZIF_BIT_DCAEVT0_OCCUR         = 1,  /*!< DCAEVT0 has occurred. It is cleared by writing 1 to TZIC.DCAEVT0.   */
} TZIF_BIT_DCAEVT0;

#define TZIF_ALL_DCAEVT0_NOT_OCCUR     ((0x0UL) << TZIF_ALL_DCAEVT0_Pos)
#define TZIF_ALL_DCAEVT0_OCCUR         ((0x1UL) << TZIF_ALL_DCAEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIF            DCAEVT1
 *  @access     PWM->TZIF.bit.DCAEVT1
 *  @brief      Latched digital compare A event 1 status flag
 */
#define TZIF_ALL_DCAEVT1_Pos (3)
#define TZIF_ALL_DCAEVT1_Msk (0x1UL << TZIF_ALL_DCAEVT1_Pos)

typedef enum
{
    TZIF_BIT_DCAEVT1_NOT_OCCUR     = 0,  /*!< DCAEVT1 did not occur                                               */
    TZIF_BIT_DCAEVT1_OCCUR         = 1,  /*!< DCAEVT1 has occurred. It is cleared by writing 1 to TZIC.DCAEVT1.   */
} TZIF_BIT_DCAEVT1;

#define TZIF_ALL_DCAEVT1_NOT_OCCUR     ((0x0UL) << TZIF_ALL_DCAEVT1_Pos)
#define TZIF_ALL_DCAEVT1_OCCUR         ((0x1UL) << TZIF_ALL_DCAEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIF            DCBEVT0
 *  @access     PWM->TZIF.bit.DCBEVT0
 *  @brief      Latched digital compare B event 0 status flag
 */
#define TZIF_ALL_DCBEVT0_Pos (4)
#define TZIF_ALL_DCBEVT0_Msk (0x1UL << TZIF_ALL_DCBEVT0_Pos)

typedef enum
{
    TZIF_BIT_DCBEVT0_NOT_OCCUR     = 0,  /*!< DCBEVT0 did not occur                                               */
    TZIF_BIT_DCBEVT0_OCCUR         = 1,  /*!< DCBEVT0 has occurred. It is cleared by writing 1 to TZIC.DCBEVT0.   */
} TZIF_BIT_DCBEVT0;

#define TZIF_ALL_DCBEVT0_NOT_OCCUR     ((0x0UL) << TZIF_ALL_DCBEVT0_Pos)
#define TZIF_ALL_DCBEVT0_OCCUR         ((0x1UL) << TZIF_ALL_DCBEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIF            DCBEVT1
 *  @access     PWM->TZIF.bit.DCBEVT1
 *  @brief      Latched digital compare B event 1 status flag
 */
#define TZIF_ALL_DCBEVT1_Pos (5)
#define TZIF_ALL_DCBEVT1_Msk (0x1UL << TZIF_ALL_DCBEVT1_Pos)

typedef enum
{
    TZIF_BIT_DCBEVT1_NOT_OCCUR     = 0,  /*!< DCBEVT1 did not occur                                               */
    TZIF_BIT_DCBEVT1_OCCUR         = 1,  /*!< DCBEVT1 has occurred. It is cleared by writing 1 to TZIC.DCBEVT1.   */
} TZIF_BIT_DCBEVT1;

#define TZIF_ALL_DCBEVT1_NOT_OCCUR     ((0x0UL) << TZIF_ALL_DCBEVT1_Pos)
#define TZIF_ALL_DCBEVT1_OCCUR         ((0x1UL) << TZIF_ALL_DCBEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIF            INT
 *  @access     PWM->TZIF.bit.INT
 *  @brief      Latched trip interrupt status flag
 */
#define TZIF_ALL_INT_Pos (6)
#define TZIF_ALL_INT_Msk (0x1UL << TZIF_ALL_INT_Pos)

typedef enum
{
    TZIF_BIT_INT_NOT_OCCUR     = 0,  /*!< No interrupt has been generated                                                          */
    TZIF_BIT_INT_OCCUR         = 1,  /*!< Trip-zone interrupt was generated.                                                      
                                          No further trip-zone interrupt will be generated until this flag is cleared by writing  
                                          1 to TZIC.INT. If TZIF[5:0]&TZIE is not 0, another interrupt pulse will be generated    
                                          when this flag is cleared.                                                               */
} TZIF_BIT_INT;

#define TZIF_ALL_INT_NOT_OCCUR     ((0x0UL) << TZIF_ALL_INT_Pos)
#define TZIF_ALL_INT_OCCUR         ((0x1UL) << TZIF_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIC            OST
 *  @access     PWM->TZIC.bit.OST
 *  @brief      Clear one-shot trip status flag
 */
#define TZIC_ALL_OST_Pos (0)
#define TZIC_ALL_OST_Msk (0x1UL << TZIC_ALL_OST_Pos)

typedef enum
{
    TZIC_BIT_OST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    TZIC_BIT_OST_CLEAR         = 1,  /*!< Write a 1 clears TZIF.OST                           */
} TZIC_BIT_OST;

#define TZIC_ALL_OST_NO_EFFECT     ((0x0UL) << TZIC_ALL_OST_Pos)
#define TZIC_ALL_OST_CLEAR         ((0x1UL) << TZIC_ALL_OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIC            CBC
 *  @access     PWM->TZIC.bit.CBC
 *  @brief      Clear cycle-by-cycle trip status flag
 */
#define TZIC_ALL_CBC_Pos (1)
#define TZIC_ALL_CBC_Msk (0x1UL << TZIC_ALL_CBC_Pos)

typedef enum
{
    TZIC_BIT_CBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    TZIC_BIT_CBC_CLEAR         = 1,  /*!< Write a 1 clears TZIF.CBC                           */
} TZIC_BIT_CBC;

#define TZIC_ALL_CBC_NO_EFFECT     ((0x0UL) << TZIC_ALL_CBC_Pos)
#define TZIC_ALL_CBC_CLEAR         ((0x1UL) << TZIC_ALL_CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIC            DCAEVT0
 *  @access     PWM->TZIC.bit.DCAEVT0
 *  @brief      Clear digital compare A event 0 status flag
 */
#define TZIC_ALL_DCAEVT0_Pos (2)
#define TZIC_ALL_DCAEVT0_Msk (0x1UL << TZIC_ALL_DCAEVT0_Pos)

typedef enum
{
    TZIC_BIT_DCAEVT0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    TZIC_BIT_DCAEVT0_CLEAR         = 1,  /*!< Write a 1 clears TZIF.DCAEVT0                       */
} TZIC_BIT_DCAEVT0;

#define TZIC_ALL_DCAEVT0_NO_EFFECT     ((0x0UL) << TZIC_ALL_DCAEVT0_Pos)
#define TZIC_ALL_DCAEVT0_CLEAR         ((0x1UL) << TZIC_ALL_DCAEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIC            DCAEVT1
 *  @access     PWM->TZIC.bit.DCAEVT1
 *  @brief      Clear digital compare A event 1 status flag
 */
#define TZIC_ALL_DCAEVT1_Pos (3)
#define TZIC_ALL_DCAEVT1_Msk (0x1UL << TZIC_ALL_DCAEVT1_Pos)

typedef enum
{
    TZIC_BIT_DCAEVT1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    TZIC_BIT_DCAEVT1_CLEAR         = 1,  /*!< Write a 1 clears TZIF.DCAEVT1                       */
} TZIC_BIT_DCAEVT1;

#define TZIC_ALL_DCAEVT1_NO_EFFECT     ((0x0UL) << TZIC_ALL_DCAEVT1_Pos)
#define TZIC_ALL_DCAEVT1_CLEAR         ((0x1UL) << TZIC_ALL_DCAEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIC            DCBEVT0
 *  @access     PWM->TZIC.bit.DCBEVT0
 *  @brief      Clear digital compare B event 0 status flag
 */
#define TZIC_ALL_DCBEVT0_Pos (4)
#define TZIC_ALL_DCBEVT0_Msk (0x1UL << TZIC_ALL_DCBEVT0_Pos)

typedef enum
{
    TZIC_BIT_DCBEVT0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    TZIC_BIT_DCBEVT0_CLEAR         = 1,  /*!< Write a 1 clears TZIF.DCBEVT0                       */
} TZIC_BIT_DCBEVT0;

#define TZIC_ALL_DCBEVT0_NO_EFFECT     ((0x0UL) << TZIC_ALL_DCBEVT0_Pos)
#define TZIC_ALL_DCBEVT0_CLEAR         ((0x1UL) << TZIC_ALL_DCBEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIC            DCBEVT1
 *  @access     PWM->TZIC.bit.DCBEVT1
 *  @brief      Clear digital compare B event 1 status flag
 */
#define TZIC_ALL_DCBEVT1_Pos (5)
#define TZIC_ALL_DCBEVT1_Msk (0x1UL << TZIC_ALL_DCBEVT1_Pos)

typedef enum
{
    TZIC_BIT_DCBEVT1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    TZIC_BIT_DCBEVT1_CLEAR         = 1,  /*!< Write a 1 clears TZIF.DCBEVT1                       */
} TZIC_BIT_DCBEVT1;

#define TZIC_ALL_DCBEVT1_NO_EFFECT     ((0x0UL) << TZIC_ALL_DCBEVT1_Pos)
#define TZIC_ALL_DCBEVT1_CLEAR         ((0x1UL) << TZIC_ALL_DCBEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIC            INT
 *  @access     PWM->TZIC.bit.INT
 *  @brief      Clear global interrupt status flag
 */
#define TZIC_ALL_INT_Pos (6)
#define TZIC_ALL_INT_Msk (0x1UL << TZIC_ALL_INT_Pos)

typedef enum
{
    TZIC_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    TZIC_BIT_INT_CLEAR         = 1,  /*!< Write a 1 clears TZIF.INT and TZ interrupt          */
} TZIC_BIT_INT;

#define TZIC_ALL_INT_NO_EFFECT     ((0x0UL) << TZIC_ALL_INT_Pos)
#define TZIC_ALL_INT_CLEAR         ((0x1UL) << TZIC_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIC            CBCCLRMODE
 *  @access     PWM->TZIC.bit.CBCCLRMODE
 *  @brief      Latched CBC trip status clear mode
 */
#define TZIC_ALL_CBCCLRMODE_Pos (7)
#define TZIC_ALL_CBCCLRMODE_Msk (0x3UL << TZIC_ALL_CBCCLRMODE_Pos)

typedef enum
{
    TZIC_BIT_CBCCLRMODE_CLEAR_ON_ZERO            = 0,  /*!< Clear CBC trip on TBCNT=0                       */
    TZIC_BIT_CBCCLRMODE_CLEAR_ON_PERIOD          = 1,  /*!< Clear CBC trip on TBCNT=TBPRD                   */
    TZIC_BIT_CBCCLRMODE_CLEAR_ON_ZERO_PERIOD     = 2,  /*!< Clear CBC trip on TBCNT=0 or TBCNT=TBPRD        */
    TZIC_BIT_CBCCLRMODE_CLEAR_DISABLE            = 3,  /*!< Clear disabled. i.e. Never clear the CBC trip   */
} TZIC_BIT_CBCCLRMODE;

#define TZIC_ALL_CBCCLRMODE_CLEAR_ON_ZERO            ((0x0UL) << TZIC_ALL_CBCCLRMODE_Pos)
#define TZIC_ALL_CBCCLRMODE_CLEAR_ON_PERIOD          ((0x1UL) << TZIC_ALL_CBCCLRMODE_Pos)
#define TZIC_ALL_CBCCLRMODE_CLEAR_ON_ZERO_PERIOD     ((0x2UL) << TZIC_ALL_CBCCLRMODE_Pos)
#define TZIC_ALL_CBCCLRMODE_CLEAR_DISABLE            ((0x3UL) << TZIC_ALL_CBCCLRMODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIE            OST
 *  @access     PWM->TZIE.bit.OST
 *  @brief      One-shot trip-zone interrupt enable
 */
#define TZIE_ALL_OST_Pos (0)
#define TZIE_ALL_OST_Msk (0x1UL << TZIE_ALL_OST_Pos)

typedef enum
{
    TZIE_BIT_OST_DISABLE     = 0,  /*!< Disable   */
    TZIE_BIT_OST_ENABLE      = 1,  /*!< Enable    */
} TZIE_BIT_OST;

#define TZIE_ALL_OST_DISABLE     ((0x0UL) << TZIE_ALL_OST_Pos)
#define TZIE_ALL_OST_ENABLE      ((0x1UL) << TZIE_ALL_OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIE            CBC
 *  @access     PWM->TZIE.bit.CBC
 *  @brief      Cycle-by-cycle trip-zone interrupt enable
 */
#define TZIE_ALL_CBC_Pos (1)
#define TZIE_ALL_CBC_Msk (0x1UL << TZIE_ALL_CBC_Pos)

typedef enum
{
    TZIE_BIT_CBC_DISABLE     = 0,  /*!< Disable   */
    TZIE_BIT_CBC_ENABLE      = 1,  /*!< Enable    */
} TZIE_BIT_CBC;

#define TZIE_ALL_CBC_DISABLE     ((0x0UL) << TZIE_ALL_CBC_Pos)
#define TZIE_ALL_CBC_ENABLE      ((0x1UL) << TZIE_ALL_CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIE            DCAEVT0
 *  @access     PWM->TZIE.bit.DCAEVT0
 *  @brief      Digital compare A event 0 interrupt enable
 */
#define TZIE_ALL_DCAEVT0_Pos (2)
#define TZIE_ALL_DCAEVT0_Msk (0x1UL << TZIE_ALL_DCAEVT0_Pos)

typedef enum
{
    TZIE_BIT_DCAEVT0_DISABLE     = 0,  /*!< Disable   */
    TZIE_BIT_DCAEVT0_ENABLE      = 1,  /*!< Enable    */
} TZIE_BIT_DCAEVT0;

#define TZIE_ALL_DCAEVT0_DISABLE     ((0x0UL) << TZIE_ALL_DCAEVT0_Pos)
#define TZIE_ALL_DCAEVT0_ENABLE      ((0x1UL) << TZIE_ALL_DCAEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIE            DCAEVT1
 *  @access     PWM->TZIE.bit.DCAEVT1
 *  @brief      Digital compare A event 1 interrupt enable
 */
#define TZIE_ALL_DCAEVT1_Pos (3)
#define TZIE_ALL_DCAEVT1_Msk (0x1UL << TZIE_ALL_DCAEVT1_Pos)

typedef enum
{
    TZIE_BIT_DCAEVT1_DISABLE     = 0,  /*!< Disable   */
    TZIE_BIT_DCAEVT1_ENABLE      = 1,  /*!< Enable    */
} TZIE_BIT_DCAEVT1;

#define TZIE_ALL_DCAEVT1_DISABLE     ((0x0UL) << TZIE_ALL_DCAEVT1_Pos)
#define TZIE_ALL_DCAEVT1_ENABLE      ((0x1UL) << TZIE_ALL_DCAEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIE            DCBEVT0
 *  @access     PWM->TZIE.bit.DCBEVT0
 *  @brief      Digital compare B event 0 interrupt enable
 */
#define TZIE_ALL_DCBEVT0_Pos (4)
#define TZIE_ALL_DCBEVT0_Msk (0x1UL << TZIE_ALL_DCBEVT0_Pos)

typedef enum
{
    TZIE_BIT_DCBEVT0_DISABLE     = 0,  /*!< Disable   */
    TZIE_BIT_DCBEVT0_ENABLE      = 1,  /*!< Enable    */
} TZIE_BIT_DCBEVT0;

#define TZIE_ALL_DCBEVT0_DISABLE     ((0x0UL) << TZIE_ALL_DCBEVT0_Pos)
#define TZIE_ALL_DCBEVT0_ENABLE      ((0x1UL) << TZIE_ALL_DCBEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZIE            DCBEVT1
 *  @access     PWM->TZIE.bit.DCBEVT1
 *  @brief      Digital compare B event 1 interrupt enable
 */
#define TZIE_ALL_DCBEVT1_Pos (5)
#define TZIE_ALL_DCBEVT1_Msk (0x1UL << TZIE_ALL_DCBEVT1_Pos)

typedef enum
{
    TZIE_BIT_DCBEVT1_DISABLE     = 0,  /*!< Disable   */
    TZIE_BIT_DCBEVT1_ENABLE      = 1,  /*!< Enable    */
} TZIE_BIT_DCBEVT1;

#define TZIE_ALL_DCBEVT1_DISABLE     ((0x0UL) << TZIE_ALL_DCBEVT1_Pos)
#define TZIE_ALL_DCBEVT1_ENABLE      ((0x1UL) << TZIE_ALL_DCBEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZFRC           OST
 *  @access     PWM->TZFRC.bit.OST
 *  @brief      Software force a one-shot trip event
 */
#define TZFRC_ALL_OST_Pos (0)
#define TZFRC_ALL_OST_Msk (0x1UL << TZFRC_ALL_OST_Pos)

typedef enum
{
    TZFRC_BIT_OST_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0          */
    TZFRC_BIT_OST_FORCE         = 1,  /*!< Write a 1 forces a one-shot trip event and sets TZIF.OST   */
} TZFRC_BIT_OST;

#define TZFRC_ALL_OST_NO_EFFECT     ((0x0UL) << TZFRC_ALL_OST_Pos)
#define TZFRC_ALL_OST_FORCE         ((0x1UL) << TZFRC_ALL_OST_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZFRC           CBC
 *  @access     PWM->TZFRC.bit.CBC
 *  @brief      Software force a cycle-by-cycle trip event
 */
#define TZFRC_ALL_CBC_Pos (1)
#define TZFRC_ALL_CBC_Msk (0x1UL << TZFRC_ALL_CBC_Pos)

typedef enum
{
    TZFRC_BIT_CBC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0                */
    TZFRC_BIT_CBC_FORCE         = 1,  /*!< Write a 1 forces a cycle-by-cycle trip event and sets TZIF.CBC   */
} TZFRC_BIT_CBC;

#define TZFRC_ALL_CBC_NO_EFFECT     ((0x0UL) << TZFRC_ALL_CBC_Pos)
#define TZFRC_ALL_CBC_FORCE         ((0x1UL) << TZFRC_ALL_CBC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZFRC           DCAEVT0
 *  @access     PWM->TZFRC.bit.DCAEVT0
 *  @brief      Software force a digital compare A event 0
 */
#define TZFRC_ALL_DCAEVT0_Pos (2)
#define TZFRC_ALL_DCAEVT0_Msk (0x1UL << TZFRC_ALL_DCAEVT0_Pos)

typedef enum
{
    TZFRC_BIT_DCAEVT0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0                    */
    TZFRC_BIT_DCAEVT0_FORCE         = 1,  /*!< Write a 1 forces a digital compare A event 0 and sets TZIF.DCAEVT0   */
} TZFRC_BIT_DCAEVT0;

#define TZFRC_ALL_DCAEVT0_NO_EFFECT     ((0x0UL) << TZFRC_ALL_DCAEVT0_Pos)
#define TZFRC_ALL_DCAEVT0_FORCE         ((0x1UL) << TZFRC_ALL_DCAEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZFRC           DCAEVT1
 *  @access     PWM->TZFRC.bit.DCAEVT1
 *  @brief      Software force a digital compare A event 1
 */
#define TZFRC_ALL_DCAEVT1_Pos (3)
#define TZFRC_ALL_DCAEVT1_Msk (0x1UL << TZFRC_ALL_DCAEVT1_Pos)

typedef enum
{
    TZFRC_BIT_DCAEVT1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0                    */
    TZFRC_BIT_DCAEVT1_FORCE         = 1,  /*!< Write a 1 forces a digital compare A event 1 and sets TZIF.DCAEVT1   */
} TZFRC_BIT_DCAEVT1;

#define TZFRC_ALL_DCAEVT1_NO_EFFECT     ((0x0UL) << TZFRC_ALL_DCAEVT1_Pos)
#define TZFRC_ALL_DCAEVT1_FORCE         ((0x1UL) << TZFRC_ALL_DCAEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZFRC           DCBEVT0
 *  @access     PWM->TZFRC.bit.DCBEVT0
 *  @brief      Software force a digital compare B event 0
 */
#define TZFRC_ALL_DCBEVT0_Pos (4)
#define TZFRC_ALL_DCBEVT0_Msk (0x1UL << TZFRC_ALL_DCBEVT0_Pos)

typedef enum
{
    TZFRC_BIT_DCBEVT0_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0                    */
    TZFRC_BIT_DCBEVT0_FORCE         = 1,  /*!< Write a 1 forces a digital compare B event 0 and sets TZIF.DCBEVT0   */
} TZFRC_BIT_DCBEVT0;

#define TZFRC_ALL_DCBEVT0_NO_EFFECT     ((0x0UL) << TZFRC_ALL_DCBEVT0_Pos)
#define TZFRC_ALL_DCBEVT0_FORCE         ((0x1UL) << TZFRC_ALL_DCBEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             TZFRC           DCBEVT1
 *  @access     PWM->TZFRC.bit.DCBEVT1
 *  @brief      Software force a digital compare B event 1
 */
#define TZFRC_ALL_DCBEVT1_Pos (5)
#define TZFRC_ALL_DCBEVT1_Msk (0x1UL << TZFRC_ALL_DCBEVT1_Pos)

typedef enum
{
    TZFRC_BIT_DCBEVT1_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0                    */
    TZFRC_BIT_DCBEVT1_FORCE         = 1,  /*!< Write a 1 forces a digital compare B event 1 and sets TZIF.DCBEVT1   */
} TZFRC_BIT_DCBEVT1;

#define TZFRC_ALL_DCBEVT1_NO_EFFECT     ((0x0UL) << TZFRC_ALL_DCBEVT1_Pos)
#define TZFRC_ALL_DCBEVT1_FORCE         ((0x1UL) << TZFRC_ALL_DCBEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     TZ0
 *  @access     PWM->DCALTRIPSEL.bit.TZ0
 *  @brief      Enable TZ0 as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_TZ0_Pos (0)
#define DCALTRIPSEL_ALL_TZ0_Msk (0x1UL << DCALTRIPSEL_ALL_TZ0_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_TZ0_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_TZ0_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_TZ0;

#define DCALTRIPSEL_ALL_TZ0_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_TZ0_Pos)
#define DCALTRIPSEL_ALL_TZ0_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_TZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     TZ1
 *  @access     PWM->DCALTRIPSEL.bit.TZ1
 *  @brief      Enable TZ1 as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_TZ1_Pos (1)
#define DCALTRIPSEL_ALL_TZ1_Msk (0x1UL << DCALTRIPSEL_ALL_TZ1_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_TZ1_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_TZ1_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_TZ1;

#define DCALTRIPSEL_ALL_TZ1_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_TZ1_Pos)
#define DCALTRIPSEL_ALL_TZ1_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_TZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     TZ2
 *  @access     PWM->DCALTRIPSEL.bit.TZ2
 *  @brief      Enable TZ2 as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_TZ2_Pos (2)
#define DCALTRIPSEL_ALL_TZ2_Msk (0x1UL << DCALTRIPSEL_ALL_TZ2_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_TZ2_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_TZ2_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_TZ2;

#define DCALTRIPSEL_ALL_TZ2_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_TZ2_Pos)
#define DCALTRIPSEL_ALL_TZ2_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_TZ2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     TZ3
 *  @access     PWM->DCALTRIPSEL.bit.TZ3
 *  @brief      Enable TZ3 as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_TZ3_Pos (3)
#define DCALTRIPSEL_ALL_TZ3_Msk (0x1UL << DCALTRIPSEL_ALL_TZ3_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_TZ3_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_TZ3_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_TZ3;

#define DCALTRIPSEL_ALL_TZ3_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_TZ3_Pos)
#define DCALTRIPSEL_ALL_TZ3_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_TZ3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     TZ4
 *  @access     PWM->DCALTRIPSEL.bit.TZ4
 *  @brief      Enable TZ4 as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_TZ4_Pos (4)
#define DCALTRIPSEL_ALL_TZ4_Msk (0x1UL << DCALTRIPSEL_ALL_TZ4_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_TZ4_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_TZ4_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_TZ4;

#define DCALTRIPSEL_ALL_TZ4_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_TZ4_Pos)
#define DCALTRIPSEL_ALL_TZ4_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_TZ4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     EPWRTZ0
 *  @access     PWM->DCALTRIPSEL.bit.EPWRTZ0
 *  @brief      Enable EPWRTZ0 as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_EPWRTZ0_Pos (5)
#define DCALTRIPSEL_ALL_EPWRTZ0_Msk (0x1UL << DCALTRIPSEL_ALL_EPWRTZ0_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_EPWRTZ0_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_EPWRTZ0_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_EPWRTZ0;

#define DCALTRIPSEL_ALL_EPWRTZ0_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_EPWRTZ0_Pos)
#define DCALTRIPSEL_ALL_EPWRTZ0_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_EPWRTZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     EPWRTZ1
 *  @access     PWM->DCALTRIPSEL.bit.EPWRTZ1
 *  @brief      Enable EPWRTZ1 as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_EPWRTZ1_Pos (6)
#define DCALTRIPSEL_ALL_EPWRTZ1_Msk (0x1UL << DCALTRIPSEL_ALL_EPWRTZ1_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_EPWRTZ1_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_EPWRTZ1_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_EPWRTZ1;

#define DCALTRIPSEL_ALL_EPWRTZ1_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_EPWRTZ1_Pos)
#define DCALTRIPSEL_ALL_EPWRTZ1_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_EPWRTZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     ADCPPU0TZ
 *  @access     PWM->DCALTRIPSEL.bit.ADCPPU0TZ
 *  @brief      Enable ADCPPU0TZ as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_ADCPPU0TZ_Pos (8)
#define DCALTRIPSEL_ALL_ADCPPU0TZ_Msk (0x1UL << DCALTRIPSEL_ALL_ADCPPU0TZ_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_ADCPPU0TZ_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_ADCPPU0TZ_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_ADCPPU0TZ;

#define DCALTRIPSEL_ALL_ADCPPU0TZ_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_ADCPPU0TZ_Pos)
#define DCALTRIPSEL_ALL_ADCPPU0TZ_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_ADCPPU0TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     ADCPPU1TZ
 *  @access     PWM->DCALTRIPSEL.bit.ADCPPU1TZ
 *  @brief      Enable ADCPPU1TZ as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_ADCPPU1TZ_Pos (9)
#define DCALTRIPSEL_ALL_ADCPPU1TZ_Msk (0x1UL << DCALTRIPSEL_ALL_ADCPPU1TZ_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_ADCPPU1TZ_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_ADCPPU1TZ_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_ADCPPU1TZ;

#define DCALTRIPSEL_ALL_ADCPPU1TZ_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_ADCPPU1TZ_Pos)
#define DCALTRIPSEL_ALL_ADCPPU1TZ_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_ADCPPU1TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     ADCPPU2TZ
 *  @access     PWM->DCALTRIPSEL.bit.ADCPPU2TZ
 *  @brief      Enable ADCPPU2TZ as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_ADCPPU2TZ_Pos (10)
#define DCALTRIPSEL_ALL_ADCPPU2TZ_Msk (0x1UL << DCALTRIPSEL_ALL_ADCPPU2TZ_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_ADCPPU2TZ_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_ADCPPU2TZ_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_ADCPPU2TZ;

#define DCALTRIPSEL_ALL_ADCPPU2TZ_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_ADCPPU2TZ_Pos)
#define DCALTRIPSEL_ALL_ADCPPU2TZ_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_ADCPPU2TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     ADCPPU3TZ
 *  @access     PWM->DCALTRIPSEL.bit.ADCPPU3TZ
 *  @brief      Enable ADCPPU3TZ as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_ADCPPU3TZ_Pos (11)
#define DCALTRIPSEL_ALL_ADCPPU3TZ_Msk (0x1UL << DCALTRIPSEL_ALL_ADCPPU3TZ_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_ADCPPU3TZ_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_ADCPPU3TZ_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_ADCPPU3TZ;

#define DCALTRIPSEL_ALL_ADCPPU3TZ_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_ADCPPU3TZ_Pos)
#define DCALTRIPSEL_ALL_ADCPPU3TZ_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_ADCPPU3TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     ADCPPU4TZ
 *  @access     PWM->DCALTRIPSEL.bit.ADCPPU4TZ
 *  @brief      Enable ADCPPU4TZ as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_ADCPPU4TZ_Pos (12)
#define DCALTRIPSEL_ALL_ADCPPU4TZ_Msk (0x1UL << DCALTRIPSEL_ALL_ADCPPU4TZ_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_ADCPPU4TZ_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_ADCPPU4TZ_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_ADCPPU4TZ;

#define DCALTRIPSEL_ALL_ADCPPU4TZ_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_ADCPPU4TZ_Pos)
#define DCALTRIPSEL_ALL_ADCPPU4TZ_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_ADCPPU4TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     ADCPPU5TZ
 *  @access     PWM->DCALTRIPSEL.bit.ADCPPU5TZ
 *  @brief      Enable ADCPPU5TZ as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_ADCPPU5TZ_Pos (13)
#define DCALTRIPSEL_ALL_ADCPPU5TZ_Msk (0x1UL << DCALTRIPSEL_ALL_ADCPPU5TZ_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_ADCPPU5TZ_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_ADCPPU5TZ_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_ADCPPU5TZ;

#define DCALTRIPSEL_ALL_ADCPPU5TZ_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_ADCPPU5TZ_Pos)
#define DCALTRIPSEL_ALL_ADCPPU5TZ_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_ADCPPU5TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP0L
 *  @access     PWM->DCALTRIPSEL.bit.COMP0L
 *  @brief      Enable COMP0L as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP0L_Pos (16)
#define DCALTRIPSEL_ALL_COMP0L_Msk (0x1UL << DCALTRIPSEL_ALL_COMP0L_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP0L_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP0L_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP0L;

#define DCALTRIPSEL_ALL_COMP0L_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP0L_Pos)
#define DCALTRIPSEL_ALL_COMP0L_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP0L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP0H
 *  @access     PWM->DCALTRIPSEL.bit.COMP0H
 *  @brief      Enable COMP0H as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP0H_Pos (17)
#define DCALTRIPSEL_ALL_COMP0H_Msk (0x1UL << DCALTRIPSEL_ALL_COMP0H_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP0H_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP0H_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP0H;

#define DCALTRIPSEL_ALL_COMP0H_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP0H_Pos)
#define DCALTRIPSEL_ALL_COMP0H_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP0H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP1L
 *  @access     PWM->DCALTRIPSEL.bit.COMP1L
 *  @brief      Enable COMP1L as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP1L_Pos (18)
#define DCALTRIPSEL_ALL_COMP1L_Msk (0x1UL << DCALTRIPSEL_ALL_COMP1L_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP1L_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP1L_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP1L;

#define DCALTRIPSEL_ALL_COMP1L_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP1L_Pos)
#define DCALTRIPSEL_ALL_COMP1L_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP1L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP1H
 *  @access     PWM->DCALTRIPSEL.bit.COMP1H
 *  @brief      Enable COMP1H as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP1H_Pos (19)
#define DCALTRIPSEL_ALL_COMP1H_Msk (0x1UL << DCALTRIPSEL_ALL_COMP1H_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP1H_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP1H_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP1H;

#define DCALTRIPSEL_ALL_COMP1H_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP1H_Pos)
#define DCALTRIPSEL_ALL_COMP1H_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP1H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP2L
 *  @access     PWM->DCALTRIPSEL.bit.COMP2L
 *  @brief      Enable COMP2L as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP2L_Pos (20)
#define DCALTRIPSEL_ALL_COMP2L_Msk (0x1UL << DCALTRIPSEL_ALL_COMP2L_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP2L_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP2L_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP2L;

#define DCALTRIPSEL_ALL_COMP2L_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP2L_Pos)
#define DCALTRIPSEL_ALL_COMP2L_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP2L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP2H
 *  @access     PWM->DCALTRIPSEL.bit.COMP2H
 *  @brief      Enable COMP2H as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP2H_Pos (21)
#define DCALTRIPSEL_ALL_COMP2H_Msk (0x1UL << DCALTRIPSEL_ALL_COMP2H_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP2H_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP2H_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP2H;

#define DCALTRIPSEL_ALL_COMP2H_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP2H_Pos)
#define DCALTRIPSEL_ALL_COMP2H_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP2H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP3L
 *  @access     PWM->DCALTRIPSEL.bit.COMP3L
 *  @brief      Enable COMP3L as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP3L_Pos (22)
#define DCALTRIPSEL_ALL_COMP3L_Msk (0x1UL << DCALTRIPSEL_ALL_COMP3L_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP3L_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP3L_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP3L;

#define DCALTRIPSEL_ALL_COMP3L_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP3L_Pos)
#define DCALTRIPSEL_ALL_COMP3L_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP3L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP3H
 *  @access     PWM->DCALTRIPSEL.bit.COMP3H
 *  @brief      Enable COMP3H as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP3H_Pos (23)
#define DCALTRIPSEL_ALL_COMP3H_Msk (0x1UL << DCALTRIPSEL_ALL_COMP3H_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP3H_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP3H_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP3H;

#define DCALTRIPSEL_ALL_COMP3H_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP3H_Pos)
#define DCALTRIPSEL_ALL_COMP3H_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP3H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP4L
 *  @access     PWM->DCALTRIPSEL.bit.COMP4L
 *  @brief      Enable COMP4L as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP4L_Pos (24)
#define DCALTRIPSEL_ALL_COMP4L_Msk (0x1UL << DCALTRIPSEL_ALL_COMP4L_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP4L_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP4L_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP4L;

#define DCALTRIPSEL_ALL_COMP4L_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP4L_Pos)
#define DCALTRIPSEL_ALL_COMP4L_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP4L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCALTRIPSEL     COMP4H
 *  @access     PWM->DCALTRIPSEL.bit.COMP4H
 *  @brief      Enable COMP4H as DCAL trip event (ORed)
 */
#define DCALTRIPSEL_ALL_COMP4H_Pos (25)
#define DCALTRIPSEL_ALL_COMP4H_Msk (0x1UL << DCALTRIPSEL_ALL_COMP4H_Pos)

typedef enum
{
    DCALTRIPSEL_BIT_COMP4H_DISABLE     = 0,  /*!< Disable   */
    DCALTRIPSEL_BIT_COMP4H_ENABLE      = 1,  /*!< Enable    */
} DCALTRIPSEL_BIT_COMP4H;

#define DCALTRIPSEL_ALL_COMP4H_DISABLE     ((0x0UL) << DCALTRIPSEL_ALL_COMP4H_Pos)
#define DCALTRIPSEL_ALL_COMP4H_ENABLE      ((0x1UL) << DCALTRIPSEL_ALL_COMP4H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     TZ0
 *  @access     PWM->DCAHTRIPSEL.bit.TZ0
 *  @brief      Enable TZ0 as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_TZ0_Pos (0)
#define DCAHTRIPSEL_ALL_TZ0_Msk (0x1UL << DCAHTRIPSEL_ALL_TZ0_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_TZ0_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_TZ0_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_TZ0;

#define DCAHTRIPSEL_ALL_TZ0_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_TZ0_Pos)
#define DCAHTRIPSEL_ALL_TZ0_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_TZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     TZ1
 *  @access     PWM->DCAHTRIPSEL.bit.TZ1
 *  @brief      Enable TZ1 as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_TZ1_Pos (1)
#define DCAHTRIPSEL_ALL_TZ1_Msk (0x1UL << DCAHTRIPSEL_ALL_TZ1_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_TZ1_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_TZ1_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_TZ1;

#define DCAHTRIPSEL_ALL_TZ1_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_TZ1_Pos)
#define DCAHTRIPSEL_ALL_TZ1_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_TZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     TZ2
 *  @access     PWM->DCAHTRIPSEL.bit.TZ2
 *  @brief      Enable TZ2 as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_TZ2_Pos (2)
#define DCAHTRIPSEL_ALL_TZ2_Msk (0x1UL << DCAHTRIPSEL_ALL_TZ2_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_TZ2_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_TZ2_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_TZ2;

#define DCAHTRIPSEL_ALL_TZ2_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_TZ2_Pos)
#define DCAHTRIPSEL_ALL_TZ2_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_TZ2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     TZ3
 *  @access     PWM->DCAHTRIPSEL.bit.TZ3
 *  @brief      Enable TZ3 as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_TZ3_Pos (3)
#define DCAHTRIPSEL_ALL_TZ3_Msk (0x1UL << DCAHTRIPSEL_ALL_TZ3_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_TZ3_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_TZ3_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_TZ3;

#define DCAHTRIPSEL_ALL_TZ3_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_TZ3_Pos)
#define DCAHTRIPSEL_ALL_TZ3_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_TZ3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     TZ4
 *  @access     PWM->DCAHTRIPSEL.bit.TZ4
 *  @brief      Enable TZ4 as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_TZ4_Pos (4)
#define DCAHTRIPSEL_ALL_TZ4_Msk (0x1UL << DCAHTRIPSEL_ALL_TZ4_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_TZ4_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_TZ4_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_TZ4;

#define DCAHTRIPSEL_ALL_TZ4_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_TZ4_Pos)
#define DCAHTRIPSEL_ALL_TZ4_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_TZ4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     EPWRTZ0
 *  @access     PWM->DCAHTRIPSEL.bit.EPWRTZ0
 *  @brief      Enable EPWRTZ0 as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_EPWRTZ0_Pos (5)
#define DCAHTRIPSEL_ALL_EPWRTZ0_Msk (0x1UL << DCAHTRIPSEL_ALL_EPWRTZ0_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_EPWRTZ0_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_EPWRTZ0_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_EPWRTZ0;

#define DCAHTRIPSEL_ALL_EPWRTZ0_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_EPWRTZ0_Pos)
#define DCAHTRIPSEL_ALL_EPWRTZ0_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_EPWRTZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     EPWRTZ1
 *  @access     PWM->DCAHTRIPSEL.bit.EPWRTZ1
 *  @brief      Enable EPWRTZ1 as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_EPWRTZ1_Pos (6)
#define DCAHTRIPSEL_ALL_EPWRTZ1_Msk (0x1UL << DCAHTRIPSEL_ALL_EPWRTZ1_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_EPWRTZ1_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_EPWRTZ1_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_EPWRTZ1;

#define DCAHTRIPSEL_ALL_EPWRTZ1_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_EPWRTZ1_Pos)
#define DCAHTRIPSEL_ALL_EPWRTZ1_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_EPWRTZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     ADCPPU0TZ
 *  @access     PWM->DCAHTRIPSEL.bit.ADCPPU0TZ
 *  @brief      Enable ADCPPU0TZ as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_ADCPPU0TZ_Pos (8)
#define DCAHTRIPSEL_ALL_ADCPPU0TZ_Msk (0x1UL << DCAHTRIPSEL_ALL_ADCPPU0TZ_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_ADCPPU0TZ_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_ADCPPU0TZ_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_ADCPPU0TZ;

#define DCAHTRIPSEL_ALL_ADCPPU0TZ_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_ADCPPU0TZ_Pos)
#define DCAHTRIPSEL_ALL_ADCPPU0TZ_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_ADCPPU0TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     ADCPPU1TZ
 *  @access     PWM->DCAHTRIPSEL.bit.ADCPPU1TZ
 *  @brief      Enable ADCPPU1TZ as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_ADCPPU1TZ_Pos (9)
#define DCAHTRIPSEL_ALL_ADCPPU1TZ_Msk (0x1UL << DCAHTRIPSEL_ALL_ADCPPU1TZ_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_ADCPPU1TZ_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_ADCPPU1TZ_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_ADCPPU1TZ;

#define DCAHTRIPSEL_ALL_ADCPPU1TZ_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_ADCPPU1TZ_Pos)
#define DCAHTRIPSEL_ALL_ADCPPU1TZ_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_ADCPPU1TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     ADCPPU2TZ
 *  @access     PWM->DCAHTRIPSEL.bit.ADCPPU2TZ
 *  @brief      Enable ADCPPU2TZ as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_ADCPPU2TZ_Pos (10)
#define DCAHTRIPSEL_ALL_ADCPPU2TZ_Msk (0x1UL << DCAHTRIPSEL_ALL_ADCPPU2TZ_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_ADCPPU2TZ_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_ADCPPU2TZ_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_ADCPPU2TZ;

#define DCAHTRIPSEL_ALL_ADCPPU2TZ_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_ADCPPU2TZ_Pos)
#define DCAHTRIPSEL_ALL_ADCPPU2TZ_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_ADCPPU2TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     ADCPPU3TZ
 *  @access     PWM->DCAHTRIPSEL.bit.ADCPPU3TZ
 *  @brief      Enable ADCPPU3TZ as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_ADCPPU3TZ_Pos (11)
#define DCAHTRIPSEL_ALL_ADCPPU3TZ_Msk (0x1UL << DCAHTRIPSEL_ALL_ADCPPU3TZ_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_ADCPPU3TZ_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_ADCPPU3TZ_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_ADCPPU3TZ;

#define DCAHTRIPSEL_ALL_ADCPPU3TZ_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_ADCPPU3TZ_Pos)
#define DCAHTRIPSEL_ALL_ADCPPU3TZ_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_ADCPPU3TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     ADCPPU4TZ
 *  @access     PWM->DCAHTRIPSEL.bit.ADCPPU4TZ
 *  @brief      Enable ADCPPU4TZ as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_ADCPPU4TZ_Pos (12)
#define DCAHTRIPSEL_ALL_ADCPPU4TZ_Msk (0x1UL << DCAHTRIPSEL_ALL_ADCPPU4TZ_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_ADCPPU4TZ_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_ADCPPU4TZ_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_ADCPPU4TZ;

#define DCAHTRIPSEL_ALL_ADCPPU4TZ_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_ADCPPU4TZ_Pos)
#define DCAHTRIPSEL_ALL_ADCPPU4TZ_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_ADCPPU4TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     ADCPPU5TZ
 *  @access     PWM->DCAHTRIPSEL.bit.ADCPPU5TZ
 *  @brief      Enable ADCPPU5TZ as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_ADCPPU5TZ_Pos (13)
#define DCAHTRIPSEL_ALL_ADCPPU5TZ_Msk (0x1UL << DCAHTRIPSEL_ALL_ADCPPU5TZ_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_ADCPPU5TZ_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_ADCPPU5TZ_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_ADCPPU5TZ;

#define DCAHTRIPSEL_ALL_ADCPPU5TZ_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_ADCPPU5TZ_Pos)
#define DCAHTRIPSEL_ALL_ADCPPU5TZ_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_ADCPPU5TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP0L
 *  @access     PWM->DCAHTRIPSEL.bit.COMP0L
 *  @brief      Enable COMP0L as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP0L_Pos (16)
#define DCAHTRIPSEL_ALL_COMP0L_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP0L_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP0L_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP0L_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP0L;

#define DCAHTRIPSEL_ALL_COMP0L_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP0L_Pos)
#define DCAHTRIPSEL_ALL_COMP0L_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP0L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP0H
 *  @access     PWM->DCAHTRIPSEL.bit.COMP0H
 *  @brief      Enable COMP0H as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP0H_Pos (17)
#define DCAHTRIPSEL_ALL_COMP0H_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP0H_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP0H_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP0H_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP0H;

#define DCAHTRIPSEL_ALL_COMP0H_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP0H_Pos)
#define DCAHTRIPSEL_ALL_COMP0H_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP0H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP1L
 *  @access     PWM->DCAHTRIPSEL.bit.COMP1L
 *  @brief      Enable COMP1L as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP1L_Pos (18)
#define DCAHTRIPSEL_ALL_COMP1L_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP1L_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP1L_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP1L_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP1L;

#define DCAHTRIPSEL_ALL_COMP1L_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP1L_Pos)
#define DCAHTRIPSEL_ALL_COMP1L_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP1L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP1H
 *  @access     PWM->DCAHTRIPSEL.bit.COMP1H
 *  @brief      Enable COMP1H as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP1H_Pos (19)
#define DCAHTRIPSEL_ALL_COMP1H_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP1H_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP1H_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP1H_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP1H;

#define DCAHTRIPSEL_ALL_COMP1H_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP1H_Pos)
#define DCAHTRIPSEL_ALL_COMP1H_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP1H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP2L
 *  @access     PWM->DCAHTRIPSEL.bit.COMP2L
 *  @brief      Enable COMP2L as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP2L_Pos (20)
#define DCAHTRIPSEL_ALL_COMP2L_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP2L_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP2L_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP2L_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP2L;

#define DCAHTRIPSEL_ALL_COMP2L_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP2L_Pos)
#define DCAHTRIPSEL_ALL_COMP2L_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP2L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP2H
 *  @access     PWM->DCAHTRIPSEL.bit.COMP2H
 *  @brief      Enable COMP2H as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP2H_Pos (21)
#define DCAHTRIPSEL_ALL_COMP2H_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP2H_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP2H_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP2H_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP2H;

#define DCAHTRIPSEL_ALL_COMP2H_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP2H_Pos)
#define DCAHTRIPSEL_ALL_COMP2H_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP2H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP3L
 *  @access     PWM->DCAHTRIPSEL.bit.COMP3L
 *  @brief      Enable COMP3L as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP3L_Pos (22)
#define DCAHTRIPSEL_ALL_COMP3L_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP3L_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP3L_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP3L_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP3L;

#define DCAHTRIPSEL_ALL_COMP3L_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP3L_Pos)
#define DCAHTRIPSEL_ALL_COMP3L_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP3L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP3H
 *  @access     PWM->DCAHTRIPSEL.bit.COMP3H
 *  @brief      Enable COMP3H as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP3H_Pos (23)
#define DCAHTRIPSEL_ALL_COMP3H_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP3H_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP3H_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP3H_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP3H;

#define DCAHTRIPSEL_ALL_COMP3H_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP3H_Pos)
#define DCAHTRIPSEL_ALL_COMP3H_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP3H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP4L
 *  @access     PWM->DCAHTRIPSEL.bit.COMP4L
 *  @brief      Enable COMP4L as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP4L_Pos (24)
#define DCAHTRIPSEL_ALL_COMP4L_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP4L_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP4L_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP4L_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP4L;

#define DCAHTRIPSEL_ALL_COMP4L_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP4L_Pos)
#define DCAHTRIPSEL_ALL_COMP4L_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP4L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCAHTRIPSEL     COMP4H
 *  @access     PWM->DCAHTRIPSEL.bit.COMP4H
 *  @brief      Enable COMP4H as DCAH trip event (ORed)
 */
#define DCAHTRIPSEL_ALL_COMP4H_Pos (25)
#define DCAHTRIPSEL_ALL_COMP4H_Msk (0x1UL << DCAHTRIPSEL_ALL_COMP4H_Pos)

typedef enum
{
    DCAHTRIPSEL_BIT_COMP4H_DISABLE     = 0,  /*!< Disable   */
    DCAHTRIPSEL_BIT_COMP4H_ENABLE      = 1,  /*!< Enable    */
} DCAHTRIPSEL_BIT_COMP4H;

#define DCAHTRIPSEL_ALL_COMP4H_DISABLE     ((0x0UL) << DCAHTRIPSEL_ALL_COMP4H_Pos)
#define DCAHTRIPSEL_ALL_COMP4H_ENABLE      ((0x1UL) << DCAHTRIPSEL_ALL_COMP4H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     TZ0
 *  @access     PWM->DCBLTRIPSEL.bit.TZ0
 *  @brief      Enable TZ0 as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_TZ0_Pos (0)
#define DCBLTRIPSEL_ALL_TZ0_Msk (0x1UL << DCBLTRIPSEL_ALL_TZ0_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_TZ0_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_TZ0_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_TZ0;

#define DCBLTRIPSEL_ALL_TZ0_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_TZ0_Pos)
#define DCBLTRIPSEL_ALL_TZ0_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_TZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     TZ1
 *  @access     PWM->DCBLTRIPSEL.bit.TZ1
 *  @brief      Enable TZ1 as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_TZ1_Pos (1)
#define DCBLTRIPSEL_ALL_TZ1_Msk (0x1UL << DCBLTRIPSEL_ALL_TZ1_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_TZ1_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_TZ1_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_TZ1;

#define DCBLTRIPSEL_ALL_TZ1_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_TZ1_Pos)
#define DCBLTRIPSEL_ALL_TZ1_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_TZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     TZ2
 *  @access     PWM->DCBLTRIPSEL.bit.TZ2
 *  @brief      Enable TZ2 as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_TZ2_Pos (2)
#define DCBLTRIPSEL_ALL_TZ2_Msk (0x1UL << DCBLTRIPSEL_ALL_TZ2_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_TZ2_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_TZ2_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_TZ2;

#define DCBLTRIPSEL_ALL_TZ2_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_TZ2_Pos)
#define DCBLTRIPSEL_ALL_TZ2_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_TZ2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     TZ3
 *  @access     PWM->DCBLTRIPSEL.bit.TZ3
 *  @brief      Enable TZ3 as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_TZ3_Pos (3)
#define DCBLTRIPSEL_ALL_TZ3_Msk (0x1UL << DCBLTRIPSEL_ALL_TZ3_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_TZ3_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_TZ3_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_TZ3;

#define DCBLTRIPSEL_ALL_TZ3_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_TZ3_Pos)
#define DCBLTRIPSEL_ALL_TZ3_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_TZ3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     TZ4
 *  @access     PWM->DCBLTRIPSEL.bit.TZ4
 *  @brief      Enable TZ4 as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_TZ4_Pos (4)
#define DCBLTRIPSEL_ALL_TZ4_Msk (0x1UL << DCBLTRIPSEL_ALL_TZ4_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_TZ4_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_TZ4_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_TZ4;

#define DCBLTRIPSEL_ALL_TZ4_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_TZ4_Pos)
#define DCBLTRIPSEL_ALL_TZ4_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_TZ4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     EPWRTZ0
 *  @access     PWM->DCBLTRIPSEL.bit.EPWRTZ0
 *  @brief      Enable EPWRTZ0 as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_EPWRTZ0_Pos (5)
#define DCBLTRIPSEL_ALL_EPWRTZ0_Msk (0x1UL << DCBLTRIPSEL_ALL_EPWRTZ0_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_EPWRTZ0_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_EPWRTZ0_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_EPWRTZ0;

#define DCBLTRIPSEL_ALL_EPWRTZ0_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_EPWRTZ0_Pos)
#define DCBLTRIPSEL_ALL_EPWRTZ0_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_EPWRTZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     EPWRTZ1
 *  @access     PWM->DCBLTRIPSEL.bit.EPWRTZ1
 *  @brief      Enable EPWRTZ1 as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_EPWRTZ1_Pos (6)
#define DCBLTRIPSEL_ALL_EPWRTZ1_Msk (0x1UL << DCBLTRIPSEL_ALL_EPWRTZ1_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_EPWRTZ1_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_EPWRTZ1_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_EPWRTZ1;

#define DCBLTRIPSEL_ALL_EPWRTZ1_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_EPWRTZ1_Pos)
#define DCBLTRIPSEL_ALL_EPWRTZ1_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_EPWRTZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     ADCPPU0TZ
 *  @access     PWM->DCBLTRIPSEL.bit.ADCPPU0TZ
 *  @brief      Enable ADCPPU0TZ as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_ADCPPU0TZ_Pos (8)
#define DCBLTRIPSEL_ALL_ADCPPU0TZ_Msk (0x1UL << DCBLTRIPSEL_ALL_ADCPPU0TZ_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_ADCPPU0TZ_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_ADCPPU0TZ_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_ADCPPU0TZ;

#define DCBLTRIPSEL_ALL_ADCPPU0TZ_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_ADCPPU0TZ_Pos)
#define DCBLTRIPSEL_ALL_ADCPPU0TZ_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_ADCPPU0TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     ADCPPU1TZ
 *  @access     PWM->DCBLTRIPSEL.bit.ADCPPU1TZ
 *  @brief      Enable ADCPPU1TZ as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_ADCPPU1TZ_Pos (9)
#define DCBLTRIPSEL_ALL_ADCPPU1TZ_Msk (0x1UL << DCBLTRIPSEL_ALL_ADCPPU1TZ_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_ADCPPU1TZ_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_ADCPPU1TZ_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_ADCPPU1TZ;

#define DCBLTRIPSEL_ALL_ADCPPU1TZ_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_ADCPPU1TZ_Pos)
#define DCBLTRIPSEL_ALL_ADCPPU1TZ_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_ADCPPU1TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     ADCPPU2TZ
 *  @access     PWM->DCBLTRIPSEL.bit.ADCPPU2TZ
 *  @brief      Enable ADCPPU2TZ as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_ADCPPU2TZ_Pos (10)
#define DCBLTRIPSEL_ALL_ADCPPU2TZ_Msk (0x1UL << DCBLTRIPSEL_ALL_ADCPPU2TZ_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_ADCPPU2TZ_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_ADCPPU2TZ_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_ADCPPU2TZ;

#define DCBLTRIPSEL_ALL_ADCPPU2TZ_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_ADCPPU2TZ_Pos)
#define DCBLTRIPSEL_ALL_ADCPPU2TZ_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_ADCPPU2TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     ADCPPU3TZ
 *  @access     PWM->DCBLTRIPSEL.bit.ADCPPU3TZ
 *  @brief      Enable ADCPPU3TZ as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_ADCPPU3TZ_Pos (11)
#define DCBLTRIPSEL_ALL_ADCPPU3TZ_Msk (0x1UL << DCBLTRIPSEL_ALL_ADCPPU3TZ_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_ADCPPU3TZ_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_ADCPPU3TZ_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_ADCPPU3TZ;

#define DCBLTRIPSEL_ALL_ADCPPU3TZ_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_ADCPPU3TZ_Pos)
#define DCBLTRIPSEL_ALL_ADCPPU3TZ_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_ADCPPU3TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     ADCPPU4TZ
 *  @access     PWM->DCBLTRIPSEL.bit.ADCPPU4TZ
 *  @brief      Enable ADCPPU4TZ as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_ADCPPU4TZ_Pos (12)
#define DCBLTRIPSEL_ALL_ADCPPU4TZ_Msk (0x1UL << DCBLTRIPSEL_ALL_ADCPPU4TZ_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_ADCPPU4TZ_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_ADCPPU4TZ_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_ADCPPU4TZ;

#define DCBLTRIPSEL_ALL_ADCPPU4TZ_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_ADCPPU4TZ_Pos)
#define DCBLTRIPSEL_ALL_ADCPPU4TZ_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_ADCPPU4TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     ADCPPU5TZ
 *  @access     PWM->DCBLTRIPSEL.bit.ADCPPU5TZ
 *  @brief      Enable ADCPPU5TZ as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_ADCPPU5TZ_Pos (13)
#define DCBLTRIPSEL_ALL_ADCPPU5TZ_Msk (0x1UL << DCBLTRIPSEL_ALL_ADCPPU5TZ_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_ADCPPU5TZ_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_ADCPPU5TZ_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_ADCPPU5TZ;

#define DCBLTRIPSEL_ALL_ADCPPU5TZ_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_ADCPPU5TZ_Pos)
#define DCBLTRIPSEL_ALL_ADCPPU5TZ_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_ADCPPU5TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP0L
 *  @access     PWM->DCBLTRIPSEL.bit.COMP0L
 *  @brief      Enable COMP0L as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP0L_Pos (16)
#define DCBLTRIPSEL_ALL_COMP0L_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP0L_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP0L_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP0L_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP0L;

#define DCBLTRIPSEL_ALL_COMP0L_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP0L_Pos)
#define DCBLTRIPSEL_ALL_COMP0L_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP0L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP0H
 *  @access     PWM->DCBLTRIPSEL.bit.COMP0H
 *  @brief      Enable COMP0H as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP0H_Pos (17)
#define DCBLTRIPSEL_ALL_COMP0H_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP0H_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP0H_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP0H_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP0H;

#define DCBLTRIPSEL_ALL_COMP0H_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP0H_Pos)
#define DCBLTRIPSEL_ALL_COMP0H_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP0H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP1L
 *  @access     PWM->DCBLTRIPSEL.bit.COMP1L
 *  @brief      Enable COMP1L as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP1L_Pos (18)
#define DCBLTRIPSEL_ALL_COMP1L_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP1L_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP1L_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP1L_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP1L;

#define DCBLTRIPSEL_ALL_COMP1L_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP1L_Pos)
#define DCBLTRIPSEL_ALL_COMP1L_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP1L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP1H
 *  @access     PWM->DCBLTRIPSEL.bit.COMP1H
 *  @brief      Enable COMP1H as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP1H_Pos (19)
#define DCBLTRIPSEL_ALL_COMP1H_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP1H_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP1H_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP1H_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP1H;

#define DCBLTRIPSEL_ALL_COMP1H_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP1H_Pos)
#define DCBLTRIPSEL_ALL_COMP1H_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP1H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP2L
 *  @access     PWM->DCBLTRIPSEL.bit.COMP2L
 *  @brief      Enable COMP2L as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP2L_Pos (20)
#define DCBLTRIPSEL_ALL_COMP2L_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP2L_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP2L_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP2L_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP2L;

#define DCBLTRIPSEL_ALL_COMP2L_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP2L_Pos)
#define DCBLTRIPSEL_ALL_COMP2L_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP2L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP2H
 *  @access     PWM->DCBLTRIPSEL.bit.COMP2H
 *  @brief      Enable COMP2H as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP2H_Pos (21)
#define DCBLTRIPSEL_ALL_COMP2H_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP2H_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP2H_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP2H_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP2H;

#define DCBLTRIPSEL_ALL_COMP2H_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP2H_Pos)
#define DCBLTRIPSEL_ALL_COMP2H_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP2H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP3L
 *  @access     PWM->DCBLTRIPSEL.bit.COMP3L
 *  @brief      Enable COMP3L as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP3L_Pos (22)
#define DCBLTRIPSEL_ALL_COMP3L_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP3L_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP3L_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP3L_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP3L;

#define DCBLTRIPSEL_ALL_COMP3L_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP3L_Pos)
#define DCBLTRIPSEL_ALL_COMP3L_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP3L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP3H
 *  @access     PWM->DCBLTRIPSEL.bit.COMP3H
 *  @brief      Enable COMP3H as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP3H_Pos (23)
#define DCBLTRIPSEL_ALL_COMP3H_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP3H_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP3H_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP3H_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP3H;

#define DCBLTRIPSEL_ALL_COMP3H_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP3H_Pos)
#define DCBLTRIPSEL_ALL_COMP3H_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP3H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP4L
 *  @access     PWM->DCBLTRIPSEL.bit.COMP4L
 *  @brief      Enable COMP4L as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP4L_Pos (24)
#define DCBLTRIPSEL_ALL_COMP4L_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP4L_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP4L_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP4L_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP4L;

#define DCBLTRIPSEL_ALL_COMP4L_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP4L_Pos)
#define DCBLTRIPSEL_ALL_COMP4L_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP4L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBLTRIPSEL     COMP4H
 *  @access     PWM->DCBLTRIPSEL.bit.COMP4H
 *  @brief      Enable COMP4H as DCBL trip event (ORed)
 */
#define DCBLTRIPSEL_ALL_COMP4H_Pos (25)
#define DCBLTRIPSEL_ALL_COMP4H_Msk (0x1UL << DCBLTRIPSEL_ALL_COMP4H_Pos)

typedef enum
{
    DCBLTRIPSEL_BIT_COMP4H_DISABLE     = 0,  /*!< Disable   */
    DCBLTRIPSEL_BIT_COMP4H_ENABLE      = 1,  /*!< Enable    */
} DCBLTRIPSEL_BIT_COMP4H;

#define DCBLTRIPSEL_ALL_COMP4H_DISABLE     ((0x0UL) << DCBLTRIPSEL_ALL_COMP4H_Pos)
#define DCBLTRIPSEL_ALL_COMP4H_ENABLE      ((0x1UL) << DCBLTRIPSEL_ALL_COMP4H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     TZ0
 *  @access     PWM->DCBHTRIPSEL.bit.TZ0
 *  @brief      Enable TZ0 as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_TZ0_Pos (0)
#define DCBHTRIPSEL_ALL_TZ0_Msk (0x1UL << DCBHTRIPSEL_ALL_TZ0_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_TZ0_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_TZ0_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_TZ0;

#define DCBHTRIPSEL_ALL_TZ0_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_TZ0_Pos)
#define DCBHTRIPSEL_ALL_TZ0_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_TZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     TZ1
 *  @access     PWM->DCBHTRIPSEL.bit.TZ1
 *  @brief      Enable TZ1 as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_TZ1_Pos (1)
#define DCBHTRIPSEL_ALL_TZ1_Msk (0x1UL << DCBHTRIPSEL_ALL_TZ1_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_TZ1_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_TZ1_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_TZ1;

#define DCBHTRIPSEL_ALL_TZ1_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_TZ1_Pos)
#define DCBHTRIPSEL_ALL_TZ1_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_TZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     TZ2
 *  @access     PWM->DCBHTRIPSEL.bit.TZ2
 *  @brief      Enable TZ2 as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_TZ2_Pos (2)
#define DCBHTRIPSEL_ALL_TZ2_Msk (0x1UL << DCBHTRIPSEL_ALL_TZ2_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_TZ2_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_TZ2_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_TZ2;

#define DCBHTRIPSEL_ALL_TZ2_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_TZ2_Pos)
#define DCBHTRIPSEL_ALL_TZ2_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_TZ2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     TZ3
 *  @access     PWM->DCBHTRIPSEL.bit.TZ3
 *  @brief      Enable TZ3 as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_TZ3_Pos (3)
#define DCBHTRIPSEL_ALL_TZ3_Msk (0x1UL << DCBHTRIPSEL_ALL_TZ3_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_TZ3_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_TZ3_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_TZ3;

#define DCBHTRIPSEL_ALL_TZ3_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_TZ3_Pos)
#define DCBHTRIPSEL_ALL_TZ3_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_TZ3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     TZ4
 *  @access     PWM->DCBHTRIPSEL.bit.TZ4
 *  @brief      Enable TZ4 as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_TZ4_Pos (4)
#define DCBHTRIPSEL_ALL_TZ4_Msk (0x1UL << DCBHTRIPSEL_ALL_TZ4_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_TZ4_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_TZ4_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_TZ4;

#define DCBHTRIPSEL_ALL_TZ4_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_TZ4_Pos)
#define DCBHTRIPSEL_ALL_TZ4_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_TZ4_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     EPWRTZ0
 *  @access     PWM->DCBHTRIPSEL.bit.EPWRTZ0
 *  @brief      Enable EPWRTZ0 as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_EPWRTZ0_Pos (5)
#define DCBHTRIPSEL_ALL_EPWRTZ0_Msk (0x1UL << DCBHTRIPSEL_ALL_EPWRTZ0_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_EPWRTZ0_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_EPWRTZ0_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_EPWRTZ0;

#define DCBHTRIPSEL_ALL_EPWRTZ0_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_EPWRTZ0_Pos)
#define DCBHTRIPSEL_ALL_EPWRTZ0_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_EPWRTZ0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     EPWRTZ1
 *  @access     PWM->DCBHTRIPSEL.bit.EPWRTZ1
 *  @brief      Enable EPWRTZ1 as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_EPWRTZ1_Pos (6)
#define DCBHTRIPSEL_ALL_EPWRTZ1_Msk (0x1UL << DCBHTRIPSEL_ALL_EPWRTZ1_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_EPWRTZ1_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_EPWRTZ1_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_EPWRTZ1;

#define DCBHTRIPSEL_ALL_EPWRTZ1_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_EPWRTZ1_Pos)
#define DCBHTRIPSEL_ALL_EPWRTZ1_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_EPWRTZ1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     ADCPPU0TZ
 *  @access     PWM->DCBHTRIPSEL.bit.ADCPPU0TZ
 *  @brief      Enable ADCPPU0TZ as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_ADCPPU0TZ_Pos (8)
#define DCBHTRIPSEL_ALL_ADCPPU0TZ_Msk (0x1UL << DCBHTRIPSEL_ALL_ADCPPU0TZ_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_ADCPPU0TZ_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_ADCPPU0TZ_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_ADCPPU0TZ;

#define DCBHTRIPSEL_ALL_ADCPPU0TZ_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_ADCPPU0TZ_Pos)
#define DCBHTRIPSEL_ALL_ADCPPU0TZ_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_ADCPPU0TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     ADCPPU1TZ
 *  @access     PWM->DCBHTRIPSEL.bit.ADCPPU1TZ
 *  @brief      Enable ADCPPU1TZ as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_ADCPPU1TZ_Pos (9)
#define DCBHTRIPSEL_ALL_ADCPPU1TZ_Msk (0x1UL << DCBHTRIPSEL_ALL_ADCPPU1TZ_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_ADCPPU1TZ_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_ADCPPU1TZ_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_ADCPPU1TZ;

#define DCBHTRIPSEL_ALL_ADCPPU1TZ_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_ADCPPU1TZ_Pos)
#define DCBHTRIPSEL_ALL_ADCPPU1TZ_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_ADCPPU1TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     ADCPPU2TZ
 *  @access     PWM->DCBHTRIPSEL.bit.ADCPPU2TZ
 *  @brief      Enable ADCPPU2TZ as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_ADCPPU2TZ_Pos (10)
#define DCBHTRIPSEL_ALL_ADCPPU2TZ_Msk (0x1UL << DCBHTRIPSEL_ALL_ADCPPU2TZ_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_ADCPPU2TZ_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_ADCPPU2TZ_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_ADCPPU2TZ;

#define DCBHTRIPSEL_ALL_ADCPPU2TZ_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_ADCPPU2TZ_Pos)
#define DCBHTRIPSEL_ALL_ADCPPU2TZ_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_ADCPPU2TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     ADCPPU3TZ
 *  @access     PWM->DCBHTRIPSEL.bit.ADCPPU3TZ
 *  @brief      Enable ADCPPU3TZ as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_ADCPPU3TZ_Pos (11)
#define DCBHTRIPSEL_ALL_ADCPPU3TZ_Msk (0x1UL << DCBHTRIPSEL_ALL_ADCPPU3TZ_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_ADCPPU3TZ_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_ADCPPU3TZ_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_ADCPPU3TZ;

#define DCBHTRIPSEL_ALL_ADCPPU3TZ_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_ADCPPU3TZ_Pos)
#define DCBHTRIPSEL_ALL_ADCPPU3TZ_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_ADCPPU3TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     ADCPPU4TZ
 *  @access     PWM->DCBHTRIPSEL.bit.ADCPPU4TZ
 *  @brief      Enable ADCPPU4TZ as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_ADCPPU4TZ_Pos (12)
#define DCBHTRIPSEL_ALL_ADCPPU4TZ_Msk (0x1UL << DCBHTRIPSEL_ALL_ADCPPU4TZ_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_ADCPPU4TZ_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_ADCPPU4TZ_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_ADCPPU4TZ;

#define DCBHTRIPSEL_ALL_ADCPPU4TZ_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_ADCPPU4TZ_Pos)
#define DCBHTRIPSEL_ALL_ADCPPU4TZ_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_ADCPPU4TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     ADCPPU5TZ
 *  @access     PWM->DCBHTRIPSEL.bit.ADCPPU5TZ
 *  @brief      Enable ADCPPU5TZ as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_ADCPPU5TZ_Pos (13)
#define DCBHTRIPSEL_ALL_ADCPPU5TZ_Msk (0x1UL << DCBHTRIPSEL_ALL_ADCPPU5TZ_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_ADCPPU5TZ_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_ADCPPU5TZ_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_ADCPPU5TZ;

#define DCBHTRIPSEL_ALL_ADCPPU5TZ_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_ADCPPU5TZ_Pos)
#define DCBHTRIPSEL_ALL_ADCPPU5TZ_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_ADCPPU5TZ_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP0L
 *  @access     PWM->DCBHTRIPSEL.bit.COMP0L
 *  @brief      Enable COMP0L as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP0L_Pos (16)
#define DCBHTRIPSEL_ALL_COMP0L_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP0L_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP0L_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP0L_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP0L;

#define DCBHTRIPSEL_ALL_COMP0L_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP0L_Pos)
#define DCBHTRIPSEL_ALL_COMP0L_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP0L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP0H
 *  @access     PWM->DCBHTRIPSEL.bit.COMP0H
 *  @brief      Enable COMP0H as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP0H_Pos (17)
#define DCBHTRIPSEL_ALL_COMP0H_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP0H_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP0H_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP0H_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP0H;

#define DCBHTRIPSEL_ALL_COMP0H_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP0H_Pos)
#define DCBHTRIPSEL_ALL_COMP0H_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP0H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP1L
 *  @access     PWM->DCBHTRIPSEL.bit.COMP1L
 *  @brief      Enable COMP1L as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP1L_Pos (18)
#define DCBHTRIPSEL_ALL_COMP1L_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP1L_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP1L_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP1L_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP1L;

#define DCBHTRIPSEL_ALL_COMP1L_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP1L_Pos)
#define DCBHTRIPSEL_ALL_COMP1L_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP1L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP1H
 *  @access     PWM->DCBHTRIPSEL.bit.COMP1H
 *  @brief      Enable COMP1H as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP1H_Pos (19)
#define DCBHTRIPSEL_ALL_COMP1H_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP1H_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP1H_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP1H_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP1H;

#define DCBHTRIPSEL_ALL_COMP1H_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP1H_Pos)
#define DCBHTRIPSEL_ALL_COMP1H_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP1H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP2L
 *  @access     PWM->DCBHTRIPSEL.bit.COMP2L
 *  @brief      Enable COMP2L as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP2L_Pos (20)
#define DCBHTRIPSEL_ALL_COMP2L_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP2L_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP2L_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP2L_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP2L;

#define DCBHTRIPSEL_ALL_COMP2L_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP2L_Pos)
#define DCBHTRIPSEL_ALL_COMP2L_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP2L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP2H
 *  @access     PWM->DCBHTRIPSEL.bit.COMP2H
 *  @brief      Enable COMP2H as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP2H_Pos (21)
#define DCBHTRIPSEL_ALL_COMP2H_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP2H_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP2H_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP2H_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP2H;

#define DCBHTRIPSEL_ALL_COMP2H_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP2H_Pos)
#define DCBHTRIPSEL_ALL_COMP2H_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP2H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP3L
 *  @access     PWM->DCBHTRIPSEL.bit.COMP3L
 *  @brief      Enable COMP3L as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP3L_Pos (22)
#define DCBHTRIPSEL_ALL_COMP3L_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP3L_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP3L_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP3L_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP3L;

#define DCBHTRIPSEL_ALL_COMP3L_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP3L_Pos)
#define DCBHTRIPSEL_ALL_COMP3L_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP3L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP3H
 *  @access     PWM->DCBHTRIPSEL.bit.COMP3H
 *  @brief      Enable COMP3H as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP3H_Pos (23)
#define DCBHTRIPSEL_ALL_COMP3H_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP3H_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP3H_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP3H_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP3H;

#define DCBHTRIPSEL_ALL_COMP3H_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP3H_Pos)
#define DCBHTRIPSEL_ALL_COMP3H_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP3H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP4L
 *  @access     PWM->DCBHTRIPSEL.bit.COMP4L
 *  @brief      Enable COMP4L as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP4L_Pos (24)
#define DCBHTRIPSEL_ALL_COMP4L_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP4L_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP4L_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP4L_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP4L;

#define DCBHTRIPSEL_ALL_COMP4L_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP4L_Pos)
#define DCBHTRIPSEL_ALL_COMP4L_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP4L_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBHTRIPSEL     COMP4H
 *  @access     PWM->DCBHTRIPSEL.bit.COMP4H
 *  @brief      Enable COMP4H as DCBH trip event (ORed)
 */
#define DCBHTRIPSEL_ALL_COMP4H_Pos (25)
#define DCBHTRIPSEL_ALL_COMP4H_Msk (0x1UL << DCBHTRIPSEL_ALL_COMP4H_Pos)

typedef enum
{
    DCBHTRIPSEL_BIT_COMP4H_DISABLE     = 0,  /*!< Disable   */
    DCBHTRIPSEL_BIT_COMP4H_ENABLE      = 1,  /*!< Enable    */
} DCBHTRIPSEL_BIT_COMP4H;

#define DCBHTRIPSEL_ALL_COMP4H_DISABLE     ((0x0UL) << DCBHTRIPSEL_ALL_COMP4H_Pos)
#define DCBHTRIPSEL_ALL_COMP4H_ENABLE      ((0x1UL) << DCBHTRIPSEL_ALL_COMP4H_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCACTL          EVT0SRCSEL
 *  @access     PWM->DCACTL.bit.EVT0SRCSEL
 *  @brief      DCAEVT0 source signal select
 */
#define DCACTL_ALL_EVT0SRCSEL_Pos (0)
#define DCACTL_ALL_EVT0SRCSEL_Msk (0x1UL << DCACTL_ALL_EVT0SRCSEL_Pos)

typedef enum
{
    DCACTL_BIT_EVT0SRCSEL_DCAEVT0       = 0,  /*!< Source signal is DCAEVT0     */
    DCACTL_BIT_EVT0SRCSEL_DCEVTFILT     = 1,  /*!< Source signal is DCEVTFILT   */
} DCACTL_BIT_EVT0SRCSEL;

#define DCACTL_ALL_EVT0SRCSEL_DCAEVT0       ((0x0UL) << DCACTL_ALL_EVT0SRCSEL_Pos)
#define DCACTL_ALL_EVT0SRCSEL_DCEVTFILT     ((0x1UL) << DCACTL_ALL_EVT0SRCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCACTL          EVT0SRCASYNC
 *  @access     PWM->DCACTL.bit.EVT0SRCASYNC
 *  @brief      DCAEVT0 source signal is asynchronous/synchronous (1/0)
 */
#define DCACTL_ALL_EVT0SRCASYNC_Pos (1)
#define DCACTL_ALL_EVT0SRCASYNC_Msk (0x1UL << DCACTL_ALL_EVT0SRCASYNC_Pos)

typedef enum
{
    DCACTL_BIT_EVT0SRCASYNC_DCAEVT0_SYNC      = 0,  /*!< Synchronous    */
    DCACTL_BIT_EVT0SRCASYNC_DCAEVT0_ASYNC     = 1,  /*!< Asynchronous   */
} DCACTL_BIT_EVT0SRCASYNC;

#define DCACTL_ALL_EVT0SRCASYNC_DCAEVT0_SYNC      ((0x0UL) << DCACTL_ALL_EVT0SRCASYNC_Pos)
#define DCACTL_ALL_EVT0SRCASYNC_DCAEVT0_ASYNC     ((0x1UL) << DCACTL_ALL_EVT0SRCASYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCACTL          EVT0SOCE
 *  @access     PWM->DCACTL.bit.EVT0SOCE
 *  @brief      DCAEVT0 SOC generation
 */
#define DCACTL_ALL_EVT0SOCE_Pos (2)
#define DCACTL_ALL_EVT0SOCE_Msk (0x1UL << DCACTL_ALL_EVT0SOCE_Pos)

typedef enum
{
    DCACTL_BIT_EVT0SOCE_DISABLE     = 0,  /*!< Disable   */
    DCACTL_BIT_EVT0SOCE_ENABLE      = 1,  /*!< Enable    */
} DCACTL_BIT_EVT0SOCE;

#define DCACTL_ALL_EVT0SOCE_DISABLE     ((0x0UL) << DCACTL_ALL_EVT0SOCE_Pos)
#define DCACTL_ALL_EVT0SOCE_ENABLE      ((0x1UL) << DCACTL_ALL_EVT0SOCE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCACTL          EVT0SYNCE
 *  @access     PWM->DCACTL.bit.EVT0SYNCE
 *  @brief      DCAEVT0 SYNC generation
 */
#define DCACTL_ALL_EVT0SYNCE_Pos (3)
#define DCACTL_ALL_EVT0SYNCE_Msk (0x1UL << DCACTL_ALL_EVT0SYNCE_Pos)

typedef enum
{
    DCACTL_BIT_EVT0SYNCE_DISABLE     = 0,  /*!< Disable   */
    DCACTL_BIT_EVT0SYNCE_ENABLE      = 1,  /*!< Enable    */
} DCACTL_BIT_EVT0SYNCE;

#define DCACTL_ALL_EVT0SYNCE_DISABLE     ((0x0UL) << DCACTL_ALL_EVT0SYNCE_Pos)
#define DCACTL_ALL_EVT0SYNCE_ENABLE      ((0x1UL) << DCACTL_ALL_EVT0SYNCE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCACTL          EVT1SRCSEL
 *  @access     PWM->DCACTL.bit.EVT1SRCSEL
 *  @brief      DCAEVT1 source signal select
 */
#define DCACTL_ALL_EVT1SRCSEL_Pos (4)
#define DCACTL_ALL_EVT1SRCSEL_Msk (0x1UL << DCACTL_ALL_EVT1SRCSEL_Pos)

typedef enum
{
    DCACTL_BIT_EVT1SRCSEL_DCAEVT1       = 0,  /*!< Source signal is DCAEVT1     */
    DCACTL_BIT_EVT1SRCSEL_DCEVTFILT     = 1,  /*!< Source signal is DCEVTFILT   */
} DCACTL_BIT_EVT1SRCSEL;

#define DCACTL_ALL_EVT1SRCSEL_DCAEVT1       ((0x0UL) << DCACTL_ALL_EVT1SRCSEL_Pos)
#define DCACTL_ALL_EVT1SRCSEL_DCEVTFILT     ((0x1UL) << DCACTL_ALL_EVT1SRCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCACTL          EVT1SRCASYNC
 *  @access     PWM->DCACTL.bit.EVT1SRCASYNC
 *  @brief      DCAEVT1 source signal is asynchronous/synchronous
 */
#define DCACTL_ALL_EVT1SRCASYNC_Pos (5)
#define DCACTL_ALL_EVT1SRCASYNC_Msk (0x1UL << DCACTL_ALL_EVT1SRCASYNC_Pos)

typedef enum
{
    DCACTL_BIT_EVT1SRCASYNC_DCAEVT1_SYNC      = 0,  /*!< Synchronous    */
    DCACTL_BIT_EVT1SRCASYNC_DCAEVT1_ASYNC     = 1,  /*!< Asynchronous   */
} DCACTL_BIT_EVT1SRCASYNC;

#define DCACTL_ALL_EVT1SRCASYNC_DCAEVT1_SYNC      ((0x0UL) << DCACTL_ALL_EVT1SRCASYNC_Pos)
#define DCACTL_ALL_EVT1SRCASYNC_DCAEVT1_ASYNC     ((0x1UL) << DCACTL_ALL_EVT1SRCASYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBCTL          EVT0SRCSEL
 *  @access     PWM->DCBCTL.bit.EVT0SRCSEL
 *  @brief      DCBEVT0 source signal select
 */
#define DCBCTL_ALL_EVT0SRCSEL_Pos (0)
#define DCBCTL_ALL_EVT0SRCSEL_Msk (0x1UL << DCBCTL_ALL_EVT0SRCSEL_Pos)

typedef enum
{
    DCBCTL_BIT_EVT0SRCSEL_DCBEVT0       = 0,  /*!< Source signal is DCBEVT0     */
    DCBCTL_BIT_EVT0SRCSEL_DCEVTFILT     = 1,  /*!< Source signal is DCEVTFILT   */
} DCBCTL_BIT_EVT0SRCSEL;

#define DCBCTL_ALL_EVT0SRCSEL_DCBEVT0       ((0x0UL) << DCBCTL_ALL_EVT0SRCSEL_Pos)
#define DCBCTL_ALL_EVT0SRCSEL_DCEVTFILT     ((0x1UL) << DCBCTL_ALL_EVT0SRCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBCTL          EVT0SRCASYNC
 *  @access     PWM->DCBCTL.bit.EVT0SRCASYNC
 *  @brief      DCBEVT0 source signal is asynchronous/synchronous
 */
#define DCBCTL_ALL_EVT0SRCASYNC_Pos (1)
#define DCBCTL_ALL_EVT0SRCASYNC_Msk (0x1UL << DCBCTL_ALL_EVT0SRCASYNC_Pos)

typedef enum
{
    DCBCTL_BIT_EVT0SRCASYNC_DCBEVT0_SYNC      = 0,  /*!< Synchronous    */
    DCBCTL_BIT_EVT0SRCASYNC_DCBEVT0_ASYNC     = 1,  /*!< Asynchronous   */
} DCBCTL_BIT_EVT0SRCASYNC;

#define DCBCTL_ALL_EVT0SRCASYNC_DCBEVT0_SYNC      ((0x0UL) << DCBCTL_ALL_EVT0SRCASYNC_Pos)
#define DCBCTL_ALL_EVT0SRCASYNC_DCBEVT0_ASYNC     ((0x1UL) << DCBCTL_ALL_EVT0SRCASYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBCTL          EVT0SOCE
 *  @access     PWM->DCBCTL.bit.EVT0SOCE
 *  @brief      DCBEVT0 SOC generation
 */
#define DCBCTL_ALL_EVT0SOCE_Pos (2)
#define DCBCTL_ALL_EVT0SOCE_Msk (0x1UL << DCBCTL_ALL_EVT0SOCE_Pos)

typedef enum
{
    DCBCTL_BIT_EVT0SOCE_DISABLE     = 0,  /*!< Disable   */
    DCBCTL_BIT_EVT0SOCE_ENABLE      = 1,  /*!< Enable    */
} DCBCTL_BIT_EVT0SOCE;

#define DCBCTL_ALL_EVT0SOCE_DISABLE     ((0x0UL) << DCBCTL_ALL_EVT0SOCE_Pos)
#define DCBCTL_ALL_EVT0SOCE_ENABLE      ((0x1UL) << DCBCTL_ALL_EVT0SOCE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBCTL          EVT0SYNCE
 *  @access     PWM->DCBCTL.bit.EVT0SYNCE
 *  @brief      DCBEVT0 SYNC generation
 */
#define DCBCTL_ALL_EVT0SYNCE_Pos (3)
#define DCBCTL_ALL_EVT0SYNCE_Msk (0x1UL << DCBCTL_ALL_EVT0SYNCE_Pos)

typedef enum
{
    DCBCTL_BIT_EVT0SYNCE_DISABLE     = 0,  /*!< Disable   */
    DCBCTL_BIT_EVT0SYNCE_ENABLE      = 1,  /*!< Enable    */
} DCBCTL_BIT_EVT0SYNCE;

#define DCBCTL_ALL_EVT0SYNCE_DISABLE     ((0x0UL) << DCBCTL_ALL_EVT0SYNCE_Pos)
#define DCBCTL_ALL_EVT0SYNCE_ENABLE      ((0x1UL) << DCBCTL_ALL_EVT0SYNCE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBCTL          EVT1SRCSEL
 *  @access     PWM->DCBCTL.bit.EVT1SRCSEL
 *  @brief      DCBEVT1 source signal select
 */
#define DCBCTL_ALL_EVT1SRCSEL_Pos (4)
#define DCBCTL_ALL_EVT1SRCSEL_Msk (0x1UL << DCBCTL_ALL_EVT1SRCSEL_Pos)

typedef enum
{
    DCBCTL_BIT_EVT1SRCSEL_DCBEVT1       = 0,  /*!< Source signal is DCBEVT1     */
    DCBCTL_BIT_EVT1SRCSEL_DCEVTFILT     = 1,  /*!< Source signal is DCEVTFILT   */
} DCBCTL_BIT_EVT1SRCSEL;

#define DCBCTL_ALL_EVT1SRCSEL_DCBEVT1       ((0x0UL) << DCBCTL_ALL_EVT1SRCSEL_Pos)
#define DCBCTL_ALL_EVT1SRCSEL_DCEVTFILT     ((0x1UL) << DCBCTL_ALL_EVT1SRCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCBCTL          EVT1SRCASYNC
 *  @access     PWM->DCBCTL.bit.EVT1SRCASYNC
 *  @brief      DCBEVT1 source signal is asynchronous/synchronous (1/0)
 */
#define DCBCTL_ALL_EVT1SRCASYNC_Pos (5)
#define DCBCTL_ALL_EVT1SRCASYNC_Msk (0x1UL << DCBCTL_ALL_EVT1SRCASYNC_Pos)

typedef enum
{
    DCBCTL_BIT_EVT1SRCASYNC_DCBEVT1_SYNC      = 0,  /*!< Synchronous    */
    DCBCTL_BIT_EVT1SRCASYNC_DCBEVT1_ASYNC     = 1,  /*!< Asynchronous   */
} DCBCTL_BIT_EVT1SRCASYNC;

#define DCBCTL_ALL_EVT1SRCASYNC_DCBEVT1_SYNC      ((0x0UL) << DCBCTL_ALL_EVT1SRCASYNC_Pos)
#define DCBCTL_ALL_EVT1SRCASYNC_DCBEVT1_ASYNC     ((0x1UL) << DCBCTL_ALL_EVT1SRCASYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          SRCSEL
 *  @access     PWM->DCFCTL.bit.SRCSEL
 *  @brief      DCEVTFILT signal source select
 */
#define DCFCTL_ALL_SRCSEL_Pos (0)
#define DCFCTL_ALL_SRCSEL_Msk (0x3UL << DCFCTL_ALL_SRCSEL_Pos)

typedef enum
{
    DCFCTL_BIT_SRCSEL_DCAEVT0     = 0,  /*!< Source is DCAEVT0   */
    DCFCTL_BIT_SRCSEL_DCAEVT1     = 1,  /*!< Source is DCAEVT1   */
    DCFCTL_BIT_SRCSEL_DCBEVT0     = 2,  /*!< Source is DCBEVT0   */
    DCFCTL_BIT_SRCSEL_DCBEVT1     = 3,  /*!< Source is DCBEVT1   */
} DCFCTL_BIT_SRCSEL;

#define DCFCTL_ALL_SRCSEL_DCAEVT0     ((0x0UL) << DCFCTL_ALL_SRCSEL_Pos)
#define DCFCTL_ALL_SRCSEL_DCAEVT1     ((0x1UL) << DCFCTL_ALL_SRCSEL_Pos)
#define DCFCTL_ALL_SRCSEL_DCBEVT0     ((0x2UL) << DCFCTL_ALL_SRCSEL_Pos)
#define DCFCTL_ALL_SRCSEL_DCBEVT1     ((0x3UL) << DCFCTL_ALL_SRCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          BLANKEN
 *  @access     PWM->DCFCTL.bit.BLANKEN
 *  @brief      blanking window
 */
#define DCFCTL_ALL_BLANKEN_Pos (2)
#define DCFCTL_ALL_BLANKEN_Msk (0x1UL << DCFCTL_ALL_BLANKEN_Pos)

typedef enum
{
    DCFCTL_BIT_BLANKEN_DISABLE     = 0,  /*!< Disable   */
    DCFCTL_BIT_BLANKEN_ENABLE      = 1,  /*!< Enable    */
} DCFCTL_BIT_BLANKEN;

#define DCFCTL_ALL_BLANKEN_DISABLE     ((0x0UL) << DCFCTL_ALL_BLANKEN_Pos)
#define DCFCTL_ALL_BLANKEN_ENABLE      ((0x1UL) << DCFCTL_ALL_BLANKEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          BLANKINV
 *  @access     PWM->DCFCTL.bit.BLANKINV
 *  @brief      blanking window inversion
 */
#define DCFCTL_ALL_BLANKINV_Pos (3)
#define DCFCTL_ALL_BLANKINV_Msk (0x1UL << DCFCTL_ALL_BLANKINV_Pos)

typedef enum
{
    DCFCTL_BIT_BLANKINV_DISABLE     = 0,  /*!< Disable   */
    DCFCTL_BIT_BLANKINV_ENABLE      = 1,  /*!< Enable    */
} DCFCTL_BIT_BLANKINV;

#define DCFCTL_ALL_BLANKINV_DISABLE     ((0x0UL) << DCFCTL_ALL_BLANKINV_Pos)
#define DCFCTL_ALL_BLANKINV_ENABLE      ((0x1UL) << DCFCTL_ALL_BLANKINV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          PULSESEL
 *  @access     PWM->DCFCTL.bit.PULSESEL
 *  @brief      Pulse select for blanking and capture alignment for this module
 */
#define DCFCTL_ALL_PULSESEL_Pos (4)
#define DCFCTL_ALL_PULSESEL_Msk (0x3UL << DCFCTL_ALL_PULSESEL_Pos)

typedef enum
{
    DCFCTL_BIT_PULSESEL_ALIGN_ON_ZERO            = 0,  /*!< Align on TBCNT=0                  */
    DCFCTL_BIT_PULSESEL_ALIGN_ON_PERIOD          = 1,  /*!< Align on TBCNT=TBPRD              */
    DCFCTL_BIT_PULSESEL_ALIGN_ON_ZERO_PERIOD     = 2,  /*!< Align on TBCNT=0 or TBCNT=TBPRD   */
} DCFCTL_BIT_PULSESEL;

#define DCFCTL_ALL_PULSESEL_ALIGN_ON_ZERO            ((0x0UL) << DCFCTL_ALL_PULSESEL_Pos)
#define DCFCTL_ALL_PULSESEL_ALIGN_ON_PERIOD          ((0x1UL) << DCFCTL_ALL_PULSESEL_Pos)
#define DCFCTL_ALL_PULSESEL_ALIGN_ON_ZERO_PERIOD     ((0x2UL) << DCFCTL_ALL_PULSESEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          WIN0EN
 *  @access     PWM->DCFCTL.bit.WIN0EN
 *  @brief      Enable blank window from PWM0 (ORed)
 */
#define DCFCTL_ALL_WIN0EN_Pos (6)
#define DCFCTL_ALL_WIN0EN_Msk (0x1UL << DCFCTL_ALL_WIN0EN_Pos)

typedef enum
{
    DCFCTL_BIT_WIN0EN_DISABLE     = 0,  /*!< Disable   */
    DCFCTL_BIT_WIN0EN_ENABLE      = 1,  /*!< Enable    */
} DCFCTL_BIT_WIN0EN;

#define DCFCTL_ALL_WIN0EN_DISABLE     ((0x0UL) << DCFCTL_ALL_WIN0EN_Pos)
#define DCFCTL_ALL_WIN0EN_ENABLE      ((0x1UL) << DCFCTL_ALL_WIN0EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          WIN1EN
 *  @access     PWM->DCFCTL.bit.WIN1EN
 *  @brief      Enable blank window from PWM1 (ORed)
 */
#define DCFCTL_ALL_WIN1EN_Pos (7)
#define DCFCTL_ALL_WIN1EN_Msk (0x1UL << DCFCTL_ALL_WIN1EN_Pos)

typedef enum
{
    DCFCTL_BIT_WIN1EN_DISABLE     = 0,  /*!< Disable   */
    DCFCTL_BIT_WIN1EN_ENABLE      = 1,  /*!< Enable    */
} DCFCTL_BIT_WIN1EN;

#define DCFCTL_ALL_WIN1EN_DISABLE     ((0x0UL) << DCFCTL_ALL_WIN1EN_Pos)
#define DCFCTL_ALL_WIN1EN_ENABLE      ((0x1UL) << DCFCTL_ALL_WIN1EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          WIN2EN
 *  @access     PWM->DCFCTL.bit.WIN2EN
 *  @brief      Enable blank window from PWM2 (ORed)
 */
#define DCFCTL_ALL_WIN2EN_Pos (8)
#define DCFCTL_ALL_WIN2EN_Msk (0x1UL << DCFCTL_ALL_WIN2EN_Pos)

typedef enum
{
    DCFCTL_BIT_WIN2EN_DISABLE     = 0,  /*!< Disable   */
    DCFCTL_BIT_WIN2EN_ENABLE      = 1,  /*!< Enable    */
} DCFCTL_BIT_WIN2EN;

#define DCFCTL_ALL_WIN2EN_DISABLE     ((0x0UL) << DCFCTL_ALL_WIN2EN_Pos)
#define DCFCTL_ALL_WIN2EN_ENABLE      ((0x1UL) << DCFCTL_ALL_WIN2EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          WIN3EN
 *  @access     PWM->DCFCTL.bit.WIN3EN
 *  @brief      Enable blank window from PWM3 (ORed)
 */
#define DCFCTL_ALL_WIN3EN_Pos (9)
#define DCFCTL_ALL_WIN3EN_Msk (0x1UL << DCFCTL_ALL_WIN3EN_Pos)

typedef enum
{
    DCFCTL_BIT_WIN3EN_DISABLE     = 0,  /*!< Disable   */
    DCFCTL_BIT_WIN3EN_ENABLE      = 1,  /*!< Enable    */
} DCFCTL_BIT_WIN3EN;

#define DCFCTL_ALL_WIN3EN_DISABLE     ((0x0UL) << DCFCTL_ALL_WIN3EN_Pos)
#define DCFCTL_ALL_WIN3EN_ENABLE      ((0x1UL) << DCFCTL_ALL_WIN3EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          WIN4EN
 *  @access     PWM->DCFCTL.bit.WIN4EN
 *  @brief      Enable blank window from PWM4 (ORed)
 */
#define DCFCTL_ALL_WIN4EN_Pos (10)
#define DCFCTL_ALL_WIN4EN_Msk (0x1UL << DCFCTL_ALL_WIN4EN_Pos)

typedef enum
{
    DCFCTL_BIT_WIN4EN_DISABLE     = 0,  /*!< Disable   */
    DCFCTL_BIT_WIN4EN_ENABLE      = 1,  /*!< Enable    */
} DCFCTL_BIT_WIN4EN;

#define DCFCTL_ALL_WIN4EN_DISABLE     ((0x0UL) << DCFCTL_ALL_WIN4EN_Pos)
#define DCFCTL_ALL_WIN4EN_ENABLE      ((0x1UL) << DCFCTL_ALL_WIN4EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFCTL          WIN5EN
 *  @access     PWM->DCFCTL.bit.WIN5EN
 *  @brief      Enable blank window from PWM5 (ORed)
 */
#define DCFCTL_ALL_WIN5EN_Pos (11)
#define DCFCTL_ALL_WIN5EN_Msk (0x1UL << DCFCTL_ALL_WIN5EN_Pos)

typedef enum
{
    DCFCTL_BIT_WIN5EN_DISABLE     = 0,  /*!< Disable   */
    DCFCTL_BIT_WIN5EN_ENABLE      = 1,  /*!< Enable    */
} DCFCTL_BIT_WIN5EN;

#define DCFCTL_ALL_WIN5EN_DISABLE     ((0x0UL) << DCFCTL_ALL_WIN5EN_Pos)
#define DCFCTL_ALL_WIN5EN_ENABLE      ((0x1UL) << DCFCTL_ALL_WIN5EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFOFFSET       VAL
 *  @access     PWM->DCFOFFSET.bit.VAL
 *  @brief      Blanking window offset
 *              It defines the number of TBCLK cycles from the blanking window reference specified
 *              by DCFCTL.PULSESEL to the point when the blanking window is applied.
 */
#define DCFOFFSET_ALL_VAL_Pos (0)
#define DCFOFFSET_ALL_VAL_Msk (0xFFFFUL << DCFOFFSET_ALL_VAL_Pos)

#define DCFOFFSET_BIT_VAL

#define DCFOFFSET_ALL_VAL_(x) ((x) << DCFOFFSET_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFOFFSETCNT    VAL
 *  @access     PWM->DCFOFFSETCNT.bit.VAL
 *  @brief      Blanking offset counter
 *              It is read only and indicates the current value of the offset counter. The counter
 *              counts down to zero and then stops until it is re-loaded on the next event defined
 *              by DCFCTL.PULSESEL.
 */
#define DCFOFFSETCNT_ALL_VAL_Pos (0)
#define DCFOFFSETCNT_ALL_VAL_Msk (0xFFFFUL << DCFOFFSETCNT_ALL_VAL_Pos)

#define DCFOFFSETCNT_BIT_VAL

#define DCFOFFSETCNT_ALL_VAL_(x) ((x) << DCFOFFSETCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFWINDOW       VAL
 *  @access     PWM->DCFWINDOW.bit.VAL
 *  @brief      Blanking window width in TBCLK cycles
 *              The blanking window begins when the offset counter expires. When this occurs, the
 *              window counter is loaded and begins to count down. If the blanking window is currently
 *              active and the offset counter expires, the blanking window counter is restarted.
 *              The blanking window can cross a PWM period boundary.
 *              No blanking window is generated when it is set to zero.
 */
#define DCFWINDOW_ALL_VAL_Pos (0)
#define DCFWINDOW_ALL_VAL_Msk (0xFFFFUL << DCFWINDOW_ALL_VAL_Pos)

#define DCFWINDOW_BIT_VAL

#define DCFWINDOW_ALL_VAL_(x) ((x) << DCFWINDOW_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCFWINDOWCNT    VAL
 *  @access     PWM->DCFWINDOWCNT.bit.VAL
 *  @brief      Blanking window counter
 *              It is read only and indicates the current value of the window counter. The counter
 *              counts down to zero and then stops until it is re-loaded when the offset counter
 *              reaches zero again.
 */
#define DCFWINDOWCNT_ALL_VAL_Pos (0)
#define DCFWINDOWCNT_ALL_VAL_Msk (0xFFFFUL << DCFWINDOWCNT_ALL_VAL_Pos)

#define DCFWINDOWCNT_BIT_VAL

#define DCFWINDOWCNT_ALL_VAL_(x) ((x) << DCFWINDOWCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCCAPCTL        CAPEN
 *  @access     PWM->DCCAPCTL.bit.CAPEN
 *  @brief      TBCNT counter capture enable
 */
#define DCCAPCTL_ALL_CAPEN_Pos (0)
#define DCCAPCTL_ALL_CAPEN_Msk (0x1UL << DCCAPCTL_ALL_CAPEN_Pos)

typedef enum
{
    DCCAPCTL_BIT_CAPEN_DISABLE     = 0,  /*!< Disable   */
    DCCAPCTL_BIT_CAPEN_ENABLE      = 1,  /*!< Enable    */
} DCCAPCTL_BIT_CAPEN;

#define DCCAPCTL_ALL_CAPEN_DISABLE     ((0x0UL) << DCCAPCTL_ALL_CAPEN_Pos)
#define DCCAPCTL_ALL_CAPEN_ENABLE      ((0x1UL) << DCCAPCTL_ALL_CAPEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCCAPCTL        DIRECT
 *  @access     PWM->DCCAPCTL.bit.DIRECT
 *  @brief      DCCAP direct load mode
 */
#define DCCAPCTL_ALL_DIRECT_Pos (1)
#define DCCAPCTL_ALL_DIRECT_Msk (0x1UL << DCCAPCTL_ALL_DIRECT_Pos)

typedef enum
{
    DCCAPCTL_BIT_DIRECT_DISABLE     = 0,  /*!< Shadow mode. The DCCAP active value is copied to shadow register on a TBCNT=TBPRD      
                                               or TBCNT=zero event as defined by DCFCTL.PULSESEL. Reads of the DCCAP register always  
                                               returns the shadow register contents.                                                   */
    DCCAPCTL_BIT_DIRECT_ENABLE      = 1,  /*!< Direct mode. Reads of the DCCAP register always returns the active value.               */
} DCCAPCTL_BIT_DIRECT;

#define DCCAPCTL_ALL_DIRECT_DISABLE     ((0x0UL) << DCCAPCTL_ALL_DIRECT_Pos)
#define DCCAPCTL_ALL_DIRECT_ENABLE      ((0x1UL) << DCCAPCTL_ALL_DIRECT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCCAPCTL        CAPCLR
 *  @access     PWM->DCCAPCTL.bit.CAPCLR
 *  @brief      Latched capture status clear
 */
#define DCCAPCTL_ALL_CAPCLR_Pos (2)
#define DCCAPCTL_ALL_CAPCLR_Msk (0x1UL << DCCAPCTL_ALL_CAPCLR_Pos)

typedef enum
{
    DCCAPCTL_BIT_CAPCLR_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0                    */
    DCCAPCTL_BIT_CAPCLR_CLEAR         = 1,  /*!< Write a 1 clears the latched status. This bit is self-cleared to 0   */
} DCCAPCTL_BIT_CAPCLR;

#define DCCAPCTL_ALL_CAPCLR_NO_EFFECT     ((0x0UL) << DCCAPCTL_ALL_CAPCLR_Pos)
#define DCCAPCTL_ALL_CAPCLR_CLEAR         ((0x1UL) << DCCAPCTL_ALL_CAPCLR_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCCAPCTL        CAPSTS
 *  @access     PWM->DCCAPCTL.bit.CAPSTS
 *  @brief      Latched capture status
 */
#define DCCAPCTL_ALL_CAPSTS_Pos (3)
#define DCCAPCTL_ALL_CAPSTS_Msk (0x1UL << DCCAPCTL_ALL_CAPSTS_Pos)

typedef enum
{
    DCCAPCTL_BIT_CAPSTS_NOT_OCCUR     = 0,  /*!< No DC capture event occurred    */
    DCCAPCTL_BIT_CAPSTS_OCCUR         = 1,  /*!< DC capture event has occurred   */
} DCCAPCTL_BIT_CAPSTS;

#define DCCAPCTL_ALL_CAPSTS_NOT_OCCUR     ((0x0UL) << DCCAPCTL_ALL_CAPSTS_Pos)
#define DCCAPCTL_ALL_CAPSTS_OCCUR         ((0x1UL) << DCCAPCTL_ALL_CAPSTS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             DCCAP           VAL
 *  @access     PWM->DCCAP.bit.VAL
 *  @brief      Captured TBCNT value upon a rising-edge of DCEVTFLT
 *              In shadow mode, the captured value is copied to the shadow register on a TBCNT=TBPRD
 *              or TBCNT=zero event as defined by DCFCTL.PULSESEL. Reads of the DCCAP register always
 *              returns the shadow register contents.
 *              In direct mode, reads of the DCCAP register always returns the active value.
 */
#define DCCAP_ALL_VAL_Pos (0)
#define DCCAP_ALL_VAL_Msk (0xFFFFUL << DCCAP_ALL_VAL_Pos)

#define DCCAP_BIT_VAL

#define DCCAP_ALL_VAL_(x) ((x) << DCCAP_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCTL           INTSEL
 *  @access     PWM->ETCTL.bit.INTSEL
 *  @brief      PWM interrupt select
 */
#define ETCTL_ALL_INTSEL_Pos (0)
#define ETCTL_ALL_INTSEL_Msk (0xFUL << ETCTL_ALL_INTSEL_Pos)

typedef enum
{
    ETCTL_BIT_INTSEL_TBCNT_EQU_ZERO            = 0,  /*!< Select event TBCNT=0                                  */
    ETCTL_BIT_INTSEL_TBCNT_EQU_PERIOD          = 1,  /*!< Select event TBCNT=TBPRD                              */
    ETCTL_BIT_INTSEL_TBCNT_EQU_ZERO_PERIOD     = 2,  /*!< Select event TBCNT=0 or TBCNT=TBPRD                   */
    ETCTL_BIT_INTSEL_TBCNT_EQU_CMPA_UP         = 3,  /*!< Select event TBCNT=CMPA when TBCNT is counting up     */
    ETCTL_BIT_INTSEL_TBCNT_EQU_CMPA_DOWN       = 4,  /*!< Select event TBCNT=CMPA when TBCNT is counting down   */
    ETCTL_BIT_INTSEL_TBCNT_EQU_CMPB_UP         = 5,  /*!< Select event TBCNT=CMPB when TBCNT is counting up     */
    ETCTL_BIT_INTSEL_TBCNT_EQU_CMPB_DOWN       = 6,  /*!< Select event TBCNT=CMPB when TBCNT is counting down   */
    ETCTL_BIT_INTSEL_TBCNT_EQU_CMPC_UP         = 7,  /*!< Select event TBCNT=CMPC when TBCNT is counting up     */
    ETCTL_BIT_INTSEL_TBCNT_EQU_CMPC_DOWN       = 8,  /*!< Select event TBCNT=CMPC when TBCNT is counting down   */
    ETCTL_BIT_INTSEL_TBCNT_EQU_CMPD_UP         = 9,  /*!< Select event TBCNT=CMPD when TBCNT is counting up     */
    ETCTL_BIT_INTSEL_TBCNT_EQU_CMPD_DOWN       = 10,  /*!< Select event TBCNT=CMPD when TBCNT is counting down   */
    ETCTL_BIT_INTSEL_DCAEVT0_SOC               = 11,  /*!< Select DCAEVT0.SOC event                              */
    ETCTL_BIT_INTSEL_DCBEVT0_SOC               = 12,  /*!< Select DCBEVT0.SOC event                              */
} ETCTL_BIT_INTSEL;

#define ETCTL_ALL_INTSEL_TBCNT_EQU_ZERO            ((0x00UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_PERIOD          ((0x01UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_ZERO_PERIOD     ((0x02UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_CMPA_UP         ((0x03UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_CMPA_DOWN       ((0x04UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_CMPB_UP         ((0x05UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_CMPB_DOWN       ((0x06UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_CMPC_UP         ((0x07UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_CMPC_DOWN       ((0x08UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_CMPD_UP         ((0x09UL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_TBCNT_EQU_CMPD_DOWN       ((0x0AUL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_DCAEVT0_SOC               ((0x0BUL) << ETCTL_ALL_INTSEL_Pos)
#define ETCTL_ALL_INTSEL_DCBEVT0_SOC               ((0x0CUL) << ETCTL_ALL_INTSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCTL           INTEN
 *  @access     PWM->ETCTL.bit.INTEN
 *  @brief      PWM interrupt enable
 */
#define ETCTL_ALL_INTEN_Pos (4)
#define ETCTL_ALL_INTEN_Msk (0x1UL << ETCTL_ALL_INTEN_Pos)

typedef enum
{
    ETCTL_BIT_INTEN_DISABLE     = 0,  /*!< Disable   */
    ETCTL_BIT_INTEN_ENABLE      = 1,  /*!< Enable    */
} ETCTL_BIT_INTEN;

#define ETCTL_ALL_INTEN_DISABLE     ((0x0UL) << ETCTL_ALL_INTEN_Pos)
#define ETCTL_ALL_INTEN_ENABLE      ((0x1UL) << ETCTL_ALL_INTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCTL           SOCASEL
 *  @access     PWM->ETCTL.bit.SOCASEL
 *  @brief      SOCA event select
 */
#define ETCTL_ALL_SOCASEL_Pos (5)
#define ETCTL_ALL_SOCASEL_Msk (0xFUL << ETCTL_ALL_SOCASEL_Pos)

typedef enum
{
    ETCTL_BIT_SOCASEL_TBCNT_EQU_ZERO            = 0,  /*!< Select event TBCNT=0                                  */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_PERIOD          = 1,  /*!< Select event TBCNT=TBPRD                              */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_ZERO_PERIOD     = 2,  /*!< Select event TBCNT=0 or TBCNT=TBPRD                   */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_CMPA_UP         = 3,  /*!< Select event TBCNT=CMPA when TBCNT is counting up     */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_CMPA_DOWN       = 4,  /*!< Select event TBCNT=CMPA when TBCNT is counting down   */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_CMPB_UP         = 5,  /*!< Select event TBCNT=CMPB when TBCNT is counting up     */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_CMPB_DOWN       = 6,  /*!< Select event TBCNT=CMPB when TBCNT is counting down   */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_CMPC_UP         = 7,  /*!< Select event TBCNT=CMPC when TBCNT is counting up     */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_CMPC_DOWN       = 8,  /*!< Select event TBCNT=CMPC when TBCNT is counting down   */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_CMPD_UP         = 9,  /*!< Select event TBCNT=CMPD when TBCNT is counting up     */
    ETCTL_BIT_SOCASEL_TBCNT_EQU_CMPD_DOWN       = 10,  /*!< Select event TBCNT=CMPD when TBCNT is counting down   */
    ETCTL_BIT_SOCASEL_DCAEVT0_SOC               = 11,  /*!< Select DCAEVT0.SOC event                              */
    ETCTL_BIT_SOCASEL_DCBEVT0_SOC               = 12,  /*!< Select DCBEVT0.SOC event                              */
} ETCTL_BIT_SOCASEL;

#define ETCTL_ALL_SOCASEL_TBCNT_EQU_ZERO            ((0x00UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_PERIOD          ((0x01UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_ZERO_PERIOD     ((0x02UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_CMPA_UP         ((0x03UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_CMPA_DOWN       ((0x04UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_CMPB_UP         ((0x05UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_CMPB_DOWN       ((0x06UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_CMPC_UP         ((0x07UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_CMPC_DOWN       ((0x08UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_CMPD_UP         ((0x09UL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_TBCNT_EQU_CMPD_DOWN       ((0x0AUL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_DCAEVT0_SOC               ((0x0BUL) << ETCTL_ALL_SOCASEL_Pos)
#define ETCTL_ALL_SOCASEL_DCBEVT0_SOC               ((0x0CUL) << ETCTL_ALL_SOCASEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCTL           SOCAEN
 *  @access     PWM->ETCTL.bit.SOCAEN
 *  @brief      ADC start of conversion A (SOCA) pulse enable
 */
#define ETCTL_ALL_SOCAEN_Pos (9)
#define ETCTL_ALL_SOCAEN_Msk (0x1UL << ETCTL_ALL_SOCAEN_Pos)

typedef enum
{
    ETCTL_BIT_SOCAEN_DISABLE     = 0,  /*!< Disable   */
    ETCTL_BIT_SOCAEN_ENABLE      = 1,  /*!< Enable    */
} ETCTL_BIT_SOCAEN;

#define ETCTL_ALL_SOCAEN_DISABLE     ((0x0UL) << ETCTL_ALL_SOCAEN_Pos)
#define ETCTL_ALL_SOCAEN_ENABLE      ((0x1UL) << ETCTL_ALL_SOCAEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCTL           SOCBSEL
 *  @access     PWM->ETCTL.bit.SOCBSEL
 *  @brief      SOCB event select
 */
#define ETCTL_ALL_SOCBSEL_Pos (10)
#define ETCTL_ALL_SOCBSEL_Msk (0xFUL << ETCTL_ALL_SOCBSEL_Pos)

typedef enum
{
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_ZERO            = 0,  /*!< Select event TBCNT=0                                  */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_PERIOD          = 1,  /*!< Select event TBCNT=TBPRD                              */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_ZERO_PERIOD     = 2,  /*!< Select event TBCNT=0 or TBCNT=TBPRD                   */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_CMPA_UP         = 3,  /*!< Select event TBCNT=CMPA when TBCNT is counting up     */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_CMPA_DOWN       = 4,  /*!< Select event TBCNT=CMPA when TBCNT is counting down   */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_CMPB_UP         = 5,  /*!< Select event TBCNT=CMPB when TBCNT is counting up     */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_CMPB_DOWN       = 6,  /*!< Select event TBCNT=CMPB when TBCNT is counting down   */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_CMPC_UP         = 7,  /*!< Select event TBCNT=CMPC when TBCNT is counting up     */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_CMPC_DOWN       = 8,  /*!< Select event TBCNT=CMPC when TBCNT is counting down   */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_CMPD_UP         = 9,  /*!< Select event TBCNT=CMPD when TBCNT is counting up     */
    ETCTL_BIT_SOCBSEL_TBCNT_EQU_CMPD_DOWN       = 10,  /*!< Select event TBCNT=CMPD when TBCNT is counting down   */
    ETCTL_BIT_SOCBSEL_DCAEVT0_SOC               = 11,  /*!< Select DCAEVT0.SOC event                              */
    ETCTL_BIT_SOCBSEL_DCBEVT0_SOC               = 12,  /*!< Select DCBEVT0.SOC event                              */
} ETCTL_BIT_SOCBSEL;

#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_ZERO            ((0x00UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_PERIOD          ((0x01UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_ZERO_PERIOD     ((0x02UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_CMPA_UP         ((0x03UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_CMPA_DOWN       ((0x04UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_CMPB_UP         ((0x05UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_CMPB_DOWN       ((0x06UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_CMPC_UP         ((0x07UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_CMPC_DOWN       ((0x08UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_CMPD_UP         ((0x09UL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_TBCNT_EQU_CMPD_DOWN       ((0x0AUL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_DCAEVT0_SOC               ((0x0BUL) << ETCTL_ALL_SOCBSEL_Pos)
#define ETCTL_ALL_SOCBSEL_DCBEVT0_SOC               ((0x0CUL) << ETCTL_ALL_SOCBSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCTL           SOCBEN
 *  @access     PWM->ETCTL.bit.SOCBEN
 *  @brief      ADC start of conversion B (SOCB) pulse enable
 */
#define ETCTL_ALL_SOCBEN_Pos (14)
#define ETCTL_ALL_SOCBEN_Msk (0x1UL << ETCTL_ALL_SOCBEN_Pos)

typedef enum
{
    ETCTL_BIT_SOCBEN_DISABLE     = 0,  /*!< Disable   */
    ETCTL_BIT_SOCBEN_ENABLE      = 1,  /*!< Enable    */
} ETCTL_BIT_SOCBEN;

#define ETCTL_ALL_SOCBEN_DISABLE     ((0x0UL) << ETCTL_ALL_SOCBEN_Pos)
#define ETCTL_ALL_SOCBEN_ENABLE      ((0x1UL) << ETCTL_ALL_SOCBEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCTL           SOCCSEL
 *  @access     PWM->ETCTL.bit.SOCCSEL
 *  @brief      SOCC event select
 */
#define ETCTL_ALL_SOCCSEL_Pos (15)
#define ETCTL_ALL_SOCCSEL_Msk (0xFUL << ETCTL_ALL_SOCCSEL_Pos)

typedef enum
{
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_ZERO            = 0,  /*!< Enable event TBCNT=0                                  */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_PERIOD          = 1,  /*!< Enable event TBCNT=TBPRD                              */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_ZERO_PERIOD     = 2,  /*!< Enable event TBCNT=0 or TBCNT=TBPRD                   */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_CMPA_UP         = 3,  /*!< Enable event TBCNT=CMPA when TBCNT is counting up     */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_CMPA_DOWN       = 4,  /*!< Enable event TBCNT=CMPA when TBCNT is counting down   */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_CMPB_UP         = 5,  /*!< Enable event TBCNT=CMPB when TBCNT is counting up     */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_CMPB_DOWN       = 6,  /*!< Enable event TBCNT=CMPB when TBCNT is counting down   */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_CMPC_UP         = 7,  /*!< Enable event TBCNT=CMPC when TBCNT is counting up     */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_CMPC_DOWN       = 8,  /*!< Enable event TBCNT=CMPC when TBCNT is counting down   */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_CMPD_UP         = 9,  /*!< Enable event TBCNT=CMPD when TBCNT is counting up     */
    ETCTL_BIT_SOCCSEL_TBCNT_EQU_CMPD_DOWN       = 10,  /*!< Enable event TBCNT=CMPD when TBCNT is counting down   */
    ETCTL_BIT_SOCCSEL_DCAEVT0_SOC               = 11,  /*!< Enable DCAEVT0.SOC event                              */
    ETCTL_BIT_SOCCSEL_DCBEVT0_SOC               = 12,  /*!< Enable DCBEVT0.SOC event                              */
} ETCTL_BIT_SOCCSEL;

#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_ZERO            ((0x00UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_PERIOD          ((0x01UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_ZERO_PERIOD     ((0x02UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_CMPA_UP         ((0x03UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_CMPA_DOWN       ((0x04UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_CMPB_UP         ((0x05UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_CMPB_DOWN       ((0x06UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_CMPC_UP         ((0x07UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_CMPC_DOWN       ((0x08UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_CMPD_UP         ((0x09UL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_TBCNT_EQU_CMPD_DOWN       ((0x0AUL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_DCAEVT0_SOC               ((0x0BUL) << ETCTL_ALL_SOCCSEL_Pos)
#define ETCTL_ALL_SOCCSEL_DCBEVT0_SOC               ((0x0CUL) << ETCTL_ALL_SOCCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCTL           SOCCEN
 *  @access     PWM->ETCTL.bit.SOCCEN
 *  @brief      ADC start of conversion C (SOCC) pulse enable
 */
#define ETCTL_ALL_SOCCEN_Pos (19)
#define ETCTL_ALL_SOCCEN_Msk (0x1UL << ETCTL_ALL_SOCCEN_Pos)

typedef enum
{
    ETCTL_BIT_SOCCEN_DISABLE     = 0,  /*!< Disable   */
    ETCTL_BIT_SOCCEN_ENABLE      = 1,  /*!< Enable    */
} ETCTL_BIT_SOCCEN;

#define ETCTL_ALL_SOCCEN_DISABLE     ((0x0UL) << ETCTL_ALL_SOCCEN_Pos)
#define ETCTL_ALL_SOCCEN_ENABLE      ((0x1UL) << ETCTL_ALL_SOCCEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETPS            INTPRD
 *  @access     PWM->ETPS.bit.INTPRD
 *  @brief      PWM interrupt period select
 *              Interrupt is generated upon INTPRD<=INTCNT and ETCTL[INTEN]=1. No interrupt will
 *              be generated if INTPRD=0
 */
#define ETPS_ALL_INTPRD_Pos (0)
#define ETPS_ALL_INTPRD_Msk (0xFUL << ETPS_ALL_INTPRD_Pos)

typedef enum
{
    ETPS_BIT_INTPRD_DISABLE                   = 0,  /*!< Disable the interrupt event counter. No interrupt will be generated and ETFRC.INT  
                                                         is ignored.                                                                         */
    ETPS_BIT_INTPRD_GEN_INT_ON_1ST_EVENT      = 1,  /*!< Generate an interrupt when ETPS.INTCNT=0001 (first event)                           */
    ETPS_BIT_INTPRD_GEN_INT_ON_2ND_EVENT      = 2,  /*!< Generate an interrupt when ETPS.INTCNT=0010 (second event)                          */
    ETPS_BIT_INTPRD_GEN_INT_ON_3RD_EVENT      = 3,  /*!< Generate an interrupt when ETPS.INTCNT=0011 (third event)                           */
    ETPS_BIT_INTPRD_GEN_INT_ON_4TH_EVENT      = 4,  /*!< Generate an interrupt when ETPS.INTCNT=0100 (fourth event)                          */
    ETPS_BIT_INTPRD_GEN_INT_ON_5TH_EVENT      = 5,  /*!< Generate an interrupt when ETPS.INTCNT=0101 (fifth event)                           */
    ETPS_BIT_INTPRD_GEN_INT_ON_6TH_EVENT      = 6,  /*!< Generate an interrupt when ETPS.INTCNT=0110(sixth event)                            */
    ETPS_BIT_INTPRD_GEN_INT_ON_7TH_EVENT      = 7,  /*!< Generate an interrupt when ETPS.INTCNT=0111 (seventh event)                         */
    ETPS_BIT_INTPRD_GEN_INT_ON_8TH_EVENT      = 8,  /*!< Generate an interrupt when ETPS.INTCNT=1000 (eighth event)                          */
    ETPS_BIT_INTPRD_GEN_INT_ON_9TH_EVENT      = 9,  /*!< Generate an interrupt when ETPS.INTCNT=1001 (ninth event)                           */
    ETPS_BIT_INTPRD_GEN_INT_ON_10TH_EVENT     = 10,  /*!< Generate an interrupt when ETPS.INTCNT=1010 (tenth event)                           */
    ETPS_BIT_INTPRD_GEN_INT_ON_11TH_EVENT     = 11,  /*!< Generate an interrupt when ETPS.INTCNT=1011 (eleventh event)                        */
    ETPS_BIT_INTPRD_GEN_INT_ON_12TH_EVENT     = 12,  /*!< Generate an interrupt when ETPS.INTCNT=1100(twelfth event)                          */
    ETPS_BIT_INTPRD_GEN_INT_ON_13TH_EVENT     = 13,  /*!< Generate an interrupt when ETPS.INTCNT=1101 (thirteenth event)                      */
    ETPS_BIT_INTPRD_GEN_INT_ON_14TH_EVENT     = 14,  /*!< Generate an interrupt when ETPS.INTCNT=1110(fourteenth event)                       */
    ETPS_BIT_INTPRD_GEN_INT_ON_15TH_EVENT     = 15,  /*!< Generate an interrupt when ETPS.INTCNT=1111 (fifteenth event)                       */
} ETPS_BIT_INTPRD;

#define ETPS_ALL_INTPRD_DISABLE                   ((0x00UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_1ST_EVENT      ((0x01UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_2ND_EVENT      ((0x02UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_3RD_EVENT      ((0x03UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_4TH_EVENT      ((0x04UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_5TH_EVENT      ((0x05UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_6TH_EVENT      ((0x06UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_7TH_EVENT      ((0x07UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_8TH_EVENT      ((0x08UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_9TH_EVENT      ((0x09UL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_10TH_EVENT     ((0x0AUL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_11TH_EVENT     ((0x0BUL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_12TH_EVENT     ((0x0CUL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_13TH_EVENT     ((0x0DUL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_14TH_EVENT     ((0x0EUL) << ETPS_ALL_INTPRD_Pos)
#define ETPS_ALL_INTPRD_GEN_INT_ON_15TH_EVENT     ((0x0FUL) << ETPS_ALL_INTPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETPS            INTCNT
 *  @access     PWM->ETPS.bit.INTCNT
 *  @brief      PWM interrupt counter
 *              It indicates how many selected ETSEL.INTSEL events have occurred. It is automatically
 *              cleared when an interrupt pulse is generated.
 *              It can be initialized via write.
 */
#define ETPS_ALL_INTCNT_Pos (4)
#define ETPS_ALL_INTCNT_Msk (0xFUL << ETPS_ALL_INTCNT_Pos)

typedef enum
{
    ETPS_BIT_INTCNT_NO_EVENT_OCCUR     = 0,  /*!< No events have occurred   */
    ETPS_BIT_INTCNT_1_EVENT_OCCUR      = 1,  /*!< 1 event has occurred      */
    ETPS_BIT_INTCNT_2_EVENT_OCCUR      = 2,  /*!< 2 events have occurred    */
    ETPS_BIT_INTCNT_3_EVENT_OCCUR      = 3,  /*!< 3 events have occurred    */
    ETPS_BIT_INTCNT_4_EVENT_OCCUR      = 4,  /*!< 4 events have occurred    */
    ETPS_BIT_INTCNT_5_EVENT_OCCUR      = 5,  /*!< 5 events have occurred    */
    ETPS_BIT_INTCNT_6_EVENT_OCCUR      = 6,  /*!< 6 events have occurred    */
    ETPS_BIT_INTCNT_7_EVENT_OCCUR      = 7,  /*!< 7 events have occurred    */
    ETPS_BIT_INTCNT_8_EVENT_OCCUR      = 8,  /*!< 8 events have occurred    */
    ETPS_BIT_INTCNT_9_EVENT_OCCUR      = 9,  /*!< 9 events have occurred    */
    ETPS_BIT_INTCNT_10_EVENT_OCCUR     = 10,  /*!< 10 events have occurred   */
    ETPS_BIT_INTCNT_11_EVENT_OCCUR     = 11,  /*!< 11 events have occurred   */
    ETPS_BIT_INTCNT_12_EVENT_OCCUR     = 12,  /*!< 12 events have occurred   */
    ETPS_BIT_INTCNT_13_EVENT_OCCUR     = 13,  /*!< 13 events have occurred   */
    ETPS_BIT_INTCNT_14_EVENT_OCCUR     = 14,  /*!< 14 events have occurred   */
    ETPS_BIT_INTCNT_15_EVENT_OCCUR     = 15,  /*!< 15 events have occurred   */
} ETPS_BIT_INTCNT;

#define ETPS_ALL_INTCNT_NO_EVENT_OCCUR     ((0x00UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_1_EVENT_OCCUR      ((0x01UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_2_EVENT_OCCUR      ((0x02UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_3_EVENT_OCCUR      ((0x03UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_4_EVENT_OCCUR      ((0x04UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_5_EVENT_OCCUR      ((0x05UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_6_EVENT_OCCUR      ((0x06UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_7_EVENT_OCCUR      ((0x07UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_8_EVENT_OCCUR      ((0x08UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_9_EVENT_OCCUR      ((0x09UL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_10_EVENT_OCCUR     ((0x0AUL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_11_EVENT_OCCUR     ((0x0BUL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_12_EVENT_OCCUR     ((0x0CUL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_13_EVENT_OCCUR     ((0x0DUL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_14_EVENT_OCCUR     ((0x0EUL) << ETPS_ALL_INTCNT_Pos)
#define ETPS_ALL_INTCNT_15_EVENT_OCCUR     ((0x0FUL) << ETPS_ALL_INTCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETPS            SOCAPRD
 *  @access     PWM->ETPS.bit.SOCAPRD
 *  @brief      PWM ADC start-of-conversion A event (SOCA) period select
 *              SOCA is generated upon SOCAPRD<=SOCACNT and ETCTL[SOCAEN]=1. No SOCA will be generated
 *              if SOCAPRD=0
 */
#define ETPS_ALL_SOCAPRD_Pos (8)
#define ETPS_ALL_SOCAPRD_Msk (0xFUL << ETPS_ALL_SOCAPRD_Pos)

typedef enum
{
    ETPS_BIT_SOCAPRD_GEN_SOCA_DISABLE           = 0,  /*!< Disable SOCA event counter. No SOCA pulse will be generated.    */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_1ST_EVENT      = 1,  /*!< Generate SOCA pulse when ETPS.SOCACNT=01 (first event)          */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_2ND_EVENT      = 2,  /*!< Generate SOCA pulse when ETPS.SOCACNT=10 (second event)         */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_3RD_EVENT      = 3,  /*!< Generate SOCA pulse when ETPS.SOCACNT=11 (third event)          */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_4TH_EVENT      = 4,  /*!< Generate SOCA pulse when ETPS.SOCACNT=0100 (fourth event)       */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_5TH_EVENT      = 5,  /*!< Generate SOCA pulse when ETPS.SOCACNT=0101 (fifth event)        */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_6TH_EVENT      = 6,  /*!< Generate SOCA pulse when ETPS.SOCACNT=0110(sixth event)         */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_7TH_EVENT      = 7,  /*!< Generate SOCA pulse when ETPS.SOCACNT=0111 (seventh event)      */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_8TH_EVENT      = 8,  /*!< Generate SOCA pulse when ETPS.SOCACNT=1000 (eighth event)       */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_9TH_EVENT      = 9,  /*!< Generate SOCA pulse when ETPS.SOCACNT=1001 (ninth event)        */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_10TH_EVENT     = 10,  /*!< Generate SOCA pulse when ETPS.SOCACNT=1010 (tenth event)        */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_11TH_EVENT     = 11,  /*!< Generate SOCA pulse when ETPS.SOCACNT=1011 (eleventh event)     */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_12TH_EVENT     = 12,  /*!< Generate SOCA pulse when ETPS.SOCACNT=1100(twelfth event)       */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_13TH_EVENT     = 13,  /*!< Generate SOCA pulse when ETPS.SOCACNT=1101 (thirteenth event)   */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_14TH_EVENT     = 14,  /*!< Generate SOCA pulse when ETPS.SOCACNT=1110(fourteenth event)    */
    ETPS_BIT_SOCAPRD_GEN_SOCA_ON_15TH_EVENT     = 15,  /*!< Generate SOCA pulse when ETPS.SOCACNT=1111 (fifteenth event)    */
} ETPS_BIT_SOCAPRD;

#define ETPS_ALL_SOCAPRD_GEN_SOCA_DISABLE           ((0x00UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_1ST_EVENT      ((0x01UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_2ND_EVENT      ((0x02UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_3RD_EVENT      ((0x03UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_4TH_EVENT      ((0x04UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_5TH_EVENT      ((0x05UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_6TH_EVENT      ((0x06UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_7TH_EVENT      ((0x07UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_8TH_EVENT      ((0x08UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_9TH_EVENT      ((0x09UL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_10TH_EVENT     ((0x0AUL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_11TH_EVENT     ((0x0BUL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_12TH_EVENT     ((0x0CUL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_13TH_EVENT     ((0x0DUL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_14TH_EVENT     ((0x0EUL) << ETPS_ALL_SOCAPRD_Pos)
#define ETPS_ALL_SOCAPRD_GEN_SOCA_ON_15TH_EVENT     ((0x0FUL) << ETPS_ALL_SOCAPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETPS            SOCACNT
 *  @access     PWM->ETPS.bit.SOCACNT
 *  @brief      PWM ADC start-of-conversion A event (SOCA) counter
 *              It indicates how many selected ETSEL.SOCASEL events have occurred. It is automatically
 *              cleared when an SOCA pulse is generated.
 *              It can be initialized via write.
 */
#define ETPS_ALL_SOCACNT_Pos (12)
#define ETPS_ALL_SOCACNT_Msk (0xFUL << ETPS_ALL_SOCACNT_Pos)

typedef enum
{
    ETPS_BIT_SOCACNT_NO_EVENT_OCCUR     = 0,  /*!< No events have occurred   */
    ETPS_BIT_SOCACNT_1_EVENT_OCCUR      = 1,  /*!< 1 event has occurred      */
    ETPS_BIT_SOCACNT_2_EVENT_OCCUR      = 2,  /*!< 2 events have occurred    */
    ETPS_BIT_SOCACNT_3_EVENT_OCCUR      = 3,  /*!< 3 events have occurred    */
    ETPS_BIT_SOCACNT_4_EVENT_OCCUR      = 4,  /*!< 4 events have occurred    */
    ETPS_BIT_SOCACNT_5_EVENT_OCCUR      = 5,  /*!< 5 events have occurred    */
    ETPS_BIT_SOCACNT_6_EVENT_OCCUR      = 6,  /*!< 6 events have occurred    */
    ETPS_BIT_SOCACNT_7_EVENT_OCCUR      = 7,  /*!< 7 events have occurred    */
    ETPS_BIT_SOCACNT_8_EVENT_OCCUR      = 8,  /*!< 8 events have occurred    */
    ETPS_BIT_SOCACNT_9_EVENT_OCCUR      = 9,  /*!< 9 events have occurred    */
    ETPS_BIT_SOCACNT_10_EVENT_OCCUR     = 10,  /*!< 10 events have occurred   */
    ETPS_BIT_SOCACNT_11_EVENT_OCCUR     = 11,  /*!< 11 events have occurred   */
    ETPS_BIT_SOCACNT_12_EVENT_OCCUR     = 12,  /*!< 12 events have occurred   */
    ETPS_BIT_SOCACNT_13_EVENT_OCCUR     = 13,  /*!< 13 events have occurred   */
    ETPS_BIT_SOCACNT_14_EVENT_OCCUR     = 14,  /*!< 14 events have occurred   */
    ETPS_BIT_SOCACNT_15_EVENT_OCCUR     = 15,  /*!< 15 events have occurred   */
} ETPS_BIT_SOCACNT;

#define ETPS_ALL_SOCACNT_NO_EVENT_OCCUR     ((0x00UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_1_EVENT_OCCUR      ((0x01UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_2_EVENT_OCCUR      ((0x02UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_3_EVENT_OCCUR      ((0x03UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_4_EVENT_OCCUR      ((0x04UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_5_EVENT_OCCUR      ((0x05UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_6_EVENT_OCCUR      ((0x06UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_7_EVENT_OCCUR      ((0x07UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_8_EVENT_OCCUR      ((0x08UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_9_EVENT_OCCUR      ((0x09UL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_10_EVENT_OCCUR     ((0x0AUL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_11_EVENT_OCCUR     ((0x0BUL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_12_EVENT_OCCUR     ((0x0CUL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_13_EVENT_OCCUR     ((0x0DUL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_14_EVENT_OCCUR     ((0x0EUL) << ETPS_ALL_SOCACNT_Pos)
#define ETPS_ALL_SOCACNT_15_EVENT_OCCUR     ((0x0FUL) << ETPS_ALL_SOCACNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETPS            SOCBPRD
 *  @access     PWM->ETPS.bit.SOCBPRD
 *  @brief      PWM ADC start-of-conversion B event (SOCB) period select
 *              SOCB is generated upon SOCBPRD<=SOCBCNT and ETCTL[SOCBEN]=1. No SOCB will be generated
 *              if SOCBPRD=0
 */
#define ETPS_ALL_SOCBPRD_Pos (16)
#define ETPS_ALL_SOCBPRD_Msk (0xFUL << ETPS_ALL_SOCBPRD_Pos)

typedef enum
{
    ETPS_BIT_SOCBPRD_GEN_SOCB_DISABLE           = 0,  /*!< Disable SOCB event counter. No SOCB pulse will be generated.    */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_1ST_EVENT      = 1,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=0001 (first event)        */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_2ND_EVENT      = 2,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=0010 (second event)       */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_3RD_EVENT      = 3,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=0011 (third event)        */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_4TH_EVENT      = 4,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=0100 (fourth event)       */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_5TH_EVENT      = 5,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=0101 (fifth event)        */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_6TH_EVENT      = 6,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=0110(sixth event)         */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_7TH_EVENT      = 7,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=0111 (seventh event)      */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_8TH_EVENT      = 8,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=1000 (eighth event)       */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_9TH_EVENT      = 9,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=1001 (ninth event)        */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_10TH_EVENT     = 10,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=1010 (tenth event)        */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_11TH_EVENT     = 11,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=1011 (eleventh event)     */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_12TH_EVENT     = 12,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=1100(twelfth event)       */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_13TH_EVENT     = 13,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=1101 (thirteenth event)   */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_14TH_EVENT     = 14,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=1110(fourteenth event)    */
    ETPS_BIT_SOCBPRD_GEN_SOCB_ON_15TH_EVENT     = 15,  /*!< Generate SOCB pulse when ETPS.SOCBCNT=1111 (fifteenth event)    */
} ETPS_BIT_SOCBPRD;

#define ETPS_ALL_SOCBPRD_GEN_SOCB_DISABLE           ((0x00UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_1ST_EVENT      ((0x01UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_2ND_EVENT      ((0x02UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_3RD_EVENT      ((0x03UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_4TH_EVENT      ((0x04UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_5TH_EVENT      ((0x05UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_6TH_EVENT      ((0x06UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_7TH_EVENT      ((0x07UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_8TH_EVENT      ((0x08UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_9TH_EVENT      ((0x09UL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_10TH_EVENT     ((0x0AUL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_11TH_EVENT     ((0x0BUL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_12TH_EVENT     ((0x0CUL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_13TH_EVENT     ((0x0DUL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_14TH_EVENT     ((0x0EUL) << ETPS_ALL_SOCBPRD_Pos)
#define ETPS_ALL_SOCBPRD_GEN_SOCB_ON_15TH_EVENT     ((0x0FUL) << ETPS_ALL_SOCBPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETPS            SOCBCNT
 *  @access     PWM->ETPS.bit.SOCBCNT
 *  @brief      PWM ADC start-of-conversion B event (SOCB) counter
 *              It indicates how many selected ETSEL.SOCBSEL events have occurred. It is automatically
 *              cleared when an SOCB pulse is generated.
 *              It can be initialized via write.
 */
#define ETPS_ALL_SOCBCNT_Pos (20)
#define ETPS_ALL_SOCBCNT_Msk (0xFUL << ETPS_ALL_SOCBCNT_Pos)

typedef enum
{
    ETPS_BIT_SOCBCNT_NO_EVENT_OCCUR     = 0,  /*!< No events have occurred   */
    ETPS_BIT_SOCBCNT_1_EVENT_OCCUR      = 1,  /*!< 1 event has occurred      */
    ETPS_BIT_SOCBCNT_2_EVENT_OCCUR      = 2,  /*!< 2 events have occurred    */
    ETPS_BIT_SOCBCNT_3_EVENT_OCCUR      = 3,  /*!< 3 events have occurred    */
    ETPS_BIT_SOCBCNT_4_EVENT_OCCUR      = 4,  /*!< 4 events have occurred    */
    ETPS_BIT_SOCBCNT_5_EVENT_OCCUR      = 5,  /*!< 5 events have occurred    */
    ETPS_BIT_SOCBCNT_6_EVENT_OCCUR      = 6,  /*!< 6 events have occurred    */
    ETPS_BIT_SOCBCNT_7_EVENT_OCCUR      = 7,  /*!< 7 events have occurred    */
    ETPS_BIT_SOCBCNT_8_EVENT_OCCUR      = 8,  /*!< 8 events have occurred    */
    ETPS_BIT_SOCBCNT_9_EVENT_OCCUR      = 9,  /*!< 9 events have occurred    */
    ETPS_BIT_SOCBCNT_10_EVENT_OCCUR     = 10,  /*!< 10 events have occurred   */
    ETPS_BIT_SOCBCNT_11_EVENT_OCCUR     = 11,  /*!< 11 events have occurred   */
    ETPS_BIT_SOCBCNT_12_EVENT_OCCUR     = 12,  /*!< 12 events have occurred   */
    ETPS_BIT_SOCBCNT_13_EVENT_OCCUR     = 13,  /*!< 13 events have occurred   */
    ETPS_BIT_SOCBCNT_14_EVENT_OCCUR     = 14,  /*!< 14 events have occurred   */
    ETPS_BIT_SOCBCNT_15_EVENT_OCCUR     = 15,  /*!< 15 events have occurred   */
} ETPS_BIT_SOCBCNT;

#define ETPS_ALL_SOCBCNT_NO_EVENT_OCCUR     ((0x00UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_1_EVENT_OCCUR      ((0x01UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_2_EVENT_OCCUR      ((0x02UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_3_EVENT_OCCUR      ((0x03UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_4_EVENT_OCCUR      ((0x04UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_5_EVENT_OCCUR      ((0x05UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_6_EVENT_OCCUR      ((0x06UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_7_EVENT_OCCUR      ((0x07UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_8_EVENT_OCCUR      ((0x08UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_9_EVENT_OCCUR      ((0x09UL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_10_EVENT_OCCUR     ((0x0AUL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_11_EVENT_OCCUR     ((0x0BUL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_12_EVENT_OCCUR     ((0x0CUL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_13_EVENT_OCCUR     ((0x0DUL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_14_EVENT_OCCUR     ((0x0EUL) << ETPS_ALL_SOCBCNT_Pos)
#define ETPS_ALL_SOCBCNT_15_EVENT_OCCUR     ((0x0FUL) << ETPS_ALL_SOCBCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETPS            SOCCPRD
 *  @access     PWM->ETPS.bit.SOCCPRD
 *  @brief      PWM ADC start-of-conversion C event (SOCC) period select
 *              SOCC is generated upon SOCCPRD<=SOCCCNT and ETCTL[SOCCEN]=1. No SOCC will be generated
 *              if SOCCPRD=0
 */
#define ETPS_ALL_SOCCPRD_Pos (24)
#define ETPS_ALL_SOCCPRD_Msk (0xFUL << ETPS_ALL_SOCCPRD_Pos)

typedef enum
{
    ETPS_BIT_SOCCPRD_GEN_SOCC_DISABLE           = 0,  /*!< Disable SOCC event counter. No SOCC pulse will be generated.    */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_1ST_EVENT      = 1,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=0001 (first event)        */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_2ND_EVENT      = 2,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=0010 (second event)       */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_3RD_EVENT      = 3,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=0011 (third event)        */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_4TH_EVENT      = 4,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=0100 (fourth event)       */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_5TH_EVENT      = 5,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=0101 (fifth event)        */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_6TH_EVENT      = 6,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=0110(sixth event)         */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_7TH_EVENT      = 7,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=0111 (seventh event)      */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_8TH_EVENT      = 8,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=1000 (eighth event)       */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_9TH_EVENT      = 9,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=1001 (ninth event)        */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_10TH_EVENT     = 10,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=1010 (tenth event)        */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_11TH_EVENT     = 11,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=1011 (eleventh event)     */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_12TH_EVENT     = 12,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=1100(twelfth event)       */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_13TH_EVENT     = 13,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=1101 (thirteenth event)   */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_14TH_EVENT     = 14,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=1110(fourteenth event)    */
    ETPS_BIT_SOCCPRD_GEN_SOCC_ON_15TH_EVENT     = 15,  /*!< Generate SOCC pulse when ETPS.SOCCCNT=1111 (fifteenth event)    */
} ETPS_BIT_SOCCPRD;

#define ETPS_ALL_SOCCPRD_GEN_SOCC_DISABLE           ((0x00UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_1ST_EVENT      ((0x01UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_2ND_EVENT      ((0x02UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_3RD_EVENT      ((0x03UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_4TH_EVENT      ((0x04UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_5TH_EVENT      ((0x05UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_6TH_EVENT      ((0x06UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_7TH_EVENT      ((0x07UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_8TH_EVENT      ((0x08UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_9TH_EVENT      ((0x09UL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_10TH_EVENT     ((0x0AUL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_11TH_EVENT     ((0x0BUL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_12TH_EVENT     ((0x0CUL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_13TH_EVENT     ((0x0DUL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_14TH_EVENT     ((0x0EUL) << ETPS_ALL_SOCCPRD_Pos)
#define ETPS_ALL_SOCCPRD_GEN_SOCC_ON_15TH_EVENT     ((0x0FUL) << ETPS_ALL_SOCCPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETPS            SOCCCNT
 *  @access     PWM->ETPS.bit.SOCCCNT
 *  @brief      PWM ADC start-of-conversion C event (SOCC) counter
 *              It indicates how many selected ETSEL.SOCCSEL events have occurred. It is automatically
 *              cleared when an SOCC pulse is generated.
 *              It can be initialized via write.
 */
#define ETPS_ALL_SOCCCNT_Pos (28)
#define ETPS_ALL_SOCCCNT_Msk (0xFUL << ETPS_ALL_SOCCCNT_Pos)

typedef enum
{
    ETPS_BIT_SOCCCNT_NO_EVENT_OCCUR     = 0,  /*!< No events have occurred   */
    ETPS_BIT_SOCCCNT_1_EVENT_OCCUR      = 1,  /*!< 1 event has occurred      */
    ETPS_BIT_SOCCCNT_2_EVENT_OCCUR      = 2,  /*!< 2 events have occurred    */
    ETPS_BIT_SOCCCNT_3_EVENT_OCCUR      = 3,  /*!< 3 events have occurred    */
    ETPS_BIT_SOCCCNT_4_EVENT_OCCUR      = 4,  /*!< 4 events have occurred    */
    ETPS_BIT_SOCCCNT_5_EVENT_OCCUR      = 5,  /*!< 5 events have occurred    */
    ETPS_BIT_SOCCCNT_6_EVENT_OCCUR      = 6,  /*!< 6 events have occurred    */
    ETPS_BIT_SOCCCNT_7_EVENT_OCCUR      = 7,  /*!< 7 events have occurred    */
    ETPS_BIT_SOCCCNT_8_EVENT_OCCUR      = 8,  /*!< 8 events have occurred    */
    ETPS_BIT_SOCCCNT_9_EVENT_OCCUR      = 9,  /*!< 9 events have occurred    */
    ETPS_BIT_SOCCCNT_10_EVENT_OCCUR     = 10,  /*!< 10 events have occurred   */
    ETPS_BIT_SOCCCNT_11_EVENT_OCCUR     = 11,  /*!< 11 events have occurred   */
    ETPS_BIT_SOCCCNT_12_EVENT_OCCUR     = 12,  /*!< 12 events have occurred   */
    ETPS_BIT_SOCCCNT_13_EVENT_OCCUR     = 13,  /*!< 13 events have occurred   */
    ETPS_BIT_SOCCCNT_14_EVENT_OCCUR     = 14,  /*!< 14 events have occurred   */
    ETPS_BIT_SOCCCNT_15_EVENT_OCCUR     = 15,  /*!< 15 events have occurred   */
} ETPS_BIT_SOCCCNT;

#define ETPS_ALL_SOCCCNT_NO_EVENT_OCCUR     ((0x00UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_1_EVENT_OCCUR      ((0x01UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_2_EVENT_OCCUR      ((0x02UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_3_EVENT_OCCUR      ((0x03UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_4_EVENT_OCCUR      ((0x04UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_5_EVENT_OCCUR      ((0x05UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_6_EVENT_OCCUR      ((0x06UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_7_EVENT_OCCUR      ((0x07UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_8_EVENT_OCCUR      ((0x08UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_9_EVENT_OCCUR      ((0x09UL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_10_EVENT_OCCUR     ((0x0AUL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_11_EVENT_OCCUR     ((0x0BUL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_12_EVENT_OCCUR     ((0x0CUL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_13_EVENT_OCCUR     ((0x0DUL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_14_EVENT_OCCUR     ((0x0EUL) << ETPS_ALL_SOCCCNT_Pos)
#define ETPS_ALL_SOCCCNT_15_EVENT_OCCUR     ((0x0FUL) << ETPS_ALL_SOCCCNT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETFLG           INT
 *  @access     PWM->ETFLG.bit.INT
 *  @brief      Latched PWM interrupt flag
 */
#define ETFLG_ALL_INT_Pos (0)
#define ETFLG_ALL_INT_Msk (0x1UL << ETFLG_ALL_INT_Pos)

typedef enum
{
    ETFLG_BIT_INT_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                                                        */
    ETFLG_BIT_INT_OCCUR         = 1,  /*!< Indicates a PWM interrupt was generated. No further interrupts will be generated  
                                           until the flag bit is cleared.                                                     */
} ETFLG_BIT_INT;

#define ETFLG_ALL_INT_NOT_OCCUR     ((0x0UL) << ETFLG_ALL_INT_Pos)
#define ETFLG_ALL_INT_OCCUR         ((0x1UL) << ETFLG_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETFLG           SOCA
 *  @access     PWM->ETFLG.bit.SOCA
 *  @brief      Latched PWM ADC start-of-conversion A flag
 */
#define ETFLG_ALL_SOCA_Pos (1)
#define ETFLG_ALL_SOCA_Msk (0x1UL << ETFLG_ALL_SOCA_Pos)

typedef enum
{
    ETFLG_BIT_SOCA_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                                                          */
    ETFLG_BIT_SOCA_OCCUR         = 1,  /*!< Indicates a SOCA event was generated. The pulse will continue to be generated even  
                                            if the flag is set.                                                                  */
} ETFLG_BIT_SOCA;

#define ETFLG_ALL_SOCA_NOT_OCCUR     ((0x0UL) << ETFLG_ALL_SOCA_Pos)
#define ETFLG_ALL_SOCA_OCCUR         ((0x1UL) << ETFLG_ALL_SOCA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETFLG           SOCB
 *  @access     PWM->ETFLG.bit.SOCB
 *  @brief      Latched PWM ADC start-of-conversion B flag
 */
#define ETFLG_ALL_SOCB_Pos (2)
#define ETFLG_ALL_SOCB_Msk (0x1UL << ETFLG_ALL_SOCB_Pos)

typedef enum
{
    ETFLG_BIT_SOCB_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                                                          */
    ETFLG_BIT_SOCB_OCCUR         = 1,  /*!< Indicates a SOCB event was generated. The pulse will continue to be generated even  
                                            if the flag is set.                                                                  */
} ETFLG_BIT_SOCB;

#define ETFLG_ALL_SOCB_NOT_OCCUR     ((0x0UL) << ETFLG_ALL_SOCB_Pos)
#define ETFLG_ALL_SOCB_OCCUR         ((0x1UL) << ETFLG_ALL_SOCB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETFLG           SOCC
 *  @access     PWM->ETFLG.bit.SOCC
 *  @brief      Latched PWM ADC start-of-conversion C flag
 */
#define ETFLG_ALL_SOCC_Pos (3)
#define ETFLG_ALL_SOCC_Msk (0x1UL << ETFLG_ALL_SOCC_Pos)

typedef enum
{
    ETFLG_BIT_SOCC_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                                                          */
    ETFLG_BIT_SOCC_OCCUR         = 1,  /*!< Indicates a SOCC event was generated. The pulse will continue to be generated even  
                                            if the flag is set.                                                                  */
} ETFLG_BIT_SOCC;

#define ETFLG_ALL_SOCC_NOT_OCCUR     ((0x0UL) << ETFLG_ALL_SOCC_Pos)
#define ETFLG_ALL_SOCC_OCCUR         ((0x1UL) << ETFLG_ALL_SOCC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCLR           INT
 *  @access     PWM->ETCLR.bit.INT
 *  @brief      Latched PWM interrupt flag clear
 */
#define ETCLR_ALL_INT_Pos (0)
#define ETCLR_ALL_INT_Msk (0x1UL << ETCLR_ALL_INT_Pos)

typedef enum
{
    ETCLR_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    ETCLR_BIT_INT_CLEAR         = 1,  /*!< Write a 1 clears ETFLG.INT                          */
} ETCLR_BIT_INT;

#define ETCLR_ALL_INT_NO_EFFECT     ((0x0UL) << ETCLR_ALL_INT_Pos)
#define ETCLR_ALL_INT_CLEAR         ((0x1UL) << ETCLR_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCLR           SOCA
 *  @access     PWM->ETCLR.bit.SOCA
 *  @brief      Latched PWM ADC start-of-conversion A flag clear
 */
#define ETCLR_ALL_SOCA_Pos (1)
#define ETCLR_ALL_SOCA_Msk (0x1UL << ETCLR_ALL_SOCA_Pos)

typedef enum
{
    ETCLR_BIT_SOCA_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    ETCLR_BIT_SOCA_CLEAR         = 1,  /*!< Write a 1 clears ETFLG.SOCA                         */
} ETCLR_BIT_SOCA;

#define ETCLR_ALL_SOCA_NO_EFFECT     ((0x0UL) << ETCLR_ALL_SOCA_Pos)
#define ETCLR_ALL_SOCA_CLEAR         ((0x1UL) << ETCLR_ALL_SOCA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCLR           SOCB
 *  @access     PWM->ETCLR.bit.SOCB
 *  @brief      Latched PWM ADC start-of-conversion B flag clear
 */
#define ETCLR_ALL_SOCB_Pos (2)
#define ETCLR_ALL_SOCB_Msk (0x1UL << ETCLR_ALL_SOCB_Pos)

typedef enum
{
    ETCLR_BIT_SOCB_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    ETCLR_BIT_SOCB_CLEAR         = 1,  /*!< Write a 1 clears ETFLG.SOCB                         */
} ETCLR_BIT_SOCB;

#define ETCLR_ALL_SOCB_NO_EFFECT     ((0x0UL) << ETCLR_ALL_SOCB_Pos)
#define ETCLR_ALL_SOCB_CLEAR         ((0x1UL) << ETCLR_ALL_SOCB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETCLR           SOCC
 *  @access     PWM->ETCLR.bit.SOCC
 *  @brief      Latched PWM ADC start-of-conversion C flag clear
 */
#define ETCLR_ALL_SOCC_Pos (3)
#define ETCLR_ALL_SOCC_Msk (0x1UL << ETCLR_ALL_SOCC_Pos)

typedef enum
{
    ETCLR_BIT_SOCC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0   */
    ETCLR_BIT_SOCC_CLEAR         = 1,  /*!< Write a 1 clears ETFLG.SOCC                         */
} ETCLR_BIT_SOCC;

#define ETCLR_ALL_SOCC_NO_EFFECT     ((0x0UL) << ETCLR_ALL_SOCC_Pos)
#define ETCLR_ALL_SOCC_CLEAR         ((0x1UL) << ETCLR_ALL_SOCC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETFRC           INT
 *  @access     PWM->ETFRC.bit.INT
 *  @brief      Software force a PWM interrupt
 *              This bit is ignored if ETSEL.INTEN=0 or ETPS.INTPRD=00
 */
#define ETFRC_ALL_INT_Pos (0)
#define ETFRC_ALL_INT_Msk (0x1UL << ETFRC_ALL_INT_Pos)

typedef enum
{
    ETFRC_BIT_INT_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0              */
    ETFRC_BIT_INT_FORCE         = 1,  /*!< Write a 1 generates an interrupt and sets the ETFLG.INT flag   */
} ETFRC_BIT_INT;

#define ETFRC_ALL_INT_NO_EFFECT     ((0x0UL) << ETFRC_ALL_INT_Pos)
#define ETFRC_ALL_INT_FORCE         ((0x1UL) << ETFRC_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETFRC           SOCA
 *  @access     PWM->ETFRC.bit.SOCA
 *  @brief      Software force a start-of-conversion A pulse
 *              This bit is ignored if ETSEL.SOCAEN=0
 */
#define ETFRC_ALL_SOCA_Pos (1)
#define ETFRC_ALL_SOCA_Msk (0x1UL << ETFRC_ALL_SOCA_Pos)

typedef enum
{
    ETFRC_BIT_SOCA_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0               */
    ETFRC_BIT_SOCA_FORCE         = 1,  /*!< Write a 1 generates an interrupt and sets the ETFLG.SOCA flag   */
} ETFRC_BIT_SOCA;

#define ETFRC_ALL_SOCA_NO_EFFECT     ((0x0UL) << ETFRC_ALL_SOCA_Pos)
#define ETFRC_ALL_SOCA_FORCE         ((0x1UL) << ETFRC_ALL_SOCA_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETFRC           SOCB
 *  @access     PWM->ETFRC.bit.SOCB
 *  @brief      Software force a start-of-conversion B pulse
 *              This bit is ignored if ETSEL.SOCBEN=0
 */
#define ETFRC_ALL_SOCB_Pos (2)
#define ETFRC_ALL_SOCB_Msk (0x1UL << ETFRC_ALL_SOCB_Pos)

typedef enum
{
    ETFRC_BIT_SOCB_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0               */
    ETFRC_BIT_SOCB_FORCE         = 1,  /*!< Write a 1 generates an interrupt and sets the ETFLG.SOCB flag   */
} ETFRC_BIT_SOCB;

#define ETFRC_ALL_SOCB_NO_EFFECT     ((0x0UL) << ETFRC_ALL_SOCB_Pos)
#define ETFRC_ALL_SOCB_FORCE         ((0x1UL) << ETFRC_ALL_SOCB_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             ETFRC           SOCC
 *  @access     PWM->ETFRC.bit.SOCC
 *  @brief      Software force a start-of-conversion C pulse
 *              This bit is ignored if ETSEL.SOCCEN=0
 */
#define ETFRC_ALL_SOCC_Pos (3)
#define ETFRC_ALL_SOCC_Msk (0x1UL << ETFRC_ALL_SOCC_Pos)

typedef enum
{
    ETFRC_BIT_SOCC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect and always reads back a 0               */
    ETFRC_BIT_SOCC_FORCE         = 1,  /*!< Write a 1 generates an interrupt and sets the ETFLG.SOCC flag   */
} ETFRC_BIT_SOCC;

#define ETFRC_ALL_SOCC_NO_EFFECT     ((0x0UL) << ETFRC_ALL_SOCC_Pos)
#define ETFRC_ALL_SOCC_FORCE         ((0x1UL) << ETFRC_ALL_SOCC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWM             PWMREGKEY       KEY
 *  @access     PWM->PWMREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected PWM registers
 */
#define PWMREGKEY_ALL_KEY_Pos (0)
#define PWMREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << PWMREGKEY_ALL_KEY_Pos)

#define PWMREGKEY_BIT_KEY

#define PWMREGKEY_ALL_KEY_(x) ((x) << PWMREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     PWMCFG
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ0SRCCTL       IOSEL
 *  @access     PWMCFG->TZ0SRCCTL.bit.IOSEL
 *  @brief      GPIO number for TZ0 event
 */
#define TZ0SRCCTL_ALL_IOSEL_Pos (0)
#define TZ0SRCCTL_ALL_IOSEL_Msk (0x3FUL << TZ0SRCCTL_ALL_IOSEL_Pos)

#define TZ0SRCCTL_BIT_IOSEL

#define TZ0SRCCTL_ALL_IOSEL_(x) ((x) << TZ0SRCCTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ0SRCCTL       POL
 *  @access     PWMCFG->TZ0SRCCTL.bit.POL
 *  @brief      TZ0 polarity
 */
#define TZ0SRCCTL_ALL_POL_Pos (6)
#define TZ0SRCCTL_ALL_POL_Msk (0x1UL << TZ0SRCCTL_ALL_POL_Pos)

typedef enum
{
    TZ0SRCCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    TZ0SRCCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} TZ0SRCCTL_BIT_POL;

#define TZ0SRCCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << TZ0SRCCTL_ALL_POL_Pos)
#define TZ0SRCCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << TZ0SRCCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ1SRCCTL       IOSEL
 *  @access     PWMCFG->TZ1SRCCTL.bit.IOSEL
 *  @brief      GPIO number for TZ1 event
 */
#define TZ1SRCCTL_ALL_IOSEL_Pos (0)
#define TZ1SRCCTL_ALL_IOSEL_Msk (0x3FUL << TZ1SRCCTL_ALL_IOSEL_Pos)

#define TZ1SRCCTL_BIT_IOSEL

#define TZ1SRCCTL_ALL_IOSEL_(x) ((x) << TZ1SRCCTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ1SRCCTL       POL
 *  @access     PWMCFG->TZ1SRCCTL.bit.POL
 *  @brief      TZ1 polarity
 */
#define TZ1SRCCTL_ALL_POL_Pos (6)
#define TZ1SRCCTL_ALL_POL_Msk (0x1UL << TZ1SRCCTL_ALL_POL_Pos)

typedef enum
{
    TZ1SRCCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    TZ1SRCCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} TZ1SRCCTL_BIT_POL;

#define TZ1SRCCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << TZ1SRCCTL_ALL_POL_Pos)
#define TZ1SRCCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << TZ1SRCCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ2SRCCTL       IOSEL
 *  @access     PWMCFG->TZ2SRCCTL.bit.IOSEL
 *  @brief      GPIO number for TZ2 event
 */
#define TZ2SRCCTL_ALL_IOSEL_Pos (0)
#define TZ2SRCCTL_ALL_IOSEL_Msk (0x3FUL << TZ2SRCCTL_ALL_IOSEL_Pos)

#define TZ2SRCCTL_BIT_IOSEL

#define TZ2SRCCTL_ALL_IOSEL_(x) ((x) << TZ2SRCCTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ2SRCCTL       POL
 *  @access     PWMCFG->TZ2SRCCTL.bit.POL
 *  @brief      TZ2 polarity
 */
#define TZ2SRCCTL_ALL_POL_Pos (6)
#define TZ2SRCCTL_ALL_POL_Msk (0x1UL << TZ2SRCCTL_ALL_POL_Pos)

typedef enum
{
    TZ2SRCCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    TZ2SRCCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} TZ2SRCCTL_BIT_POL;

#define TZ2SRCCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << TZ2SRCCTL_ALL_POL_Pos)
#define TZ2SRCCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << TZ2SRCCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ3SRCCTL       IOSEL
 *  @access     PWMCFG->TZ3SRCCTL.bit.IOSEL
 *  @brief      GPIO number for TZ3 event
 */
#define TZ3SRCCTL_ALL_IOSEL_Pos (0)
#define TZ3SRCCTL_ALL_IOSEL_Msk (0x3FUL << TZ3SRCCTL_ALL_IOSEL_Pos)

#define TZ3SRCCTL_BIT_IOSEL

#define TZ3SRCCTL_ALL_IOSEL_(x) ((x) << TZ3SRCCTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ3SRCCTL       POL
 *  @access     PWMCFG->TZ3SRCCTL.bit.POL
 *  @brief      TZ3 polarity
 */
#define TZ3SRCCTL_ALL_POL_Pos (6)
#define TZ3SRCCTL_ALL_POL_Msk (0x1UL << TZ3SRCCTL_ALL_POL_Pos)

typedef enum
{
    TZ3SRCCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    TZ3SRCCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} TZ3SRCCTL_BIT_POL;

#define TZ3SRCCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << TZ3SRCCTL_ALL_POL_Pos)
#define TZ3SRCCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << TZ3SRCCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ4SRCCTL       IOSEL
 *  @access     PWMCFG->TZ4SRCCTL.bit.IOSEL
 *  @brief      GPIO number for TZ4 event
 */
#define TZ4SRCCTL_ALL_IOSEL_Pos (0)
#define TZ4SRCCTL_ALL_IOSEL_Msk (0x3FUL << TZ4SRCCTL_ALL_IOSEL_Pos)

#define TZ4SRCCTL_BIT_IOSEL

#define TZ4SRCCTL_ALL_IOSEL_(x) ((x) << TZ4SRCCTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TZ4SRCCTL       POL
 *  @access     PWMCFG->TZ4SRCCTL.bit.POL
 *  @brief      TZ4 polarity
 */
#define TZ4SRCCTL_ALL_POL_Pos (6)
#define TZ4SRCCTL_ALL_POL_Msk (0x1UL << TZ4SRCCTL_ALL_POL_Pos)

typedef enum
{
    TZ4SRCCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    TZ4SRCCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} TZ4SRCCTL_BIT_POL;

#define TZ4SRCCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << TZ4SRCCTL_ALL_POL_Pos)
#define TZ4SRCCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << TZ4SRCCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          FRCSYNC         PWM0SYNC
 *  @access     PWMCFG->FRCSYNC.bit.PWM0SYNC
 *  @brief      Software forced synchronization on PWM0
 */
#define FRCSYNC_ALL_PWM0SYNC_Pos (0)
#define FRCSYNC_ALL_PWM0SYNC_Msk (0x1UL << FRCSYNC_ALL_PWM0SYNC_Pos)

typedef enum
{
    FRCSYNC_BIT_PWM0SYNC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    FRCSYNC_BIT_PWM0SYNC_FORCE         = 1,  /*!< Write a 1 will force a SYNC event on PWM0.  
                                                  This bit is self-cleared                     */
} FRCSYNC_BIT_PWM0SYNC;

#define FRCSYNC_ALL_PWM0SYNC_NO_EFFECT     ((0x0UL) << FRCSYNC_ALL_PWM0SYNC_Pos)
#define FRCSYNC_ALL_PWM0SYNC_FORCE         ((0x1UL) << FRCSYNC_ALL_PWM0SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          FRCSYNC         PWM1SYNC
 *  @access     PWMCFG->FRCSYNC.bit.PWM1SYNC
 *  @brief      Software forced synchronization on PWM1
 */
#define FRCSYNC_ALL_PWM1SYNC_Pos (1)
#define FRCSYNC_ALL_PWM1SYNC_Msk (0x1UL << FRCSYNC_ALL_PWM1SYNC_Pos)

typedef enum
{
    FRCSYNC_BIT_PWM1SYNC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    FRCSYNC_BIT_PWM1SYNC_FORCE         = 1,  /*!< Write a 1 will force a SYNC event on PWM1.  
                                                  This bit is self-cleared                     */
} FRCSYNC_BIT_PWM1SYNC;

#define FRCSYNC_ALL_PWM1SYNC_NO_EFFECT     ((0x0UL) << FRCSYNC_ALL_PWM1SYNC_Pos)
#define FRCSYNC_ALL_PWM1SYNC_FORCE         ((0x1UL) << FRCSYNC_ALL_PWM1SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          FRCSYNC         PWM2SYNC
 *  @access     PWMCFG->FRCSYNC.bit.PWM2SYNC
 *  @brief      Software forced synchronization on PWM2
 */
#define FRCSYNC_ALL_PWM2SYNC_Pos (2)
#define FRCSYNC_ALL_PWM2SYNC_Msk (0x1UL << FRCSYNC_ALL_PWM2SYNC_Pos)

typedef enum
{
    FRCSYNC_BIT_PWM2SYNC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    FRCSYNC_BIT_PWM2SYNC_FORCE         = 1,  /*!< Write a 1 will force a SYNC event on PWM2.  
                                                  This bit is self-cleared                     */
} FRCSYNC_BIT_PWM2SYNC;

#define FRCSYNC_ALL_PWM2SYNC_NO_EFFECT     ((0x0UL) << FRCSYNC_ALL_PWM2SYNC_Pos)
#define FRCSYNC_ALL_PWM2SYNC_FORCE         ((0x1UL) << FRCSYNC_ALL_PWM2SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          FRCSYNC         PWM3SYNC
 *  @access     PWMCFG->FRCSYNC.bit.PWM3SYNC
 *  @brief      Software forced synchronization on PWM3
 */
#define FRCSYNC_ALL_PWM3SYNC_Pos (3)
#define FRCSYNC_ALL_PWM3SYNC_Msk (0x1UL << FRCSYNC_ALL_PWM3SYNC_Pos)

typedef enum
{
    FRCSYNC_BIT_PWM3SYNC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    FRCSYNC_BIT_PWM3SYNC_FORCE         = 1,  /*!< Write a 1 will force a SYNC event on PWM3.  
                                                  This bit is self-cleared                     */
} FRCSYNC_BIT_PWM3SYNC;

#define FRCSYNC_ALL_PWM3SYNC_NO_EFFECT     ((0x0UL) << FRCSYNC_ALL_PWM3SYNC_Pos)
#define FRCSYNC_ALL_PWM3SYNC_FORCE         ((0x1UL) << FRCSYNC_ALL_PWM3SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          FRCSYNC         PWM4SYNC
 *  @access     PWMCFG->FRCSYNC.bit.PWM4SYNC
 *  @brief      Software forced synchronization on PWM4
 */
#define FRCSYNC_ALL_PWM4SYNC_Pos (4)
#define FRCSYNC_ALL_PWM4SYNC_Msk (0x1UL << FRCSYNC_ALL_PWM4SYNC_Pos)

typedef enum
{
    FRCSYNC_BIT_PWM4SYNC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    FRCSYNC_BIT_PWM4SYNC_FORCE         = 1,  /*!< Write a 1 will force a SYNC event on PWM4.  
                                                  This bit is self-cleared                     */
} FRCSYNC_BIT_PWM4SYNC;

#define FRCSYNC_ALL_PWM4SYNC_NO_EFFECT     ((0x0UL) << FRCSYNC_ALL_PWM4SYNC_Pos)
#define FRCSYNC_ALL_PWM4SYNC_FORCE         ((0x1UL) << FRCSYNC_ALL_PWM4SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          FRCSYNC         PWM5SYNC
 *  @access     PWMCFG->FRCSYNC.bit.PWM5SYNC
 *  @brief      Software forced synchronization on PWM5
 */
#define FRCSYNC_ALL_PWM5SYNC_Pos (5)
#define FRCSYNC_ALL_PWM5SYNC_Msk (0x1UL << FRCSYNC_ALL_PWM5SYNC_Pos)

typedef enum
{
    FRCSYNC_BIT_PWM5SYNC_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                    
                                                  Always readback 0.                           */
    FRCSYNC_BIT_PWM5SYNC_FORCE         = 1,  /*!< Write a 1 will force a SYNC event on PWM5.  
                                                  This bit is self-cleared                     */
} FRCSYNC_BIT_PWM5SYNC;

#define FRCSYNC_ALL_PWM5SYNC_NO_EFFECT     ((0x0UL) << FRCSYNC_ALL_PWM5SYNC_Pos)
#define FRCSYNC_ALL_PWM5SYNC_FORCE         ((0x1UL) << FRCSYNC_ALL_PWM5SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          FRCSYNC         PWMCLK
 *  @access     PWMCFG->FRCSYNC.bit.PWMCLK
 *  @brief      Software forced synchronization on clock for all PWMs
 */
#define FRCSYNC_ALL_PWMCLK_Pos (31)
#define FRCSYNC_ALL_PWMCLK_Msk (0x1UL << FRCSYNC_ALL_PWMCLK_Pos)

typedef enum
{
    FRCSYNC_BIT_PWMCLK_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                       
                                                Always readback 0.                              */
    FRCSYNC_BIT_PWMCLK_FORCE         = 1,  /*!< Write a 1 will force a SYNC on all PWM clocks  
                                                This bit is self-cleared                        */
} FRCSYNC_BIT_PWMCLK;

#define FRCSYNC_ALL_PWMCLK_NO_EFFECT     ((0x0UL) << FRCSYNC_ALL_PWMCLK_Pos)
#define FRCSYNC_ALL_PWMCLK_FORCE         ((0x1UL) << FRCSYNC_ALL_PWMCLK_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          GPIOSYNCCTL     IOSEL
 *  @access     PWMCFG->GPIOSYNCCTL.bit.IOSEL
 *  @brief      GPIO number for PWMSYNCI input
 */
#define GPIOSYNCCTL_ALL_IOSEL_Pos (0)
#define GPIOSYNCCTL_ALL_IOSEL_Msk (0x3FUL << GPIOSYNCCTL_ALL_IOSEL_Pos)

#define GPIOSYNCCTL_BIT_IOSEL

#define GPIOSYNCCTL_ALL_IOSEL_(x) ((x) << GPIOSYNCCTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          GPIOSYNCCTL     POL
 *  @access     PWMCFG->GPIOSYNCCTL.bit.POL
 *  @brief      PWMSYNCI input polarity
 */
#define GPIOSYNCCTL_ALL_POL_Pos (6)
#define GPIOSYNCCTL_ALL_POL_Msk (0x1UL << GPIOSYNCCTL_ALL_POL_Pos)

typedef enum
{
    GPIOSYNCCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    GPIOSYNCCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} GPIOSYNCCTL_BIT_POL;

#define GPIOSYNCCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << GPIOSYNCCTL_ALL_POL_Pos)
#define GPIOSYNCCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << GPIOSYNCCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          GPIOSYNCEN      PWM0SYNC
 *  @access     PWMCFG->GPIOSYNCEN.bit.PWM0SYNC
 *  @brief      Enable PWM0 synchronization by GPIO
 */
#define GPIOSYNCEN_ALL_PWM0SYNC_Pos (0)
#define GPIOSYNCEN_ALL_PWM0SYNC_Msk (0x1UL << GPIOSYNCEN_ALL_PWM0SYNC_Pos)

typedef enum
{
    GPIOSYNCEN_BIT_PWM0SYNC_DISABLE     = 0,  /*!< Disable   */
    GPIOSYNCEN_BIT_PWM0SYNC_ENABLE      = 1,  /*!< Enable    */
} GPIOSYNCEN_BIT_PWM0SYNC;

#define GPIOSYNCEN_ALL_PWM0SYNC_DISABLE     ((0x0UL) << GPIOSYNCEN_ALL_PWM0SYNC_Pos)
#define GPIOSYNCEN_ALL_PWM0SYNC_ENABLE      ((0x1UL) << GPIOSYNCEN_ALL_PWM0SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          GPIOSYNCEN      PWM1SYNC
 *  @access     PWMCFG->GPIOSYNCEN.bit.PWM1SYNC
 *  @brief      Enable PWM1 synchronization by GPIO
 */
#define GPIOSYNCEN_ALL_PWM1SYNC_Pos (1)
#define GPIOSYNCEN_ALL_PWM1SYNC_Msk (0x1UL << GPIOSYNCEN_ALL_PWM1SYNC_Pos)

typedef enum
{
    GPIOSYNCEN_BIT_PWM1SYNC_DISABLE     = 0,  /*!< Disable   */
    GPIOSYNCEN_BIT_PWM1SYNC_ENABLE      = 1,  /*!< Enable    */
} GPIOSYNCEN_BIT_PWM1SYNC;

#define GPIOSYNCEN_ALL_PWM1SYNC_DISABLE     ((0x0UL) << GPIOSYNCEN_ALL_PWM1SYNC_Pos)
#define GPIOSYNCEN_ALL_PWM1SYNC_ENABLE      ((0x1UL) << GPIOSYNCEN_ALL_PWM1SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          GPIOSYNCEN      PWM2SYNC
 *  @access     PWMCFG->GPIOSYNCEN.bit.PWM2SYNC
 *  @brief      Enable PWM2 synchronization by GPIO
 */
#define GPIOSYNCEN_ALL_PWM2SYNC_Pos (2)
#define GPIOSYNCEN_ALL_PWM2SYNC_Msk (0x1UL << GPIOSYNCEN_ALL_PWM2SYNC_Pos)

typedef enum
{
    GPIOSYNCEN_BIT_PWM2SYNC_DISABLE     = 0,  /*!< Disable   */
    GPIOSYNCEN_BIT_PWM2SYNC_ENABLE      = 1,  /*!< Enable    */
} GPIOSYNCEN_BIT_PWM2SYNC;

#define GPIOSYNCEN_ALL_PWM2SYNC_DISABLE     ((0x0UL) << GPIOSYNCEN_ALL_PWM2SYNC_Pos)
#define GPIOSYNCEN_ALL_PWM2SYNC_ENABLE      ((0x1UL) << GPIOSYNCEN_ALL_PWM2SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          GPIOSYNCEN      PWM3SYNC
 *  @access     PWMCFG->GPIOSYNCEN.bit.PWM3SYNC
 *  @brief      Enable PWM3 synchronization by GPIO
 */
#define GPIOSYNCEN_ALL_PWM3SYNC_Pos (3)
#define GPIOSYNCEN_ALL_PWM3SYNC_Msk (0x1UL << GPIOSYNCEN_ALL_PWM3SYNC_Pos)

typedef enum
{
    GPIOSYNCEN_BIT_PWM3SYNC_DISABLE     = 0,  /*!< Disable   */
    GPIOSYNCEN_BIT_PWM3SYNC_ENABLE      = 1,  /*!< Enable    */
} GPIOSYNCEN_BIT_PWM3SYNC;

#define GPIOSYNCEN_ALL_PWM3SYNC_DISABLE     ((0x0UL) << GPIOSYNCEN_ALL_PWM3SYNC_Pos)
#define GPIOSYNCEN_ALL_PWM3SYNC_ENABLE      ((0x1UL) << GPIOSYNCEN_ALL_PWM3SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          GPIOSYNCEN      PWM4SYNC
 *  @access     PWMCFG->GPIOSYNCEN.bit.PWM4SYNC
 *  @brief      Enable PWM4 synchronization by GPIO
 */
#define GPIOSYNCEN_ALL_PWM4SYNC_Pos (4)
#define GPIOSYNCEN_ALL_PWM4SYNC_Msk (0x1UL << GPIOSYNCEN_ALL_PWM4SYNC_Pos)

typedef enum
{
    GPIOSYNCEN_BIT_PWM4SYNC_DISABLE     = 0,  /*!< Disable   */
    GPIOSYNCEN_BIT_PWM4SYNC_ENABLE      = 1,  /*!< Enable    */
} GPIOSYNCEN_BIT_PWM4SYNC;

#define GPIOSYNCEN_ALL_PWM4SYNC_DISABLE     ((0x0UL) << GPIOSYNCEN_ALL_PWM4SYNC_Pos)
#define GPIOSYNCEN_ALL_PWM4SYNC_ENABLE      ((0x1UL) << GPIOSYNCEN_ALL_PWM4SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          GPIOSYNCEN      PWM5SYNC
 *  @access     PWMCFG->GPIOSYNCEN.bit.PWM5SYNC
 *  @brief      Enable PWM5 synchronization by GPIO
 */
#define GPIOSYNCEN_ALL_PWM5SYNC_Pos (5)
#define GPIOSYNCEN_ALL_PWM5SYNC_Msk (0x1UL << GPIOSYNCEN_ALL_PWM5SYNC_Pos)

typedef enum
{
    GPIOSYNCEN_BIT_PWM5SYNC_DISABLE     = 0,  /*!< Disable   */
    GPIOSYNCEN_BIT_PWM5SYNC_ENABLE      = 1,  /*!< Enable    */
} GPIOSYNCEN_BIT_PWM5SYNC;

#define GPIOSYNCEN_ALL_PWM5SYNC_DISABLE     ((0x0UL) << GPIOSYNCEN_ALL_PWM5SYNC_Pos)
#define GPIOSYNCEN_ALL_PWM5SYNC_ENABLE      ((0x1UL) << GPIOSYNCEN_ALL_PWM5SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR0SYNCEN      PWM0SYNC
 *  @access     PWMCFG->TMR0SYNCEN.bit.PWM0SYNC
 *  @brief      Enable PWM0 synchronization by Timer 0
 */
#define TMR0SYNCEN_ALL_PWM0SYNC_Pos (0)
#define TMR0SYNCEN_ALL_PWM0SYNC_Msk (0x1UL << TMR0SYNCEN_ALL_PWM0SYNC_Pos)

typedef enum
{
    TMR0SYNCEN_BIT_PWM0SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR0SYNCEN_BIT_PWM0SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR0SYNCEN_BIT_PWM0SYNC;

#define TMR0SYNCEN_ALL_PWM0SYNC_DISABLE     ((0x0UL) << TMR0SYNCEN_ALL_PWM0SYNC_Pos)
#define TMR0SYNCEN_ALL_PWM0SYNC_ENABLE      ((0x1UL) << TMR0SYNCEN_ALL_PWM0SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR0SYNCEN      PWM1SYNC
 *  @access     PWMCFG->TMR0SYNCEN.bit.PWM1SYNC
 *  @brief      Enable PWM1 synchronization by Timer 0
 */
#define TMR0SYNCEN_ALL_PWM1SYNC_Pos (1)
#define TMR0SYNCEN_ALL_PWM1SYNC_Msk (0x1UL << TMR0SYNCEN_ALL_PWM1SYNC_Pos)

typedef enum
{
    TMR0SYNCEN_BIT_PWM1SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR0SYNCEN_BIT_PWM1SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR0SYNCEN_BIT_PWM1SYNC;

#define TMR0SYNCEN_ALL_PWM1SYNC_DISABLE     ((0x0UL) << TMR0SYNCEN_ALL_PWM1SYNC_Pos)
#define TMR0SYNCEN_ALL_PWM1SYNC_ENABLE      ((0x1UL) << TMR0SYNCEN_ALL_PWM1SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR0SYNCEN      PWM2SYNC
 *  @access     PWMCFG->TMR0SYNCEN.bit.PWM2SYNC
 *  @brief      Enable PWM2 synchronization by Timer 0
 */
#define TMR0SYNCEN_ALL_PWM2SYNC_Pos (2)
#define TMR0SYNCEN_ALL_PWM2SYNC_Msk (0x1UL << TMR0SYNCEN_ALL_PWM2SYNC_Pos)

typedef enum
{
    TMR0SYNCEN_BIT_PWM2SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR0SYNCEN_BIT_PWM2SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR0SYNCEN_BIT_PWM2SYNC;

#define TMR0SYNCEN_ALL_PWM2SYNC_DISABLE     ((0x0UL) << TMR0SYNCEN_ALL_PWM2SYNC_Pos)
#define TMR0SYNCEN_ALL_PWM2SYNC_ENABLE      ((0x1UL) << TMR0SYNCEN_ALL_PWM2SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR0SYNCEN      PWM3SYNC
 *  @access     PWMCFG->TMR0SYNCEN.bit.PWM3SYNC
 *  @brief      Enable PWM3 synchronization by Timer 0
 */
#define TMR0SYNCEN_ALL_PWM3SYNC_Pos (3)
#define TMR0SYNCEN_ALL_PWM3SYNC_Msk (0x1UL << TMR0SYNCEN_ALL_PWM3SYNC_Pos)

typedef enum
{
    TMR0SYNCEN_BIT_PWM3SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR0SYNCEN_BIT_PWM3SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR0SYNCEN_BIT_PWM3SYNC;

#define TMR0SYNCEN_ALL_PWM3SYNC_DISABLE     ((0x0UL) << TMR0SYNCEN_ALL_PWM3SYNC_Pos)
#define TMR0SYNCEN_ALL_PWM3SYNC_ENABLE      ((0x1UL) << TMR0SYNCEN_ALL_PWM3SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR0SYNCEN      PWM4SYNC
 *  @access     PWMCFG->TMR0SYNCEN.bit.PWM4SYNC
 *  @brief      Enable PWM4 synchronization by Timer 0
 */
#define TMR0SYNCEN_ALL_PWM4SYNC_Pos (4)
#define TMR0SYNCEN_ALL_PWM4SYNC_Msk (0x1UL << TMR0SYNCEN_ALL_PWM4SYNC_Pos)

typedef enum
{
    TMR0SYNCEN_BIT_PWM4SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR0SYNCEN_BIT_PWM4SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR0SYNCEN_BIT_PWM4SYNC;

#define TMR0SYNCEN_ALL_PWM4SYNC_DISABLE     ((0x0UL) << TMR0SYNCEN_ALL_PWM4SYNC_Pos)
#define TMR0SYNCEN_ALL_PWM4SYNC_ENABLE      ((0x1UL) << TMR0SYNCEN_ALL_PWM4SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR0SYNCEN      PWM5SYNC
 *  @access     PWMCFG->TMR0SYNCEN.bit.PWM5SYNC
 *  @brief      Enable PWM5 synchronization by Timer 0
 */
#define TMR0SYNCEN_ALL_PWM5SYNC_Pos (5)
#define TMR0SYNCEN_ALL_PWM5SYNC_Msk (0x1UL << TMR0SYNCEN_ALL_PWM5SYNC_Pos)

typedef enum
{
    TMR0SYNCEN_BIT_PWM5SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR0SYNCEN_BIT_PWM5SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR0SYNCEN_BIT_PWM5SYNC;

#define TMR0SYNCEN_ALL_PWM5SYNC_DISABLE     ((0x0UL) << TMR0SYNCEN_ALL_PWM5SYNC_Pos)
#define TMR0SYNCEN_ALL_PWM5SYNC_ENABLE      ((0x1UL) << TMR0SYNCEN_ALL_PWM5SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR1SYNCEN      PWM0SYNC
 *  @access     PWMCFG->TMR1SYNCEN.bit.PWM0SYNC
 *  @brief      Enable PWM0 synchronization by Timer 1
 */
#define TMR1SYNCEN_ALL_PWM0SYNC_Pos (0)
#define TMR1SYNCEN_ALL_PWM0SYNC_Msk (0x1UL << TMR1SYNCEN_ALL_PWM0SYNC_Pos)

typedef enum
{
    TMR1SYNCEN_BIT_PWM0SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR1SYNCEN_BIT_PWM0SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR1SYNCEN_BIT_PWM0SYNC;

#define TMR1SYNCEN_ALL_PWM0SYNC_DISABLE     ((0x0UL) << TMR1SYNCEN_ALL_PWM0SYNC_Pos)
#define TMR1SYNCEN_ALL_PWM0SYNC_ENABLE      ((0x1UL) << TMR1SYNCEN_ALL_PWM0SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR1SYNCEN      PWM1SYNC
 *  @access     PWMCFG->TMR1SYNCEN.bit.PWM1SYNC
 *  @brief      Enable PWM1 synchronization by Timer 1
 */
#define TMR1SYNCEN_ALL_PWM1SYNC_Pos (1)
#define TMR1SYNCEN_ALL_PWM1SYNC_Msk (0x1UL << TMR1SYNCEN_ALL_PWM1SYNC_Pos)

typedef enum
{
    TMR1SYNCEN_BIT_PWM1SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR1SYNCEN_BIT_PWM1SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR1SYNCEN_BIT_PWM1SYNC;

#define TMR1SYNCEN_ALL_PWM1SYNC_DISABLE     ((0x0UL) << TMR1SYNCEN_ALL_PWM1SYNC_Pos)
#define TMR1SYNCEN_ALL_PWM1SYNC_ENABLE      ((0x1UL) << TMR1SYNCEN_ALL_PWM1SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR1SYNCEN      PWM2SYNC
 *  @access     PWMCFG->TMR1SYNCEN.bit.PWM2SYNC
 *  @brief      Enable PWM2 synchronization by Timer 1
 */
#define TMR1SYNCEN_ALL_PWM2SYNC_Pos (2)
#define TMR1SYNCEN_ALL_PWM2SYNC_Msk (0x1UL << TMR1SYNCEN_ALL_PWM2SYNC_Pos)

typedef enum
{
    TMR1SYNCEN_BIT_PWM2SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR1SYNCEN_BIT_PWM2SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR1SYNCEN_BIT_PWM2SYNC;

#define TMR1SYNCEN_ALL_PWM2SYNC_DISABLE     ((0x0UL) << TMR1SYNCEN_ALL_PWM2SYNC_Pos)
#define TMR1SYNCEN_ALL_PWM2SYNC_ENABLE      ((0x1UL) << TMR1SYNCEN_ALL_PWM2SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR1SYNCEN      PWM3SYNC
 *  @access     PWMCFG->TMR1SYNCEN.bit.PWM3SYNC
 *  @brief      Enable PWM3 synchronization by Timer 1
 */
#define TMR1SYNCEN_ALL_PWM3SYNC_Pos (3)
#define TMR1SYNCEN_ALL_PWM3SYNC_Msk (0x1UL << TMR1SYNCEN_ALL_PWM3SYNC_Pos)

typedef enum
{
    TMR1SYNCEN_BIT_PWM3SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR1SYNCEN_BIT_PWM3SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR1SYNCEN_BIT_PWM3SYNC;

#define TMR1SYNCEN_ALL_PWM3SYNC_DISABLE     ((0x0UL) << TMR1SYNCEN_ALL_PWM3SYNC_Pos)
#define TMR1SYNCEN_ALL_PWM3SYNC_ENABLE      ((0x1UL) << TMR1SYNCEN_ALL_PWM3SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR1SYNCEN      PWM4SYNC
 *  @access     PWMCFG->TMR1SYNCEN.bit.PWM4SYNC
 *  @brief      Enable PWM4 synchronization by Timer 1
 */
#define TMR1SYNCEN_ALL_PWM4SYNC_Pos (4)
#define TMR1SYNCEN_ALL_PWM4SYNC_Msk (0x1UL << TMR1SYNCEN_ALL_PWM4SYNC_Pos)

typedef enum
{
    TMR1SYNCEN_BIT_PWM4SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR1SYNCEN_BIT_PWM4SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR1SYNCEN_BIT_PWM4SYNC;

#define TMR1SYNCEN_ALL_PWM4SYNC_DISABLE     ((0x0UL) << TMR1SYNCEN_ALL_PWM4SYNC_Pos)
#define TMR1SYNCEN_ALL_PWM4SYNC_ENABLE      ((0x1UL) << TMR1SYNCEN_ALL_PWM4SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR1SYNCEN      PWM5SYNC
 *  @access     PWMCFG->TMR1SYNCEN.bit.PWM5SYNC
 *  @brief      Enable PWM5 synchronization by Timer 1
 */
#define TMR1SYNCEN_ALL_PWM5SYNC_Pos (5)
#define TMR1SYNCEN_ALL_PWM5SYNC_Msk (0x1UL << TMR1SYNCEN_ALL_PWM5SYNC_Pos)

typedef enum
{
    TMR1SYNCEN_BIT_PWM5SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR1SYNCEN_BIT_PWM5SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR1SYNCEN_BIT_PWM5SYNC;

#define TMR1SYNCEN_ALL_PWM5SYNC_DISABLE     ((0x0UL) << TMR1SYNCEN_ALL_PWM5SYNC_Pos)
#define TMR1SYNCEN_ALL_PWM5SYNC_ENABLE      ((0x1UL) << TMR1SYNCEN_ALL_PWM5SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR2SYNCEN      PWM0SYNC
 *  @access     PWMCFG->TMR2SYNCEN.bit.PWM0SYNC
 *  @brief      Enable PWM0 synchronization by Timer 2
 */
#define TMR2SYNCEN_ALL_PWM0SYNC_Pos (0)
#define TMR2SYNCEN_ALL_PWM0SYNC_Msk (0x1UL << TMR2SYNCEN_ALL_PWM0SYNC_Pos)

typedef enum
{
    TMR2SYNCEN_BIT_PWM0SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR2SYNCEN_BIT_PWM0SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR2SYNCEN_BIT_PWM0SYNC;

#define TMR2SYNCEN_ALL_PWM0SYNC_DISABLE     ((0x0UL) << TMR2SYNCEN_ALL_PWM0SYNC_Pos)
#define TMR2SYNCEN_ALL_PWM0SYNC_ENABLE      ((0x1UL) << TMR2SYNCEN_ALL_PWM0SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR2SYNCEN      PWM1SYNC
 *  @access     PWMCFG->TMR2SYNCEN.bit.PWM1SYNC
 *  @brief      Enable PWM1 synchronization by Timer 2
 */
#define TMR2SYNCEN_ALL_PWM1SYNC_Pos (1)
#define TMR2SYNCEN_ALL_PWM1SYNC_Msk (0x1UL << TMR2SYNCEN_ALL_PWM1SYNC_Pos)

typedef enum
{
    TMR2SYNCEN_BIT_PWM1SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR2SYNCEN_BIT_PWM1SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR2SYNCEN_BIT_PWM1SYNC;

#define TMR2SYNCEN_ALL_PWM1SYNC_DISABLE     ((0x0UL) << TMR2SYNCEN_ALL_PWM1SYNC_Pos)
#define TMR2SYNCEN_ALL_PWM1SYNC_ENABLE      ((0x1UL) << TMR2SYNCEN_ALL_PWM1SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR2SYNCEN      PWM2SYNC
 *  @access     PWMCFG->TMR2SYNCEN.bit.PWM2SYNC
 *  @brief      Enable PWM2 synchronization by Timer 2
 */
#define TMR2SYNCEN_ALL_PWM2SYNC_Pos (2)
#define TMR2SYNCEN_ALL_PWM2SYNC_Msk (0x1UL << TMR2SYNCEN_ALL_PWM2SYNC_Pos)

typedef enum
{
    TMR2SYNCEN_BIT_PWM2SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR2SYNCEN_BIT_PWM2SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR2SYNCEN_BIT_PWM2SYNC;

#define TMR2SYNCEN_ALL_PWM2SYNC_DISABLE     ((0x0UL) << TMR2SYNCEN_ALL_PWM2SYNC_Pos)
#define TMR2SYNCEN_ALL_PWM2SYNC_ENABLE      ((0x1UL) << TMR2SYNCEN_ALL_PWM2SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR2SYNCEN      PWM3SYNC
 *  @access     PWMCFG->TMR2SYNCEN.bit.PWM3SYNC
 *  @brief      Enable PWM3 synchronization by Timer 2
 */
#define TMR2SYNCEN_ALL_PWM3SYNC_Pos (3)
#define TMR2SYNCEN_ALL_PWM3SYNC_Msk (0x1UL << TMR2SYNCEN_ALL_PWM3SYNC_Pos)

typedef enum
{
    TMR2SYNCEN_BIT_PWM3SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR2SYNCEN_BIT_PWM3SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR2SYNCEN_BIT_PWM3SYNC;

#define TMR2SYNCEN_ALL_PWM3SYNC_DISABLE     ((0x0UL) << TMR2SYNCEN_ALL_PWM3SYNC_Pos)
#define TMR2SYNCEN_ALL_PWM3SYNC_ENABLE      ((0x1UL) << TMR2SYNCEN_ALL_PWM3SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR2SYNCEN      PWM4SYNC
 *  @access     PWMCFG->TMR2SYNCEN.bit.PWM4SYNC
 *  @brief      Enable PWM4 synchronization by Timer 2
 */
#define TMR2SYNCEN_ALL_PWM4SYNC_Pos (4)
#define TMR2SYNCEN_ALL_PWM4SYNC_Msk (0x1UL << TMR2SYNCEN_ALL_PWM4SYNC_Pos)

typedef enum
{
    TMR2SYNCEN_BIT_PWM4SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR2SYNCEN_BIT_PWM4SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR2SYNCEN_BIT_PWM4SYNC;

#define TMR2SYNCEN_ALL_PWM4SYNC_DISABLE     ((0x0UL) << TMR2SYNCEN_ALL_PWM4SYNC_Pos)
#define TMR2SYNCEN_ALL_PWM4SYNC_ENABLE      ((0x1UL) << TMR2SYNCEN_ALL_PWM4SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          TMR2SYNCEN      PWM5SYNC
 *  @access     PWMCFG->TMR2SYNCEN.bit.PWM5SYNC
 *  @brief      Enable PWM5 synchronization by Timer 2
 */
#define TMR2SYNCEN_ALL_PWM5SYNC_Pos (5)
#define TMR2SYNCEN_ALL_PWM5SYNC_Msk (0x1UL << TMR2SYNCEN_ALL_PWM5SYNC_Pos)

typedef enum
{
    TMR2SYNCEN_BIT_PWM5SYNC_DISABLE     = 0,  /*!< Disable   */
    TMR2SYNCEN_BIT_PWM5SYNC_ENABLE      = 1,  /*!< Enable    */
} TMR2SYNCEN_BIT_PWM5SYNC;

#define TMR2SYNCEN_ALL_PWM5SYNC_DISABLE     ((0x0UL) << TMR2SYNCEN_ALL_PWM5SYNC_Pos)
#define TMR2SYNCEN_ALL_PWM5SYNC_ENABLE      ((0x1UL) << TMR2SYNCEN_ALL_PWM5SYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SYNCOCTL        DURATION
 *  @access     PWMCFG->SYNCOCTL.bit.DURATION
 *  @brief      Pulse duration of PWMSYNCO to the pin
 */
#define SYNCOCTL_ALL_DURATION_Pos (0)
#define SYNCOCTL_ALL_DURATION_Msk (0x3UL << SYNCOCTL_ALL_DURATION_Pos)

typedef enum
{
    SYNCOCTL_BIT_DURATION_4_PWM_CLK      = 0,  /*!< Duration of PWMSYNCO pulse to the pin is 4 PWM clocks    */
    SYNCOCTL_BIT_DURATION_8_PWM_CLK      = 1,  /*!< Duration of PWMSYNCO pulse to the pin is 8 PWM clocks    */
    SYNCOCTL_BIT_DURATION_16_PWM_CLK     = 2,  /*!< Duration of PWMSYNCO pulse to the pin is 16 PWM clocks   */
    SYNCOCTL_BIT_DURATION_32_PWM_CLK     = 3,  /*!< Duration of PWMSYNCO pulse to the pin is 32 PWM clocks   */
} SYNCOCTL_BIT_DURATION;

#define SYNCOCTL_ALL_DURATION_4_PWM_CLK      ((0x0UL) << SYNCOCTL_ALL_DURATION_Pos)
#define SYNCOCTL_ALL_DURATION_8_PWM_CLK      ((0x1UL) << SYNCOCTL_ALL_DURATION_Pos)
#define SYNCOCTL_ALL_DURATION_16_PWM_CLK     ((0x2UL) << SYNCOCTL_ALL_DURATION_Pos)
#define SYNCOCTL_ALL_DURATION_32_PWM_CLK     ((0x3UL) << SYNCOCTL_ALL_DURATION_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SYNCOCTL        POL
 *  @access     PWMCFG->SYNCOCTL.bit.POL
 *  @brief      Polarity of PWMSYNCO to the pin
 */
#define SYNCOCTL_ALL_POL_Pos (2)
#define SYNCOCTL_ALL_POL_Msk (0x1UL << SYNCOCTL_ALL_POL_Pos)

typedef enum
{
    SYNCOCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    SYNCOCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} SYNCOCTL_BIT_POL;

#define SYNCOCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << SYNCOCTL_ALL_POL_Pos)
#define SYNCOCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << SYNCOCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SYNCOCTL        SRCSEL
 *  @access     PWMCFG->SYNCOCTL.bit.SRCSEL
 *  @brief      PWMSYNCO source select
 */
#define SYNCOCTL_ALL_SRCSEL_Pos (3)
#define SYNCOCTL_ALL_SRCSEL_Msk (0x7UL << SYNCOCTL_ALL_SRCSEL_Pos)

typedef enum
{
    SYNCOCTL_BIT_SRCSEL_PWM0     = 0,  /*!< Source select from PWM0   */
    SYNCOCTL_BIT_SRCSEL_PWM1     = 1,  /*!< Source select from PWM1   */
    SYNCOCTL_BIT_SRCSEL_PWM2     = 2,  /*!< Source select from PWM2   */
    SYNCOCTL_BIT_SRCSEL_PWM3     = 3,  /*!< Source select from PWM3   */
    SYNCOCTL_BIT_SRCSEL_PWM4     = 4,  /*!< Source select from PWM4   */
    SYNCOCTL_BIT_SRCSEL_PWM5     = 5,  /*!< Source select from PWM5   */
} SYNCOCTL_BIT_SRCSEL;

#define SYNCOCTL_ALL_SRCSEL_PWM0     ((0x0UL) << SYNCOCTL_ALL_SRCSEL_Pos)
#define SYNCOCTL_ALL_SRCSEL_PWM1     ((0x1UL) << SYNCOCTL_ALL_SRCSEL_Pos)
#define SYNCOCTL_ALL_SRCSEL_PWM2     ((0x2UL) << SYNCOCTL_ALL_SRCSEL_Pos)
#define SYNCOCTL_ALL_SRCSEL_PWM3     ((0x3UL) << SYNCOCTL_ALL_SRCSEL_Pos)
#define SYNCOCTL_ALL_SRCSEL_PWM4     ((0x4UL) << SYNCOCTL_ALL_SRCSEL_Pos)
#define SYNCOCTL_ALL_SRCSEL_PWM5     ((0x5UL) << SYNCOCTL_ALL_SRCSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCAOCTL        DURATION
 *  @access     PWMCFG->SOCAOCTL.bit.DURATION
 *  @brief      Pulse duration of PWMSOCA output to the pin
 */
#define SOCAOCTL_ALL_DURATION_Pos (0)
#define SOCAOCTL_ALL_DURATION_Msk (0x3UL << SOCAOCTL_ALL_DURATION_Pos)

typedef enum
{
    SOCAOCTL_BIT_DURATION_4_PWM_CLK      = 0,  /*!< Duration of PWMSOCA pulse to the pin is 4 PWM clocks    */
    SOCAOCTL_BIT_DURATION_8_PWM_CLK      = 1,  /*!< Duration of PWMSOCA pulse to the pin is 8 PWM clocks    */
    SOCAOCTL_BIT_DURATION_16_PWM_CLK     = 2,  /*!< Duration of PWMSOCA pulse to the pin is 16 PWM clocks   */
    SOCAOCTL_BIT_DURATION_32_PWM_CLK     = 3,  /*!< Duration of PWMSOCA pulse to the pin is 32 PWM clocks   */
} SOCAOCTL_BIT_DURATION;

#define SOCAOCTL_ALL_DURATION_4_PWM_CLK      ((0x0UL) << SOCAOCTL_ALL_DURATION_Pos)
#define SOCAOCTL_ALL_DURATION_8_PWM_CLK      ((0x1UL) << SOCAOCTL_ALL_DURATION_Pos)
#define SOCAOCTL_ALL_DURATION_16_PWM_CLK     ((0x2UL) << SOCAOCTL_ALL_DURATION_Pos)
#define SOCAOCTL_ALL_DURATION_32_PWM_CLK     ((0x3UL) << SOCAOCTL_ALL_DURATION_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCAOCTL        POL
 *  @access     PWMCFG->SOCAOCTL.bit.POL
 *  @brief      Polarity of PWMSOCA output to the pin
 */
#define SOCAOCTL_ALL_POL_Pos (2)
#define SOCAOCTL_ALL_POL_Msk (0x1UL << SOCAOCTL_ALL_POL_Pos)

typedef enum
{
    SOCAOCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    SOCAOCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} SOCAOCTL_BIT_POL;

#define SOCAOCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << SOCAOCTL_ALL_POL_Pos)
#define SOCAOCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << SOCAOCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCAOCTL        SOCA0EN
 *  @access     PWMCFG->SOCAOCTL.bit.SOCA0EN
 *  @brief      Enable PWM0SOCA output to the pin
 */
#define SOCAOCTL_ALL_SOCA0EN_Pos (3)
#define SOCAOCTL_ALL_SOCA0EN_Msk (0x1UL << SOCAOCTL_ALL_SOCA0EN_Pos)

typedef enum
{
    SOCAOCTL_BIT_SOCA0EN_DISABLE     = 0,  /*!< Disable   */
    SOCAOCTL_BIT_SOCA0EN_ENABLE      = 1,  /*!< Enable    */
} SOCAOCTL_BIT_SOCA0EN;

#define SOCAOCTL_ALL_SOCA0EN_DISABLE     ((0x0UL) << SOCAOCTL_ALL_SOCA0EN_Pos)
#define SOCAOCTL_ALL_SOCA0EN_ENABLE      ((0x1UL) << SOCAOCTL_ALL_SOCA0EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCAOCTL        SOCA1EN
 *  @access     PWMCFG->SOCAOCTL.bit.SOCA1EN
 *  @brief      Enable PWM1SOCA output to the pin
 */
#define SOCAOCTL_ALL_SOCA1EN_Pos (4)
#define SOCAOCTL_ALL_SOCA1EN_Msk (0x1UL << SOCAOCTL_ALL_SOCA1EN_Pos)

typedef enum
{
    SOCAOCTL_BIT_SOCA1EN_DISABLE     = 0,  /*!< Disable   */
    SOCAOCTL_BIT_SOCA1EN_ENABLE      = 1,  /*!< Enable    */
} SOCAOCTL_BIT_SOCA1EN;

#define SOCAOCTL_ALL_SOCA1EN_DISABLE     ((0x0UL) << SOCAOCTL_ALL_SOCA1EN_Pos)
#define SOCAOCTL_ALL_SOCA1EN_ENABLE      ((0x1UL) << SOCAOCTL_ALL_SOCA1EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCAOCTL        SOCA2EN
 *  @access     PWMCFG->SOCAOCTL.bit.SOCA2EN
 *  @brief      Enable PWM2SOCA output to the pin
 */
#define SOCAOCTL_ALL_SOCA2EN_Pos (5)
#define SOCAOCTL_ALL_SOCA2EN_Msk (0x1UL << SOCAOCTL_ALL_SOCA2EN_Pos)

typedef enum
{
    SOCAOCTL_BIT_SOCA2EN_DISABLE     = 0,  /*!< Disable   */
    SOCAOCTL_BIT_SOCA2EN_ENABLE      = 1,  /*!< Enable    */
} SOCAOCTL_BIT_SOCA2EN;

#define SOCAOCTL_ALL_SOCA2EN_DISABLE     ((0x0UL) << SOCAOCTL_ALL_SOCA2EN_Pos)
#define SOCAOCTL_ALL_SOCA2EN_ENABLE      ((0x1UL) << SOCAOCTL_ALL_SOCA2EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCAOCTL        SOCA3EN
 *  @access     PWMCFG->SOCAOCTL.bit.SOCA3EN
 *  @brief      Enable PWM3SOCA output to the pin
 */
#define SOCAOCTL_ALL_SOCA3EN_Pos (6)
#define SOCAOCTL_ALL_SOCA3EN_Msk (0x1UL << SOCAOCTL_ALL_SOCA3EN_Pos)

typedef enum
{
    SOCAOCTL_BIT_SOCA3EN_DISABLE     = 0,  /*!< Disable   */
    SOCAOCTL_BIT_SOCA3EN_ENABLE      = 1,  /*!< Enable    */
} SOCAOCTL_BIT_SOCA3EN;

#define SOCAOCTL_ALL_SOCA3EN_DISABLE     ((0x0UL) << SOCAOCTL_ALL_SOCA3EN_Pos)
#define SOCAOCTL_ALL_SOCA3EN_ENABLE      ((0x1UL) << SOCAOCTL_ALL_SOCA3EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCAOCTL        SOCA4EN
 *  @access     PWMCFG->SOCAOCTL.bit.SOCA4EN
 *  @brief      Enable PWM4SOCA output to the pin
 */
#define SOCAOCTL_ALL_SOCA4EN_Pos (7)
#define SOCAOCTL_ALL_SOCA4EN_Msk (0x1UL << SOCAOCTL_ALL_SOCA4EN_Pos)

typedef enum
{
    SOCAOCTL_BIT_SOCA4EN_DISABLE     = 0,  /*!< Disable   */
    SOCAOCTL_BIT_SOCA4EN_ENABLE      = 1,  /*!< Enable    */
} SOCAOCTL_BIT_SOCA4EN;

#define SOCAOCTL_ALL_SOCA4EN_DISABLE     ((0x0UL) << SOCAOCTL_ALL_SOCA4EN_Pos)
#define SOCAOCTL_ALL_SOCA4EN_ENABLE      ((0x1UL) << SOCAOCTL_ALL_SOCA4EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCAOCTL        SOCA5EN
 *  @access     PWMCFG->SOCAOCTL.bit.SOCA5EN
 *  @brief      Enable PWM5SOCA output to the pin
 */
#define SOCAOCTL_ALL_SOCA5EN_Pos (8)
#define SOCAOCTL_ALL_SOCA5EN_Msk (0x1UL << SOCAOCTL_ALL_SOCA5EN_Pos)

typedef enum
{
    SOCAOCTL_BIT_SOCA5EN_DISABLE     = 0,  /*!< Disable   */
    SOCAOCTL_BIT_SOCA5EN_ENABLE      = 1,  /*!< Enable    */
} SOCAOCTL_BIT_SOCA5EN;

#define SOCAOCTL_ALL_SOCA5EN_DISABLE     ((0x0UL) << SOCAOCTL_ALL_SOCA5EN_Pos)
#define SOCAOCTL_ALL_SOCA5EN_ENABLE      ((0x1UL) << SOCAOCTL_ALL_SOCA5EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCBOCTL        DURATION
 *  @access     PWMCFG->SOCBOCTL.bit.DURATION
 *  @brief      Pulse duration of PWMSOCB output to the pin
 */
#define SOCBOCTL_ALL_DURATION_Pos (0)
#define SOCBOCTL_ALL_DURATION_Msk (0x3UL << SOCBOCTL_ALL_DURATION_Pos)

typedef enum
{
    SOCBOCTL_BIT_DURATION_4_PWM_CLK      = 0,  /*!< Duration of PWMSOCB pulse to the pin is 4 PWM clocks    */
    SOCBOCTL_BIT_DURATION_8_PWM_CLK      = 1,  /*!< Duration of PWMSOCB pulse to the pin is 8 PWM clocks    */
    SOCBOCTL_BIT_DURATION_16_PWM_CLK     = 2,  /*!< Duration of PWMSOCB pulse to the pin is 16 PWM clocks   */
    SOCBOCTL_BIT_DURATION_32_PWM_CLK     = 3,  /*!< Duration of PWMSOCB pulse to the pin is 32 PWM clocks   */
} SOCBOCTL_BIT_DURATION;

#define SOCBOCTL_ALL_DURATION_4_PWM_CLK      ((0x0UL) << SOCBOCTL_ALL_DURATION_Pos)
#define SOCBOCTL_ALL_DURATION_8_PWM_CLK      ((0x1UL) << SOCBOCTL_ALL_DURATION_Pos)
#define SOCBOCTL_ALL_DURATION_16_PWM_CLK     ((0x2UL) << SOCBOCTL_ALL_DURATION_Pos)
#define SOCBOCTL_ALL_DURATION_32_PWM_CLK     ((0x3UL) << SOCBOCTL_ALL_DURATION_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCBOCTL        POL
 *  @access     PWMCFG->SOCBOCTL.bit.POL
 *  @brief      Polarity of PWMSOCB output to the pin
 */
#define SOCBOCTL_ALL_POL_Pos (2)
#define SOCBOCTL_ALL_POL_Msk (0x1UL << SOCBOCTL_ALL_POL_Pos)

typedef enum
{
    SOCBOCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    SOCBOCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} SOCBOCTL_BIT_POL;

#define SOCBOCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << SOCBOCTL_ALL_POL_Pos)
#define SOCBOCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << SOCBOCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCBOCTL        SOCB0EN
 *  @access     PWMCFG->SOCBOCTL.bit.SOCB0EN
 *  @brief      Enable PWM0SOCB output to the pin
 */
#define SOCBOCTL_ALL_SOCB0EN_Pos (3)
#define SOCBOCTL_ALL_SOCB0EN_Msk (0x1UL << SOCBOCTL_ALL_SOCB0EN_Pos)

typedef enum
{
    SOCBOCTL_BIT_SOCB0EN_DISABLE     = 0,  /*!< Disable   */
    SOCBOCTL_BIT_SOCB0EN_ENABLE      = 1,  /*!< Enable    */
} SOCBOCTL_BIT_SOCB0EN;

#define SOCBOCTL_ALL_SOCB0EN_DISABLE     ((0x0UL) << SOCBOCTL_ALL_SOCB0EN_Pos)
#define SOCBOCTL_ALL_SOCB0EN_ENABLE      ((0x1UL) << SOCBOCTL_ALL_SOCB0EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCBOCTL        SOCB1EN
 *  @access     PWMCFG->SOCBOCTL.bit.SOCB1EN
 *  @brief      Enable PWM1SOCB output to the pin
 */
#define SOCBOCTL_ALL_SOCB1EN_Pos (4)
#define SOCBOCTL_ALL_SOCB1EN_Msk (0x1UL << SOCBOCTL_ALL_SOCB1EN_Pos)

typedef enum
{
    SOCBOCTL_BIT_SOCB1EN_DISABLE     = 0,  /*!< Disable   */
    SOCBOCTL_BIT_SOCB1EN_ENABLE      = 1,  /*!< Enable    */
} SOCBOCTL_BIT_SOCB1EN;

#define SOCBOCTL_ALL_SOCB1EN_DISABLE     ((0x0UL) << SOCBOCTL_ALL_SOCB1EN_Pos)
#define SOCBOCTL_ALL_SOCB1EN_ENABLE      ((0x1UL) << SOCBOCTL_ALL_SOCB1EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCBOCTL        SOCB2EN
 *  @access     PWMCFG->SOCBOCTL.bit.SOCB2EN
 *  @brief      Enable PWM2SOCB output to the pin
 */
#define SOCBOCTL_ALL_SOCB2EN_Pos (5)
#define SOCBOCTL_ALL_SOCB2EN_Msk (0x1UL << SOCBOCTL_ALL_SOCB2EN_Pos)

typedef enum
{
    SOCBOCTL_BIT_SOCB2EN_DISABLE     = 0,  /*!< Disable   */
    SOCBOCTL_BIT_SOCB2EN_ENABLE      = 1,  /*!< Enable    */
} SOCBOCTL_BIT_SOCB2EN;

#define SOCBOCTL_ALL_SOCB2EN_DISABLE     ((0x0UL) << SOCBOCTL_ALL_SOCB2EN_Pos)
#define SOCBOCTL_ALL_SOCB2EN_ENABLE      ((0x1UL) << SOCBOCTL_ALL_SOCB2EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCBOCTL        SOCB3EN
 *  @access     PWMCFG->SOCBOCTL.bit.SOCB3EN
 *  @brief      Enable PWM3SOCB output to the pin
 */
#define SOCBOCTL_ALL_SOCB3EN_Pos (6)
#define SOCBOCTL_ALL_SOCB3EN_Msk (0x1UL << SOCBOCTL_ALL_SOCB3EN_Pos)

typedef enum
{
    SOCBOCTL_BIT_SOCB3EN_DISABLE     = 0,  /*!< Disable   */
    SOCBOCTL_BIT_SOCB3EN_ENABLE      = 1,  /*!< Enable    */
} SOCBOCTL_BIT_SOCB3EN;

#define SOCBOCTL_ALL_SOCB3EN_DISABLE     ((0x0UL) << SOCBOCTL_ALL_SOCB3EN_Pos)
#define SOCBOCTL_ALL_SOCB3EN_ENABLE      ((0x1UL) << SOCBOCTL_ALL_SOCB3EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCBOCTL        SOCB4EN
 *  @access     PWMCFG->SOCBOCTL.bit.SOCB4EN
 *  @brief      Enable PWM4SOCB output to the pin
 */
#define SOCBOCTL_ALL_SOCB4EN_Pos (7)
#define SOCBOCTL_ALL_SOCB4EN_Msk (0x1UL << SOCBOCTL_ALL_SOCB4EN_Pos)

typedef enum
{
    SOCBOCTL_BIT_SOCB4EN_DISABLE     = 0,  /*!< Disable   */
    SOCBOCTL_BIT_SOCB4EN_ENABLE      = 1,  /*!< Enable    */
} SOCBOCTL_BIT_SOCB4EN;

#define SOCBOCTL_ALL_SOCB4EN_DISABLE     ((0x0UL) << SOCBOCTL_ALL_SOCB4EN_Pos)
#define SOCBOCTL_ALL_SOCB4EN_ENABLE      ((0x1UL) << SOCBOCTL_ALL_SOCB4EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCBOCTL        SOCB5EN
 *  @access     PWMCFG->SOCBOCTL.bit.SOCB5EN
 *  @brief      Enable PWM5SOCB output to the pin
 */
#define SOCBOCTL_ALL_SOCB5EN_Pos (8)
#define SOCBOCTL_ALL_SOCB5EN_Msk (0x1UL << SOCBOCTL_ALL_SOCB5EN_Pos)

typedef enum
{
    SOCBOCTL_BIT_SOCB5EN_DISABLE     = 0,  /*!< Disable   */
    SOCBOCTL_BIT_SOCB5EN_ENABLE      = 1,  /*!< Enable    */
} SOCBOCTL_BIT_SOCB5EN;

#define SOCBOCTL_ALL_SOCB5EN_DISABLE     ((0x0UL) << SOCBOCTL_ALL_SOCB5EN_Pos)
#define SOCBOCTL_ALL_SOCB5EN_ENABLE      ((0x1UL) << SOCBOCTL_ALL_SOCB5EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCCOCTL        DURATION
 *  @access     PWMCFG->SOCCOCTL.bit.DURATION
 *  @brief      Pulse duration of PWMSOCC output to the pin
 */
#define SOCCOCTL_ALL_DURATION_Pos (0)
#define SOCCOCTL_ALL_DURATION_Msk (0x3UL << SOCCOCTL_ALL_DURATION_Pos)

typedef enum
{
    SOCCOCTL_BIT_DURATION_4_PWM_CLK      = 0,  /*!< Duration of PWMSOCC pulse to the pin is 4 PWM clocks    */
    SOCCOCTL_BIT_DURATION_8_PWM_CLK      = 1,  /*!< Duration of PWMSOCC pulse to the pin is 8 PWM clocks    */
    SOCCOCTL_BIT_DURATION_16_PWM_CLK     = 2,  /*!< Duration of PWMSOCC pulse to the pin is 16 PWM clocks   */
    SOCCOCTL_BIT_DURATION_32_PWM_CLK     = 3,  /*!< Duration of PWMSOCC pulse to the pin is 32 PWM clocks   */
} SOCCOCTL_BIT_DURATION;

#define SOCCOCTL_ALL_DURATION_4_PWM_CLK      ((0x0UL) << SOCCOCTL_ALL_DURATION_Pos)
#define SOCCOCTL_ALL_DURATION_8_PWM_CLK      ((0x1UL) << SOCCOCTL_ALL_DURATION_Pos)
#define SOCCOCTL_ALL_DURATION_16_PWM_CLK     ((0x2UL) << SOCCOCTL_ALL_DURATION_Pos)
#define SOCCOCTL_ALL_DURATION_32_PWM_CLK     ((0x3UL) << SOCCOCTL_ALL_DURATION_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCCOCTL        POL
 *  @access     PWMCFG->SOCCOCTL.bit.POL
 *  @brief      Polarity of PWMSOCC output to the pin
 */
#define SOCCOCTL_ALL_POL_Pos (2)
#define SOCCOCTL_ALL_POL_Msk (0x1UL << SOCCOCTL_ALL_POL_Pos)

typedef enum
{
    SOCCOCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active when low    */
    SOCCOCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active when high   */
} SOCCOCTL_BIT_POL;

#define SOCCOCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << SOCCOCTL_ALL_POL_Pos)
#define SOCCOCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << SOCCOCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCCOCTL        SOCC0EN
 *  @access     PWMCFG->SOCCOCTL.bit.SOCC0EN
 *  @brief      Enable PWM0SOCC output to the pin
 */
#define SOCCOCTL_ALL_SOCC0EN_Pos (3)
#define SOCCOCTL_ALL_SOCC0EN_Msk (0x1UL << SOCCOCTL_ALL_SOCC0EN_Pos)

typedef enum
{
    SOCCOCTL_BIT_SOCC0EN_DISABLE     = 0,  /*!< Disable   */
    SOCCOCTL_BIT_SOCC0EN_ENABLE      = 1,  /*!< Enable    */
} SOCCOCTL_BIT_SOCC0EN;

#define SOCCOCTL_ALL_SOCC0EN_DISABLE     ((0x0UL) << SOCCOCTL_ALL_SOCC0EN_Pos)
#define SOCCOCTL_ALL_SOCC0EN_ENABLE      ((0x1UL) << SOCCOCTL_ALL_SOCC0EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCCOCTL        SOCC1EN
 *  @access     PWMCFG->SOCCOCTL.bit.SOCC1EN
 *  @brief      Enable PWM1SOCC output to the pin
 */
#define SOCCOCTL_ALL_SOCC1EN_Pos (4)
#define SOCCOCTL_ALL_SOCC1EN_Msk (0x1UL << SOCCOCTL_ALL_SOCC1EN_Pos)

typedef enum
{
    SOCCOCTL_BIT_SOCC1EN_DISABLE     = 0,  /*!< Disable   */
    SOCCOCTL_BIT_SOCC1EN_ENABLE      = 1,  /*!< Enable    */
} SOCCOCTL_BIT_SOCC1EN;

#define SOCCOCTL_ALL_SOCC1EN_DISABLE     ((0x0UL) << SOCCOCTL_ALL_SOCC1EN_Pos)
#define SOCCOCTL_ALL_SOCC1EN_ENABLE      ((0x1UL) << SOCCOCTL_ALL_SOCC1EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCCOCTL        SOCC2EN
 *  @access     PWMCFG->SOCCOCTL.bit.SOCC2EN
 *  @brief      Enable PWM2SOCC output to the pin
 */
#define SOCCOCTL_ALL_SOCC2EN_Pos (5)
#define SOCCOCTL_ALL_SOCC2EN_Msk (0x1UL << SOCCOCTL_ALL_SOCC2EN_Pos)

typedef enum
{
    SOCCOCTL_BIT_SOCC2EN_DISABLE     = 0,  /*!< Disable   */
    SOCCOCTL_BIT_SOCC2EN_ENABLE      = 1,  /*!< Enable    */
} SOCCOCTL_BIT_SOCC2EN;

#define SOCCOCTL_ALL_SOCC2EN_DISABLE     ((0x0UL) << SOCCOCTL_ALL_SOCC2EN_Pos)
#define SOCCOCTL_ALL_SOCC2EN_ENABLE      ((0x1UL) << SOCCOCTL_ALL_SOCC2EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCCOCTL        SOCC3EN
 *  @access     PWMCFG->SOCCOCTL.bit.SOCC3EN
 *  @brief      Enable PWM3SOCC output to the pin
 */
#define SOCCOCTL_ALL_SOCC3EN_Pos (6)
#define SOCCOCTL_ALL_SOCC3EN_Msk (0x1UL << SOCCOCTL_ALL_SOCC3EN_Pos)

typedef enum
{
    SOCCOCTL_BIT_SOCC3EN_DISABLE     = 0,  /*!< Disable   */
    SOCCOCTL_BIT_SOCC3EN_ENABLE      = 1,  /*!< Enable    */
} SOCCOCTL_BIT_SOCC3EN;

#define SOCCOCTL_ALL_SOCC3EN_DISABLE     ((0x0UL) << SOCCOCTL_ALL_SOCC3EN_Pos)
#define SOCCOCTL_ALL_SOCC3EN_ENABLE      ((0x1UL) << SOCCOCTL_ALL_SOCC3EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCCOCTL        SOCC4EN
 *  @access     PWMCFG->SOCCOCTL.bit.SOCC4EN
 *  @brief      Enable PWM4SOCC output to the pin
 */
#define SOCCOCTL_ALL_SOCC4EN_Pos (7)
#define SOCCOCTL_ALL_SOCC4EN_Msk (0x1UL << SOCCOCTL_ALL_SOCC4EN_Pos)

typedef enum
{
    SOCCOCTL_BIT_SOCC4EN_DISABLE     = 0,  /*!< Disable   */
    SOCCOCTL_BIT_SOCC4EN_ENABLE      = 1,  /*!< Enable    */
} SOCCOCTL_BIT_SOCC4EN;

#define SOCCOCTL_ALL_SOCC4EN_DISABLE     ((0x0UL) << SOCCOCTL_ALL_SOCC4EN_Pos)
#define SOCCOCTL_ALL_SOCC4EN_ENABLE      ((0x1UL) << SOCCOCTL_ALL_SOCC4EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          SOCCOCTL        SOCC5EN
 *  @access     PWMCFG->SOCCOCTL.bit.SOCC5EN
 *  @brief      Enable PWM5SOCC output to the pin
 */
#define SOCCOCTL_ALL_SOCC5EN_Pos (8)
#define SOCCOCTL_ALL_SOCC5EN_Msk (0x1UL << SOCCOCTL_ALL_SOCC5EN_Pos)

typedef enum
{
    SOCCOCTL_BIT_SOCC5EN_DISABLE     = 0,  /*!< Disable   */
    SOCCOCTL_BIT_SOCC5EN_ENABLE      = 1,  /*!< Enable    */
} SOCCOCTL_BIT_SOCC5EN;

#define SOCCOCTL_ALL_SOCC5EN_DISABLE     ((0x0UL) << SOCCOCTL_ALL_SOCC5EN_Pos)
#define SOCCOCTL_ALL_SOCC5EN_ENABLE      ((0x1UL) << SOCCOCTL_ALL_SOCC5EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   PWMCFG          PWMCFGREGKEY    KEY
 *  @access     PWMCFG->PWMCFGREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected PWMCFG registers
 */
#define PWMCFGREGKEY_ALL_KEY_Pos (0)
#define PWMCFGREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << PWMCFGREGKEY_ALL_KEY_Pos)

#define PWMCFGREGKEY_BIT_KEY

#define PWMCFGREGKEY_ALL_KEY_(x) ((x) << PWMCFGREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     ECAP
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPSRCCTL       IOSEL
 *  @access     ECAP->CAPSRCCTL.bit.IOSEL
 *  @brief      GPIO number to be selected as capture input
 */
#define CAPSRCCTL_ALL_IOSEL_Pos (0)
#define CAPSRCCTL_ALL_IOSEL_Msk (0x3FUL << CAPSRCCTL_ALL_IOSEL_Pos)

#define CAPSRCCTL_BIT_IOSEL

#define CAPSRCCTL_ALL_IOSEL_(x) ((x) << CAPSRCCTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPSRCCTL       POL
 *  @access     ECAP->CAPSRCCTL.bit.POL
 *  @brief      Source input polarity
 */
#define CAPSRCCTL_ALL_POL_Pos (6)
#define CAPSRCCTL_ALL_POL_Msk (0x1UL << CAPSRCCTL_ALL_POL_Pos)

typedef enum
{
    CAPSRCCTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active low    */
    CAPSRCCTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active high   */
} CAPSRCCTL_BIT_POL;

#define CAPSRCCTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << CAPSRCCTL_ALL_POL_Pos)
#define CAPSRCCTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << CAPSRCCTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPSYNCICTL     IOSEL
 *  @access     ECAP->CAPSYNCICTL.bit.IOSEL
 *  @brief      GPIO number to be selected as sync input
 */
#define CAPSYNCICTL_ALL_IOSEL_Pos (0)
#define CAPSYNCICTL_ALL_IOSEL_Msk (0x3FUL << CAPSYNCICTL_ALL_IOSEL_Pos)

#define CAPSYNCICTL_BIT_IOSEL

#define CAPSYNCICTL_ALL_IOSEL_(x) ((x) << CAPSYNCICTL_ALL_IOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPSYNCICTL     POL
 *  @access     ECAP->CAPSYNCICTL.bit.POL
 *  @brief      Source input polarity
 */
#define CAPSYNCICTL_ALL_POL_Pos (6)
#define CAPSYNCICTL_ALL_POL_Msk (0x1UL << CAPSYNCICTL_ALL_POL_Pos)

typedef enum
{
    CAPSYNCICTL_BIT_POL_ACTIVE_LOW      = 0,  /*!< Active low    */
    CAPSYNCICTL_BIT_POL_ACTIVE_HIGH     = 1,  /*!< Active high   */
} CAPSYNCICTL_BIT_POL;

#define CAPSYNCICTL_ALL_POL_ACTIVE_LOW      ((0x0UL) << CAPSYNCICTL_ALL_POL_Pos)
#define CAPSYNCICTL_ALL_POL_ACTIVE_HIGH     ((0x1UL) << CAPSYNCICTL_ALL_POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPTSCNT        VAL
 *  @access     ECAP->CAPTSCNT.bit.VAL
 *  @brief      Active 32-bit counter register that is used as the capture time-base.
 */
#define CAPTSCNT_ALL_VAL_Pos (0)
#define CAPTSCNT_ALL_VAL_Msk (0xFFFFFFFFUL << CAPTSCNT_ALL_VAL_Pos)

#define CAPTSCNT_BIT_VAL

#define CAPTSCNT_ALL_VAL_(x) ((x) << CAPTSCNT_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCNTPHS       VAL
 *  @access     ECAP->CAPCNTPHS.bit.VAL
 *  @brief      Counter phase value register that can be programmed for phase lag/lead.
 */
#define CAPCNTPHS_ALL_VAL_Pos (0)
#define CAPCNTPHS_ALL_VAL_Msk (0xFFFFFFFFUL << CAPCNTPHS_ALL_VAL_Pos)

#define CAPCNTPHS_BIT_VAL

#define CAPCNTPHS_ALL_VAL_(x) ((x) << CAPCNTPHS_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAP0            VAL
 *  @access     ECAP->CAP0.bit.VAL
 *  @brief      This register can be loaded by:
 *              - Time-Stamp(i.e., counter value) during a capture event
 *              - Software - may be useful for test purposes
 *              - APRD shadow register(i.e., CAP2) when used in APWM mode
 *              NOTE: In APWM mode, writing to CAP0/CAP1 active registers also writes the same value
 *              to the corresponding shadow registers CAP2/CAP3. This emulates immediate mode. Writing
 *              to the shadow registers CAP2/CAP3 invokes the shadow mode.
 */
#define CAP0_ALL_VAL_Pos (0)
#define CAP0_ALL_VAL_Msk (0xFFFFFFFFUL << CAP0_ALL_VAL_Pos)

#define CAP0_BIT_VAL

#define CAP0_ALL_VAL_(x) ((x) << CAP0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAP1            VAL
 *  @access     ECAP->CAP1.bit.VAL
 *  @brief      This register can be loaded by:
 *              - Time-Stamp(i.e., counter value) during a capture event
 *              - Software - may be useful for test purposes
 *              - ACMP shadow register(i.e., CAP3) when used in APWM mode
 *              NOTE: In APWM mode, writing to CAP0/CAP1 active registers also writes the same value
 *              to the corresponding shadow registers CAP2/CAP3. This emulates immediate mode. Writing
 *              to the shadow registers CAP2/CAP3 invokes the shadow mode.
 */
#define CAP1_ALL_VAL_Pos (0)
#define CAP1_ALL_VAL_Msk (0xFFFFFFFFUL << CAP1_ALL_VAL_Pos)

#define CAP1_BIT_VAL

#define CAP1_ALL_VAL_(x) ((x) << CAP1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAP2            VAL
 *  @access     ECAP->CAP2.bit.VAL
 *  @brief      In CMP mode, this is a time-stamp capture register. In APWM mode, this is the period
 *              shadow(APRD) register. You update the PWM period value through this register. In
 *              this mode, CAP2(APRD) shadows CAP0.
 */
#define CAP2_ALL_VAL_Pos (0)
#define CAP2_ALL_VAL_Msk (0xFFFFFFFFUL << CAP2_ALL_VAL_Pos)

#define CAP2_BIT_VAL

#define CAP2_ALL_VAL_(x) ((x) << CAP2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAP3            VAL
 *  @access     ECAP->CAP3.bit.VAL
 *  @brief      In CMP mode, this is a time-stamp capture register. In APWM mode, this is the compare
 *              shadow(ACMP) register. You update the PWM compare value via this register. In this
 *              mode, CAP3(ACMP) shadows CAP1.
 */
#define CAP3_ALL_VAL_Pos (0)
#define CAP3_ALL_VAL_Msk (0xFFFFFFFFUL << CAP3_ALL_VAL_Pos)

#define CAP3_BIT_VAL

#define CAP3_ALL_VAL_(x) ((x) << CAP3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CAP0POL
 *  @access     ECAP->CAPCTL.bit.CAP0POL
 *  @brief      Capture event 0 polarity select
 */
#define CAPCTL_ALL_CAP0POL_Pos (0)
#define CAPCTL_ALL_CAP0POL_Msk (0x1UL << CAPCTL_ALL_CAP0POL_Pos)

typedef enum
{
    CAPCTL_BIT_CAP0POL_TRIG_ON_FALLING_EDGE     = 0,  /*!< Capture Event 0 triggered on a falling edge (FE)   */
    CAPCTL_BIT_CAP0POL_TRIG_ON_RISING_EDGE      = 1,  /*!< Capture Event 0 triggered on a rising edge (RE)    */
} CAPCTL_BIT_CAP0POL;

#define CAPCTL_ALL_CAP0POL_TRIG_ON_FALLING_EDGE     ((0x0UL) << CAPCTL_ALL_CAP0POL_Pos)
#define CAPCTL_ALL_CAP0POL_TRIG_ON_RISING_EDGE      ((0x1UL) << CAPCTL_ALL_CAP0POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CNTRST0
 *  @access     ECAP->CAPCTL.bit.CNTRST0
 *  @brief      Counter reset on capture event 0
 */
#define CAPCTL_ALL_CNTRST0_Pos (1)
#define CAPCTL_ALL_CNTRST0_Msk (0x1UL << CAPCTL_ALL_CNTRST0_Pos)

typedef enum
{
    CAPCTL_BIT_CNTRST0_DISABLE     = 0,  /*!< Do not reset counter on Capture Event 0 (absolute time stamp)                       */
    CAPCTL_BIT_CNTRST0_ENABLE      = 1,  /*!< Reset counter after Event 0 time-stamp has been captured (used in difference mode  
                                              operation)                                                                          */
} CAPCTL_BIT_CNTRST0;

#define CAPCTL_ALL_CNTRST0_DISABLE     ((0x0UL) << CAPCTL_ALL_CNTRST0_Pos)
#define CAPCTL_ALL_CNTRST0_ENABLE      ((0x1UL) << CAPCTL_ALL_CNTRST0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CAP1POL
 *  @access     ECAP->CAPCTL.bit.CAP1POL
 *  @brief      Capture event 1 polarity select
 */
#define CAPCTL_ALL_CAP1POL_Pos (2)
#define CAPCTL_ALL_CAP1POL_Msk (0x1UL << CAPCTL_ALL_CAP1POL_Pos)

typedef enum
{
    CAPCTL_BIT_CAP1POL_TRIG_ON_FALLING_EDGE     = 0,  /*!< Capture Event 1 triggered on a falling edge (FE)   */
    CAPCTL_BIT_CAP1POL_TRIG_ON_RISING_EDGE      = 1,  /*!< Capture Event 1 triggered on a rising edge (RE)    */
} CAPCTL_BIT_CAP1POL;

#define CAPCTL_ALL_CAP1POL_TRIG_ON_FALLING_EDGE     ((0x0UL) << CAPCTL_ALL_CAP1POL_Pos)
#define CAPCTL_ALL_CAP1POL_TRIG_ON_RISING_EDGE      ((0x1UL) << CAPCTL_ALL_CAP1POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CNTRST1
 *  @access     ECAP->CAPCTL.bit.CNTRST1
 *  @brief      Counter reset on capture event 1
 */
#define CAPCTL_ALL_CNTRST1_Pos (3)
#define CAPCTL_ALL_CNTRST1_Msk (0x1UL << CAPCTL_ALL_CNTRST1_Pos)

typedef enum
{
    CAPCTL_BIT_CNTRST1_DISABLE     = 0,  /*!< Do not reset counter on Capture Event 1 (absolute time stamp)                       */
    CAPCTL_BIT_CNTRST1_ENABLE      = 1,  /*!< Reset counter after Event 1 time-stamp has been captured (used in difference mode  
                                              operation)                                                                          */
} CAPCTL_BIT_CNTRST1;

#define CAPCTL_ALL_CNTRST1_DISABLE     ((0x0UL) << CAPCTL_ALL_CNTRST1_Pos)
#define CAPCTL_ALL_CNTRST1_ENABLE      ((0x1UL) << CAPCTL_ALL_CNTRST1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CAP2POL
 *  @access     ECAP->CAPCTL.bit.CAP2POL
 *  @brief      Capture event 2 polarity select
 */
#define CAPCTL_ALL_CAP2POL_Pos (4)
#define CAPCTL_ALL_CAP2POL_Msk (0x1UL << CAPCTL_ALL_CAP2POL_Pos)

typedef enum
{
    CAPCTL_BIT_CAP2POL_TRIG_ON_FALLING_EDGE     = 0,  /*!< Capture Event 2 triggered on a falling edge (FE)   */
    CAPCTL_BIT_CAP2POL_TRIG_ON_RISING_EDGE      = 1,  /*!< Capture Event 2 triggered on a rising edge (RE)    */
} CAPCTL_BIT_CAP2POL;

#define CAPCTL_ALL_CAP2POL_TRIG_ON_FALLING_EDGE     ((0x0UL) << CAPCTL_ALL_CAP2POL_Pos)
#define CAPCTL_ALL_CAP2POL_TRIG_ON_RISING_EDGE      ((0x1UL) << CAPCTL_ALL_CAP2POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CNTRST2
 *  @access     ECAP->CAPCTL.bit.CNTRST2
 *  @brief      Counter reset on capture event 2
 */
#define CAPCTL_ALL_CNTRST2_Pos (5)
#define CAPCTL_ALL_CNTRST2_Msk (0x1UL << CAPCTL_ALL_CNTRST2_Pos)

typedef enum
{
    CAPCTL_BIT_CNTRST2_DISABLE     = 0,  /*!< Do not reset counter on Capture Event 2 (absolute time stamp)                       */
    CAPCTL_BIT_CNTRST2_ENABLE      = 1,  /*!< Reset counter after Event 2 time-stamp has been captured (used in difference mode  
                                              operation)                                                                          */
} CAPCTL_BIT_CNTRST2;

#define CAPCTL_ALL_CNTRST2_DISABLE     ((0x0UL) << CAPCTL_ALL_CNTRST2_Pos)
#define CAPCTL_ALL_CNTRST2_ENABLE      ((0x1UL) << CAPCTL_ALL_CNTRST2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CAP3POL
 *  @access     ECAP->CAPCTL.bit.CAP3POL
 *  @brief      Capture event 3 polarity select
 */
#define CAPCTL_ALL_CAP3POL_Pos (6)
#define CAPCTL_ALL_CAP3POL_Msk (0x1UL << CAPCTL_ALL_CAP3POL_Pos)

typedef enum
{
    CAPCTL_BIT_CAP3POL_TRIG_ON_FALLING_EDGE     = 0,  /*!< Capture Event 3 triggered on a falling edge (FE)   */
    CAPCTL_BIT_CAP3POL_TRIG_ON_RISING_EDGE      = 1,  /*!< Capture Event 3 triggered on a rising edge (RE)    */
} CAPCTL_BIT_CAP3POL;

#define CAPCTL_ALL_CAP3POL_TRIG_ON_FALLING_EDGE     ((0x0UL) << CAPCTL_ALL_CAP3POL_Pos)
#define CAPCTL_ALL_CAP3POL_TRIG_ON_RISING_EDGE      ((0x1UL) << CAPCTL_ALL_CAP3POL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CNTRST3
 *  @access     ECAP->CAPCTL.bit.CNTRST3
 *  @brief      Counter reset on capture event 3
 */
#define CAPCTL_ALL_CNTRST3_Pos (7)
#define CAPCTL_ALL_CNTRST3_Msk (0x1UL << CAPCTL_ALL_CNTRST3_Pos)

typedef enum
{
    CAPCTL_BIT_CNTRST3_DISABLE     = 0,  /*!< Do not reset counter on Capture Event 3 (absolute time stamp operation)                */
    CAPCTL_BIT_CNTRST3_ENABLE      = 1,  /*!< Reset counter after Capture Event 3 time-stamp has been captured (used in difference  
                                              mode operation)                                                                        */
} CAPCTL_BIT_CNTRST3;

#define CAPCTL_ALL_CNTRST3_DISABLE     ((0x0UL) << CAPCTL_ALL_CNTRST3_Pos)
#define CAPCTL_ALL_CNTRST3_ENABLE      ((0x1UL) << CAPCTL_ALL_CNTRST3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          CAPLDEN
 *  @access     ECAP->CAPCTL.bit.CAPLDEN
 *  @brief      Enable CAP0-3  loading on a capture event
 */
#define CAPCTL_ALL_CAPLDEN_Pos (8)
#define CAPCTL_ALL_CAPLDEN_Msk (0x1UL << CAPCTL_ALL_CAPLDEN_Pos)

typedef enum
{
    CAPCTL_BIT_CAPLDEN_DISABLE     = 0,  /*!< Disable CAP0-3 register loads at capture event time   */
    CAPCTL_BIT_CAPLDEN_ENABLE      = 1,  /*!< Enable CAP0-3 register loads at capture event time    */
} CAPCTL_BIT_CAPLDEN;

#define CAPCTL_ALL_CAPLDEN_DISABLE     ((0x0UL) << CAPCTL_ALL_CAPLDEN_Pos)
#define CAPCTL_ALL_CAPLDEN_ENABLE      ((0x1UL) << CAPCTL_ALL_CAPLDEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          EVTDIV
 *  @access     ECAP->CAPCTL.bit.EVTDIV
 *  @brief      Event Filter prescale select
 */
#define CAPCTL_ALL_EVTDIV_Pos (9)
#define CAPCTL_ALL_EVTDIV_Msk (0xFFUL << CAPCTL_ALL_EVTDIV_Pos)

#define CAPCTL_BIT_EVTDIV

#define CAPCTL_ALL_EVTDIV_(x) ((x) << CAPCTL_ALL_EVTDIV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          ONESHOT
 *  @access     ECAP->CAPCTL.bit.ONESHOT
 *  @brief      One-shot mode enable (applicable only in capture mode)
 */
#define CAPCTL_ALL_ONESHOT_Pos (17)
#define CAPCTL_ALL_ONESHOT_Msk (0x1UL << CAPCTL_ALL_ONESHOT_Pos)

typedef enum
{
    CAPCTL_BIT_ONESHOT_DISABLE     = 0,  /*!< Operate in continuous mode   */
    CAPCTL_BIT_ONESHOT_ENABLE      = 1,  /*!< Operate in one-shot mode     */
} CAPCTL_BIT_ONESHOT;

#define CAPCTL_ALL_ONESHOT_DISABLE     ((0x0UL) << CAPCTL_ALL_ONESHOT_Pos)
#define CAPCTL_ALL_ONESHOT_ENABLE      ((0x1UL) << CAPCTL_ALL_ONESHOT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          STOPWRAP
 *  @access     ECAP->CAPCTL.bit.STOPWRAP
 *  @brief      Stop value for one-shot mode
 *              This is the number (between 0-3) of captures allowed to occur before the CAP(0-3)
 *              registers are frozen, i.e., capture sequence is stopped.
 *              Wrap value for continuous mode. This is the number (between 0-3) of the capture register
 *              in which the circular buffer wraps around and starts again.
 *              Notes: STOP_WRAP is compared to Mod4 counter and, when equal, 2 actions occur:
 *              - Mod4 counter is stopped (frozen)
 *              - Capture register loads are inhibited
 *              In one-shot mode, further interrupt events are blocked until re-armed.
 */
#define CAPCTL_ALL_STOPWRAP_Pos (18)
#define CAPCTL_ALL_STOPWRAP_Msk (0x3UL << CAPCTL_ALL_STOPWRAP_Pos)

typedef enum
{
    CAPCTL_BIT_STOPWRAP_ON_CAPTURE_EVENT0     = 0,  /*!< Stop after capture event 0 in one-shot mode.    
                                                         Wrap after capture event 0 in continuous mode.   */
    CAPCTL_BIT_STOPWRAP_ON_CAPTURE_EVENT1     = 1,  /*!< Stop after capture event 1 in one-shot mode.    
                                                         Wrap after capture event 1 in continuous mode.   */
    CAPCTL_BIT_STOPWRAP_ON_CAPTURE_EVENT2     = 2,  /*!< Stop after capture event 2 in one-shot mode.    
                                                         Wrap after capture event 2 in continuous mode.   */
    CAPCTL_BIT_STOPWRAP_ON_CAPTURE_EVENT3     = 3,  /*!< Stop after capture event 3 in one-shot mode.    
                                                         Wrap after capture event 3 in continuous mode.   */
} CAPCTL_BIT_STOPWRAP;

#define CAPCTL_ALL_STOPWRAP_ON_CAPTURE_EVENT0     ((0x0UL) << CAPCTL_ALL_STOPWRAP_Pos)
#define CAPCTL_ALL_STOPWRAP_ON_CAPTURE_EVENT1     ((0x1UL) << CAPCTL_ALL_STOPWRAP_Pos)
#define CAPCTL_ALL_STOPWRAP_ON_CAPTURE_EVENT2     ((0x2UL) << CAPCTL_ALL_STOPWRAP_Pos)
#define CAPCTL_ALL_STOPWRAP_ON_CAPTURE_EVENT3     ((0x3UL) << CAPCTL_ALL_STOPWRAP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          REARM
 *  @access     ECAP->CAPCTL.bit.REARM
 *  @brief      One-Shot Re-Arming Control, i.e. wait for stop trigger. Note: The re-arm function
 *              is valid in one shot or continuous mode.
 */
#define CAPCTL_ALL_REARM_Pos (20)
#define CAPCTL_ALL_REARM_Msk (0x1UL << CAPCTL_ALL_REARM_Pos)

typedef enum
{
    CAPCTL_BIT_REARM_NO_EFFECT     = 0,  /*!< Write a 0 has no effect.                
                                              Always reads back a 0.                   */
    CAPCTL_BIT_REARM_ENABLE        = 1,  /*!< Arms the one-shot sequence as follows:  
                                              1) Resets the Mod4 counter to zero      
                                              2) Unfreezes the Mod4 counter           
                                              3) Enables capture register loads        */
} CAPCTL_BIT_REARM;

#define CAPCTL_ALL_REARM_NO_EFFECT     ((0x0UL) << CAPCTL_ALL_REARM_Pos)
#define CAPCTL_ALL_REARM_ENABLE        ((0x1UL) << CAPCTL_ALL_REARM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          TSCNTRUN
 *  @access     ECAP->CAPCTL.bit.TSCNTRUN
 *  @brief      Time stamp counter (TSCNT) run/stop control
 */
#define CAPCTL_ALL_TSCNTRUN_Pos (21)
#define CAPCTL_ALL_TSCNTRUN_Msk (0x1UL << CAPCTL_ALL_TSCNTRUN_Pos)

typedef enum
{
    CAPCTL_BIT_TSCNTRUN_STOP_COUNTER      = 0,  /*!< TSCNT stopped        */
    CAPCTL_BIT_TSCNTRUN_START_COUNTER     = 1,  /*!< TSCNT free-running   */
} CAPCTL_BIT_TSCNTRUN;

#define CAPCTL_ALL_TSCNTRUN_STOP_COUNTER      ((0x0UL) << CAPCTL_ALL_TSCNTRUN_Pos)
#define CAPCTL_ALL_TSCNTRUN_START_COUNTER     ((0x1UL) << CAPCTL_ALL_TSCNTRUN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          PHSEN
 *  @access     ECAP->CAPCTL.bit.PHSEN
 *  @brief      Phase synchronization enable
 */
#define CAPCTL_ALL_PHSEN_Pos (22)
#define CAPCTL_ALL_PHSEN_Msk (0x1UL << CAPCTL_ALL_PHSEN_Pos)

typedef enum
{
    CAPCTL_BIT_PHSEN_DISABLE     = 0,  /*!< Disable synchronization                                                              */
    CAPCTL_BIT_PHSEN_ENABLE      = 1,  /*!< Enable counter (CAPTSCNT) to be loaded from CAPCNTPHS register upon either a SYNCI  
                                            signal or a S/W force event                                                          */
} CAPCTL_BIT_PHSEN;

#define CAPCTL_ALL_PHSEN_DISABLE     ((0x0UL) << CAPCTL_ALL_PHSEN_Pos)
#define CAPCTL_ALL_PHSEN_ENABLE      ((0x1UL) << CAPCTL_ALL_PHSEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          SYNCOSEL
 *  @access     ECAP->CAPCTL.bit.SYNCOSEL
 *  @brief      Sync-Out Select
 */
#define CAPCTL_ALL_SYNCOSEL_Pos (23)
#define CAPCTL_ALL_SYNCOSEL_Msk (0x3UL << CAPCTL_ALL_SYNCOSEL_Pos)

typedef enum
{
    CAPCTL_BIT_SYNCOSEL_DISABLE_SYNC_OUT     = 0,  /*!< Disable sync out signal                                         */
    CAPCTL_BIT_SYNCOSEL_SYNC_IN              = 2,  /*!< Select sync-in event to be the sync-out signal (pass through)   */
    CAPCTL_BIT_SYNCOSEL_CNT_EQU_PRD          = 3,  /*!< Select CNT = PRD event to be the sync-out signal                */
} CAPCTL_BIT_SYNCOSEL;

#define CAPCTL_ALL_SYNCOSEL_DISABLE_SYNC_OUT     ((0x0UL) << CAPCTL_ALL_SYNCOSEL_Pos)
#define CAPCTL_ALL_SYNCOSEL_SYNC_IN              ((0x2UL) << CAPCTL_ALL_SYNCOSEL_Pos)
#define CAPCTL_ALL_SYNCOSEL_CNT_EQU_PRD          ((0x3UL) << CAPCTL_ALL_SYNCOSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          FRCSYNC
 *  @access     ECAP->CAPCTL.bit.FRCSYNC
 *  @brief      Software-forced Counter (TSCNT) Synchronizing. This provides a convenient software
 *              method to synchronize some or all ECAP time bases. In APWM mode, the synchronizing
 *              can also be done via the CNT = PRD event.
 *              Note: Selection CNT = PRD is meaningful only in APWM mode; however, you can choose
 *              it in CAP mode if you find doing so useful.
 */
#define CAPCTL_ALL_FRCSYNC_Pos (25)
#define CAPCTL_ALL_FRCSYNC_Msk (0x1UL << CAPCTL_ALL_FRCSYNC_Pos)

typedef enum
{
    CAPCTL_BIT_FRCSYNC_NO_EFFECT     = 0,  /*!< Writing a zero has no effect. Reading always returns a zero                            */
    CAPCTL_BIT_FRCSYNC_ENABLE        = 1,  /*!< Writing a one forces a TSCNT shadow load of current ECAP module and any ECAP modules  
                                                down-stream providing the SYNCOSEL bits are 00. After writing a 1, this bit returns   
                                                to a zero.                                                                             */
} CAPCTL_BIT_FRCSYNC;

#define CAPCTL_ALL_FRCSYNC_NO_EFFECT     ((0x0UL) << CAPCTL_ALL_FRCSYNC_Pos)
#define CAPCTL_ALL_FRCSYNC_ENABLE        ((0x1UL) << CAPCTL_ALL_FRCSYNC_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          APWMMODE
 *  @access     ECAP->CAPCTL.bit.APWMMODE
 *  @brief      CAP/APWM operating mode select
 */
#define CAPCTL_ALL_APWMMODE_Pos (26)
#define CAPCTL_ALL_APWMMODE_Msk (0x1UL << CAPCTL_ALL_APWMMODE_Pos)

typedef enum
{
    CAPCTL_BIT_APWMMODE_CAPTURE_MODE     = 0,  /*!< ECAP module operates in capture mode. This mode forces the following configuration:  
                                                    - Inhibits TSCNT resets via CNT = PRD event                                          
                                                    - Inhibits shadow loads on CAP0 and CAP1 registers                                   
                                                    - Permits user to enable CAP0-3 register load                                        
                                                    - CAPx/APWMx pin operates as a capture input                                          */
    CAPCTL_BIT_APWMMODE_APWM_MODE        = 1,  /*!< ECAP module operates in APWM mode. This mode forces the following configuration:     
                                                    - Resets TSCNT on CNT = PRD event (period boundary                                   
                                                    - Permits shadow loading on CAP0 and CAP1 registers                                  
                                                    - Disables loading of time-stamps into CAP0-3 registers                              
                                                    - CAPx/APWMx pin operates as a APWM output                                            */
} CAPCTL_BIT_APWMMODE;

#define CAPCTL_ALL_APWMMODE_CAPTURE_MODE     ((0x0UL) << CAPCTL_ALL_APWMMODE_Pos)
#define CAPCTL_ALL_APWMMODE_APWM_MODE        ((0x1UL) << CAPCTL_ALL_APWMMODE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          APWMPOL
 *  @access     ECAP->CAPCTL.bit.APWMPOL
 *  @brief      APWM output polarity select. This is applicable only in APWM operating mode.
 */
#define CAPCTL_ALL_APWMPOL_Pos (27)
#define CAPCTL_ALL_APWMPOL_Msk (0x1UL << CAPCTL_ALL_APWMPOL_Pos)

typedef enum
{
    CAPCTL_BIT_APWMPOL_ACTIVE_LOW      = 0,  /*!< Output is active low (i.e., Compare value defines low time)     */
    CAPCTL_BIT_APWMPOL_ACTIVE_HIGH     = 1,  /*!< Output is active high (i.e., Compare value defines high time)   */
} CAPCTL_BIT_APWMPOL;

#define CAPCTL_ALL_APWMPOL_ACTIVE_LOW      ((0x0UL) << CAPCTL_ALL_APWMPOL_Pos)
#define CAPCTL_ALL_APWMPOL_ACTIVE_HIGH     ((0x1UL) << CAPCTL_ALL_APWMPOL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPCTL          DBGRUN
 *  @access     ECAP->CAPCTL.bit.DBGRUN
 *  @brief      ECAP counter behaviour when CPU is halted
 *              Note: Debug operation and CPU fault exceptions both can cause CPU halted.
 */
#define CAPCTL_ALL_DBGRUN_Pos (28)
#define CAPCTL_ALL_DBGRUN_Msk (0x3UL << CAPCTL_ALL_DBGRUN_Pos)

typedef enum
{
    CAPCTL_BIT_DBGRUN_STOP_IMMEDIATELY     = 0,  /*!< TSCNT counter stops immediately when CPU is halted   */
    CAPCTL_BIT_DBGRUN_STOP_AT_ZERO         = 1,  /*!< TSCNT counter runs until = 0 when CPU is halted      */
    CAPCTL_BIT_DBGRUN_KEEP_RUN             = 2,  /*!< TSCNT counter is unaffected when CPU is halted       */
} CAPCTL_BIT_DBGRUN;

#define CAPCTL_ALL_DBGRUN_STOP_IMMEDIATELY     ((0x0UL) << CAPCTL_ALL_DBGRUN_Pos)
#define CAPCTL_ALL_DBGRUN_STOP_AT_ZERO         ((0x1UL) << CAPCTL_ALL_DBGRUN_Pos)
#define CAPCTL_ALL_DBGRUN_KEEP_RUN             ((0x2UL) << CAPCTL_ALL_DBGRUN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIF           CEVT0
 *  @access     ECAP->CAPIF.bit.CEVT0
 *  @brief      Capture event 0 flag.
 *              This flag is only active in CAP mode.
 */
#define CAPIF_ALL_CEVT0_Pos (0)
#define CAPIF_ALL_CEVT0_Msk (0x1UL << CAPIF_ALL_CEVT0_Pos)

typedef enum
{
    CAPIF_BIT_CEVT0_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                       */
    CAPIF_BIT_CEVT0_OCCUR         = 1,  /*!< Indicates the first event occurred at ECAPx pin   */
} CAPIF_BIT_CEVT0;

#define CAPIF_ALL_CEVT0_NOT_OCCUR     ((0x0UL) << CAPIF_ALL_CEVT0_Pos)
#define CAPIF_ALL_CEVT0_OCCUR         ((0x1UL) << CAPIF_ALL_CEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIF           CEVT1
 *  @access     ECAP->CAPIF.bit.CEVT1
 *  @brief      Capture event 1 flag.
 *              This flag is only active in CAP mode.
 */
#define CAPIF_ALL_CEVT1_Pos (1)
#define CAPIF_ALL_CEVT1_Msk (0x1UL << CAPIF_ALL_CEVT1_Pos)

typedef enum
{
    CAPIF_BIT_CEVT1_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                        */
    CAPIF_BIT_CEVT1_OCCUR         = 1,  /*!< Indicates the second event occurred at ECAPx pin   */
} CAPIF_BIT_CEVT1;

#define CAPIF_ALL_CEVT1_NOT_OCCUR     ((0x0UL) << CAPIF_ALL_CEVT1_Pos)
#define CAPIF_ALL_CEVT1_OCCUR         ((0x1UL) << CAPIF_ALL_CEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIF           CEVT2
 *  @access     ECAP->CAPIF.bit.CEVT2
 *  @brief      Capture event 2 flag.
 *              This flag is active only in CAP mode.
 */
#define CAPIF_ALL_CEVT2_Pos (2)
#define CAPIF_ALL_CEVT2_Msk (0x1UL << CAPIF_ALL_CEVT2_Pos)

typedef enum
{
    CAPIF_BIT_CEVT2_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                       */
    CAPIF_BIT_CEVT2_OCCUR         = 1,  /*!< Indicates the third event occurred at ECAPx pin   */
} CAPIF_BIT_CEVT2;

#define CAPIF_ALL_CEVT2_NOT_OCCUR     ((0x0UL) << CAPIF_ALL_CEVT2_Pos)
#define CAPIF_ALL_CEVT2_OCCUR         ((0x1UL) << CAPIF_ALL_CEVT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIF           CEVT3
 *  @access     ECAP->CAPIF.bit.CEVT3
 *  @brief      Capture event 3 flag.
 *              This flag is only active in CAP mode.
 */
#define CAPIF_ALL_CEVT3_Pos (3)
#define CAPIF_ALL_CEVT3_Msk (0x1UL << CAPIF_ALL_CEVT3_Pos)

typedef enum
{
    CAPIF_BIT_CEVT3_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                        */
    CAPIF_BIT_CEVT3_OCCUR         = 1,  /*!< Indicates the fourth event occurred at ECAPx pin   */
} CAPIF_BIT_CEVT3;

#define CAPIF_ALL_CEVT3_NOT_OCCUR     ((0x0UL) << CAPIF_ALL_CEVT3_Pos)
#define CAPIF_ALL_CEVT3_OCCUR         ((0x1UL) << CAPIF_ALL_CEVT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIF           CNTOVF
 *  @access     ECAP->CAPIF.bit.CNTOVF
 *  @brief      Counter overflow status Flag.
 *              This flag is active in CAP and APWM mode.
 */
#define CAPIF_ALL_CNTOVF_Pos (4)
#define CAPIF_ALL_CNTOVF_Msk (0x1UL << CAPIF_ALL_CNTOVF_Pos)

typedef enum
{
    CAPIF_BIT_CNTOVF_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                                                       */
    CAPIF_BIT_CNTOVF_OCCUR         = 1,  /*!< Indicates the counter (TSCNT) has made the transition from FFFFFFFF to 00000000   */
} CAPIF_BIT_CNTOVF;

#define CAPIF_ALL_CNTOVF_NOT_OCCUR     ((0x0UL) << CAPIF_ALL_CNTOVF_Pos)
#define CAPIF_ALL_CNTOVF_OCCUR         ((0x1UL) << CAPIF_ALL_CNTOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIF           PRD
 *  @access     ECAP->CAPIF.bit.PRD
 *  @brief      Counter equal period flag.
 *              This flag is only active in APWM mode.
 */
#define CAPIF_ALL_PRD_Pos (5)
#define CAPIF_ALL_PRD_Msk (0x1UL << CAPIF_ALL_PRD_Pos)

typedef enum
{
    CAPIF_BIT_PRD_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                                                            */
    CAPIF_BIT_PRD_OCCUR         = 1,  /*!< Indicates the counter (TSCNT) reached the period register value (APRD) and was reset   */
} CAPIF_BIT_PRD;

#define CAPIF_ALL_PRD_NOT_OCCUR     ((0x0UL) << CAPIF_ALL_PRD_Pos)
#define CAPIF_ALL_PRD_OCCUR         ((0x1UL) << CAPIF_ALL_PRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIF           CMP
 *  @access     ECAP->CAPIF.bit.CMP
 *  @brief      Counter comparison equal flag.
 *              This flag is active only in APWM mode.
 */
#define CAPIF_ALL_CMP_Pos (6)
#define CAPIF_ALL_CMP_Msk (0x1UL << CAPIF_ALL_CMP_Pos)

typedef enum
{
    CAPIF_BIT_CMP_NOT_OCCUR     = 0,  /*!< Indicates no event occurred                                               */
    CAPIF_BIT_CMP_OCCUR         = 1,  /*!< Indicates the counter (TSCNT) reached the compare register value (ACMP)   */
} CAPIF_BIT_CMP;

#define CAPIF_ALL_CMP_NOT_OCCUR     ((0x0UL) << CAPIF_ALL_CMP_Pos)
#define CAPIF_ALL_CMP_OCCUR         ((0x1UL) << CAPIF_ALL_CMP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIF           INT
 *  @access     ECAP->CAPIF.bit.INT
 *  @brief      Global interrupt flag
 */
#define CAPIF_ALL_INT_Pos (7)
#define CAPIF_ALL_INT_Msk (0x1UL << CAPIF_ALL_INT_Pos)

typedef enum
{
    CAPIF_BIT_INT_NOT_OCCUR     = 0,  /*!< Indicates no interrupt generated            */
    CAPIF_BIT_INT_OCCUR         = 1,  /*!< Indicates that an interrupt was generated   */
} CAPIF_BIT_INT;

#define CAPIF_ALL_INT_NOT_OCCUR     ((0x0UL) << CAPIF_ALL_INT_Pos)
#define CAPIF_ALL_INT_OCCUR         ((0x1UL) << CAPIF_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIE           CEVT0
 *  @access     ECAP->CAPIE.bit.CEVT0
 *  @brief      Capture event 0 interrupt enable
 */
#define CAPIE_ALL_CEVT0_Pos (0)
#define CAPIE_ALL_CEVT0_Msk (0x1UL << CAPIE_ALL_CEVT0_Pos)

typedef enum
{
    CAPIE_BIT_CEVT0_DISABLE     = 0,  /*!< Disable Capture Event 0 as an Interrupt source   */
    CAPIE_BIT_CEVT0_ENABLE      = 1,  /*!< Enable Capture Event 0 as an Interrupt source    */
} CAPIE_BIT_CEVT0;

#define CAPIE_ALL_CEVT0_DISABLE     ((0x0UL) << CAPIE_ALL_CEVT0_Pos)
#define CAPIE_ALL_CEVT0_ENABLE      ((0x1UL) << CAPIE_ALL_CEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIE           CEVT1
 *  @access     ECAP->CAPIE.bit.CEVT1
 *  @brief      Capture event 1 interrupt enable
 */
#define CAPIE_ALL_CEVT1_Pos (1)
#define CAPIE_ALL_CEVT1_Msk (0x1UL << CAPIE_ALL_CEVT1_Pos)

typedef enum
{
    CAPIE_BIT_CEVT1_DISABLE     = 0,  /*!< Disable Capture Event 1 as an Interrupt source   */
    CAPIE_BIT_CEVT1_ENABLE      = 1,  /*!< Enable Capture Event 1 as an Interrupt source    */
} CAPIE_BIT_CEVT1;

#define CAPIE_ALL_CEVT1_DISABLE     ((0x0UL) << CAPIE_ALL_CEVT1_Pos)
#define CAPIE_ALL_CEVT1_ENABLE      ((0x1UL) << CAPIE_ALL_CEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIE           CEVT2
 *  @access     ECAP->CAPIE.bit.CEVT2
 *  @brief      Capture event 2 interrupt enable
 */
#define CAPIE_ALL_CEVT2_Pos (2)
#define CAPIE_ALL_CEVT2_Msk (0x1UL << CAPIE_ALL_CEVT2_Pos)

typedef enum
{
    CAPIE_BIT_CEVT2_DISABLE     = 0,  /*!< Disable Capture Event 2 as an Interrupt source   */
    CAPIE_BIT_CEVT2_ENABLE      = 1,  /*!< Enable Capture Event 2 as an Interrupt source    */
} CAPIE_BIT_CEVT2;

#define CAPIE_ALL_CEVT2_DISABLE     ((0x0UL) << CAPIE_ALL_CEVT2_Pos)
#define CAPIE_ALL_CEVT2_ENABLE      ((0x1UL) << CAPIE_ALL_CEVT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIE           CEVT3
 *  @access     ECAP->CAPIE.bit.CEVT3
 *  @brief      Capture event 3 interrupt enable
 */
#define CAPIE_ALL_CEVT3_Pos (3)
#define CAPIE_ALL_CEVT3_Msk (0x1UL << CAPIE_ALL_CEVT3_Pos)

typedef enum
{
    CAPIE_BIT_CEVT3_DISABLE     = 0,  /*!< Disable Capture Event 3 as an Interrupt source   */
    CAPIE_BIT_CEVT3_ENABLE      = 1,  /*!< Enable Capture Event 3 as an Interrupt source    */
} CAPIE_BIT_CEVT3;

#define CAPIE_ALL_CEVT3_DISABLE     ((0x0UL) << CAPIE_ALL_CEVT3_Pos)
#define CAPIE_ALL_CEVT3_ENABLE      ((0x1UL) << CAPIE_ALL_CEVT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIE           CNTOVF
 *  @access     ECAP->CAPIE.bit.CNTOVF
 *  @brief      Counter overflow interrupt enable
 */
#define CAPIE_ALL_CNTOVF_Pos (4)
#define CAPIE_ALL_CNTOVF_Msk (0x1UL << CAPIE_ALL_CNTOVF_Pos)

typedef enum
{
    CAPIE_BIT_CNTOVF_DISABLE     = 0,  /*!< Disabled counter Overflow as an Interrupt source   */
    CAPIE_BIT_CNTOVF_ENABLE      = 1,  /*!< Enable counter Overflow as an Interrupt source     */
} CAPIE_BIT_CNTOVF;

#define CAPIE_ALL_CNTOVF_DISABLE     ((0x0UL) << CAPIE_ALL_CNTOVF_Pos)
#define CAPIE_ALL_CNTOVF_ENABLE      ((0x1UL) << CAPIE_ALL_CNTOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIE           PRD
 *  @access     ECAP->CAPIE.bit.PRD
 *  @brief      Counter equal period interrupt enable
 */
#define CAPIE_ALL_PRD_Pos (5)
#define CAPIE_ALL_PRD_Msk (0x1UL << CAPIE_ALL_PRD_Pos)

typedef enum
{
    CAPIE_BIT_PRD_DISABLE     = 0,  /*!< Disable Period Equal as an Interrupt source   */
    CAPIE_BIT_PRD_ENABLE      = 1,  /*!< Enable Period Equal as an Interrupt source    */
} CAPIE_BIT_PRD;

#define CAPIE_ALL_PRD_DISABLE     ((0x0UL) << CAPIE_ALL_PRD_Pos)
#define CAPIE_ALL_PRD_ENABLE      ((0x1UL) << CAPIE_ALL_PRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIE           CMP
 *  @access     ECAP->CAPIE.bit.CMP
 *  @brief      Counter comparison equal interrupt enable
 */
#define CAPIE_ALL_CMP_Pos (6)
#define CAPIE_ALL_CMP_Msk (0x1UL << CAPIE_ALL_CMP_Pos)

typedef enum
{
    CAPIE_BIT_CMP_DISABLE     = 0,  /*!< Disable Compare Equal as an Interrupt source   */
    CAPIE_BIT_CMP_ENABLE      = 1,  /*!< Enable Compare Equal as an Interrupt source    */
} CAPIE_BIT_CMP;

#define CAPIE_ALL_CMP_DISABLE     ((0x0UL) << CAPIE_ALL_CMP_Pos)
#define CAPIE_ALL_CMP_ENABLE      ((0x1UL) << CAPIE_ALL_CMP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIC           CEVT0
 *  @access     ECAP->CAPIC.bit.CEVT0
 *  @brief      Capture event 0 flag clear
 */
#define CAPIC_ALL_CEVT0_Pos (0)
#define CAPIC_ALL_CEVT0_Msk (0x1UL << CAPIC_ALL_CEVT0_Pos)

typedef enum
{
    CAPIC_BIT_CEVT0_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.          
                                             Always reads back a 0.               */
    CAPIC_BIT_CEVT0_CLEAR         = 1,  /*!< Writing a 1 clears the CEVT0 flag.  
                                             This bit is self-cleared to 0.       */
} CAPIC_BIT_CEVT0;

#define CAPIC_ALL_CEVT0_NO_EFFECT     ((0x0UL) << CAPIC_ALL_CEVT0_Pos)
#define CAPIC_ALL_CEVT0_CLEAR         ((0x1UL) << CAPIC_ALL_CEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIC           CEVT1
 *  @access     ECAP->CAPIC.bit.CEVT1
 *  @brief      Capture event 1 flag clear
 */
#define CAPIC_ALL_CEVT1_Pos (1)
#define CAPIC_ALL_CEVT1_Msk (0x1UL << CAPIC_ALL_CEVT1_Pos)

typedef enum
{
    CAPIC_BIT_CEVT1_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.          
                                             Always reads back a 0.               */
    CAPIC_BIT_CEVT1_CLEAR         = 1,  /*!< Writing a 1 clears the CEVT1 flag.  
                                             This bit is self-cleared to 0        */
} CAPIC_BIT_CEVT1;

#define CAPIC_ALL_CEVT1_NO_EFFECT     ((0x0UL) << CAPIC_ALL_CEVT1_Pos)
#define CAPIC_ALL_CEVT1_CLEAR         ((0x1UL) << CAPIC_ALL_CEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIC           CEVT2
 *  @access     ECAP->CAPIC.bit.CEVT2
 *  @brief      Capture event 2 flag clear
 */
#define CAPIC_ALL_CEVT2_Pos (2)
#define CAPIC_ALL_CEVT2_Msk (0x1UL << CAPIC_ALL_CEVT2_Pos)

typedef enum
{
    CAPIC_BIT_CEVT2_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.          
                                             Always reads back a 0.               */
    CAPIC_BIT_CEVT2_CLEAR         = 1,  /*!< Writing a 1 clears the CEVT2 flag.  
                                             This bit is self-cleared to 0.       */
} CAPIC_BIT_CEVT2;

#define CAPIC_ALL_CEVT2_NO_EFFECT     ((0x0UL) << CAPIC_ALL_CEVT2_Pos)
#define CAPIC_ALL_CEVT2_CLEAR         ((0x1UL) << CAPIC_ALL_CEVT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIC           CEVT3
 *  @access     ECAP->CAPIC.bit.CEVT3
 *  @brief      Capture event 3 flag clear
 */
#define CAPIC_ALL_CEVT3_Pos (3)
#define CAPIC_ALL_CEVT3_Msk (0x1UL << CAPIC_ALL_CEVT3_Pos)

typedef enum
{
    CAPIC_BIT_CEVT3_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.          
                                             Always reads back a 0.               */
    CAPIC_BIT_CEVT3_CLEAR         = 1,  /*!< Writing a 1 clears the CEVT3 flag.  
                                             This bit is self-cleared to 0.       */
} CAPIC_BIT_CEVT3;

#define CAPIC_ALL_CEVT3_NO_EFFECT     ((0x0UL) << CAPIC_ALL_CEVT3_Pos)
#define CAPIC_ALL_CEVT3_CLEAR         ((0x1UL) << CAPIC_ALL_CEVT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIC           CNTOVF
 *  @access     ECAP->CAPIC.bit.CNTOVF
 *  @brief      Counter overflow flag clear
 */
#define CAPIC_ALL_CNTOVF_Pos (4)
#define CAPIC_ALL_CNTOVF_Msk (0x1UL << CAPIC_ALL_CNTOVF_Pos)

typedef enum
{
    CAPIC_BIT_CNTOVF_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.           
                                              Always reads back a 0                 */
    CAPIC_BIT_CNTOVF_CLEAR         = 1,  /*!< Writing a 1 clears the CNTOVF flag.  
                                              This bit is self-cleared to 0.        */
} CAPIC_BIT_CNTOVF;

#define CAPIC_ALL_CNTOVF_NO_EFFECT     ((0x0UL) << CAPIC_ALL_CNTOVF_Pos)
#define CAPIC_ALL_CNTOVF_CLEAR         ((0x1UL) << CAPIC_ALL_CNTOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIC           PRD
 *  @access     ECAP->CAPIC.bit.PRD
 *  @brief      Counter equal to period flag clear
 */
#define CAPIC_ALL_PRD_Pos (5)
#define CAPIC_ALL_PRD_Msk (0x1UL << CAPIC_ALL_PRD_Pos)

typedef enum
{
    CAPIC_BIT_PRD_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.            
                                           Always reads back a 0                  */
    CAPIC_BIT_PRD_CLEAR         = 1,  /*!< Writing a 1 clears the CNT=PRD flag.  
                                           This bit is self-cleared to 0.         */
} CAPIC_BIT_PRD;

#define CAPIC_ALL_PRD_NO_EFFECT     ((0x0UL) << CAPIC_ALL_PRD_Pos)
#define CAPIC_ALL_PRD_CLEAR         ((0x1UL) << CAPIC_ALL_PRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIC           CMP
 *  @access     ECAP->CAPIC.bit.CMP
 *  @brief      Counter comparison equal flag clear
 */
#define CAPIC_ALL_CMP_Pos (6)
#define CAPIC_ALL_CMP_Msk (0x1UL << CAPIC_ALL_CMP_Pos)

typedef enum
{
    CAPIC_BIT_CMP_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.            
                                           Always reads back a 0                  */
    CAPIC_BIT_CMP_CLEAR         = 1,  /*!< Writing a 1 clears the CNT=CMP flag.  
                                           This bit is self-cleared to 0.         */
} CAPIC_BIT_CMP;

#define CAPIC_ALL_CMP_NO_EFFECT     ((0x0UL) << CAPIC_ALL_CMP_Pos)
#define CAPIC_ALL_CMP_CLEAR         ((0x1UL) << CAPIC_ALL_CMP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIC           INT
 *  @access     ECAP->CAPIC.bit.INT
 *  @brief      Global interrupt clear
 */
#define CAPIC_ALL_INT_Pos (7)
#define CAPIC_ALL_INT_Msk (0x1UL << CAPIC_ALL_INT_Pos)

typedef enum
{
    CAPIC_BIT_INT_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.                                                        
                                           Always reads back a 0.                                                             */
    CAPIC_BIT_INT_CLEAR         = 1,  /*!< Writing a 1 clears the INT flag and enable further interrupts to be generated if  
                                           any of the event flags are set to 1.                                              
                                           This bit is self-cleared to 0.                                                     */
} CAPIC_BIT_INT;

#define CAPIC_ALL_INT_NO_EFFECT     ((0x0UL) << CAPIC_ALL_INT_Pos)
#define CAPIC_ALL_INT_CLEAR         ((0x1UL) << CAPIC_ALL_INT_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIFRC         CEVT0
 *  @access     ECAP->CAPIFRC.bit.CEVT0
 *  @brief      Capture event 0 flag force
 */
#define CAPIFRC_ALL_CEVT0_Pos (0)
#define CAPIFRC_ALL_CEVT0_Msk (0x1UL << CAPIFRC_ALL_CEVT0_Pos)

typedef enum
{
    CAPIFRC_BIT_CEVT0_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.          
                                               Always reads back a 0.               */
    CAPIFRC_BIT_CEVT0_FORCE         = 1,  /*!< Writing a 1 forces the CEVT0 flag.  
                                               This bit is self-cleared to 0.       */
} CAPIFRC_BIT_CEVT0;

#define CAPIFRC_ALL_CEVT0_NO_EFFECT     ((0x0UL) << CAPIFRC_ALL_CEVT0_Pos)
#define CAPIFRC_ALL_CEVT0_FORCE         ((0x1UL) << CAPIFRC_ALL_CEVT0_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIFRC         CEVT1
 *  @access     ECAP->CAPIFRC.bit.CEVT1
 *  @brief      Capture event 1 flag force
 */
#define CAPIFRC_ALL_CEVT1_Pos (1)
#define CAPIFRC_ALL_CEVT1_Msk (0x1UL << CAPIFRC_ALL_CEVT1_Pos)

typedef enum
{
    CAPIFRC_BIT_CEVT1_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.          
                                               Always reads back a 0.               */
    CAPIFRC_BIT_CEVT1_FORCE         = 1,  /*!< Writing a 1 forces the CEVT1 flag.  
                                               This bit is self-cleared to 0        */
} CAPIFRC_BIT_CEVT1;

#define CAPIFRC_ALL_CEVT1_NO_EFFECT     ((0x0UL) << CAPIFRC_ALL_CEVT1_Pos)
#define CAPIFRC_ALL_CEVT1_FORCE         ((0x1UL) << CAPIFRC_ALL_CEVT1_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIFRC         CEVT2
 *  @access     ECAP->CAPIFRC.bit.CEVT2
 *  @brief      Capture event 2 flag force
 */
#define CAPIFRC_ALL_CEVT2_Pos (2)
#define CAPIFRC_ALL_CEVT2_Msk (0x1UL << CAPIFRC_ALL_CEVT2_Pos)

typedef enum
{
    CAPIFRC_BIT_CEVT2_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.          
                                               Always reads back a 0.               */
    CAPIFRC_BIT_CEVT2_FORCE         = 1,  /*!< Writing a 1 forces the CEVT2 flag.  
                                               This bit is self-cleared to 0.       */
} CAPIFRC_BIT_CEVT2;

#define CAPIFRC_ALL_CEVT2_NO_EFFECT     ((0x0UL) << CAPIFRC_ALL_CEVT2_Pos)
#define CAPIFRC_ALL_CEVT2_FORCE         ((0x1UL) << CAPIFRC_ALL_CEVT2_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIFRC         CEVT3
 *  @access     ECAP->CAPIFRC.bit.CEVT3
 *  @brief      Capture event 3 flag force
 */
#define CAPIFRC_ALL_CEVT3_Pos (3)
#define CAPIFRC_ALL_CEVT3_Msk (0x1UL << CAPIFRC_ALL_CEVT3_Pos)

typedef enum
{
    CAPIFRC_BIT_CEVT3_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.          
                                               Always reads back a 0.               */
    CAPIFRC_BIT_CEVT3_FORCE         = 1,  /*!< Writing a 1 forces the CEVT3 flag.  
                                               This bit is self-cleared to 0.       */
} CAPIFRC_BIT_CEVT3;

#define CAPIFRC_ALL_CEVT3_NO_EFFECT     ((0x0UL) << CAPIFRC_ALL_CEVT3_Pos)
#define CAPIFRC_ALL_CEVT3_FORCE         ((0x1UL) << CAPIFRC_ALL_CEVT3_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIFRC         CNTOVF
 *  @access     ECAP->CAPIFRC.bit.CNTOVF
 *  @brief      Counter overflow flag force
 */
#define CAPIFRC_ALL_CNTOVF_Pos (4)
#define CAPIFRC_ALL_CNTOVF_Msk (0x1UL << CAPIFRC_ALL_CNTOVF_Pos)

typedef enum
{
    CAPIFRC_BIT_CNTOVF_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.           
                                                Always reads back a 0                 */
    CAPIFRC_BIT_CNTOVF_FORCE         = 1,  /*!< Writing a 1 forces the CNTOVF flag.  
                                                This bit is self-cleared to 0.        */
} CAPIFRC_BIT_CNTOVF;

#define CAPIFRC_ALL_CNTOVF_NO_EFFECT     ((0x0UL) << CAPIFRC_ALL_CNTOVF_Pos)
#define CAPIFRC_ALL_CNTOVF_FORCE         ((0x1UL) << CAPIFRC_ALL_CNTOVF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIFRC         PRD
 *  @access     ECAP->CAPIFRC.bit.PRD
 *  @brief      Counter equal to period flag force
 */
#define CAPIFRC_ALL_PRD_Pos (5)
#define CAPIFRC_ALL_PRD_Msk (0x1UL << CAPIFRC_ALL_PRD_Pos)

typedef enum
{
    CAPIFRC_BIT_PRD_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.            
                                             Always reads back a 0.                 */
    CAPIFRC_BIT_PRD_FORCE         = 1,  /*!< Writing a 1 forces the CNT=PRD flag.  
                                             This bit is self-cleared to 0.         */
} CAPIFRC_BIT_PRD;

#define CAPIFRC_ALL_PRD_NO_EFFECT     ((0x0UL) << CAPIFRC_ALL_PRD_Pos)
#define CAPIFRC_ALL_PRD_FORCE         ((0x1UL) << CAPIFRC_ALL_PRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPIFRC         CMP
 *  @access     ECAP->CAPIFRC.bit.CMP
 *  @brief      Counter comparison equal flag force
 */
#define CAPIFRC_ALL_CMP_Pos (6)
#define CAPIFRC_ALL_CMP_Msk (0x1UL << CAPIFRC_ALL_CMP_Pos)

typedef enum
{
    CAPIFRC_BIT_CMP_NO_EFFECT     = 0,  /*!< Writing a 0 has no effect.            
                                             Always reads back a 0.                 */
    CAPIFRC_BIT_CMP_FORCE         = 1,  /*!< Writing a 1 forces the CNT=CMP flag.  
                                             This bit is self-cleared to 0.         */
} CAPIFRC_BIT_CMP;

#define CAPIFRC_ALL_CMP_NO_EFFECT     ((0x0UL) << CAPIFRC_ALL_CMP_Pos)
#define CAPIFRC_ALL_CMP_FORCE         ((0x1UL) << CAPIFRC_ALL_CMP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   ECAP            CAPREGKEY       KEY
 *  @access     ECAP->CAPREGKEY.bit.KEY
 *  @brief      Write 0x1ACCE551 to unlock protected capture registers
 */
#define CAPREGKEY_ALL_KEY_Pos (0)
#define CAPREGKEY_ALL_KEY_Msk (0xFFFFFFFFUL << CAPREGKEY_ALL_KEY_Pos)

#define CAPREGKEY_BIT_KEY

#define CAPREGKEY_ALL_KEY_(x) ((x) << CAPREGKEY_ALL_KEY_Pos)



/********************************************************************************
*
* Module Name     SIO
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM0           VAL
 *  @access     SIO->SIOM0.bit.VAL
 *  @brief      
 */
#define SIOM0_ALL_VAL_Pos (0)
#define SIOM0_ALL_VAL_Msk (0xFFFFUL << SIOM0_ALL_VAL_Pos)

#define SIOM0_BIT_VAL

#define SIOM0_ALL_VAL_(x) ((x) << SIOM0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM1           VAL
 *  @access     SIO->SIOM1.bit.VAL
 *  @brief      
 */
#define SIOM1_ALL_VAL_Pos (0)
#define SIOM1_ALL_VAL_Msk (0xFFFFUL << SIOM1_ALL_VAL_Pos)

#define SIOM1_BIT_VAL

#define SIOM1_ALL_VAL_(x) ((x) << SIOM1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM2           VAL
 *  @access     SIO->SIOM2.bit.VAL
 *  @brief      
 */
#define SIOM2_ALL_VAL_Pos (0)
#define SIOM2_ALL_VAL_Msk (0xFFFFUL << SIOM2_ALL_VAL_Pos)

#define SIOM2_BIT_VAL

#define SIOM2_ALL_VAL_(x) ((x) << SIOM2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM3           VAL
 *  @access     SIO->SIOM3.bit.VAL
 *  @brief      
 */
#define SIOM3_ALL_VAL_Pos (0)
#define SIOM3_ALL_VAL_Msk (0xFFFFUL << SIOM3_ALL_VAL_Pos)

#define SIOM3_BIT_VAL

#define SIOM3_ALL_VAL_(x) ((x) << SIOM3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM4           VAL
 *  @access     SIO->SIOM4.bit.VAL
 *  @brief      
 */
#define SIOM4_ALL_VAL_Pos (0)
#define SIOM4_ALL_VAL_Msk (0xFFFFUL << SIOM4_ALL_VAL_Pos)

#define SIOM4_BIT_VAL

#define SIOM4_ALL_VAL_(x) ((x) << SIOM4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM5           VAL
 *  @access     SIO->SIOM5.bit.VAL
 *  @brief      
 */
#define SIOM5_ALL_VAL_Pos (0)
#define SIOM5_ALL_VAL_Msk (0xFFFFUL << SIOM5_ALL_VAL_Pos)

#define SIOM5_BIT_VAL

#define SIOM5_ALL_VAL_(x) ((x) << SIOM5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM6           VAL
 *  @access     SIO->SIOM6.bit.VAL
 *  @brief      
 */
#define SIOM6_ALL_VAL_Pos (0)
#define SIOM6_ALL_VAL_Msk (0xFFFFUL << SIOM6_ALL_VAL_Pos)

#define SIOM6_BIT_VAL

#define SIOM6_ALL_VAL_(x) ((x) << SIOM6_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM7           VAL
 *  @access     SIO->SIOM7.bit.VAL
 *  @brief      
 */
#define SIOM7_ALL_VAL_Pos (0)
#define SIOM7_ALL_VAL_Msk (0xFFFFUL << SIOM7_ALL_VAL_Pos)

#define SIOM7_BIT_VAL

#define SIOM7_ALL_VAL_(x) ((x) << SIOM7_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM8           VAL
 *  @access     SIO->SIOM8.bit.VAL
 *  @brief      
 */
#define SIOM8_ALL_VAL_Pos (0)
#define SIOM8_ALL_VAL_Msk (0xFFFFUL << SIOM8_ALL_VAL_Pos)

#define SIOM8_BIT_VAL

#define SIOM8_ALL_VAL_(x) ((x) << SIOM8_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM9           VAL
 *  @access     SIO->SIOM9.bit.VAL
 *  @brief      
 */
#define SIOM9_ALL_VAL_Pos (0)
#define SIOM9_ALL_VAL_Msk (0xFFFFUL << SIOM9_ALL_VAL_Pos)

#define SIOM9_BIT_VAL

#define SIOM9_ALL_VAL_(x) ((x) << SIOM9_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM10          VAL
 *  @access     SIO->SIOM10.bit.VAL
 *  @brief      
 */
#define SIOM10_ALL_VAL_Pos (0)
#define SIOM10_ALL_VAL_Msk (0xFFFFUL << SIOM10_ALL_VAL_Pos)

#define SIOM10_BIT_VAL

#define SIOM10_ALL_VAL_(x) ((x) << SIOM10_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM11          VAL
 *  @access     SIO->SIOM11.bit.VAL
 *  @brief      
 */
#define SIOM11_ALL_VAL_Pos (0)
#define SIOM11_ALL_VAL_Msk (0xFFFFUL << SIOM11_ALL_VAL_Pos)

#define SIOM11_BIT_VAL

#define SIOM11_ALL_VAL_(x) ((x) << SIOM11_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM12          VAL
 *  @access     SIO->SIOM12.bit.VAL
 *  @brief      
 */
#define SIOM12_ALL_VAL_Pos (0)
#define SIOM12_ALL_VAL_Msk (0xFFFFUL << SIOM12_ALL_VAL_Pos)

#define SIOM12_BIT_VAL

#define SIOM12_ALL_VAL_(x) ((x) << SIOM12_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM13          VAL
 *  @access     SIO->SIOM13.bit.VAL
 *  @brief      
 */
#define SIOM13_ALL_VAL_Pos (0)
#define SIOM13_ALL_VAL_Msk (0xFFFFUL << SIOM13_ALL_VAL_Pos)

#define SIOM13_BIT_VAL

#define SIOM13_ALL_VAL_(x) ((x) << SIOM13_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM14          VAL
 *  @access     SIO->SIOM14.bit.VAL
 *  @brief      
 */
#define SIOM14_ALL_VAL_Pos (0)
#define SIOM14_ALL_VAL_Msk (0xFFFFUL << SIOM14_ALL_VAL_Pos)

#define SIOM14_BIT_VAL

#define SIOM14_ALL_VAL_(x) ((x) << SIOM14_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM15          VAL
 *  @access     SIO->SIOM15.bit.VAL
 *  @brief      
 */
#define SIOM15_ALL_VAL_Pos (0)
#define SIOM15_ALL_VAL_Msk (0xFFFFUL << SIOM15_ALL_VAL_Pos)

#define SIOM15_BIT_VAL

#define SIOM15_ALL_VAL_(x) ((x) << SIOM15_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM16          VAL
 *  @access     SIO->SIOM16.bit.VAL
 *  @brief      
 */
#define SIOM16_ALL_VAL_Pos (0)
#define SIOM16_ALL_VAL_Msk (0xFFFFUL << SIOM16_ALL_VAL_Pos)

#define SIOM16_BIT_VAL

#define SIOM16_ALL_VAL_(x) ((x) << SIOM16_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM17          VAL
 *  @access     SIO->SIOM17.bit.VAL
 *  @brief      
 */
#define SIOM17_ALL_VAL_Pos (0)
#define SIOM17_ALL_VAL_Msk (0xFFFFUL << SIOM17_ALL_VAL_Pos)

#define SIOM17_BIT_VAL

#define SIOM17_ALL_VAL_(x) ((x) << SIOM17_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM18          VAL
 *  @access     SIO->SIOM18.bit.VAL
 *  @brief      
 */
#define SIOM18_ALL_VAL_Pos (0)
#define SIOM18_ALL_VAL_Msk (0xFFFFUL << SIOM18_ALL_VAL_Pos)

#define SIOM18_BIT_VAL

#define SIOM18_ALL_VAL_(x) ((x) << SIOM18_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM19          VAL
 *  @access     SIO->SIOM19.bit.VAL
 *  @brief      
 */
#define SIOM19_ALL_VAL_Pos (0)
#define SIOM19_ALL_VAL_Msk (0xFFFFUL << SIOM19_ALL_VAL_Pos)

#define SIOM19_BIT_VAL

#define SIOM19_ALL_VAL_(x) ((x) << SIOM19_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM20          VAL
 *  @access     SIO->SIOM20.bit.VAL
 *  @brief      
 */
#define SIOM20_ALL_VAL_Pos (0)
#define SIOM20_ALL_VAL_Msk (0xFFFFUL << SIOM20_ALL_VAL_Pos)

#define SIOM20_BIT_VAL

#define SIOM20_ALL_VAL_(x) ((x) << SIOM20_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM21          VAL
 *  @access     SIO->SIOM21.bit.VAL
 *  @brief      
 */
#define SIOM21_ALL_VAL_Pos (0)
#define SIOM21_ALL_VAL_Msk (0xFFFFUL << SIOM21_ALL_VAL_Pos)

#define SIOM21_BIT_VAL

#define SIOM21_ALL_VAL_(x) ((x) << SIOM21_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM22          VAL
 *  @access     SIO->SIOM22.bit.VAL
 *  @brief      
 */
#define SIOM22_ALL_VAL_Pos (0)
#define SIOM22_ALL_VAL_Msk (0xFFFFUL << SIOM22_ALL_VAL_Pos)

#define SIOM22_BIT_VAL

#define SIOM22_ALL_VAL_(x) ((x) << SIOM22_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM23          VAL
 *  @access     SIO->SIOM23.bit.VAL
 *  @brief      
 */
#define SIOM23_ALL_VAL_Pos (0)
#define SIOM23_ALL_VAL_Msk (0xFFFFUL << SIOM23_ALL_VAL_Pos)

#define SIOM23_BIT_VAL

#define SIOM23_ALL_VAL_(x) ((x) << SIOM23_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM24          VAL
 *  @access     SIO->SIOM24.bit.VAL
 *  @brief      
 */
#define SIOM24_ALL_VAL_Pos (0)
#define SIOM24_ALL_VAL_Msk (0xFFFFUL << SIOM24_ALL_VAL_Pos)

#define SIOM24_BIT_VAL

#define SIOM24_ALL_VAL_(x) ((x) << SIOM24_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM25          VAL
 *  @access     SIO->SIOM25.bit.VAL
 *  @brief      
 */
#define SIOM25_ALL_VAL_Pos (0)
#define SIOM25_ALL_VAL_Msk (0xFFFFUL << SIOM25_ALL_VAL_Pos)

#define SIOM25_BIT_VAL

#define SIOM25_ALL_VAL_(x) ((x) << SIOM25_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM26          VAL
 *  @access     SIO->SIOM26.bit.VAL
 *  @brief      
 */
#define SIOM26_ALL_VAL_Pos (0)
#define SIOM26_ALL_VAL_Msk (0xFFFFUL << SIOM26_ALL_VAL_Pos)

#define SIOM26_BIT_VAL

#define SIOM26_ALL_VAL_(x) ((x) << SIOM26_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM27          VAL
 *  @access     SIO->SIOM27.bit.VAL
 *  @brief      
 */
#define SIOM27_ALL_VAL_Pos (0)
#define SIOM27_ALL_VAL_Msk (0xFFFFUL << SIOM27_ALL_VAL_Pos)

#define SIOM27_BIT_VAL

#define SIOM27_ALL_VAL_(x) ((x) << SIOM27_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM28          VAL
 *  @access     SIO->SIOM28.bit.VAL
 *  @brief      
 */
#define SIOM28_ALL_VAL_Pos (0)
#define SIOM28_ALL_VAL_Msk (0xFFFFUL << SIOM28_ALL_VAL_Pos)

#define SIOM28_BIT_VAL

#define SIOM28_ALL_VAL_(x) ((x) << SIOM28_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM29          VAL
 *  @access     SIO->SIOM29.bit.VAL
 *  @brief      
 */
#define SIOM29_ALL_VAL_Pos (0)
#define SIOM29_ALL_VAL_Msk (0xFFFFUL << SIOM29_ALL_VAL_Pos)

#define SIOM29_BIT_VAL

#define SIOM29_ALL_VAL_(x) ((x) << SIOM29_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM30          VAL
 *  @access     SIO->SIOM30.bit.VAL
 *  @brief      
 */
#define SIOM30_ALL_VAL_Pos (0)
#define SIOM30_ALL_VAL_Msk (0xFFFFUL << SIOM30_ALL_VAL_Pos)

#define SIOM30_BIT_VAL

#define SIOM30_ALL_VAL_(x) ((x) << SIOM30_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOM31          VAL
 *  @access     SIO->SIOM31.bit.VAL
 *  @brief      
 */
#define SIOM31_ALL_VAL_Pos (0)
#define SIOM31_ALL_VAL_Msk (0xFFFFUL << SIOM31_ALL_VAL_Pos)

#define SIOM31_BIT_VAL

#define SIOM31_ALL_VAL_(x) ((x) << SIOM31_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSADDR        VAL
 *  @access     SIO->SIOSADDR.bit.VAL
 *  @brief      
 */
#define SIOSADDR_ALL_VAL_Pos (0)
#define SIOSADDR_ALL_VAL_Msk (0x3FFUL << SIOSADDR_ALL_VAL_Pos)

#define SIOSADDR_BIT_VAL

#define SIOSADDR_ALL_VAL_(x) ((x) << SIOSADDR_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSDATA        VAL
 *  @access     SIO->SIOSDATA.bit.VAL
 *  @brief      Always readback 0.
 */
#define SIOSDATA_ALL_VAL_Pos (0)
#define SIOSDATA_ALL_VAL_Msk (0xFFFFFFFFUL << SIOSDATA_ALL_VAL_Pos)

#define SIOSDATA_BIT_VAL

#define SIOSDATA_ALL_VAL_(x) ((x) << SIOSDATA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOPLDPARA      VAL
 *  @access     SIO->SIOPLDPARA.bit.VAL
 *  @brief      
 */
#define SIOPLDPARA_ALL_VAL_Pos (0)
#define SIOPLDPARA_ALL_VAL_Msk (0xFFFFUL << SIOPLDPARA_ALL_VAL_Pos)

#define SIOPLDPARA_BIT_VAL

#define SIOPLDPARA_ALL_VAL_(x) ((x) << SIOPLDPARA_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSD0          VAL
 *  @access     SIO->SIOSD0.bit.VAL
 *  @brief      
 */
#define SIOSD0_ALL_VAL_Pos (0)
#define SIOSD0_ALL_VAL_Msk (0xFFFFFFFFUL << SIOSD0_ALL_VAL_Pos)

#define SIOSD0_BIT_VAL

#define SIOSD0_ALL_VAL_(x) ((x) << SIOSD0_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSD1          VAL
 *  @access     SIO->SIOSD1.bit.VAL
 *  @brief      
 */
#define SIOSD1_ALL_VAL_Pos (0)
#define SIOSD1_ALL_VAL_Msk (0xFFFFFFFFUL << SIOSD1_ALL_VAL_Pos)

#define SIOSD1_BIT_VAL

#define SIOSD1_ALL_VAL_(x) ((x) << SIOSD1_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSD2          VAL
 *  @access     SIO->SIOSD2.bit.VAL
 *  @brief      
 */
#define SIOSD2_ALL_VAL_Pos (0)
#define SIOSD2_ALL_VAL_Msk (0xFFFFFFFFUL << SIOSD2_ALL_VAL_Pos)

#define SIOSD2_BIT_VAL

#define SIOSD2_ALL_VAL_(x) ((x) << SIOSD2_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSD3          VAL
 *  @access     SIO->SIOSD3.bit.VAL
 *  @brief      
 */
#define SIOSD3_ALL_VAL_Pos (0)
#define SIOSD3_ALL_VAL_Msk (0xFFFFFFFFUL << SIOSD3_ALL_VAL_Pos)

#define SIOSD3_BIT_VAL

#define SIOSD3_ALL_VAL_(x) ((x) << SIOSD3_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSD4          VAL
 *  @access     SIO->SIOSD4.bit.VAL
 *  @brief      
 */
#define SIOSD4_ALL_VAL_Pos (0)
#define SIOSD4_ALL_VAL_Msk (0xFFFFFFFFUL << SIOSD4_ALL_VAL_Pos)

#define SIOSD4_BIT_VAL

#define SIOSD4_ALL_VAL_(x) ((x) << SIOSD4_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSD5          VAL
 *  @access     SIO->SIOSD5.bit.VAL
 *  @brief      
 */
#define SIOSD5_ALL_VAL_Pos (0)
#define SIOSD5_ALL_VAL_Msk (0xFFFFFFFFUL << SIOSD5_ALL_VAL_Pos)

#define SIOSD5_BIT_VAL

#define SIOSD5_ALL_VAL_(x) ((x) << SIOSD5_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSD6          VAL
 *  @access     SIO->SIOSD6.bit.VAL
 *  @brief      
 */
#define SIOSD6_ALL_VAL_Pos (0)
#define SIOSD6_ALL_VAL_Msk (0xFFFFFFFFUL << SIOSD6_ALL_VAL_Pos)

#define SIOSD6_BIT_VAL

#define SIOSD6_ALL_VAL_(x) ((x) << SIOSD6_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             SIOSD7          VAL
 *  @access     SIO->SIOSD7.bit.VAL
 *  @brief      
 */
#define SIOSD7_ALL_VAL_Pos (0)
#define SIOSD7_ALL_VAL_Msk (0xFFFFFFUL << SIOSD7_ALL_VAL_Pos)

#define SIOSD7_BIT_VAL

#define SIOSD7_ALL_VAL_(x) ((x) << SIOSD7_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM000          VAL
 *  @access     SIO->BSM000.bit.VAL
 *  @brief      
 */
#define BSM000_ALL_VAL_Pos (0)
#define BSM000_ALL_VAL_Msk (0xFFFFFFUL << BSM000_ALL_VAL_Pos)

#define BSM000_BIT_VAL

#define BSM000_ALL_VAL_(x) ((x) << BSM000_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM001          VAL
 *  @access     SIO->BSM001.bit.VAL
 *  @brief      
 */
#define BSM001_ALL_VAL_Pos (0)
#define BSM001_ALL_VAL_Msk (0xFFFFFFUL << BSM001_ALL_VAL_Pos)

#define BSM001_BIT_VAL

#define BSM001_ALL_VAL_(x) ((x) << BSM001_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM002          VAL
 *  @access     SIO->BSM002.bit.VAL
 *  @brief      
 */
#define BSM002_ALL_VAL_Pos (0)
#define BSM002_ALL_VAL_Msk (0xFFFFFFUL << BSM002_ALL_VAL_Pos)

#define BSM002_BIT_VAL

#define BSM002_ALL_VAL_(x) ((x) << BSM002_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM003          VAL
 *  @access     SIO->BSM003.bit.VAL
 *  @brief      
 */
#define BSM003_ALL_VAL_Pos (0)
#define BSM003_ALL_VAL_Msk (0xFFFFFFUL << BSM003_ALL_VAL_Pos)

#define BSM003_BIT_VAL

#define BSM003_ALL_VAL_(x) ((x) << BSM003_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM004          VAL
 *  @access     SIO->BSM004.bit.VAL
 *  @brief      
 */
#define BSM004_ALL_VAL_Pos (0)
#define BSM004_ALL_VAL_Msk (0xFFFFFFUL << BSM004_ALL_VAL_Pos)

#define BSM004_BIT_VAL

#define BSM004_ALL_VAL_(x) ((x) << BSM004_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM005          VAL
 *  @access     SIO->BSM005.bit.VAL
 *  @brief      
 */
#define BSM005_ALL_VAL_Pos (0)
#define BSM005_ALL_VAL_Msk (0xFFFFFFUL << BSM005_ALL_VAL_Pos)

#define BSM005_BIT_VAL

#define BSM005_ALL_VAL_(x) ((x) << BSM005_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM006          VAL
 *  @access     SIO->BSM006.bit.VAL
 *  @brief      
 */
#define BSM006_ALL_VAL_Pos (0)
#define BSM006_ALL_VAL_Msk (0xFFFFFFUL << BSM006_ALL_VAL_Pos)

#define BSM006_BIT_VAL

#define BSM006_ALL_VAL_(x) ((x) << BSM006_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM007          VAL
 *  @access     SIO->BSM007.bit.VAL
 *  @brief      
 */
#define BSM007_ALL_VAL_Pos (0)
#define BSM007_ALL_VAL_Msk (0xFFFFFFUL << BSM007_ALL_VAL_Pos)

#define BSM007_BIT_VAL

#define BSM007_ALL_VAL_(x) ((x) << BSM007_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM008          VAL
 *  @access     SIO->BSM008.bit.VAL
 *  @brief      
 */
#define BSM008_ALL_VAL_Pos (0)
#define BSM008_ALL_VAL_Msk (0xFFFFFFUL << BSM008_ALL_VAL_Pos)

#define BSM008_BIT_VAL

#define BSM008_ALL_VAL_(x) ((x) << BSM008_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM009          VAL
 *  @access     SIO->BSM009.bit.VAL
 *  @brief      
 */
#define BSM009_ALL_VAL_Pos (0)
#define BSM009_ALL_VAL_Msk (0xFFFFFFUL << BSM009_ALL_VAL_Pos)

#define BSM009_BIT_VAL

#define BSM009_ALL_VAL_(x) ((x) << BSM009_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM010          VAL
 *  @access     SIO->BSM010.bit.VAL
 *  @brief      
 */
#define BSM010_ALL_VAL_Pos (0)
#define BSM010_ALL_VAL_Msk (0xFFFFFFUL << BSM010_ALL_VAL_Pos)

#define BSM010_BIT_VAL

#define BSM010_ALL_VAL_(x) ((x) << BSM010_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM011          VAL
 *  @access     SIO->BSM011.bit.VAL
 *  @brief      
 */
#define BSM011_ALL_VAL_Pos (0)
#define BSM011_ALL_VAL_Msk (0xFFFFFFUL << BSM011_ALL_VAL_Pos)

#define BSM011_BIT_VAL

#define BSM011_ALL_VAL_(x) ((x) << BSM011_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM012          VAL
 *  @access     SIO->BSM012.bit.VAL
 *  @brief      
 */
#define BSM012_ALL_VAL_Pos (0)
#define BSM012_ALL_VAL_Msk (0xFFFFFFUL << BSM012_ALL_VAL_Pos)

#define BSM012_BIT_VAL

#define BSM012_ALL_VAL_(x) ((x) << BSM012_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM013          VAL
 *  @access     SIO->BSM013.bit.VAL
 *  @brief      
 */
#define BSM013_ALL_VAL_Pos (0)
#define BSM013_ALL_VAL_Msk (0xFFFFFFUL << BSM013_ALL_VAL_Pos)

#define BSM013_BIT_VAL

#define BSM013_ALL_VAL_(x) ((x) << BSM013_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM014          VAL
 *  @access     SIO->BSM014.bit.VAL
 *  @brief      
 */
#define BSM014_ALL_VAL_Pos (0)
#define BSM014_ALL_VAL_Msk (0xFFFFFFUL << BSM014_ALL_VAL_Pos)

#define BSM014_BIT_VAL

#define BSM014_ALL_VAL_(x) ((x) << BSM014_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM015          VAL
 *  @access     SIO->BSM015.bit.VAL
 *  @brief      
 */
#define BSM015_ALL_VAL_Pos (0)
#define BSM015_ALL_VAL_Msk (0xFFFFFFUL << BSM015_ALL_VAL_Pos)

#define BSM015_BIT_VAL

#define BSM015_ALL_VAL_(x) ((x) << BSM015_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM016          VAL
 *  @access     SIO->BSM016.bit.VAL
 *  @brief      
 */
#define BSM016_ALL_VAL_Pos (0)
#define BSM016_ALL_VAL_Msk (0xFFFFFFUL << BSM016_ALL_VAL_Pos)

#define BSM016_BIT_VAL

#define BSM016_ALL_VAL_(x) ((x) << BSM016_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM017          VAL
 *  @access     SIO->BSM017.bit.VAL
 *  @brief      
 */
#define BSM017_ALL_VAL_Pos (0)
#define BSM017_ALL_VAL_Msk (0xFFFFFFUL << BSM017_ALL_VAL_Pos)

#define BSM017_BIT_VAL

#define BSM017_ALL_VAL_(x) ((x) << BSM017_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM018          VAL
 *  @access     SIO->BSM018.bit.VAL
 *  @brief      
 */
#define BSM018_ALL_VAL_Pos (0)
#define BSM018_ALL_VAL_Msk (0xFFFFFFUL << BSM018_ALL_VAL_Pos)

#define BSM018_BIT_VAL

#define BSM018_ALL_VAL_(x) ((x) << BSM018_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM019          VAL
 *  @access     SIO->BSM019.bit.VAL
 *  @brief      
 */
#define BSM019_ALL_VAL_Pos (0)
#define BSM019_ALL_VAL_Msk (0xFFFFFFUL << BSM019_ALL_VAL_Pos)

#define BSM019_BIT_VAL

#define BSM019_ALL_VAL_(x) ((x) << BSM019_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM020          VAL
 *  @access     SIO->BSM020.bit.VAL
 *  @brief      
 */
#define BSM020_ALL_VAL_Pos (0)
#define BSM020_ALL_VAL_Msk (0xFFFFFFUL << BSM020_ALL_VAL_Pos)

#define BSM020_BIT_VAL

#define BSM020_ALL_VAL_(x) ((x) << BSM020_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM021          VAL
 *  @access     SIO->BSM021.bit.VAL
 *  @brief      
 */
#define BSM021_ALL_VAL_Pos (0)
#define BSM021_ALL_VAL_Msk (0xFFFFFFUL << BSM021_ALL_VAL_Pos)

#define BSM021_BIT_VAL

#define BSM021_ALL_VAL_(x) ((x) << BSM021_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM022          VAL
 *  @access     SIO->BSM022.bit.VAL
 *  @brief      
 */
#define BSM022_ALL_VAL_Pos (0)
#define BSM022_ALL_VAL_Msk (0xFFFFFFUL << BSM022_ALL_VAL_Pos)

#define BSM022_BIT_VAL

#define BSM022_ALL_VAL_(x) ((x) << BSM022_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM023          VAL
 *  @access     SIO->BSM023.bit.VAL
 *  @brief      
 */
#define BSM023_ALL_VAL_Pos (0)
#define BSM023_ALL_VAL_Msk (0xFFFFFFUL << BSM023_ALL_VAL_Pos)

#define BSM023_BIT_VAL

#define BSM023_ALL_VAL_(x) ((x) << BSM023_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM024          VAL
 *  @access     SIO->BSM024.bit.VAL
 *  @brief      
 */
#define BSM024_ALL_VAL_Pos (0)
#define BSM024_ALL_VAL_Msk (0xFFFFFFUL << BSM024_ALL_VAL_Pos)

#define BSM024_BIT_VAL

#define BSM024_ALL_VAL_(x) ((x) << BSM024_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM025          VAL
 *  @access     SIO->BSM025.bit.VAL
 *  @brief      
 */
#define BSM025_ALL_VAL_Pos (0)
#define BSM025_ALL_VAL_Msk (0xFFFFFFUL << BSM025_ALL_VAL_Pos)

#define BSM025_BIT_VAL

#define BSM025_ALL_VAL_(x) ((x) << BSM025_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM026          VAL
 *  @access     SIO->BSM026.bit.VAL
 *  @brief      
 */
#define BSM026_ALL_VAL_Pos (0)
#define BSM026_ALL_VAL_Msk (0xFFFFFFUL << BSM026_ALL_VAL_Pos)

#define BSM026_BIT_VAL

#define BSM026_ALL_VAL_(x) ((x) << BSM026_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM027          VAL
 *  @access     SIO->BSM027.bit.VAL
 *  @brief      
 */
#define BSM027_ALL_VAL_Pos (0)
#define BSM027_ALL_VAL_Msk (0xFFFFFFUL << BSM027_ALL_VAL_Pos)

#define BSM027_BIT_VAL

#define BSM027_ALL_VAL_(x) ((x) << BSM027_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM028          VAL
 *  @access     SIO->BSM028.bit.VAL
 *  @brief      
 */
#define BSM028_ALL_VAL_Pos (0)
#define BSM028_ALL_VAL_Msk (0xFFFFFFUL << BSM028_ALL_VAL_Pos)

#define BSM028_BIT_VAL

#define BSM028_ALL_VAL_(x) ((x) << BSM028_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM029          VAL
 *  @access     SIO->BSM029.bit.VAL
 *  @brief      
 */
#define BSM029_ALL_VAL_Pos (0)
#define BSM029_ALL_VAL_Msk (0xFFFFFFUL << BSM029_ALL_VAL_Pos)

#define BSM029_BIT_VAL

#define BSM029_ALL_VAL_(x) ((x) << BSM029_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM030          VAL
 *  @access     SIO->BSM030.bit.VAL
 *  @brief      
 */
#define BSM030_ALL_VAL_Pos (0)
#define BSM030_ALL_VAL_Msk (0xFFFFFFUL << BSM030_ALL_VAL_Pos)

#define BSM030_BIT_VAL

#define BSM030_ALL_VAL_(x) ((x) << BSM030_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM031          VAL
 *  @access     SIO->BSM031.bit.VAL
 *  @brief      
 */
#define BSM031_ALL_VAL_Pos (0)
#define BSM031_ALL_VAL_Msk (0xFFFFFFUL << BSM031_ALL_VAL_Pos)

#define BSM031_BIT_VAL

#define BSM031_ALL_VAL_(x) ((x) << BSM031_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM032          VAL
 *  @access     SIO->BSM032.bit.VAL
 *  @brief      
 */
#define BSM032_ALL_VAL_Pos (0)
#define BSM032_ALL_VAL_Msk (0xFFFFFFUL << BSM032_ALL_VAL_Pos)

#define BSM032_BIT_VAL

#define BSM032_ALL_VAL_(x) ((x) << BSM032_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM033          VAL
 *  @access     SIO->BSM033.bit.VAL
 *  @brief      
 */
#define BSM033_ALL_VAL_Pos (0)
#define BSM033_ALL_VAL_Msk (0xFFFFFFUL << BSM033_ALL_VAL_Pos)

#define BSM033_BIT_VAL

#define BSM033_ALL_VAL_(x) ((x) << BSM033_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM034          VAL
 *  @access     SIO->BSM034.bit.VAL
 *  @brief      
 */
#define BSM034_ALL_VAL_Pos (0)
#define BSM034_ALL_VAL_Msk (0xFFFFFFUL << BSM034_ALL_VAL_Pos)

#define BSM034_BIT_VAL

#define BSM034_ALL_VAL_(x) ((x) << BSM034_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM035          VAL
 *  @access     SIO->BSM035.bit.VAL
 *  @brief      
 */
#define BSM035_ALL_VAL_Pos (0)
#define BSM035_ALL_VAL_Msk (0xFFFFFFUL << BSM035_ALL_VAL_Pos)

#define BSM035_BIT_VAL

#define BSM035_ALL_VAL_(x) ((x) << BSM035_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM036          VAL
 *  @access     SIO->BSM036.bit.VAL
 *  @brief      
 */
#define BSM036_ALL_VAL_Pos (0)
#define BSM036_ALL_VAL_Msk (0xFFFFFFUL << BSM036_ALL_VAL_Pos)

#define BSM036_BIT_VAL

#define BSM036_ALL_VAL_(x) ((x) << BSM036_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM037          VAL
 *  @access     SIO->BSM037.bit.VAL
 *  @brief      
 */
#define BSM037_ALL_VAL_Pos (0)
#define BSM037_ALL_VAL_Msk (0xFFFFFFUL << BSM037_ALL_VAL_Pos)

#define BSM037_BIT_VAL

#define BSM037_ALL_VAL_(x) ((x) << BSM037_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM038          VAL
 *  @access     SIO->BSM038.bit.VAL
 *  @brief      
 */
#define BSM038_ALL_VAL_Pos (0)
#define BSM038_ALL_VAL_Msk (0xFFFFFFUL << BSM038_ALL_VAL_Pos)

#define BSM038_BIT_VAL

#define BSM038_ALL_VAL_(x) ((x) << BSM038_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM039          VAL
 *  @access     SIO->BSM039.bit.VAL
 *  @brief      
 */
#define BSM039_ALL_VAL_Pos (0)
#define BSM039_ALL_VAL_Msk (0xFFFFFFUL << BSM039_ALL_VAL_Pos)

#define BSM039_BIT_VAL

#define BSM039_ALL_VAL_(x) ((x) << BSM039_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM040          VAL
 *  @access     SIO->BSM040.bit.VAL
 *  @brief      
 */
#define BSM040_ALL_VAL_Pos (0)
#define BSM040_ALL_VAL_Msk (0xFFFFFFUL << BSM040_ALL_VAL_Pos)

#define BSM040_BIT_VAL

#define BSM040_ALL_VAL_(x) ((x) << BSM040_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM041          VAL
 *  @access     SIO->BSM041.bit.VAL
 *  @brief      
 */
#define BSM041_ALL_VAL_Pos (0)
#define BSM041_ALL_VAL_Msk (0xFFFFFFUL << BSM041_ALL_VAL_Pos)

#define BSM041_BIT_VAL

#define BSM041_ALL_VAL_(x) ((x) << BSM041_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM042          VAL
 *  @access     SIO->BSM042.bit.VAL
 *  @brief      
 */
#define BSM042_ALL_VAL_Pos (0)
#define BSM042_ALL_VAL_Msk (0xFFFFFFUL << BSM042_ALL_VAL_Pos)

#define BSM042_BIT_VAL

#define BSM042_ALL_VAL_(x) ((x) << BSM042_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM043          VAL
 *  @access     SIO->BSM043.bit.VAL
 *  @brief      
 */
#define BSM043_ALL_VAL_Pos (0)
#define BSM043_ALL_VAL_Msk (0xFFFFFFUL << BSM043_ALL_VAL_Pos)

#define BSM043_BIT_VAL

#define BSM043_ALL_VAL_(x) ((x) << BSM043_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM044          VAL
 *  @access     SIO->BSM044.bit.VAL
 *  @brief      
 */
#define BSM044_ALL_VAL_Pos (0)
#define BSM044_ALL_VAL_Msk (0xFFFFFFUL << BSM044_ALL_VAL_Pos)

#define BSM044_BIT_VAL

#define BSM044_ALL_VAL_(x) ((x) << BSM044_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM045          VAL
 *  @access     SIO->BSM045.bit.VAL
 *  @brief      
 */
#define BSM045_ALL_VAL_Pos (0)
#define BSM045_ALL_VAL_Msk (0xFFFFFFUL << BSM045_ALL_VAL_Pos)

#define BSM045_BIT_VAL

#define BSM045_ALL_VAL_(x) ((x) << BSM045_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM046          VAL
 *  @access     SIO->BSM046.bit.VAL
 *  @brief      
 */
#define BSM046_ALL_VAL_Pos (0)
#define BSM046_ALL_VAL_Msk (0xFFFFFFUL << BSM046_ALL_VAL_Pos)

#define BSM046_BIT_VAL

#define BSM046_ALL_VAL_(x) ((x) << BSM046_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM047          VAL
 *  @access     SIO->BSM047.bit.VAL
 *  @brief      
 */
#define BSM047_ALL_VAL_Pos (0)
#define BSM047_ALL_VAL_Msk (0xFFFFFFUL << BSM047_ALL_VAL_Pos)

#define BSM047_BIT_VAL

#define BSM047_ALL_VAL_(x) ((x) << BSM047_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM048          VAL
 *  @access     SIO->BSM048.bit.VAL
 *  @brief      
 */
#define BSM048_ALL_VAL_Pos (0)
#define BSM048_ALL_VAL_Msk (0xFFFFFFUL << BSM048_ALL_VAL_Pos)

#define BSM048_BIT_VAL

#define BSM048_ALL_VAL_(x) ((x) << BSM048_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM049          VAL
 *  @access     SIO->BSM049.bit.VAL
 *  @brief      
 */
#define BSM049_ALL_VAL_Pos (0)
#define BSM049_ALL_VAL_Msk (0xFFFFFFUL << BSM049_ALL_VAL_Pos)

#define BSM049_BIT_VAL

#define BSM049_ALL_VAL_(x) ((x) << BSM049_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM050          VAL
 *  @access     SIO->BSM050.bit.VAL
 *  @brief      
 */
#define BSM050_ALL_VAL_Pos (0)
#define BSM050_ALL_VAL_Msk (0xFFFFFFUL << BSM050_ALL_VAL_Pos)

#define BSM050_BIT_VAL

#define BSM050_ALL_VAL_(x) ((x) << BSM050_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM051          VAL
 *  @access     SIO->BSM051.bit.VAL
 *  @brief      
 */
#define BSM051_ALL_VAL_Pos (0)
#define BSM051_ALL_VAL_Msk (0xFFFFFFUL << BSM051_ALL_VAL_Pos)

#define BSM051_BIT_VAL

#define BSM051_ALL_VAL_(x) ((x) << BSM051_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM052          VAL
 *  @access     SIO->BSM052.bit.VAL
 *  @brief      
 */
#define BSM052_ALL_VAL_Pos (0)
#define BSM052_ALL_VAL_Msk (0xFFFFFFUL << BSM052_ALL_VAL_Pos)

#define BSM052_BIT_VAL

#define BSM052_ALL_VAL_(x) ((x) << BSM052_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM053          VAL
 *  @access     SIO->BSM053.bit.VAL
 *  @brief      
 */
#define BSM053_ALL_VAL_Pos (0)
#define BSM053_ALL_VAL_Msk (0xFFFFFFUL << BSM053_ALL_VAL_Pos)

#define BSM053_BIT_VAL

#define BSM053_ALL_VAL_(x) ((x) << BSM053_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM054          VAL
 *  @access     SIO->BSM054.bit.VAL
 *  @brief      
 */
#define BSM054_ALL_VAL_Pos (0)
#define BSM054_ALL_VAL_Msk (0xFFFFFFUL << BSM054_ALL_VAL_Pos)

#define BSM054_BIT_VAL

#define BSM054_ALL_VAL_(x) ((x) << BSM054_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM055          VAL
 *  @access     SIO->BSM055.bit.VAL
 *  @brief      
 */
#define BSM055_ALL_VAL_Pos (0)
#define BSM055_ALL_VAL_Msk (0xFFFFFFUL << BSM055_ALL_VAL_Pos)

#define BSM055_BIT_VAL

#define BSM055_ALL_VAL_(x) ((x) << BSM055_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM056          VAL
 *  @access     SIO->BSM056.bit.VAL
 *  @brief      
 */
#define BSM056_ALL_VAL_Pos (0)
#define BSM056_ALL_VAL_Msk (0xFFFFFFUL << BSM056_ALL_VAL_Pos)

#define BSM056_BIT_VAL

#define BSM056_ALL_VAL_(x) ((x) << BSM056_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM057          VAL
 *  @access     SIO->BSM057.bit.VAL
 *  @brief      
 */
#define BSM057_ALL_VAL_Pos (0)
#define BSM057_ALL_VAL_Msk (0xFFFFFFUL << BSM057_ALL_VAL_Pos)

#define BSM057_BIT_VAL

#define BSM057_ALL_VAL_(x) ((x) << BSM057_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM058          VAL
 *  @access     SIO->BSM058.bit.VAL
 *  @brief      
 */
#define BSM058_ALL_VAL_Pos (0)
#define BSM058_ALL_VAL_Msk (0xFFFFFFUL << BSM058_ALL_VAL_Pos)

#define BSM058_BIT_VAL

#define BSM058_ALL_VAL_(x) ((x) << BSM058_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM059          VAL
 *  @access     SIO->BSM059.bit.VAL
 *  @brief      
 */
#define BSM059_ALL_VAL_Pos (0)
#define BSM059_ALL_VAL_Msk (0xFFFFFFUL << BSM059_ALL_VAL_Pos)

#define BSM059_BIT_VAL

#define BSM059_ALL_VAL_(x) ((x) << BSM059_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM060          VAL
 *  @access     SIO->BSM060.bit.VAL
 *  @brief      
 */
#define BSM060_ALL_VAL_Pos (0)
#define BSM060_ALL_VAL_Msk (0xFFFFFFUL << BSM060_ALL_VAL_Pos)

#define BSM060_BIT_VAL

#define BSM060_ALL_VAL_(x) ((x) << BSM060_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM061          VAL
 *  @access     SIO->BSM061.bit.VAL
 *  @brief      
 */
#define BSM061_ALL_VAL_Pos (0)
#define BSM061_ALL_VAL_Msk (0xFFFFFFUL << BSM061_ALL_VAL_Pos)

#define BSM061_BIT_VAL

#define BSM061_ALL_VAL_(x) ((x) << BSM061_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM062          VAL
 *  @access     SIO->BSM062.bit.VAL
 *  @brief      
 */
#define BSM062_ALL_VAL_Pos (0)
#define BSM062_ALL_VAL_Msk (0xFFFFFFUL << BSM062_ALL_VAL_Pos)

#define BSM062_BIT_VAL

#define BSM062_ALL_VAL_(x) ((x) << BSM062_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM063          VAL
 *  @access     SIO->BSM063.bit.VAL
 *  @brief      
 */
#define BSM063_ALL_VAL_Pos (0)
#define BSM063_ALL_VAL_Msk (0xFFFFFFUL << BSM063_ALL_VAL_Pos)

#define BSM063_BIT_VAL

#define BSM063_ALL_VAL_(x) ((x) << BSM063_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM064          VAL
 *  @access     SIO->BSM064.bit.VAL
 *  @brief      
 */
#define BSM064_ALL_VAL_Pos (0)
#define BSM064_ALL_VAL_Msk (0xFFFFFFUL << BSM064_ALL_VAL_Pos)

#define BSM064_BIT_VAL

#define BSM064_ALL_VAL_(x) ((x) << BSM064_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM065          VAL
 *  @access     SIO->BSM065.bit.VAL
 *  @brief      
 */
#define BSM065_ALL_VAL_Pos (0)
#define BSM065_ALL_VAL_Msk (0xFFFFFFUL << BSM065_ALL_VAL_Pos)

#define BSM065_BIT_VAL

#define BSM065_ALL_VAL_(x) ((x) << BSM065_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM066          VAL
 *  @access     SIO->BSM066.bit.VAL
 *  @brief      
 */
#define BSM066_ALL_VAL_Pos (0)
#define BSM066_ALL_VAL_Msk (0xFFFFFFUL << BSM066_ALL_VAL_Pos)

#define BSM066_BIT_VAL

#define BSM066_ALL_VAL_(x) ((x) << BSM066_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM067          VAL
 *  @access     SIO->BSM067.bit.VAL
 *  @brief      
 */
#define BSM067_ALL_VAL_Pos (0)
#define BSM067_ALL_VAL_Msk (0xFFFFFFUL << BSM067_ALL_VAL_Pos)

#define BSM067_BIT_VAL

#define BSM067_ALL_VAL_(x) ((x) << BSM067_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM068          VAL
 *  @access     SIO->BSM068.bit.VAL
 *  @brief      
 */
#define BSM068_ALL_VAL_Pos (0)
#define BSM068_ALL_VAL_Msk (0xFFFFFFUL << BSM068_ALL_VAL_Pos)

#define BSM068_BIT_VAL

#define BSM068_ALL_VAL_(x) ((x) << BSM068_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM069          VAL
 *  @access     SIO->BSM069.bit.VAL
 *  @brief      
 */
#define BSM069_ALL_VAL_Pos (0)
#define BSM069_ALL_VAL_Msk (0xFFFFFFUL << BSM069_ALL_VAL_Pos)

#define BSM069_BIT_VAL

#define BSM069_ALL_VAL_(x) ((x) << BSM069_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM070          VAL
 *  @access     SIO->BSM070.bit.VAL
 *  @brief      
 */
#define BSM070_ALL_VAL_Pos (0)
#define BSM070_ALL_VAL_Msk (0xFFFFFFUL << BSM070_ALL_VAL_Pos)

#define BSM070_BIT_VAL

#define BSM070_ALL_VAL_(x) ((x) << BSM070_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM071          VAL
 *  @access     SIO->BSM071.bit.VAL
 *  @brief      
 */
#define BSM071_ALL_VAL_Pos (0)
#define BSM071_ALL_VAL_Msk (0xFFFFFFUL << BSM071_ALL_VAL_Pos)

#define BSM071_BIT_VAL

#define BSM071_ALL_VAL_(x) ((x) << BSM071_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM072          VAL
 *  @access     SIO->BSM072.bit.VAL
 *  @brief      
 */
#define BSM072_ALL_VAL_Pos (0)
#define BSM072_ALL_VAL_Msk (0xFFFFFFUL << BSM072_ALL_VAL_Pos)

#define BSM072_BIT_VAL

#define BSM072_ALL_VAL_(x) ((x) << BSM072_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM073          VAL
 *  @access     SIO->BSM073.bit.VAL
 *  @brief      
 */
#define BSM073_ALL_VAL_Pos (0)
#define BSM073_ALL_VAL_Msk (0xFFFFFFUL << BSM073_ALL_VAL_Pos)

#define BSM073_BIT_VAL

#define BSM073_ALL_VAL_(x) ((x) << BSM073_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM074          VAL
 *  @access     SIO->BSM074.bit.VAL
 *  @brief      
 */
#define BSM074_ALL_VAL_Pos (0)
#define BSM074_ALL_VAL_Msk (0xFFFFFFUL << BSM074_ALL_VAL_Pos)

#define BSM074_BIT_VAL

#define BSM074_ALL_VAL_(x) ((x) << BSM074_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM075          VAL
 *  @access     SIO->BSM075.bit.VAL
 *  @brief      
 */
#define BSM075_ALL_VAL_Pos (0)
#define BSM075_ALL_VAL_Msk (0xFFFFFFUL << BSM075_ALL_VAL_Pos)

#define BSM075_BIT_VAL

#define BSM075_ALL_VAL_(x) ((x) << BSM075_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM076          VAL
 *  @access     SIO->BSM076.bit.VAL
 *  @brief      
 */
#define BSM076_ALL_VAL_Pos (0)
#define BSM076_ALL_VAL_Msk (0xFFFFFFUL << BSM076_ALL_VAL_Pos)

#define BSM076_BIT_VAL

#define BSM076_ALL_VAL_(x) ((x) << BSM076_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM077          VAL
 *  @access     SIO->BSM077.bit.VAL
 *  @brief      
 */
#define BSM077_ALL_VAL_Pos (0)
#define BSM077_ALL_VAL_Msk (0xFFFFFFUL << BSM077_ALL_VAL_Pos)

#define BSM077_BIT_VAL

#define BSM077_ALL_VAL_(x) ((x) << BSM077_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM078          VAL
 *  @access     SIO->BSM078.bit.VAL
 *  @brief      
 */
#define BSM078_ALL_VAL_Pos (0)
#define BSM078_ALL_VAL_Msk (0xFFFFFFUL << BSM078_ALL_VAL_Pos)

#define BSM078_BIT_VAL

#define BSM078_ALL_VAL_(x) ((x) << BSM078_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM079          VAL
 *  @access     SIO->BSM079.bit.VAL
 *  @brief      
 */
#define BSM079_ALL_VAL_Pos (0)
#define BSM079_ALL_VAL_Msk (0xFFFFFFUL << BSM079_ALL_VAL_Pos)

#define BSM079_BIT_VAL

#define BSM079_ALL_VAL_(x) ((x) << BSM079_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM080          VAL
 *  @access     SIO->BSM080.bit.VAL
 *  @brief      
 */
#define BSM080_ALL_VAL_Pos (0)
#define BSM080_ALL_VAL_Msk (0xFFFFFFUL << BSM080_ALL_VAL_Pos)

#define BSM080_BIT_VAL

#define BSM080_ALL_VAL_(x) ((x) << BSM080_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM081          VAL
 *  @access     SIO->BSM081.bit.VAL
 *  @brief      
 */
#define BSM081_ALL_VAL_Pos (0)
#define BSM081_ALL_VAL_Msk (0xFFFFFFUL << BSM081_ALL_VAL_Pos)

#define BSM081_BIT_VAL

#define BSM081_ALL_VAL_(x) ((x) << BSM081_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM082          VAL
 *  @access     SIO->BSM082.bit.VAL
 *  @brief      
 */
#define BSM082_ALL_VAL_Pos (0)
#define BSM082_ALL_VAL_Msk (0xFFFFFFUL << BSM082_ALL_VAL_Pos)

#define BSM082_BIT_VAL

#define BSM082_ALL_VAL_(x) ((x) << BSM082_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM083          VAL
 *  @access     SIO->BSM083.bit.VAL
 *  @brief      
 */
#define BSM083_ALL_VAL_Pos (0)
#define BSM083_ALL_VAL_Msk (0xFFFFFFUL << BSM083_ALL_VAL_Pos)

#define BSM083_BIT_VAL

#define BSM083_ALL_VAL_(x) ((x) << BSM083_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM084          VAL
 *  @access     SIO->BSM084.bit.VAL
 *  @brief      
 */
#define BSM084_ALL_VAL_Pos (0)
#define BSM084_ALL_VAL_Msk (0xFFFFFFUL << BSM084_ALL_VAL_Pos)

#define BSM084_BIT_VAL

#define BSM084_ALL_VAL_(x) ((x) << BSM084_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM085          VAL
 *  @access     SIO->BSM085.bit.VAL
 *  @brief      
 */
#define BSM085_ALL_VAL_Pos (0)
#define BSM085_ALL_VAL_Msk (0xFFFFFFUL << BSM085_ALL_VAL_Pos)

#define BSM085_BIT_VAL

#define BSM085_ALL_VAL_(x) ((x) << BSM085_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM086          VAL
 *  @access     SIO->BSM086.bit.VAL
 *  @brief      
 */
#define BSM086_ALL_VAL_Pos (0)
#define BSM086_ALL_VAL_Msk (0xFFFFFFUL << BSM086_ALL_VAL_Pos)

#define BSM086_BIT_VAL

#define BSM086_ALL_VAL_(x) ((x) << BSM086_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM087          VAL
 *  @access     SIO->BSM087.bit.VAL
 *  @brief      
 */
#define BSM087_ALL_VAL_Pos (0)
#define BSM087_ALL_VAL_Msk (0xFFFFFFUL << BSM087_ALL_VAL_Pos)

#define BSM087_BIT_VAL

#define BSM087_ALL_VAL_(x) ((x) << BSM087_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM088          VAL
 *  @access     SIO->BSM088.bit.VAL
 *  @brief      
 */
#define BSM088_ALL_VAL_Pos (0)
#define BSM088_ALL_VAL_Msk (0xFFFFFFUL << BSM088_ALL_VAL_Pos)

#define BSM088_BIT_VAL

#define BSM088_ALL_VAL_(x) ((x) << BSM088_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM089          VAL
 *  @access     SIO->BSM089.bit.VAL
 *  @brief      
 */
#define BSM089_ALL_VAL_Pos (0)
#define BSM089_ALL_VAL_Msk (0xFFFFFFUL << BSM089_ALL_VAL_Pos)

#define BSM089_BIT_VAL

#define BSM089_ALL_VAL_(x) ((x) << BSM089_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM090          VAL
 *  @access     SIO->BSM090.bit.VAL
 *  @brief      
 */
#define BSM090_ALL_VAL_Pos (0)
#define BSM090_ALL_VAL_Msk (0xFFFFFFUL << BSM090_ALL_VAL_Pos)

#define BSM090_BIT_VAL

#define BSM090_ALL_VAL_(x) ((x) << BSM090_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM091          VAL
 *  @access     SIO->BSM091.bit.VAL
 *  @brief      
 */
#define BSM091_ALL_VAL_Pos (0)
#define BSM091_ALL_VAL_Msk (0xFFFFFFUL << BSM091_ALL_VAL_Pos)

#define BSM091_BIT_VAL

#define BSM091_ALL_VAL_(x) ((x) << BSM091_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM092          VAL
 *  @access     SIO->BSM092.bit.VAL
 *  @brief      
 */
#define BSM092_ALL_VAL_Pos (0)
#define BSM092_ALL_VAL_Msk (0xFFFFFFUL << BSM092_ALL_VAL_Pos)

#define BSM092_BIT_VAL

#define BSM092_ALL_VAL_(x) ((x) << BSM092_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM093          VAL
 *  @access     SIO->BSM093.bit.VAL
 *  @brief      
 */
#define BSM093_ALL_VAL_Pos (0)
#define BSM093_ALL_VAL_Msk (0xFFFFFFUL << BSM093_ALL_VAL_Pos)

#define BSM093_BIT_VAL

#define BSM093_ALL_VAL_(x) ((x) << BSM093_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM094          VAL
 *  @access     SIO->BSM094.bit.VAL
 *  @brief      
 */
#define BSM094_ALL_VAL_Pos (0)
#define BSM094_ALL_VAL_Msk (0xFFFFFFUL << BSM094_ALL_VAL_Pos)

#define BSM094_BIT_VAL

#define BSM094_ALL_VAL_(x) ((x) << BSM094_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM095          VAL
 *  @access     SIO->BSM095.bit.VAL
 *  @brief      
 */
#define BSM095_ALL_VAL_Pos (0)
#define BSM095_ALL_VAL_Msk (0xFFFFFFUL << BSM095_ALL_VAL_Pos)

#define BSM095_BIT_VAL

#define BSM095_ALL_VAL_(x) ((x) << BSM095_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM096          VAL
 *  @access     SIO->BSM096.bit.VAL
 *  @brief      
 */
#define BSM096_ALL_VAL_Pos (0)
#define BSM096_ALL_VAL_Msk (0xFFFFFFUL << BSM096_ALL_VAL_Pos)

#define BSM096_BIT_VAL

#define BSM096_ALL_VAL_(x) ((x) << BSM096_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM097          VAL
 *  @access     SIO->BSM097.bit.VAL
 *  @brief      
 */
#define BSM097_ALL_VAL_Pos (0)
#define BSM097_ALL_VAL_Msk (0xFFFFFFUL << BSM097_ALL_VAL_Pos)

#define BSM097_BIT_VAL

#define BSM097_ALL_VAL_(x) ((x) << BSM097_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM098          VAL
 *  @access     SIO->BSM098.bit.VAL
 *  @brief      
 */
#define BSM098_ALL_VAL_Pos (0)
#define BSM098_ALL_VAL_Msk (0xFFFFFFUL << BSM098_ALL_VAL_Pos)

#define BSM098_BIT_VAL

#define BSM098_ALL_VAL_(x) ((x) << BSM098_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM099          VAL
 *  @access     SIO->BSM099.bit.VAL
 *  @brief      
 */
#define BSM099_ALL_VAL_Pos (0)
#define BSM099_ALL_VAL_Msk (0xFFFFFFUL << BSM099_ALL_VAL_Pos)

#define BSM099_BIT_VAL

#define BSM099_ALL_VAL_(x) ((x) << BSM099_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM100          VAL
 *  @access     SIO->BSM100.bit.VAL
 *  @brief      
 */
#define BSM100_ALL_VAL_Pos (0)
#define BSM100_ALL_VAL_Msk (0xFFFFFFUL << BSM100_ALL_VAL_Pos)

#define BSM100_BIT_VAL

#define BSM100_ALL_VAL_(x) ((x) << BSM100_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM101          VAL
 *  @access     SIO->BSM101.bit.VAL
 *  @brief      
 */
#define BSM101_ALL_VAL_Pos (0)
#define BSM101_ALL_VAL_Msk (0xFFFFFFUL << BSM101_ALL_VAL_Pos)

#define BSM101_BIT_VAL

#define BSM101_ALL_VAL_(x) ((x) << BSM101_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM102          VAL
 *  @access     SIO->BSM102.bit.VAL
 *  @brief      
 */
#define BSM102_ALL_VAL_Pos (0)
#define BSM102_ALL_VAL_Msk (0xFFFFFFUL << BSM102_ALL_VAL_Pos)

#define BSM102_BIT_VAL

#define BSM102_ALL_VAL_(x) ((x) << BSM102_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM103          VAL
 *  @access     SIO->BSM103.bit.VAL
 *  @brief      
 */
#define BSM103_ALL_VAL_Pos (0)
#define BSM103_ALL_VAL_Msk (0xFFFFFFUL << BSM103_ALL_VAL_Pos)

#define BSM103_BIT_VAL

#define BSM103_ALL_VAL_(x) ((x) << BSM103_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM104          VAL
 *  @access     SIO->BSM104.bit.VAL
 *  @brief      
 */
#define BSM104_ALL_VAL_Pos (0)
#define BSM104_ALL_VAL_Msk (0xFFFFFFUL << BSM104_ALL_VAL_Pos)

#define BSM104_BIT_VAL

#define BSM104_ALL_VAL_(x) ((x) << BSM104_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM105          VAL
 *  @access     SIO->BSM105.bit.VAL
 *  @brief      
 */
#define BSM105_ALL_VAL_Pos (0)
#define BSM105_ALL_VAL_Msk (0xFFFFFFUL << BSM105_ALL_VAL_Pos)

#define BSM105_BIT_VAL

#define BSM105_ALL_VAL_(x) ((x) << BSM105_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM106          VAL
 *  @access     SIO->BSM106.bit.VAL
 *  @brief      
 */
#define BSM106_ALL_VAL_Pos (0)
#define BSM106_ALL_VAL_Msk (0xFFFFFFUL << BSM106_ALL_VAL_Pos)

#define BSM106_BIT_VAL

#define BSM106_ALL_VAL_(x) ((x) << BSM106_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM107          VAL
 *  @access     SIO->BSM107.bit.VAL
 *  @brief      
 */
#define BSM107_ALL_VAL_Pos (0)
#define BSM107_ALL_VAL_Msk (0xFFFFFFUL << BSM107_ALL_VAL_Pos)

#define BSM107_BIT_VAL

#define BSM107_ALL_VAL_(x) ((x) << BSM107_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM108          VAL
 *  @access     SIO->BSM108.bit.VAL
 *  @brief      
 */
#define BSM108_ALL_VAL_Pos (0)
#define BSM108_ALL_VAL_Msk (0xFFFFFFUL << BSM108_ALL_VAL_Pos)

#define BSM108_BIT_VAL

#define BSM108_ALL_VAL_(x) ((x) << BSM108_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM109          VAL
 *  @access     SIO->BSM109.bit.VAL
 *  @brief      
 */
#define BSM109_ALL_VAL_Pos (0)
#define BSM109_ALL_VAL_Msk (0xFFFFFFUL << BSM109_ALL_VAL_Pos)

#define BSM109_BIT_VAL

#define BSM109_ALL_VAL_(x) ((x) << BSM109_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM110          VAL
 *  @access     SIO->BSM110.bit.VAL
 *  @brief      
 */
#define BSM110_ALL_VAL_Pos (0)
#define BSM110_ALL_VAL_Msk (0xFFFFFFUL << BSM110_ALL_VAL_Pos)

#define BSM110_BIT_VAL

#define BSM110_ALL_VAL_(x) ((x) << BSM110_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM111          VAL
 *  @access     SIO->BSM111.bit.VAL
 *  @brief      
 */
#define BSM111_ALL_VAL_Pos (0)
#define BSM111_ALL_VAL_Msk (0xFFFFFFUL << BSM111_ALL_VAL_Pos)

#define BSM111_BIT_VAL

#define BSM111_ALL_VAL_(x) ((x) << BSM111_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM112          VAL
 *  @access     SIO->BSM112.bit.VAL
 *  @brief      
 */
#define BSM112_ALL_VAL_Pos (0)
#define BSM112_ALL_VAL_Msk (0xFFFFFFUL << BSM112_ALL_VAL_Pos)

#define BSM112_BIT_VAL

#define BSM112_ALL_VAL_(x) ((x) << BSM112_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM113          VAL
 *  @access     SIO->BSM113.bit.VAL
 *  @brief      
 */
#define BSM113_ALL_VAL_Pos (0)
#define BSM113_ALL_VAL_Msk (0xFFFFFFUL << BSM113_ALL_VAL_Pos)

#define BSM113_BIT_VAL

#define BSM113_ALL_VAL_(x) ((x) << BSM113_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM114          VAL
 *  @access     SIO->BSM114.bit.VAL
 *  @brief      
 */
#define BSM114_ALL_VAL_Pos (0)
#define BSM114_ALL_VAL_Msk (0xFFFFFFUL << BSM114_ALL_VAL_Pos)

#define BSM114_BIT_VAL

#define BSM114_ALL_VAL_(x) ((x) << BSM114_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM115          VAL
 *  @access     SIO->BSM115.bit.VAL
 *  @brief      
 */
#define BSM115_ALL_VAL_Pos (0)
#define BSM115_ALL_VAL_Msk (0xFFFFFFUL << BSM115_ALL_VAL_Pos)

#define BSM115_BIT_VAL

#define BSM115_ALL_VAL_(x) ((x) << BSM115_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM116          VAL
 *  @access     SIO->BSM116.bit.VAL
 *  @brief      
 */
#define BSM116_ALL_VAL_Pos (0)
#define BSM116_ALL_VAL_Msk (0xFFFFFFUL << BSM116_ALL_VAL_Pos)

#define BSM116_BIT_VAL

#define BSM116_ALL_VAL_(x) ((x) << BSM116_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM117          VAL
 *  @access     SIO->BSM117.bit.VAL
 *  @brief      
 */
#define BSM117_ALL_VAL_Pos (0)
#define BSM117_ALL_VAL_Msk (0xFFFFFFUL << BSM117_ALL_VAL_Pos)

#define BSM117_BIT_VAL

#define BSM117_ALL_VAL_(x) ((x) << BSM117_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM118          VAL
 *  @access     SIO->BSM118.bit.VAL
 *  @brief      
 */
#define BSM118_ALL_VAL_Pos (0)
#define BSM118_ALL_VAL_Msk (0xFFFFFFUL << BSM118_ALL_VAL_Pos)

#define BSM118_BIT_VAL

#define BSM118_ALL_VAL_(x) ((x) << BSM118_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM119          VAL
 *  @access     SIO->BSM119.bit.VAL
 *  @brief      
 */
#define BSM119_ALL_VAL_Pos (0)
#define BSM119_ALL_VAL_Msk (0xFFFFFFUL << BSM119_ALL_VAL_Pos)

#define BSM119_BIT_VAL

#define BSM119_ALL_VAL_(x) ((x) << BSM119_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM120          VAL
 *  @access     SIO->BSM120.bit.VAL
 *  @brief      
 */
#define BSM120_ALL_VAL_Pos (0)
#define BSM120_ALL_VAL_Msk (0xFFFFFFUL << BSM120_ALL_VAL_Pos)

#define BSM120_BIT_VAL

#define BSM120_ALL_VAL_(x) ((x) << BSM120_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM121          VAL
 *  @access     SIO->BSM121.bit.VAL
 *  @brief      
 */
#define BSM121_ALL_VAL_Pos (0)
#define BSM121_ALL_VAL_Msk (0xFFFFFFUL << BSM121_ALL_VAL_Pos)

#define BSM121_BIT_VAL

#define BSM121_ALL_VAL_(x) ((x) << BSM121_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM122          VAL
 *  @access     SIO->BSM122.bit.VAL
 *  @brief      
 */
#define BSM122_ALL_VAL_Pos (0)
#define BSM122_ALL_VAL_Msk (0xFFFFFFUL << BSM122_ALL_VAL_Pos)

#define BSM122_BIT_VAL

#define BSM122_ALL_VAL_(x) ((x) << BSM122_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM123          VAL
 *  @access     SIO->BSM123.bit.VAL
 *  @brief      
 */
#define BSM123_ALL_VAL_Pos (0)
#define BSM123_ALL_VAL_Msk (0xFFFFFFUL << BSM123_ALL_VAL_Pos)

#define BSM123_BIT_VAL

#define BSM123_ALL_VAL_(x) ((x) << BSM123_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM124          VAL
 *  @access     SIO->BSM124.bit.VAL
 *  @brief      
 */
#define BSM124_ALL_VAL_Pos (0)
#define BSM124_ALL_VAL_Msk (0xFFFFFFUL << BSM124_ALL_VAL_Pos)

#define BSM124_BIT_VAL

#define BSM124_ALL_VAL_(x) ((x) << BSM124_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM125          VAL
 *  @access     SIO->BSM125.bit.VAL
 *  @brief      
 */
#define BSM125_ALL_VAL_Pos (0)
#define BSM125_ALL_VAL_Msk (0xFFFFFFUL << BSM125_ALL_VAL_Pos)

#define BSM125_BIT_VAL

#define BSM125_ALL_VAL_(x) ((x) << BSM125_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM126          VAL
 *  @access     SIO->BSM126.bit.VAL
 *  @brief      
 */
#define BSM126_ALL_VAL_Pos (0)
#define BSM126_ALL_VAL_Msk (0xFFFFFFUL << BSM126_ALL_VAL_Pos)

#define BSM126_BIT_VAL

#define BSM126_ALL_VAL_(x) ((x) << BSM126_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM127          VAL
 *  @access     SIO->BSM127.bit.VAL
 *  @brief      
 */
#define BSM127_ALL_VAL_Pos (0)
#define BSM127_ALL_VAL_Msk (0xFFFFFFUL << BSM127_ALL_VAL_Pos)

#define BSM127_BIT_VAL

#define BSM127_ALL_VAL_(x) ((x) << BSM127_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM128          VAL
 *  @access     SIO->BSM128.bit.VAL
 *  @brief      
 */
#define BSM128_ALL_VAL_Pos (0)
#define BSM128_ALL_VAL_Msk (0xFFFFFFUL << BSM128_ALL_VAL_Pos)

#define BSM128_BIT_VAL

#define BSM128_ALL_VAL_(x) ((x) << BSM128_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM129          VAL
 *  @access     SIO->BSM129.bit.VAL
 *  @brief      
 */
#define BSM129_ALL_VAL_Pos (0)
#define BSM129_ALL_VAL_Msk (0xFFFFFFUL << BSM129_ALL_VAL_Pos)

#define BSM129_BIT_VAL

#define BSM129_ALL_VAL_(x) ((x) << BSM129_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM130          VAL
 *  @access     SIO->BSM130.bit.VAL
 *  @brief      
 */
#define BSM130_ALL_VAL_Pos (0)
#define BSM130_ALL_VAL_Msk (0xFFFFFFUL << BSM130_ALL_VAL_Pos)

#define BSM130_BIT_VAL

#define BSM130_ALL_VAL_(x) ((x) << BSM130_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM131          VAL
 *  @access     SIO->BSM131.bit.VAL
 *  @brief      
 */
#define BSM131_ALL_VAL_Pos (0)
#define BSM131_ALL_VAL_Msk (0xFFFFFFUL << BSM131_ALL_VAL_Pos)

#define BSM131_BIT_VAL

#define BSM131_ALL_VAL_(x) ((x) << BSM131_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM132          VAL
 *  @access     SIO->BSM132.bit.VAL
 *  @brief      
 */
#define BSM132_ALL_VAL_Pos (0)
#define BSM132_ALL_VAL_Msk (0xFFFFFFUL << BSM132_ALL_VAL_Pos)

#define BSM132_BIT_VAL

#define BSM132_ALL_VAL_(x) ((x) << BSM132_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM133          VAL
 *  @access     SIO->BSM133.bit.VAL
 *  @brief      
 */
#define BSM133_ALL_VAL_Pos (0)
#define BSM133_ALL_VAL_Msk (0xFFFFFFUL << BSM133_ALL_VAL_Pos)

#define BSM133_BIT_VAL

#define BSM133_ALL_VAL_(x) ((x) << BSM133_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM134          VAL
 *  @access     SIO->BSM134.bit.VAL
 *  @brief      
 */
#define BSM134_ALL_VAL_Pos (0)
#define BSM134_ALL_VAL_Msk (0xFFFFFFUL << BSM134_ALL_VAL_Pos)

#define BSM134_BIT_VAL

#define BSM134_ALL_VAL_(x) ((x) << BSM134_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM135          VAL
 *  @access     SIO->BSM135.bit.VAL
 *  @brief      
 */
#define BSM135_ALL_VAL_Pos (0)
#define BSM135_ALL_VAL_Msk (0xFFFFFFUL << BSM135_ALL_VAL_Pos)

#define BSM135_BIT_VAL

#define BSM135_ALL_VAL_(x) ((x) << BSM135_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM136          VAL
 *  @access     SIO->BSM136.bit.VAL
 *  @brief      
 */
#define BSM136_ALL_VAL_Pos (0)
#define BSM136_ALL_VAL_Msk (0xFFFFFFUL << BSM136_ALL_VAL_Pos)

#define BSM136_BIT_VAL

#define BSM136_ALL_VAL_(x) ((x) << BSM136_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM137          VAL
 *  @access     SIO->BSM137.bit.VAL
 *  @brief      
 */
#define BSM137_ALL_VAL_Pos (0)
#define BSM137_ALL_VAL_Msk (0xFFFFFFUL << BSM137_ALL_VAL_Pos)

#define BSM137_BIT_VAL

#define BSM137_ALL_VAL_(x) ((x) << BSM137_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM138          VAL
 *  @access     SIO->BSM138.bit.VAL
 *  @brief      
 */
#define BSM138_ALL_VAL_Pos (0)
#define BSM138_ALL_VAL_Msk (0xFFFFFFUL << BSM138_ALL_VAL_Pos)

#define BSM138_BIT_VAL

#define BSM138_ALL_VAL_(x) ((x) << BSM138_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM139          VAL
 *  @access     SIO->BSM139.bit.VAL
 *  @brief      
 */
#define BSM139_ALL_VAL_Pos (0)
#define BSM139_ALL_VAL_Msk (0xFFFFFFUL << BSM139_ALL_VAL_Pos)

#define BSM139_BIT_VAL

#define BSM139_ALL_VAL_(x) ((x) << BSM139_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM140          VAL
 *  @access     SIO->BSM140.bit.VAL
 *  @brief      
 */
#define BSM140_ALL_VAL_Pos (0)
#define BSM140_ALL_VAL_Msk (0xFFFFFFUL << BSM140_ALL_VAL_Pos)

#define BSM140_BIT_VAL

#define BSM140_ALL_VAL_(x) ((x) << BSM140_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM141          VAL
 *  @access     SIO->BSM141.bit.VAL
 *  @brief      
 */
#define BSM141_ALL_VAL_Pos (0)
#define BSM141_ALL_VAL_Msk (0xFFFFFFUL << BSM141_ALL_VAL_Pos)

#define BSM141_BIT_VAL

#define BSM141_ALL_VAL_(x) ((x) << BSM141_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM142          VAL
 *  @access     SIO->BSM142.bit.VAL
 *  @brief      
 */
#define BSM142_ALL_VAL_Pos (0)
#define BSM142_ALL_VAL_Msk (0xFFFFFFUL << BSM142_ALL_VAL_Pos)

#define BSM142_BIT_VAL

#define BSM142_ALL_VAL_(x) ((x) << BSM142_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM143          VAL
 *  @access     SIO->BSM143.bit.VAL
 *  @brief      
 */
#define BSM143_ALL_VAL_Pos (0)
#define BSM143_ALL_VAL_Msk (0xFFFFFFUL << BSM143_ALL_VAL_Pos)

#define BSM143_BIT_VAL

#define BSM143_ALL_VAL_(x) ((x) << BSM143_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM144          VAL
 *  @access     SIO->BSM144.bit.VAL
 *  @brief      
 */
#define BSM144_ALL_VAL_Pos (0)
#define BSM144_ALL_VAL_Msk (0xFFFFFFUL << BSM144_ALL_VAL_Pos)

#define BSM144_BIT_VAL

#define BSM144_ALL_VAL_(x) ((x) << BSM144_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM145          VAL
 *  @access     SIO->BSM145.bit.VAL
 *  @brief      
 */
#define BSM145_ALL_VAL_Pos (0)
#define BSM145_ALL_VAL_Msk (0xFFFFFFUL << BSM145_ALL_VAL_Pos)

#define BSM145_BIT_VAL

#define BSM145_ALL_VAL_(x) ((x) << BSM145_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM146          VAL
 *  @access     SIO->BSM146.bit.VAL
 *  @brief      
 */
#define BSM146_ALL_VAL_Pos (0)
#define BSM146_ALL_VAL_Msk (0xFFFFFFUL << BSM146_ALL_VAL_Pos)

#define BSM146_BIT_VAL

#define BSM146_ALL_VAL_(x) ((x) << BSM146_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM147          VAL
 *  @access     SIO->BSM147.bit.VAL
 *  @brief      
 */
#define BSM147_ALL_VAL_Pos (0)
#define BSM147_ALL_VAL_Msk (0xFFFFFFUL << BSM147_ALL_VAL_Pos)

#define BSM147_BIT_VAL

#define BSM147_ALL_VAL_(x) ((x) << BSM147_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM148          VAL
 *  @access     SIO->BSM148.bit.VAL
 *  @brief      
 */
#define BSM148_ALL_VAL_Pos (0)
#define BSM148_ALL_VAL_Msk (0xFFFFFFUL << BSM148_ALL_VAL_Pos)

#define BSM148_BIT_VAL

#define BSM148_ALL_VAL_(x) ((x) << BSM148_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM149          VAL
 *  @access     SIO->BSM149.bit.VAL
 *  @brief      
 */
#define BSM149_ALL_VAL_Pos (0)
#define BSM149_ALL_VAL_Msk (0xFFFFFFUL << BSM149_ALL_VAL_Pos)

#define BSM149_BIT_VAL

#define BSM149_ALL_VAL_(x) ((x) << BSM149_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM150          VAL
 *  @access     SIO->BSM150.bit.VAL
 *  @brief      
 */
#define BSM150_ALL_VAL_Pos (0)
#define BSM150_ALL_VAL_Msk (0xFFFFFFUL << BSM150_ALL_VAL_Pos)

#define BSM150_BIT_VAL

#define BSM150_ALL_VAL_(x) ((x) << BSM150_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM151          VAL
 *  @access     SIO->BSM151.bit.VAL
 *  @brief      
 */
#define BSM151_ALL_VAL_Pos (0)
#define BSM151_ALL_VAL_Msk (0xFFFFFFUL << BSM151_ALL_VAL_Pos)

#define BSM151_BIT_VAL

#define BSM151_ALL_VAL_(x) ((x) << BSM151_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM152          VAL
 *  @access     SIO->BSM152.bit.VAL
 *  @brief      
 */
#define BSM152_ALL_VAL_Pos (0)
#define BSM152_ALL_VAL_Msk (0xFFFFFFUL << BSM152_ALL_VAL_Pos)

#define BSM152_BIT_VAL

#define BSM152_ALL_VAL_(x) ((x) << BSM152_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM153          VAL
 *  @access     SIO->BSM153.bit.VAL
 *  @brief      
 */
#define BSM153_ALL_VAL_Pos (0)
#define BSM153_ALL_VAL_Msk (0xFFFFFFUL << BSM153_ALL_VAL_Pos)

#define BSM153_BIT_VAL

#define BSM153_ALL_VAL_(x) ((x) << BSM153_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM154          VAL
 *  @access     SIO->BSM154.bit.VAL
 *  @brief      
 */
#define BSM154_ALL_VAL_Pos (0)
#define BSM154_ALL_VAL_Msk (0xFFFFFFUL << BSM154_ALL_VAL_Pos)

#define BSM154_BIT_VAL

#define BSM154_ALL_VAL_(x) ((x) << BSM154_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM155          VAL
 *  @access     SIO->BSM155.bit.VAL
 *  @brief      
 */
#define BSM155_ALL_VAL_Pos (0)
#define BSM155_ALL_VAL_Msk (0xFFFFFFUL << BSM155_ALL_VAL_Pos)

#define BSM155_BIT_VAL

#define BSM155_ALL_VAL_(x) ((x) << BSM155_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM156          VAL
 *  @access     SIO->BSM156.bit.VAL
 *  @brief      
 */
#define BSM156_ALL_VAL_Pos (0)
#define BSM156_ALL_VAL_Msk (0xFFFFFFUL << BSM156_ALL_VAL_Pos)

#define BSM156_BIT_VAL

#define BSM156_ALL_VAL_(x) ((x) << BSM156_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM157          VAL
 *  @access     SIO->BSM157.bit.VAL
 *  @brief      
 */
#define BSM157_ALL_VAL_Pos (0)
#define BSM157_ALL_VAL_Msk (0xFFFFFFUL << BSM157_ALL_VAL_Pos)

#define BSM157_BIT_VAL

#define BSM157_ALL_VAL_(x) ((x) << BSM157_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM158          VAL
 *  @access     SIO->BSM158.bit.VAL
 *  @brief      
 */
#define BSM158_ALL_VAL_Pos (0)
#define BSM158_ALL_VAL_Msk (0xFFFFFFUL << BSM158_ALL_VAL_Pos)

#define BSM158_BIT_VAL

#define BSM158_ALL_VAL_(x) ((x) << BSM158_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM159          VAL
 *  @access     SIO->BSM159.bit.VAL
 *  @brief      
 */
#define BSM159_ALL_VAL_Pos (0)
#define BSM159_ALL_VAL_Msk (0xFFFFFFUL << BSM159_ALL_VAL_Pos)

#define BSM159_BIT_VAL

#define BSM159_ALL_VAL_(x) ((x) << BSM159_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM160          VAL
 *  @access     SIO->BSM160.bit.VAL
 *  @brief      
 */
#define BSM160_ALL_VAL_Pos (0)
#define BSM160_ALL_VAL_Msk (0xFFFFFFUL << BSM160_ALL_VAL_Pos)

#define BSM160_BIT_VAL

#define BSM160_ALL_VAL_(x) ((x) << BSM160_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM161          VAL
 *  @access     SIO->BSM161.bit.VAL
 *  @brief      
 */
#define BSM161_ALL_VAL_Pos (0)
#define BSM161_ALL_VAL_Msk (0xFFFFFFUL << BSM161_ALL_VAL_Pos)

#define BSM161_BIT_VAL

#define BSM161_ALL_VAL_(x) ((x) << BSM161_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM162          VAL
 *  @access     SIO->BSM162.bit.VAL
 *  @brief      
 */
#define BSM162_ALL_VAL_Pos (0)
#define BSM162_ALL_VAL_Msk (0xFFFFFFUL << BSM162_ALL_VAL_Pos)

#define BSM162_BIT_VAL

#define BSM162_ALL_VAL_(x) ((x) << BSM162_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM163          VAL
 *  @access     SIO->BSM163.bit.VAL
 *  @brief      
 */
#define BSM163_ALL_VAL_Pos (0)
#define BSM163_ALL_VAL_Msk (0xFFFFFFUL << BSM163_ALL_VAL_Pos)

#define BSM163_BIT_VAL

#define BSM163_ALL_VAL_(x) ((x) << BSM163_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM164          VAL
 *  @access     SIO->BSM164.bit.VAL
 *  @brief      
 */
#define BSM164_ALL_VAL_Pos (0)
#define BSM164_ALL_VAL_Msk (0xFFFFFFUL << BSM164_ALL_VAL_Pos)

#define BSM164_BIT_VAL

#define BSM164_ALL_VAL_(x) ((x) << BSM164_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM165          VAL
 *  @access     SIO->BSM165.bit.VAL
 *  @brief      
 */
#define BSM165_ALL_VAL_Pos (0)
#define BSM165_ALL_VAL_Msk (0xFFFFFFUL << BSM165_ALL_VAL_Pos)

#define BSM165_BIT_VAL

#define BSM165_ALL_VAL_(x) ((x) << BSM165_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM166          VAL
 *  @access     SIO->BSM166.bit.VAL
 *  @brief      
 */
#define BSM166_ALL_VAL_Pos (0)
#define BSM166_ALL_VAL_Msk (0xFFFFFFUL << BSM166_ALL_VAL_Pos)

#define BSM166_BIT_VAL

#define BSM166_ALL_VAL_(x) ((x) << BSM166_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM167          VAL
 *  @access     SIO->BSM167.bit.VAL
 *  @brief      
 */
#define BSM167_ALL_VAL_Pos (0)
#define BSM167_ALL_VAL_Msk (0xFFFFFFUL << BSM167_ALL_VAL_Pos)

#define BSM167_BIT_VAL

#define BSM167_ALL_VAL_(x) ((x) << BSM167_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM168          VAL
 *  @access     SIO->BSM168.bit.VAL
 *  @brief      
 */
#define BSM168_ALL_VAL_Pos (0)
#define BSM168_ALL_VAL_Msk (0xFFFFFFUL << BSM168_ALL_VAL_Pos)

#define BSM168_BIT_VAL

#define BSM168_ALL_VAL_(x) ((x) << BSM168_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM169          VAL
 *  @access     SIO->BSM169.bit.VAL
 *  @brief      
 */
#define BSM169_ALL_VAL_Pos (0)
#define BSM169_ALL_VAL_Msk (0xFFFFFFUL << BSM169_ALL_VAL_Pos)

#define BSM169_BIT_VAL

#define BSM169_ALL_VAL_(x) ((x) << BSM169_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM170          VAL
 *  @access     SIO->BSM170.bit.VAL
 *  @brief      
 */
#define BSM170_ALL_VAL_Pos (0)
#define BSM170_ALL_VAL_Msk (0xFFFFFFUL << BSM170_ALL_VAL_Pos)

#define BSM170_BIT_VAL

#define BSM170_ALL_VAL_(x) ((x) << BSM170_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM171          VAL
 *  @access     SIO->BSM171.bit.VAL
 *  @brief      
 */
#define BSM171_ALL_VAL_Pos (0)
#define BSM171_ALL_VAL_Msk (0xFFFFFFUL << BSM171_ALL_VAL_Pos)

#define BSM171_BIT_VAL

#define BSM171_ALL_VAL_(x) ((x) << BSM171_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM172          VAL
 *  @access     SIO->BSM172.bit.VAL
 *  @brief      
 */
#define BSM172_ALL_VAL_Pos (0)
#define BSM172_ALL_VAL_Msk (0xFFFFFFUL << BSM172_ALL_VAL_Pos)

#define BSM172_BIT_VAL

#define BSM172_ALL_VAL_(x) ((x) << BSM172_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM173          VAL
 *  @access     SIO->BSM173.bit.VAL
 *  @brief      
 */
#define BSM173_ALL_VAL_Pos (0)
#define BSM173_ALL_VAL_Msk (0xFFFFFFUL << BSM173_ALL_VAL_Pos)

#define BSM173_BIT_VAL

#define BSM173_ALL_VAL_(x) ((x) << BSM173_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM174          VAL
 *  @access     SIO->BSM174.bit.VAL
 *  @brief      
 */
#define BSM174_ALL_VAL_Pos (0)
#define BSM174_ALL_VAL_Msk (0xFFFFFFUL << BSM174_ALL_VAL_Pos)

#define BSM174_BIT_VAL

#define BSM174_ALL_VAL_(x) ((x) << BSM174_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM175          VAL
 *  @access     SIO->BSM175.bit.VAL
 *  @brief      
 */
#define BSM175_ALL_VAL_Pos (0)
#define BSM175_ALL_VAL_Msk (0xFFFFFFUL << BSM175_ALL_VAL_Pos)

#define BSM175_BIT_VAL

#define BSM175_ALL_VAL_(x) ((x) << BSM175_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM176          VAL
 *  @access     SIO->BSM176.bit.VAL
 *  @brief      
 */
#define BSM176_ALL_VAL_Pos (0)
#define BSM176_ALL_VAL_Msk (0xFFFFFFUL << BSM176_ALL_VAL_Pos)

#define BSM176_BIT_VAL

#define BSM176_ALL_VAL_(x) ((x) << BSM176_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM177          VAL
 *  @access     SIO->BSM177.bit.VAL
 *  @brief      
 */
#define BSM177_ALL_VAL_Pos (0)
#define BSM177_ALL_VAL_Msk (0xFFFFFFUL << BSM177_ALL_VAL_Pos)

#define BSM177_BIT_VAL

#define BSM177_ALL_VAL_(x) ((x) << BSM177_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM178          VAL
 *  @access     SIO->BSM178.bit.VAL
 *  @brief      
 */
#define BSM178_ALL_VAL_Pos (0)
#define BSM178_ALL_VAL_Msk (0xFFFFFFUL << BSM178_ALL_VAL_Pos)

#define BSM178_BIT_VAL

#define BSM178_ALL_VAL_(x) ((x) << BSM178_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM179          VAL
 *  @access     SIO->BSM179.bit.VAL
 *  @brief      
 */
#define BSM179_ALL_VAL_Pos (0)
#define BSM179_ALL_VAL_Msk (0xFFFFFFUL << BSM179_ALL_VAL_Pos)

#define BSM179_BIT_VAL

#define BSM179_ALL_VAL_(x) ((x) << BSM179_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM180          VAL
 *  @access     SIO->BSM180.bit.VAL
 *  @brief      
 */
#define BSM180_ALL_VAL_Pos (0)
#define BSM180_ALL_VAL_Msk (0xFFFFFFUL << BSM180_ALL_VAL_Pos)

#define BSM180_BIT_VAL

#define BSM180_ALL_VAL_(x) ((x) << BSM180_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM181          VAL
 *  @access     SIO->BSM181.bit.VAL
 *  @brief      
 */
#define BSM181_ALL_VAL_Pos (0)
#define BSM181_ALL_VAL_Msk (0xFFFFFFUL << BSM181_ALL_VAL_Pos)

#define BSM181_BIT_VAL

#define BSM181_ALL_VAL_(x) ((x) << BSM181_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM182          VAL
 *  @access     SIO->BSM182.bit.VAL
 *  @brief      
 */
#define BSM182_ALL_VAL_Pos (0)
#define BSM182_ALL_VAL_Msk (0xFFFFFFUL << BSM182_ALL_VAL_Pos)

#define BSM182_BIT_VAL

#define BSM182_ALL_VAL_(x) ((x) << BSM182_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM183          VAL
 *  @access     SIO->BSM183.bit.VAL
 *  @brief      
 */
#define BSM183_ALL_VAL_Pos (0)
#define BSM183_ALL_VAL_Msk (0xFFFFFFUL << BSM183_ALL_VAL_Pos)

#define BSM183_BIT_VAL

#define BSM183_ALL_VAL_(x) ((x) << BSM183_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM184          VAL
 *  @access     SIO->BSM184.bit.VAL
 *  @brief      
 */
#define BSM184_ALL_VAL_Pos (0)
#define BSM184_ALL_VAL_Msk (0xFFFFFFUL << BSM184_ALL_VAL_Pos)

#define BSM184_BIT_VAL

#define BSM184_ALL_VAL_(x) ((x) << BSM184_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM185          VAL
 *  @access     SIO->BSM185.bit.VAL
 *  @brief      
 */
#define BSM185_ALL_VAL_Pos (0)
#define BSM185_ALL_VAL_Msk (0xFFFFFFUL << BSM185_ALL_VAL_Pos)

#define BSM185_BIT_VAL

#define BSM185_ALL_VAL_(x) ((x) << BSM185_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM186          VAL
 *  @access     SIO->BSM186.bit.VAL
 *  @brief      
 */
#define BSM186_ALL_VAL_Pos (0)
#define BSM186_ALL_VAL_Msk (0xFFFFFFUL << BSM186_ALL_VAL_Pos)

#define BSM186_BIT_VAL

#define BSM186_ALL_VAL_(x) ((x) << BSM186_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM187          VAL
 *  @access     SIO->BSM187.bit.VAL
 *  @brief      
 */
#define BSM187_ALL_VAL_Pos (0)
#define BSM187_ALL_VAL_Msk (0xFFFFFFUL << BSM187_ALL_VAL_Pos)

#define BSM187_BIT_VAL

#define BSM187_ALL_VAL_(x) ((x) << BSM187_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM188          VAL
 *  @access     SIO->BSM188.bit.VAL
 *  @brief      
 */
#define BSM188_ALL_VAL_Pos (0)
#define BSM188_ALL_VAL_Msk (0xFFFFFFUL << BSM188_ALL_VAL_Pos)

#define BSM188_BIT_VAL

#define BSM188_ALL_VAL_(x) ((x) << BSM188_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM189          VAL
 *  @access     SIO->BSM189.bit.VAL
 *  @brief      
 */
#define BSM189_ALL_VAL_Pos (0)
#define BSM189_ALL_VAL_Msk (0xFFFFFFUL << BSM189_ALL_VAL_Pos)

#define BSM189_BIT_VAL

#define BSM189_ALL_VAL_(x) ((x) << BSM189_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM190          VAL
 *  @access     SIO->BSM190.bit.VAL
 *  @brief      
 */
#define BSM190_ALL_VAL_Pos (0)
#define BSM190_ALL_VAL_Msk (0xFFFFFFUL << BSM190_ALL_VAL_Pos)

#define BSM190_BIT_VAL

#define BSM190_ALL_VAL_(x) ((x) << BSM190_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM191          VAL
 *  @access     SIO->BSM191.bit.VAL
 *  @brief      
 */
#define BSM191_ALL_VAL_Pos (0)
#define BSM191_ALL_VAL_Msk (0xFFFFFFUL << BSM191_ALL_VAL_Pos)

#define BSM191_BIT_VAL

#define BSM191_ALL_VAL_(x) ((x) << BSM191_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM192          VAL
 *  @access     SIO->BSM192.bit.VAL
 *  @brief      
 */
#define BSM192_ALL_VAL_Pos (0)
#define BSM192_ALL_VAL_Msk (0xFFFFFFUL << BSM192_ALL_VAL_Pos)

#define BSM192_BIT_VAL

#define BSM192_ALL_VAL_(x) ((x) << BSM192_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM193          VAL
 *  @access     SIO->BSM193.bit.VAL
 *  @brief      
 */
#define BSM193_ALL_VAL_Pos (0)
#define BSM193_ALL_VAL_Msk (0xFFFFFFUL << BSM193_ALL_VAL_Pos)

#define BSM193_BIT_VAL

#define BSM193_ALL_VAL_(x) ((x) << BSM193_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM194          VAL
 *  @access     SIO->BSM194.bit.VAL
 *  @brief      
 */
#define BSM194_ALL_VAL_Pos (0)
#define BSM194_ALL_VAL_Msk (0xFFFFFFUL << BSM194_ALL_VAL_Pos)

#define BSM194_BIT_VAL

#define BSM194_ALL_VAL_(x) ((x) << BSM194_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM195          VAL
 *  @access     SIO->BSM195.bit.VAL
 *  @brief      
 */
#define BSM195_ALL_VAL_Pos (0)
#define BSM195_ALL_VAL_Msk (0xFFFFFFUL << BSM195_ALL_VAL_Pos)

#define BSM195_BIT_VAL

#define BSM195_ALL_VAL_(x) ((x) << BSM195_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM196          VAL
 *  @access     SIO->BSM196.bit.VAL
 *  @brief      
 */
#define BSM196_ALL_VAL_Pos (0)
#define BSM196_ALL_VAL_Msk (0xFFFFFFUL << BSM196_ALL_VAL_Pos)

#define BSM196_BIT_VAL

#define BSM196_ALL_VAL_(x) ((x) << BSM196_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM197          VAL
 *  @access     SIO->BSM197.bit.VAL
 *  @brief      
 */
#define BSM197_ALL_VAL_Pos (0)
#define BSM197_ALL_VAL_Msk (0xFFFFFFUL << BSM197_ALL_VAL_Pos)

#define BSM197_BIT_VAL

#define BSM197_ALL_VAL_(x) ((x) << BSM197_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM198          VAL
 *  @access     SIO->BSM198.bit.VAL
 *  @brief      
 */
#define BSM198_ALL_VAL_Pos (0)
#define BSM198_ALL_VAL_Msk (0xFFFFFFUL << BSM198_ALL_VAL_Pos)

#define BSM198_BIT_VAL

#define BSM198_ALL_VAL_(x) ((x) << BSM198_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM199          VAL
 *  @access     SIO->BSM199.bit.VAL
 *  @brief      
 */
#define BSM199_ALL_VAL_Pos (0)
#define BSM199_ALL_VAL_Msk (0xFFFFFFUL << BSM199_ALL_VAL_Pos)

#define BSM199_BIT_VAL

#define BSM199_ALL_VAL_(x) ((x) << BSM199_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM200          VAL
 *  @access     SIO->BSM200.bit.VAL
 *  @brief      
 */
#define BSM200_ALL_VAL_Pos (0)
#define BSM200_ALL_VAL_Msk (0xFFFFFFUL << BSM200_ALL_VAL_Pos)

#define BSM200_BIT_VAL

#define BSM200_ALL_VAL_(x) ((x) << BSM200_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM201          VAL
 *  @access     SIO->BSM201.bit.VAL
 *  @brief      
 */
#define BSM201_ALL_VAL_Pos (0)
#define BSM201_ALL_VAL_Msk (0xFFFFFFUL << BSM201_ALL_VAL_Pos)

#define BSM201_BIT_VAL

#define BSM201_ALL_VAL_(x) ((x) << BSM201_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM202          VAL
 *  @access     SIO->BSM202.bit.VAL
 *  @brief      
 */
#define BSM202_ALL_VAL_Pos (0)
#define BSM202_ALL_VAL_Msk (0xFFFFFFUL << BSM202_ALL_VAL_Pos)

#define BSM202_BIT_VAL

#define BSM202_ALL_VAL_(x) ((x) << BSM202_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM203          VAL
 *  @access     SIO->BSM203.bit.VAL
 *  @brief      
 */
#define BSM203_ALL_VAL_Pos (0)
#define BSM203_ALL_VAL_Msk (0xFFFFFFUL << BSM203_ALL_VAL_Pos)

#define BSM203_BIT_VAL

#define BSM203_ALL_VAL_(x) ((x) << BSM203_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM204          VAL
 *  @access     SIO->BSM204.bit.VAL
 *  @brief      
 */
#define BSM204_ALL_VAL_Pos (0)
#define BSM204_ALL_VAL_Msk (0xFFFFFFUL << BSM204_ALL_VAL_Pos)

#define BSM204_BIT_VAL

#define BSM204_ALL_VAL_(x) ((x) << BSM204_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM205          VAL
 *  @access     SIO->BSM205.bit.VAL
 *  @brief      
 */
#define BSM205_ALL_VAL_Pos (0)
#define BSM205_ALL_VAL_Msk (0xFFFFFFUL << BSM205_ALL_VAL_Pos)

#define BSM205_BIT_VAL

#define BSM205_ALL_VAL_(x) ((x) << BSM205_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM206          VAL
 *  @access     SIO->BSM206.bit.VAL
 *  @brief      
 */
#define BSM206_ALL_VAL_Pos (0)
#define BSM206_ALL_VAL_Msk (0xFFFFFFUL << BSM206_ALL_VAL_Pos)

#define BSM206_BIT_VAL

#define BSM206_ALL_VAL_(x) ((x) << BSM206_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM207          VAL
 *  @access     SIO->BSM207.bit.VAL
 *  @brief      
 */
#define BSM207_ALL_VAL_Pos (0)
#define BSM207_ALL_VAL_Msk (0xFFFFFFUL << BSM207_ALL_VAL_Pos)

#define BSM207_BIT_VAL

#define BSM207_ALL_VAL_(x) ((x) << BSM207_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM208          VAL
 *  @access     SIO->BSM208.bit.VAL
 *  @brief      
 */
#define BSM208_ALL_VAL_Pos (0)
#define BSM208_ALL_VAL_Msk (0xFFFFFFUL << BSM208_ALL_VAL_Pos)

#define BSM208_BIT_VAL

#define BSM208_ALL_VAL_(x) ((x) << BSM208_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM209          VAL
 *  @access     SIO->BSM209.bit.VAL
 *  @brief      
 */
#define BSM209_ALL_VAL_Pos (0)
#define BSM209_ALL_VAL_Msk (0xFFFFFFUL << BSM209_ALL_VAL_Pos)

#define BSM209_BIT_VAL

#define BSM209_ALL_VAL_(x) ((x) << BSM209_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM210          VAL
 *  @access     SIO->BSM210.bit.VAL
 *  @brief      
 */
#define BSM210_ALL_VAL_Pos (0)
#define BSM210_ALL_VAL_Msk (0xFFFFFFUL << BSM210_ALL_VAL_Pos)

#define BSM210_BIT_VAL

#define BSM210_ALL_VAL_(x) ((x) << BSM210_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM211          VAL
 *  @access     SIO->BSM211.bit.VAL
 *  @brief      
 */
#define BSM211_ALL_VAL_Pos (0)
#define BSM211_ALL_VAL_Msk (0xFFFFFFUL << BSM211_ALL_VAL_Pos)

#define BSM211_BIT_VAL

#define BSM211_ALL_VAL_(x) ((x) << BSM211_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM212          VAL
 *  @access     SIO->BSM212.bit.VAL
 *  @brief      
 */
#define BSM212_ALL_VAL_Pos (0)
#define BSM212_ALL_VAL_Msk (0xFFFFFFUL << BSM212_ALL_VAL_Pos)

#define BSM212_BIT_VAL

#define BSM212_ALL_VAL_(x) ((x) << BSM212_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM213          VAL
 *  @access     SIO->BSM213.bit.VAL
 *  @brief      
 */
#define BSM213_ALL_VAL_Pos (0)
#define BSM213_ALL_VAL_Msk (0xFFFFFFUL << BSM213_ALL_VAL_Pos)

#define BSM213_BIT_VAL

#define BSM213_ALL_VAL_(x) ((x) << BSM213_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM214          VAL
 *  @access     SIO->BSM214.bit.VAL
 *  @brief      
 */
#define BSM214_ALL_VAL_Pos (0)
#define BSM214_ALL_VAL_Msk (0xFFFFFFUL << BSM214_ALL_VAL_Pos)

#define BSM214_BIT_VAL

#define BSM214_ALL_VAL_(x) ((x) << BSM214_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM215          VAL
 *  @access     SIO->BSM215.bit.VAL
 *  @brief      
 */
#define BSM215_ALL_VAL_Pos (0)
#define BSM215_ALL_VAL_Msk (0xFFFFFFUL << BSM215_ALL_VAL_Pos)

#define BSM215_BIT_VAL

#define BSM215_ALL_VAL_(x) ((x) << BSM215_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM216          VAL
 *  @access     SIO->BSM216.bit.VAL
 *  @brief      
 */
#define BSM216_ALL_VAL_Pos (0)
#define BSM216_ALL_VAL_Msk (0xFFFFFFUL << BSM216_ALL_VAL_Pos)

#define BSM216_BIT_VAL

#define BSM216_ALL_VAL_(x) ((x) << BSM216_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM217          VAL
 *  @access     SIO->BSM217.bit.VAL
 *  @brief      
 */
#define BSM217_ALL_VAL_Pos (0)
#define BSM217_ALL_VAL_Msk (0xFFFFFFUL << BSM217_ALL_VAL_Pos)

#define BSM217_BIT_VAL

#define BSM217_ALL_VAL_(x) ((x) << BSM217_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM218          VAL
 *  @access     SIO->BSM218.bit.VAL
 *  @brief      
 */
#define BSM218_ALL_VAL_Pos (0)
#define BSM218_ALL_VAL_Msk (0xFFFFFFUL << BSM218_ALL_VAL_Pos)

#define BSM218_BIT_VAL

#define BSM218_ALL_VAL_(x) ((x) << BSM218_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM219          VAL
 *  @access     SIO->BSM219.bit.VAL
 *  @brief      
 */
#define BSM219_ALL_VAL_Pos (0)
#define BSM219_ALL_VAL_Msk (0xFFFFFFUL << BSM219_ALL_VAL_Pos)

#define BSM219_BIT_VAL

#define BSM219_ALL_VAL_(x) ((x) << BSM219_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM220          VAL
 *  @access     SIO->BSM220.bit.VAL
 *  @brief      
 */
#define BSM220_ALL_VAL_Pos (0)
#define BSM220_ALL_VAL_Msk (0xFFFFFFUL << BSM220_ALL_VAL_Pos)

#define BSM220_BIT_VAL

#define BSM220_ALL_VAL_(x) ((x) << BSM220_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM221          VAL
 *  @access     SIO->BSM221.bit.VAL
 *  @brief      
 */
#define BSM221_ALL_VAL_Pos (0)
#define BSM221_ALL_VAL_Msk (0xFFFFFFUL << BSM221_ALL_VAL_Pos)

#define BSM221_BIT_VAL

#define BSM221_ALL_VAL_(x) ((x) << BSM221_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM222          VAL
 *  @access     SIO->BSM222.bit.VAL
 *  @brief      
 */
#define BSM222_ALL_VAL_Pos (0)
#define BSM222_ALL_VAL_Msk (0xFFFFFFUL << BSM222_ALL_VAL_Pos)

#define BSM222_BIT_VAL

#define BSM222_ALL_VAL_(x) ((x) << BSM222_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM223          VAL
 *  @access     SIO->BSM223.bit.VAL
 *  @brief      
 */
#define BSM223_ALL_VAL_Pos (0)
#define BSM223_ALL_VAL_Msk (0xFFFFFFUL << BSM223_ALL_VAL_Pos)

#define BSM223_BIT_VAL

#define BSM223_ALL_VAL_(x) ((x) << BSM223_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM224          VAL
 *  @access     SIO->BSM224.bit.VAL
 *  @brief      
 */
#define BSM224_ALL_VAL_Pos (0)
#define BSM224_ALL_VAL_Msk (0xFFFFFFUL << BSM224_ALL_VAL_Pos)

#define BSM224_BIT_VAL

#define BSM224_ALL_VAL_(x) ((x) << BSM224_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM225          VAL
 *  @access     SIO->BSM225.bit.VAL
 *  @brief      
 */
#define BSM225_ALL_VAL_Pos (0)
#define BSM225_ALL_VAL_Msk (0xFFFFFFUL << BSM225_ALL_VAL_Pos)

#define BSM225_BIT_VAL

#define BSM225_ALL_VAL_(x) ((x) << BSM225_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM226          VAL
 *  @access     SIO->BSM226.bit.VAL
 *  @brief      
 */
#define BSM226_ALL_VAL_Pos (0)
#define BSM226_ALL_VAL_Msk (0xFFFFFFUL << BSM226_ALL_VAL_Pos)

#define BSM226_BIT_VAL

#define BSM226_ALL_VAL_(x) ((x) << BSM226_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM227          VAL
 *  @access     SIO->BSM227.bit.VAL
 *  @brief      
 */
#define BSM227_ALL_VAL_Pos (0)
#define BSM227_ALL_VAL_Msk (0xFFFFFFUL << BSM227_ALL_VAL_Pos)

#define BSM227_BIT_VAL

#define BSM227_ALL_VAL_(x) ((x) << BSM227_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM228          VAL
 *  @access     SIO->BSM228.bit.VAL
 *  @brief      
 */
#define BSM228_ALL_VAL_Pos (0)
#define BSM228_ALL_VAL_Msk (0xFFFFFFUL << BSM228_ALL_VAL_Pos)

#define BSM228_BIT_VAL

#define BSM228_ALL_VAL_(x) ((x) << BSM228_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM229          VAL
 *  @access     SIO->BSM229.bit.VAL
 *  @brief      
 */
#define BSM229_ALL_VAL_Pos (0)
#define BSM229_ALL_VAL_Msk (0xFFFFFFUL << BSM229_ALL_VAL_Pos)

#define BSM229_BIT_VAL

#define BSM229_ALL_VAL_(x) ((x) << BSM229_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM230          VAL
 *  @access     SIO->BSM230.bit.VAL
 *  @brief      
 */
#define BSM230_ALL_VAL_Pos (0)
#define BSM230_ALL_VAL_Msk (0xFFFFFFUL << BSM230_ALL_VAL_Pos)

#define BSM230_BIT_VAL

#define BSM230_ALL_VAL_(x) ((x) << BSM230_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM231          VAL
 *  @access     SIO->BSM231.bit.VAL
 *  @brief      
 */
#define BSM231_ALL_VAL_Pos (0)
#define BSM231_ALL_VAL_Msk (0xFFFFFFUL << BSM231_ALL_VAL_Pos)

#define BSM231_BIT_VAL

#define BSM231_ALL_VAL_(x) ((x) << BSM231_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM232          VAL
 *  @access     SIO->BSM232.bit.VAL
 *  @brief      
 */
#define BSM232_ALL_VAL_Pos (0)
#define BSM232_ALL_VAL_Msk (0xFFFFFFUL << BSM232_ALL_VAL_Pos)

#define BSM232_BIT_VAL

#define BSM232_ALL_VAL_(x) ((x) << BSM232_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM233          VAL
 *  @access     SIO->BSM233.bit.VAL
 *  @brief      
 */
#define BSM233_ALL_VAL_Pos (0)
#define BSM233_ALL_VAL_Msk (0xFFFFFFUL << BSM233_ALL_VAL_Pos)

#define BSM233_BIT_VAL

#define BSM233_ALL_VAL_(x) ((x) << BSM233_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM234          VAL
 *  @access     SIO->BSM234.bit.VAL
 *  @brief      
 */
#define BSM234_ALL_VAL_Pos (0)
#define BSM234_ALL_VAL_Msk (0xFFFFFFUL << BSM234_ALL_VAL_Pos)

#define BSM234_BIT_VAL

#define BSM234_ALL_VAL_(x) ((x) << BSM234_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM235          VAL
 *  @access     SIO->BSM235.bit.VAL
 *  @brief      
 */
#define BSM235_ALL_VAL_Pos (0)
#define BSM235_ALL_VAL_Msk (0xFFFFFFUL << BSM235_ALL_VAL_Pos)

#define BSM235_BIT_VAL

#define BSM235_ALL_VAL_(x) ((x) << BSM235_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM236          VAL
 *  @access     SIO->BSM236.bit.VAL
 *  @brief      
 */
#define BSM236_ALL_VAL_Pos (0)
#define BSM236_ALL_VAL_Msk (0xFFFFFFUL << BSM236_ALL_VAL_Pos)

#define BSM236_BIT_VAL

#define BSM236_ALL_VAL_(x) ((x) << BSM236_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM237          VAL
 *  @access     SIO->BSM237.bit.VAL
 *  @brief      
 */
#define BSM237_ALL_VAL_Pos (0)
#define BSM237_ALL_VAL_Msk (0xFFFFFFUL << BSM237_ALL_VAL_Pos)

#define BSM237_BIT_VAL

#define BSM237_ALL_VAL_(x) ((x) << BSM237_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM238          VAL
 *  @access     SIO->BSM238.bit.VAL
 *  @brief      
 */
#define BSM238_ALL_VAL_Pos (0)
#define BSM238_ALL_VAL_Msk (0xFFFFFFUL << BSM238_ALL_VAL_Pos)

#define BSM238_BIT_VAL

#define BSM238_ALL_VAL_(x) ((x) << BSM238_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM239          VAL
 *  @access     SIO->BSM239.bit.VAL
 *  @brief      
 */
#define BSM239_ALL_VAL_Pos (0)
#define BSM239_ALL_VAL_Msk (0xFFFFFFUL << BSM239_ALL_VAL_Pos)

#define BSM239_BIT_VAL

#define BSM239_ALL_VAL_(x) ((x) << BSM239_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM240          VAL
 *  @access     SIO->BSM240.bit.VAL
 *  @brief      
 */
#define BSM240_ALL_VAL_Pos (0)
#define BSM240_ALL_VAL_Msk (0xFFFFFFUL << BSM240_ALL_VAL_Pos)

#define BSM240_BIT_VAL

#define BSM240_ALL_VAL_(x) ((x) << BSM240_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM241          VAL
 *  @access     SIO->BSM241.bit.VAL
 *  @brief      
 */
#define BSM241_ALL_VAL_Pos (0)
#define BSM241_ALL_VAL_Msk (0xFFFFFFUL << BSM241_ALL_VAL_Pos)

#define BSM241_BIT_VAL

#define BSM241_ALL_VAL_(x) ((x) << BSM241_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM242          VAL
 *  @access     SIO->BSM242.bit.VAL
 *  @brief      
 */
#define BSM242_ALL_VAL_Pos (0)
#define BSM242_ALL_VAL_Msk (0xFFFFFFUL << BSM242_ALL_VAL_Pos)

#define BSM242_BIT_VAL

#define BSM242_ALL_VAL_(x) ((x) << BSM242_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM243          VAL
 *  @access     SIO->BSM243.bit.VAL
 *  @brief      
 */
#define BSM243_ALL_VAL_Pos (0)
#define BSM243_ALL_VAL_Msk (0xFFFFFFUL << BSM243_ALL_VAL_Pos)

#define BSM243_BIT_VAL

#define BSM243_ALL_VAL_(x) ((x) << BSM243_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM244          VAL
 *  @access     SIO->BSM244.bit.VAL
 *  @brief      
 */
#define BSM244_ALL_VAL_Pos (0)
#define BSM244_ALL_VAL_Msk (0xFFFFFFUL << BSM244_ALL_VAL_Pos)

#define BSM244_BIT_VAL

#define BSM244_ALL_VAL_(x) ((x) << BSM244_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM245          VAL
 *  @access     SIO->BSM245.bit.VAL
 *  @brief      
 */
#define BSM245_ALL_VAL_Pos (0)
#define BSM245_ALL_VAL_Msk (0xFFFFFFUL << BSM245_ALL_VAL_Pos)

#define BSM245_BIT_VAL

#define BSM245_ALL_VAL_(x) ((x) << BSM245_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM246          VAL
 *  @access     SIO->BSM246.bit.VAL
 *  @brief      
 */
#define BSM246_ALL_VAL_Pos (0)
#define BSM246_ALL_VAL_Msk (0xFFFFFFUL << BSM246_ALL_VAL_Pos)

#define BSM246_BIT_VAL

#define BSM246_ALL_VAL_(x) ((x) << BSM246_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM247          VAL
 *  @access     SIO->BSM247.bit.VAL
 *  @brief      
 */
#define BSM247_ALL_VAL_Pos (0)
#define BSM247_ALL_VAL_Msk (0xFFFFFFUL << BSM247_ALL_VAL_Pos)

#define BSM247_BIT_VAL

#define BSM247_ALL_VAL_(x) ((x) << BSM247_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM248          VAL
 *  @access     SIO->BSM248.bit.VAL
 *  @brief      
 */
#define BSM248_ALL_VAL_Pos (0)
#define BSM248_ALL_VAL_Msk (0xFFFFFFUL << BSM248_ALL_VAL_Pos)

#define BSM248_BIT_VAL

#define BSM248_ALL_VAL_(x) ((x) << BSM248_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM249          VAL
 *  @access     SIO->BSM249.bit.VAL
 *  @brief      
 */
#define BSM249_ALL_VAL_Pos (0)
#define BSM249_ALL_VAL_Msk (0xFFFFFFUL << BSM249_ALL_VAL_Pos)

#define BSM249_BIT_VAL

#define BSM249_ALL_VAL_(x) ((x) << BSM249_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM250          VAL
 *  @access     SIO->BSM250.bit.VAL
 *  @brief      
 */
#define BSM250_ALL_VAL_Pos (0)
#define BSM250_ALL_VAL_Msk (0xFFFFFFUL << BSM250_ALL_VAL_Pos)

#define BSM250_BIT_VAL

#define BSM250_ALL_VAL_(x) ((x) << BSM250_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM251          VAL
 *  @access     SIO->BSM251.bit.VAL
 *  @brief      
 */
#define BSM251_ALL_VAL_Pos (0)
#define BSM251_ALL_VAL_Msk (0xFFFFFFUL << BSM251_ALL_VAL_Pos)

#define BSM251_BIT_VAL

#define BSM251_ALL_VAL_(x) ((x) << BSM251_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM252          VAL
 *  @access     SIO->BSM252.bit.VAL
 *  @brief      
 */
#define BSM252_ALL_VAL_Pos (0)
#define BSM252_ALL_VAL_Msk (0xFFFFFFUL << BSM252_ALL_VAL_Pos)

#define BSM252_BIT_VAL

#define BSM252_ALL_VAL_(x) ((x) << BSM252_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM253          VAL
 *  @access     SIO->BSM253.bit.VAL
 *  @brief      
 */
#define BSM253_ALL_VAL_Pos (0)
#define BSM253_ALL_VAL_Msk (0xFFFFFFUL << BSM253_ALL_VAL_Pos)

#define BSM253_BIT_VAL

#define BSM253_ALL_VAL_(x) ((x) << BSM253_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM254          VAL
 *  @access     SIO->BSM254.bit.VAL
 *  @brief      
 */
#define BSM254_ALL_VAL_Pos (0)
#define BSM254_ALL_VAL_Msk (0xFFFFFFUL << BSM254_ALL_VAL_Pos)

#define BSM254_BIT_VAL

#define BSM254_ALL_VAL_(x) ((x) << BSM254_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM255          VAL
 *  @access     SIO->BSM255.bit.VAL
 *  @brief      
 */
#define BSM255_ALL_VAL_Pos (0)
#define BSM255_ALL_VAL_Msk (0xFFFFFFUL << BSM255_ALL_VAL_Pos)

#define BSM255_BIT_VAL

#define BSM255_ALL_VAL_(x) ((x) << BSM255_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM256          VAL
 *  @access     SIO->BSM256.bit.VAL
 *  @brief      
 */
#define BSM256_ALL_VAL_Pos (0)
#define BSM256_ALL_VAL_Msk (0xFFFFFFUL << BSM256_ALL_VAL_Pos)

#define BSM256_BIT_VAL

#define BSM256_ALL_VAL_(x) ((x) << BSM256_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM257          VAL
 *  @access     SIO->BSM257.bit.VAL
 *  @brief      
 */
#define BSM257_ALL_VAL_Pos (0)
#define BSM257_ALL_VAL_Msk (0xFFFFFFUL << BSM257_ALL_VAL_Pos)

#define BSM257_BIT_VAL

#define BSM257_ALL_VAL_(x) ((x) << BSM257_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM258          VAL
 *  @access     SIO->BSM258.bit.VAL
 *  @brief      
 */
#define BSM258_ALL_VAL_Pos (0)
#define BSM258_ALL_VAL_Msk (0xFFFFFFUL << BSM258_ALL_VAL_Pos)

#define BSM258_BIT_VAL

#define BSM258_ALL_VAL_(x) ((x) << BSM258_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM259          VAL
 *  @access     SIO->BSM259.bit.VAL
 *  @brief      
 */
#define BSM259_ALL_VAL_Pos (0)
#define BSM259_ALL_VAL_Msk (0xFFFFFFUL << BSM259_ALL_VAL_Pos)

#define BSM259_BIT_VAL

#define BSM259_ALL_VAL_(x) ((x) << BSM259_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM260          VAL
 *  @access     SIO->BSM260.bit.VAL
 *  @brief      
 */
#define BSM260_ALL_VAL_Pos (0)
#define BSM260_ALL_VAL_Msk (0xFFFFFFUL << BSM260_ALL_VAL_Pos)

#define BSM260_BIT_VAL

#define BSM260_ALL_VAL_(x) ((x) << BSM260_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM261          VAL
 *  @access     SIO->BSM261.bit.VAL
 *  @brief      
 */
#define BSM261_ALL_VAL_Pos (0)
#define BSM261_ALL_VAL_Msk (0xFFFFFFUL << BSM261_ALL_VAL_Pos)

#define BSM261_BIT_VAL

#define BSM261_ALL_VAL_(x) ((x) << BSM261_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM262          VAL
 *  @access     SIO->BSM262.bit.VAL
 *  @brief      
 */
#define BSM262_ALL_VAL_Pos (0)
#define BSM262_ALL_VAL_Msk (0xFFFFFFUL << BSM262_ALL_VAL_Pos)

#define BSM262_BIT_VAL

#define BSM262_ALL_VAL_(x) ((x) << BSM262_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM263          VAL
 *  @access     SIO->BSM263.bit.VAL
 *  @brief      
 */
#define BSM263_ALL_VAL_Pos (0)
#define BSM263_ALL_VAL_Msk (0xFFFFFFUL << BSM263_ALL_VAL_Pos)

#define BSM263_BIT_VAL

#define BSM263_ALL_VAL_(x) ((x) << BSM263_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM264          VAL
 *  @access     SIO->BSM264.bit.VAL
 *  @brief      
 */
#define BSM264_ALL_VAL_Pos (0)
#define BSM264_ALL_VAL_Msk (0xFFFFFFUL << BSM264_ALL_VAL_Pos)

#define BSM264_BIT_VAL

#define BSM264_ALL_VAL_(x) ((x) << BSM264_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM265          VAL
 *  @access     SIO->BSM265.bit.VAL
 *  @brief      
 */
#define BSM265_ALL_VAL_Pos (0)
#define BSM265_ALL_VAL_Msk (0xFFFFFFUL << BSM265_ALL_VAL_Pos)

#define BSM265_BIT_VAL

#define BSM265_ALL_VAL_(x) ((x) << BSM265_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM266          VAL
 *  @access     SIO->BSM266.bit.VAL
 *  @brief      
 */
#define BSM266_ALL_VAL_Pos (0)
#define BSM266_ALL_VAL_Msk (0xFFFFFFUL << BSM266_ALL_VAL_Pos)

#define BSM266_BIT_VAL

#define BSM266_ALL_VAL_(x) ((x) << BSM266_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM267          VAL
 *  @access     SIO->BSM267.bit.VAL
 *  @brief      
 */
#define BSM267_ALL_VAL_Pos (0)
#define BSM267_ALL_VAL_Msk (0xFFFFFFUL << BSM267_ALL_VAL_Pos)

#define BSM267_BIT_VAL

#define BSM267_ALL_VAL_(x) ((x) << BSM267_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM268          VAL
 *  @access     SIO->BSM268.bit.VAL
 *  @brief      
 */
#define BSM268_ALL_VAL_Pos (0)
#define BSM268_ALL_VAL_Msk (0xFFFFFFUL << BSM268_ALL_VAL_Pos)

#define BSM268_BIT_VAL

#define BSM268_ALL_VAL_(x) ((x) << BSM268_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM269          VAL
 *  @access     SIO->BSM269.bit.VAL
 *  @brief      
 */
#define BSM269_ALL_VAL_Pos (0)
#define BSM269_ALL_VAL_Msk (0xFFFFFFUL << BSM269_ALL_VAL_Pos)

#define BSM269_BIT_VAL

#define BSM269_ALL_VAL_(x) ((x) << BSM269_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM270          VAL
 *  @access     SIO->BSM270.bit.VAL
 *  @brief      
 */
#define BSM270_ALL_VAL_Pos (0)
#define BSM270_ALL_VAL_Msk (0xFFFFFFUL << BSM270_ALL_VAL_Pos)

#define BSM270_BIT_VAL

#define BSM270_ALL_VAL_(x) ((x) << BSM270_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM271          VAL
 *  @access     SIO->BSM271.bit.VAL
 *  @brief      
 */
#define BSM271_ALL_VAL_Pos (0)
#define BSM271_ALL_VAL_Msk (0xFFFFFFUL << BSM271_ALL_VAL_Pos)

#define BSM271_BIT_VAL

#define BSM271_ALL_VAL_(x) ((x) << BSM271_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM272          VAL
 *  @access     SIO->BSM272.bit.VAL
 *  @brief      
 */
#define BSM272_ALL_VAL_Pos (0)
#define BSM272_ALL_VAL_Msk (0xFFFFFFUL << BSM272_ALL_VAL_Pos)

#define BSM272_BIT_VAL

#define BSM272_ALL_VAL_(x) ((x) << BSM272_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM273          VAL
 *  @access     SIO->BSM273.bit.VAL
 *  @brief      
 */
#define BSM273_ALL_VAL_Pos (0)
#define BSM273_ALL_VAL_Msk (0xFFFFFFUL << BSM273_ALL_VAL_Pos)

#define BSM273_BIT_VAL

#define BSM273_ALL_VAL_(x) ((x) << BSM273_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM274          VAL
 *  @access     SIO->BSM274.bit.VAL
 *  @brief      
 */
#define BSM274_ALL_VAL_Pos (0)
#define BSM274_ALL_VAL_Msk (0xFFFFFFUL << BSM274_ALL_VAL_Pos)

#define BSM274_BIT_VAL

#define BSM274_ALL_VAL_(x) ((x) << BSM274_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM275          VAL
 *  @access     SIO->BSM275.bit.VAL
 *  @brief      
 */
#define BSM275_ALL_VAL_Pos (0)
#define BSM275_ALL_VAL_Msk (0xFFFFFFUL << BSM275_ALL_VAL_Pos)

#define BSM275_BIT_VAL

#define BSM275_ALL_VAL_(x) ((x) << BSM275_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM276          VAL
 *  @access     SIO->BSM276.bit.VAL
 *  @brief      
 */
#define BSM276_ALL_VAL_Pos (0)
#define BSM276_ALL_VAL_Msk (0xFFFFFFUL << BSM276_ALL_VAL_Pos)

#define BSM276_BIT_VAL

#define BSM276_ALL_VAL_(x) ((x) << BSM276_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM277          VAL
 *  @access     SIO->BSM277.bit.VAL
 *  @brief      
 */
#define BSM277_ALL_VAL_Pos (0)
#define BSM277_ALL_VAL_Msk (0xFFFFFFUL << BSM277_ALL_VAL_Pos)

#define BSM277_BIT_VAL

#define BSM277_ALL_VAL_(x) ((x) << BSM277_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM278          VAL
 *  @access     SIO->BSM278.bit.VAL
 *  @brief      
 */
#define BSM278_ALL_VAL_Pos (0)
#define BSM278_ALL_VAL_Msk (0xFFFFFFUL << BSM278_ALL_VAL_Pos)

#define BSM278_BIT_VAL

#define BSM278_ALL_VAL_(x) ((x) << BSM278_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM279          VAL
 *  @access     SIO->BSM279.bit.VAL
 *  @brief      
 */
#define BSM279_ALL_VAL_Pos (0)
#define BSM279_ALL_VAL_Msk (0xFFFFFFUL << BSM279_ALL_VAL_Pos)

#define BSM279_BIT_VAL

#define BSM279_ALL_VAL_(x) ((x) << BSM279_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM280          VAL
 *  @access     SIO->BSM280.bit.VAL
 *  @brief      
 */
#define BSM280_ALL_VAL_Pos (0)
#define BSM280_ALL_VAL_Msk (0xFFFFFFUL << BSM280_ALL_VAL_Pos)

#define BSM280_BIT_VAL

#define BSM280_ALL_VAL_(x) ((x) << BSM280_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM281          VAL
 *  @access     SIO->BSM281.bit.VAL
 *  @brief      
 */
#define BSM281_ALL_VAL_Pos (0)
#define BSM281_ALL_VAL_Msk (0xFFFFFFUL << BSM281_ALL_VAL_Pos)

#define BSM281_BIT_VAL

#define BSM281_ALL_VAL_(x) ((x) << BSM281_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM282          VAL
 *  @access     SIO->BSM282.bit.VAL
 *  @brief      
 */
#define BSM282_ALL_VAL_Pos (0)
#define BSM282_ALL_VAL_Msk (0xFFFFFFUL << BSM282_ALL_VAL_Pos)

#define BSM282_BIT_VAL

#define BSM282_ALL_VAL_(x) ((x) << BSM282_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM283          VAL
 *  @access     SIO->BSM283.bit.VAL
 *  @brief      
 */
#define BSM283_ALL_VAL_Pos (0)
#define BSM283_ALL_VAL_Msk (0xFFFFFFUL << BSM283_ALL_VAL_Pos)

#define BSM283_BIT_VAL

#define BSM283_ALL_VAL_(x) ((x) << BSM283_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM284          VAL
 *  @access     SIO->BSM284.bit.VAL
 *  @brief      
 */
#define BSM284_ALL_VAL_Pos (0)
#define BSM284_ALL_VAL_Msk (0xFFFFFFUL << BSM284_ALL_VAL_Pos)

#define BSM284_BIT_VAL

#define BSM284_ALL_VAL_(x) ((x) << BSM284_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM285          VAL
 *  @access     SIO->BSM285.bit.VAL
 *  @brief      
 */
#define BSM285_ALL_VAL_Pos (0)
#define BSM285_ALL_VAL_Msk (0xFFFFFFUL << BSM285_ALL_VAL_Pos)

#define BSM285_BIT_VAL

#define BSM285_ALL_VAL_(x) ((x) << BSM285_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM286          VAL
 *  @access     SIO->BSM286.bit.VAL
 *  @brief      
 */
#define BSM286_ALL_VAL_Pos (0)
#define BSM286_ALL_VAL_Msk (0xFFFFFFUL << BSM286_ALL_VAL_Pos)

#define BSM286_BIT_VAL

#define BSM286_ALL_VAL_(x) ((x) << BSM286_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM287          VAL
 *  @access     SIO->BSM287.bit.VAL
 *  @brief      
 */
#define BSM287_ALL_VAL_Pos (0)
#define BSM287_ALL_VAL_Msk (0xFFFFFFUL << BSM287_ALL_VAL_Pos)

#define BSM287_BIT_VAL

#define BSM287_ALL_VAL_(x) ((x) << BSM287_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM288          VAL
 *  @access     SIO->BSM288.bit.VAL
 *  @brief      
 */
#define BSM288_ALL_VAL_Pos (0)
#define BSM288_ALL_VAL_Msk (0xFFFFFFUL << BSM288_ALL_VAL_Pos)

#define BSM288_BIT_VAL

#define BSM288_ALL_VAL_(x) ((x) << BSM288_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM289          VAL
 *  @access     SIO->BSM289.bit.VAL
 *  @brief      
 */
#define BSM289_ALL_VAL_Pos (0)
#define BSM289_ALL_VAL_Msk (0xFFFFFFUL << BSM289_ALL_VAL_Pos)

#define BSM289_BIT_VAL

#define BSM289_ALL_VAL_(x) ((x) << BSM289_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM290          VAL
 *  @access     SIO->BSM290.bit.VAL
 *  @brief      
 */
#define BSM290_ALL_VAL_Pos (0)
#define BSM290_ALL_VAL_Msk (0xFFFFFFUL << BSM290_ALL_VAL_Pos)

#define BSM290_BIT_VAL

#define BSM290_ALL_VAL_(x) ((x) << BSM290_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM291          VAL
 *  @access     SIO->BSM291.bit.VAL
 *  @brief      
 */
#define BSM291_ALL_VAL_Pos (0)
#define BSM291_ALL_VAL_Msk (0xFFFFFFUL << BSM291_ALL_VAL_Pos)

#define BSM291_BIT_VAL

#define BSM291_ALL_VAL_(x) ((x) << BSM291_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM292          VAL
 *  @access     SIO->BSM292.bit.VAL
 *  @brief      
 */
#define BSM292_ALL_VAL_Pos (0)
#define BSM292_ALL_VAL_Msk (0xFFFFFFUL << BSM292_ALL_VAL_Pos)

#define BSM292_BIT_VAL

#define BSM292_ALL_VAL_(x) ((x) << BSM292_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM293          VAL
 *  @access     SIO->BSM293.bit.VAL
 *  @brief      
 */
#define BSM293_ALL_VAL_Pos (0)
#define BSM293_ALL_VAL_Msk (0xFFFFFFUL << BSM293_ALL_VAL_Pos)

#define BSM293_BIT_VAL

#define BSM293_ALL_VAL_(x) ((x) << BSM293_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM294          VAL
 *  @access     SIO->BSM294.bit.VAL
 *  @brief      
 */
#define BSM294_ALL_VAL_Pos (0)
#define BSM294_ALL_VAL_Msk (0xFFFFFFUL << BSM294_ALL_VAL_Pos)

#define BSM294_BIT_VAL

#define BSM294_ALL_VAL_(x) ((x) << BSM294_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM295          VAL
 *  @access     SIO->BSM295.bit.VAL
 *  @brief      
 */
#define BSM295_ALL_VAL_Pos (0)
#define BSM295_ALL_VAL_Msk (0xFFFFFFUL << BSM295_ALL_VAL_Pos)

#define BSM295_BIT_VAL

#define BSM295_ALL_VAL_(x) ((x) << BSM295_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM296          VAL
 *  @access     SIO->BSM296.bit.VAL
 *  @brief      
 */
#define BSM296_ALL_VAL_Pos (0)
#define BSM296_ALL_VAL_Msk (0xFFFFFFUL << BSM296_ALL_VAL_Pos)

#define BSM296_BIT_VAL

#define BSM296_ALL_VAL_(x) ((x) << BSM296_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM297          VAL
 *  @access     SIO->BSM297.bit.VAL
 *  @brief      
 */
#define BSM297_ALL_VAL_Pos (0)
#define BSM297_ALL_VAL_Msk (0xFFFFFFUL << BSM297_ALL_VAL_Pos)

#define BSM297_BIT_VAL

#define BSM297_ALL_VAL_(x) ((x) << BSM297_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM298          VAL
 *  @access     SIO->BSM298.bit.VAL
 *  @brief      
 */
#define BSM298_ALL_VAL_Pos (0)
#define BSM298_ALL_VAL_Msk (0xFFFFFFUL << BSM298_ALL_VAL_Pos)

#define BSM298_BIT_VAL

#define BSM298_ALL_VAL_(x) ((x) << BSM298_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM299          VAL
 *  @access     SIO->BSM299.bit.VAL
 *  @brief      
 */
#define BSM299_ALL_VAL_Pos (0)
#define BSM299_ALL_VAL_Msk (0xFFFFFFUL << BSM299_ALL_VAL_Pos)

#define BSM299_BIT_VAL

#define BSM299_ALL_VAL_(x) ((x) << BSM299_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM300          VAL
 *  @access     SIO->BSM300.bit.VAL
 *  @brief      
 */
#define BSM300_ALL_VAL_Pos (0)
#define BSM300_ALL_VAL_Msk (0xFFFFFFUL << BSM300_ALL_VAL_Pos)

#define BSM300_BIT_VAL

#define BSM300_ALL_VAL_(x) ((x) << BSM300_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM301          VAL
 *  @access     SIO->BSM301.bit.VAL
 *  @brief      
 */
#define BSM301_ALL_VAL_Pos (0)
#define BSM301_ALL_VAL_Msk (0xFFFFFFUL << BSM301_ALL_VAL_Pos)

#define BSM301_BIT_VAL

#define BSM301_ALL_VAL_(x) ((x) << BSM301_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM302          VAL
 *  @access     SIO->BSM302.bit.VAL
 *  @brief      
 */
#define BSM302_ALL_VAL_Pos (0)
#define BSM302_ALL_VAL_Msk (0xFFFFFFUL << BSM302_ALL_VAL_Pos)

#define BSM302_BIT_VAL

#define BSM302_ALL_VAL_(x) ((x) << BSM302_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM303          VAL
 *  @access     SIO->BSM303.bit.VAL
 *  @brief      
 */
#define BSM303_ALL_VAL_Pos (0)
#define BSM303_ALL_VAL_Msk (0xFFFFFFUL << BSM303_ALL_VAL_Pos)

#define BSM303_BIT_VAL

#define BSM303_ALL_VAL_(x) ((x) << BSM303_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM304          VAL
 *  @access     SIO->BSM304.bit.VAL
 *  @brief      
 */
#define BSM304_ALL_VAL_Pos (0)
#define BSM304_ALL_VAL_Msk (0xFFFFFFUL << BSM304_ALL_VAL_Pos)

#define BSM304_BIT_VAL

#define BSM304_ALL_VAL_(x) ((x) << BSM304_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM305          VAL
 *  @access     SIO->BSM305.bit.VAL
 *  @brief      
 */
#define BSM305_ALL_VAL_Pos (0)
#define BSM305_ALL_VAL_Msk (0xFFFFFFUL << BSM305_ALL_VAL_Pos)

#define BSM305_BIT_VAL

#define BSM305_ALL_VAL_(x) ((x) << BSM305_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM306          VAL
 *  @access     SIO->BSM306.bit.VAL
 *  @brief      
 */
#define BSM306_ALL_VAL_Pos (0)
#define BSM306_ALL_VAL_Msk (0xFFFFFFUL << BSM306_ALL_VAL_Pos)

#define BSM306_BIT_VAL

#define BSM306_ALL_VAL_(x) ((x) << BSM306_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM307          VAL
 *  @access     SIO->BSM307.bit.VAL
 *  @brief      
 */
#define BSM307_ALL_VAL_Pos (0)
#define BSM307_ALL_VAL_Msk (0xFFFFFFUL << BSM307_ALL_VAL_Pos)

#define BSM307_BIT_VAL

#define BSM307_ALL_VAL_(x) ((x) << BSM307_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM308          VAL
 *  @access     SIO->BSM308.bit.VAL
 *  @brief      
 */
#define BSM308_ALL_VAL_Pos (0)
#define BSM308_ALL_VAL_Msk (0xFFFFFFUL << BSM308_ALL_VAL_Pos)

#define BSM308_BIT_VAL

#define BSM308_ALL_VAL_(x) ((x) << BSM308_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM309          VAL
 *  @access     SIO->BSM309.bit.VAL
 *  @brief      
 */
#define BSM309_ALL_VAL_Pos (0)
#define BSM309_ALL_VAL_Msk (0xFFFFFFUL << BSM309_ALL_VAL_Pos)

#define BSM309_BIT_VAL

#define BSM309_ALL_VAL_(x) ((x) << BSM309_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM310          VAL
 *  @access     SIO->BSM310.bit.VAL
 *  @brief      
 */
#define BSM310_ALL_VAL_Pos (0)
#define BSM310_ALL_VAL_Msk (0xFFFFFFUL << BSM310_ALL_VAL_Pos)

#define BSM310_BIT_VAL

#define BSM310_ALL_VAL_(x) ((x) << BSM310_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM311          VAL
 *  @access     SIO->BSM311.bit.VAL
 *  @brief      
 */
#define BSM311_ALL_VAL_Pos (0)
#define BSM311_ALL_VAL_Msk (0xFFFFFFUL << BSM311_ALL_VAL_Pos)

#define BSM311_BIT_VAL

#define BSM311_ALL_VAL_(x) ((x) << BSM311_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM312          VAL
 *  @access     SIO->BSM312.bit.VAL
 *  @brief      
 */
#define BSM312_ALL_VAL_Pos (0)
#define BSM312_ALL_VAL_Msk (0xFFFFFFUL << BSM312_ALL_VAL_Pos)

#define BSM312_BIT_VAL

#define BSM312_ALL_VAL_(x) ((x) << BSM312_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM313          VAL
 *  @access     SIO->BSM313.bit.VAL
 *  @brief      
 */
#define BSM313_ALL_VAL_Pos (0)
#define BSM313_ALL_VAL_Msk (0xFFFFFFUL << BSM313_ALL_VAL_Pos)

#define BSM313_BIT_VAL

#define BSM313_ALL_VAL_(x) ((x) << BSM313_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM314          VAL
 *  @access     SIO->BSM314.bit.VAL
 *  @brief      
 */
#define BSM314_ALL_VAL_Pos (0)
#define BSM314_ALL_VAL_Msk (0xFFFFFFUL << BSM314_ALL_VAL_Pos)

#define BSM314_BIT_VAL

#define BSM314_ALL_VAL_(x) ((x) << BSM314_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM315          VAL
 *  @access     SIO->BSM315.bit.VAL
 *  @brief      
 */
#define BSM315_ALL_VAL_Pos (0)
#define BSM315_ALL_VAL_Msk (0xFFFFFFUL << BSM315_ALL_VAL_Pos)

#define BSM315_BIT_VAL

#define BSM315_ALL_VAL_(x) ((x) << BSM315_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM316          VAL
 *  @access     SIO->BSM316.bit.VAL
 *  @brief      
 */
#define BSM316_ALL_VAL_Pos (0)
#define BSM316_ALL_VAL_Msk (0xFFFFFFUL << BSM316_ALL_VAL_Pos)

#define BSM316_BIT_VAL

#define BSM316_ALL_VAL_(x) ((x) << BSM316_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM317          VAL
 *  @access     SIO->BSM317.bit.VAL
 *  @brief      
 */
#define BSM317_ALL_VAL_Pos (0)
#define BSM317_ALL_VAL_Msk (0xFFFFFFUL << BSM317_ALL_VAL_Pos)

#define BSM317_BIT_VAL

#define BSM317_ALL_VAL_(x) ((x) << BSM317_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM318          VAL
 *  @access     SIO->BSM318.bit.VAL
 *  @brief      
 */
#define BSM318_ALL_VAL_Pos (0)
#define BSM318_ALL_VAL_Msk (0xFFFFFFUL << BSM318_ALL_VAL_Pos)

#define BSM318_BIT_VAL

#define BSM318_ALL_VAL_(x) ((x) << BSM318_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM319          VAL
 *  @access     SIO->BSM319.bit.VAL
 *  @brief      
 */
#define BSM319_ALL_VAL_Pos (0)
#define BSM319_ALL_VAL_Msk (0xFFFFFFUL << BSM319_ALL_VAL_Pos)

#define BSM319_BIT_VAL

#define BSM319_ALL_VAL_(x) ((x) << BSM319_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM320          VAL
 *  @access     SIO->BSM320.bit.VAL
 *  @brief      
 */
#define BSM320_ALL_VAL_Pos (0)
#define BSM320_ALL_VAL_Msk (0xFFFFFFUL << BSM320_ALL_VAL_Pos)

#define BSM320_BIT_VAL

#define BSM320_ALL_VAL_(x) ((x) << BSM320_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM321          VAL
 *  @access     SIO->BSM321.bit.VAL
 *  @brief      
 */
#define BSM321_ALL_VAL_Pos (0)
#define BSM321_ALL_VAL_Msk (0xFFFFFFUL << BSM321_ALL_VAL_Pos)

#define BSM321_BIT_VAL

#define BSM321_ALL_VAL_(x) ((x) << BSM321_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM322          VAL
 *  @access     SIO->BSM322.bit.VAL
 *  @brief      
 */
#define BSM322_ALL_VAL_Pos (0)
#define BSM322_ALL_VAL_Msk (0xFFFFFFUL << BSM322_ALL_VAL_Pos)

#define BSM322_BIT_VAL

#define BSM322_ALL_VAL_(x) ((x) << BSM322_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM323          VAL
 *  @access     SIO->BSM323.bit.VAL
 *  @brief      
 */
#define BSM323_ALL_VAL_Pos (0)
#define BSM323_ALL_VAL_Msk (0xFFFFFFUL << BSM323_ALL_VAL_Pos)

#define BSM323_BIT_VAL

#define BSM323_ALL_VAL_(x) ((x) << BSM323_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM324          VAL
 *  @access     SIO->BSM324.bit.VAL
 *  @brief      
 */
#define BSM324_ALL_VAL_Pos (0)
#define BSM324_ALL_VAL_Msk (0xFFFFFFUL << BSM324_ALL_VAL_Pos)

#define BSM324_BIT_VAL

#define BSM324_ALL_VAL_(x) ((x) << BSM324_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM325          VAL
 *  @access     SIO->BSM325.bit.VAL
 *  @brief      
 */
#define BSM325_ALL_VAL_Pos (0)
#define BSM325_ALL_VAL_Msk (0xFFFFFFUL << BSM325_ALL_VAL_Pos)

#define BSM325_BIT_VAL

#define BSM325_ALL_VAL_(x) ((x) << BSM325_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM326          VAL
 *  @access     SIO->BSM326.bit.VAL
 *  @brief      
 */
#define BSM326_ALL_VAL_Pos (0)
#define BSM326_ALL_VAL_Msk (0xFFFFFFUL << BSM326_ALL_VAL_Pos)

#define BSM326_BIT_VAL

#define BSM326_ALL_VAL_(x) ((x) << BSM326_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM327          VAL
 *  @access     SIO->BSM327.bit.VAL
 *  @brief      
 */
#define BSM327_ALL_VAL_Pos (0)
#define BSM327_ALL_VAL_Msk (0xFFFFFFUL << BSM327_ALL_VAL_Pos)

#define BSM327_BIT_VAL

#define BSM327_ALL_VAL_(x) ((x) << BSM327_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM328          VAL
 *  @access     SIO->BSM328.bit.VAL
 *  @brief      
 */
#define BSM328_ALL_VAL_Pos (0)
#define BSM328_ALL_VAL_Msk (0xFFFFFFUL << BSM328_ALL_VAL_Pos)

#define BSM328_BIT_VAL

#define BSM328_ALL_VAL_(x) ((x) << BSM328_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM329          VAL
 *  @access     SIO->BSM329.bit.VAL
 *  @brief      
 */
#define BSM329_ALL_VAL_Pos (0)
#define BSM329_ALL_VAL_Msk (0xFFFFFFUL << BSM329_ALL_VAL_Pos)

#define BSM329_BIT_VAL

#define BSM329_ALL_VAL_(x) ((x) << BSM329_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM330          VAL
 *  @access     SIO->BSM330.bit.VAL
 *  @brief      
 */
#define BSM330_ALL_VAL_Pos (0)
#define BSM330_ALL_VAL_Msk (0xFFFFFFUL << BSM330_ALL_VAL_Pos)

#define BSM330_BIT_VAL

#define BSM330_ALL_VAL_(x) ((x) << BSM330_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM331          VAL
 *  @access     SIO->BSM331.bit.VAL
 *  @brief      
 */
#define BSM331_ALL_VAL_Pos (0)
#define BSM331_ALL_VAL_Msk (0xFFFFFFUL << BSM331_ALL_VAL_Pos)

#define BSM331_BIT_VAL

#define BSM331_ALL_VAL_(x) ((x) << BSM331_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM332          VAL
 *  @access     SIO->BSM332.bit.VAL
 *  @brief      
 */
#define BSM332_ALL_VAL_Pos (0)
#define BSM332_ALL_VAL_Msk (0xFFFFFFUL << BSM332_ALL_VAL_Pos)

#define BSM332_BIT_VAL

#define BSM332_ALL_VAL_(x) ((x) << BSM332_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM333          VAL
 *  @access     SIO->BSM333.bit.VAL
 *  @brief      
 */
#define BSM333_ALL_VAL_Pos (0)
#define BSM333_ALL_VAL_Msk (0xFFFFFFUL << BSM333_ALL_VAL_Pos)

#define BSM333_BIT_VAL

#define BSM333_ALL_VAL_(x) ((x) << BSM333_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM334          VAL
 *  @access     SIO->BSM334.bit.VAL
 *  @brief      
 */
#define BSM334_ALL_VAL_Pos (0)
#define BSM334_ALL_VAL_Msk (0xFFFFFFUL << BSM334_ALL_VAL_Pos)

#define BSM334_BIT_VAL

#define BSM334_ALL_VAL_(x) ((x) << BSM334_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM335          VAL
 *  @access     SIO->BSM335.bit.VAL
 *  @brief      
 */
#define BSM335_ALL_VAL_Pos (0)
#define BSM335_ALL_VAL_Msk (0xFFFFFFUL << BSM335_ALL_VAL_Pos)

#define BSM335_BIT_VAL

#define BSM335_ALL_VAL_(x) ((x) << BSM335_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM336          VAL
 *  @access     SIO->BSM336.bit.VAL
 *  @brief      
 */
#define BSM336_ALL_VAL_Pos (0)
#define BSM336_ALL_VAL_Msk (0xFFFFFFUL << BSM336_ALL_VAL_Pos)

#define BSM336_BIT_VAL

#define BSM336_ALL_VAL_(x) ((x) << BSM336_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM337          VAL
 *  @access     SIO->BSM337.bit.VAL
 *  @brief      
 */
#define BSM337_ALL_VAL_Pos (0)
#define BSM337_ALL_VAL_Msk (0xFFFFFFUL << BSM337_ALL_VAL_Pos)

#define BSM337_BIT_VAL

#define BSM337_ALL_VAL_(x) ((x) << BSM337_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM338          VAL
 *  @access     SIO->BSM338.bit.VAL
 *  @brief      
 */
#define BSM338_ALL_VAL_Pos (0)
#define BSM338_ALL_VAL_Msk (0xFFFFFFUL << BSM338_ALL_VAL_Pos)

#define BSM338_BIT_VAL

#define BSM338_ALL_VAL_(x) ((x) << BSM338_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM339          VAL
 *  @access     SIO->BSM339.bit.VAL
 *  @brief      
 */
#define BSM339_ALL_VAL_Pos (0)
#define BSM339_ALL_VAL_Msk (0xFFFFFFUL << BSM339_ALL_VAL_Pos)

#define BSM339_BIT_VAL

#define BSM339_ALL_VAL_(x) ((x) << BSM339_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM340          VAL
 *  @access     SIO->BSM340.bit.VAL
 *  @brief      
 */
#define BSM340_ALL_VAL_Pos (0)
#define BSM340_ALL_VAL_Msk (0xFFFFFFUL << BSM340_ALL_VAL_Pos)

#define BSM340_BIT_VAL

#define BSM340_ALL_VAL_(x) ((x) << BSM340_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM341          VAL
 *  @access     SIO->BSM341.bit.VAL
 *  @brief      
 */
#define BSM341_ALL_VAL_Pos (0)
#define BSM341_ALL_VAL_Msk (0xFFFFFFUL << BSM341_ALL_VAL_Pos)

#define BSM341_BIT_VAL

#define BSM341_ALL_VAL_(x) ((x) << BSM341_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM342          VAL
 *  @access     SIO->BSM342.bit.VAL
 *  @brief      
 */
#define BSM342_ALL_VAL_Pos (0)
#define BSM342_ALL_VAL_Msk (0xFFFFFFUL << BSM342_ALL_VAL_Pos)

#define BSM342_BIT_VAL

#define BSM342_ALL_VAL_(x) ((x) << BSM342_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM343          VAL
 *  @access     SIO->BSM343.bit.VAL
 *  @brief      
 */
#define BSM343_ALL_VAL_Pos (0)
#define BSM343_ALL_VAL_Msk (0xFFFFFFUL << BSM343_ALL_VAL_Pos)

#define BSM343_BIT_VAL

#define BSM343_ALL_VAL_(x) ((x) << BSM343_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM344          VAL
 *  @access     SIO->BSM344.bit.VAL
 *  @brief      
 */
#define BSM344_ALL_VAL_Pos (0)
#define BSM344_ALL_VAL_Msk (0xFFFFFFUL << BSM344_ALL_VAL_Pos)

#define BSM344_BIT_VAL

#define BSM344_ALL_VAL_(x) ((x) << BSM344_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM345          VAL
 *  @access     SIO->BSM345.bit.VAL
 *  @brief      
 */
#define BSM345_ALL_VAL_Pos (0)
#define BSM345_ALL_VAL_Msk (0xFFFFFFUL << BSM345_ALL_VAL_Pos)

#define BSM345_BIT_VAL

#define BSM345_ALL_VAL_(x) ((x) << BSM345_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM346          VAL
 *  @access     SIO->BSM346.bit.VAL
 *  @brief      
 */
#define BSM346_ALL_VAL_Pos (0)
#define BSM346_ALL_VAL_Msk (0xFFFFFFUL << BSM346_ALL_VAL_Pos)

#define BSM346_BIT_VAL

#define BSM346_ALL_VAL_(x) ((x) << BSM346_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM347          VAL
 *  @access     SIO->BSM347.bit.VAL
 *  @brief      
 */
#define BSM347_ALL_VAL_Pos (0)
#define BSM347_ALL_VAL_Msk (0xFFFFFFUL << BSM347_ALL_VAL_Pos)

#define BSM347_BIT_VAL

#define BSM347_ALL_VAL_(x) ((x) << BSM347_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM348          VAL
 *  @access     SIO->BSM348.bit.VAL
 *  @brief      
 */
#define BSM348_ALL_VAL_Pos (0)
#define BSM348_ALL_VAL_Msk (0xFFFFFFUL << BSM348_ALL_VAL_Pos)

#define BSM348_BIT_VAL

#define BSM348_ALL_VAL_(x) ((x) << BSM348_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM349          VAL
 *  @access     SIO->BSM349.bit.VAL
 *  @brief      
 */
#define BSM349_ALL_VAL_Pos (0)
#define BSM349_ALL_VAL_Msk (0xFFFFFFUL << BSM349_ALL_VAL_Pos)

#define BSM349_BIT_VAL

#define BSM349_ALL_VAL_(x) ((x) << BSM349_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM350          VAL
 *  @access     SIO->BSM350.bit.VAL
 *  @brief      
 */
#define BSM350_ALL_VAL_Pos (0)
#define BSM350_ALL_VAL_Msk (0xFFFFFFUL << BSM350_ALL_VAL_Pos)

#define BSM350_BIT_VAL

#define BSM350_ALL_VAL_(x) ((x) << BSM350_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM351          VAL
 *  @access     SIO->BSM351.bit.VAL
 *  @brief      
 */
#define BSM351_ALL_VAL_Pos (0)
#define BSM351_ALL_VAL_Msk (0xFFFFFFUL << BSM351_ALL_VAL_Pos)

#define BSM351_BIT_VAL

#define BSM351_ALL_VAL_(x) ((x) << BSM351_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM352          VAL
 *  @access     SIO->BSM352.bit.VAL
 *  @brief      
 */
#define BSM352_ALL_VAL_Pos (0)
#define BSM352_ALL_VAL_Msk (0xFFFFFFUL << BSM352_ALL_VAL_Pos)

#define BSM352_BIT_VAL

#define BSM352_ALL_VAL_(x) ((x) << BSM352_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM353          VAL
 *  @access     SIO->BSM353.bit.VAL
 *  @brief      
 */
#define BSM353_ALL_VAL_Pos (0)
#define BSM353_ALL_VAL_Msk (0xFFFFFFUL << BSM353_ALL_VAL_Pos)

#define BSM353_BIT_VAL

#define BSM353_ALL_VAL_(x) ((x) << BSM353_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM354          VAL
 *  @access     SIO->BSM354.bit.VAL
 *  @brief      
 */
#define BSM354_ALL_VAL_Pos (0)
#define BSM354_ALL_VAL_Msk (0xFFFFFFUL << BSM354_ALL_VAL_Pos)

#define BSM354_BIT_VAL

#define BSM354_ALL_VAL_(x) ((x) << BSM354_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM355          VAL
 *  @access     SIO->BSM355.bit.VAL
 *  @brief      
 */
#define BSM355_ALL_VAL_Pos (0)
#define BSM355_ALL_VAL_Msk (0xFFFFFFUL << BSM355_ALL_VAL_Pos)

#define BSM355_BIT_VAL

#define BSM355_ALL_VAL_(x) ((x) << BSM355_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM356          VAL
 *  @access     SIO->BSM356.bit.VAL
 *  @brief      
 */
#define BSM356_ALL_VAL_Pos (0)
#define BSM356_ALL_VAL_Msk (0xFFFFFFUL << BSM356_ALL_VAL_Pos)

#define BSM356_BIT_VAL

#define BSM356_ALL_VAL_(x) ((x) << BSM356_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM357          VAL
 *  @access     SIO->BSM357.bit.VAL
 *  @brief      
 */
#define BSM357_ALL_VAL_Pos (0)
#define BSM357_ALL_VAL_Msk (0xFFFFFFUL << BSM357_ALL_VAL_Pos)

#define BSM357_BIT_VAL

#define BSM357_ALL_VAL_(x) ((x) << BSM357_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM358          VAL
 *  @access     SIO->BSM358.bit.VAL
 *  @brief      
 */
#define BSM358_ALL_VAL_Pos (0)
#define BSM358_ALL_VAL_Msk (0xFFFFFFUL << BSM358_ALL_VAL_Pos)

#define BSM358_BIT_VAL

#define BSM358_ALL_VAL_(x) ((x) << BSM358_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM359          VAL
 *  @access     SIO->BSM359.bit.VAL
 *  @brief      
 */
#define BSM359_ALL_VAL_Pos (0)
#define BSM359_ALL_VAL_Msk (0xFFFFFFUL << BSM359_ALL_VAL_Pos)

#define BSM359_BIT_VAL

#define BSM359_ALL_VAL_(x) ((x) << BSM359_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM360          VAL
 *  @access     SIO->BSM360.bit.VAL
 *  @brief      
 */
#define BSM360_ALL_VAL_Pos (0)
#define BSM360_ALL_VAL_Msk (0xFFFFFFUL << BSM360_ALL_VAL_Pos)

#define BSM360_BIT_VAL

#define BSM360_ALL_VAL_(x) ((x) << BSM360_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM361          VAL
 *  @access     SIO->BSM361.bit.VAL
 *  @brief      
 */
#define BSM361_ALL_VAL_Pos (0)
#define BSM361_ALL_VAL_Msk (0xFFFFFFUL << BSM361_ALL_VAL_Pos)

#define BSM361_BIT_VAL

#define BSM361_ALL_VAL_(x) ((x) << BSM361_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM362          VAL
 *  @access     SIO->BSM362.bit.VAL
 *  @brief      
 */
#define BSM362_ALL_VAL_Pos (0)
#define BSM362_ALL_VAL_Msk (0xFFFFFFUL << BSM362_ALL_VAL_Pos)

#define BSM362_BIT_VAL

#define BSM362_ALL_VAL_(x) ((x) << BSM362_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM363          VAL
 *  @access     SIO->BSM363.bit.VAL
 *  @brief      
 */
#define BSM363_ALL_VAL_Pos (0)
#define BSM363_ALL_VAL_Msk (0xFFFFFFUL << BSM363_ALL_VAL_Pos)

#define BSM363_BIT_VAL

#define BSM363_ALL_VAL_(x) ((x) << BSM363_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM364          VAL
 *  @access     SIO->BSM364.bit.VAL
 *  @brief      
 */
#define BSM364_ALL_VAL_Pos (0)
#define BSM364_ALL_VAL_Msk (0xFFFFFFUL << BSM364_ALL_VAL_Pos)

#define BSM364_BIT_VAL

#define BSM364_ALL_VAL_(x) ((x) << BSM364_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM365          VAL
 *  @access     SIO->BSM365.bit.VAL
 *  @brief      
 */
#define BSM365_ALL_VAL_Pos (0)
#define BSM365_ALL_VAL_Msk (0xFFFFFFUL << BSM365_ALL_VAL_Pos)

#define BSM365_BIT_VAL

#define BSM365_ALL_VAL_(x) ((x) << BSM365_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM366          VAL
 *  @access     SIO->BSM366.bit.VAL
 *  @brief      
 */
#define BSM366_ALL_VAL_Pos (0)
#define BSM366_ALL_VAL_Msk (0xFFFFFFUL << BSM366_ALL_VAL_Pos)

#define BSM366_BIT_VAL

#define BSM366_ALL_VAL_(x) ((x) << BSM366_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM367          VAL
 *  @access     SIO->BSM367.bit.VAL
 *  @brief      
 */
#define BSM367_ALL_VAL_Pos (0)
#define BSM367_ALL_VAL_Msk (0xFFFFFFUL << BSM367_ALL_VAL_Pos)

#define BSM367_BIT_VAL

#define BSM367_ALL_VAL_(x) ((x) << BSM367_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM368          VAL
 *  @access     SIO->BSM368.bit.VAL
 *  @brief      
 */
#define BSM368_ALL_VAL_Pos (0)
#define BSM368_ALL_VAL_Msk (0xFFFFFFUL << BSM368_ALL_VAL_Pos)

#define BSM368_BIT_VAL

#define BSM368_ALL_VAL_(x) ((x) << BSM368_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM369          VAL
 *  @access     SIO->BSM369.bit.VAL
 *  @brief      
 */
#define BSM369_ALL_VAL_Pos (0)
#define BSM369_ALL_VAL_Msk (0xFFFFFFUL << BSM369_ALL_VAL_Pos)

#define BSM369_BIT_VAL

#define BSM369_ALL_VAL_(x) ((x) << BSM369_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM370          VAL
 *  @access     SIO->BSM370.bit.VAL
 *  @brief      
 */
#define BSM370_ALL_VAL_Pos (0)
#define BSM370_ALL_VAL_Msk (0xFFFFFFUL << BSM370_ALL_VAL_Pos)

#define BSM370_BIT_VAL

#define BSM370_ALL_VAL_(x) ((x) << BSM370_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM371          VAL
 *  @access     SIO->BSM371.bit.VAL
 *  @brief      
 */
#define BSM371_ALL_VAL_Pos (0)
#define BSM371_ALL_VAL_Msk (0xFFFFFFUL << BSM371_ALL_VAL_Pos)

#define BSM371_BIT_VAL

#define BSM371_ALL_VAL_(x) ((x) << BSM371_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM372          VAL
 *  @access     SIO->BSM372.bit.VAL
 *  @brief      
 */
#define BSM372_ALL_VAL_Pos (0)
#define BSM372_ALL_VAL_Msk (0xFFFFFFUL << BSM372_ALL_VAL_Pos)

#define BSM372_BIT_VAL

#define BSM372_ALL_VAL_(x) ((x) << BSM372_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM373          VAL
 *  @access     SIO->BSM373.bit.VAL
 *  @brief      
 */
#define BSM373_ALL_VAL_Pos (0)
#define BSM373_ALL_VAL_Msk (0xFFFFFFUL << BSM373_ALL_VAL_Pos)

#define BSM373_BIT_VAL

#define BSM373_ALL_VAL_(x) ((x) << BSM373_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM374          VAL
 *  @access     SIO->BSM374.bit.VAL
 *  @brief      
 */
#define BSM374_ALL_VAL_Pos (0)
#define BSM374_ALL_VAL_Msk (0xFFFFFFUL << BSM374_ALL_VAL_Pos)

#define BSM374_BIT_VAL

#define BSM374_ALL_VAL_(x) ((x) << BSM374_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM375          VAL
 *  @access     SIO->BSM375.bit.VAL
 *  @brief      
 */
#define BSM375_ALL_VAL_Pos (0)
#define BSM375_ALL_VAL_Msk (0xFFFFFFUL << BSM375_ALL_VAL_Pos)

#define BSM375_BIT_VAL

#define BSM375_ALL_VAL_(x) ((x) << BSM375_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM376          VAL
 *  @access     SIO->BSM376.bit.VAL
 *  @brief      
 */
#define BSM376_ALL_VAL_Pos (0)
#define BSM376_ALL_VAL_Msk (0xFFFFFFUL << BSM376_ALL_VAL_Pos)

#define BSM376_BIT_VAL

#define BSM376_ALL_VAL_(x) ((x) << BSM376_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM377          VAL
 *  @access     SIO->BSM377.bit.VAL
 *  @brief      
 */
#define BSM377_ALL_VAL_Pos (0)
#define BSM377_ALL_VAL_Msk (0xFFFFFFUL << BSM377_ALL_VAL_Pos)

#define BSM377_BIT_VAL

#define BSM377_ALL_VAL_(x) ((x) << BSM377_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM378          VAL
 *  @access     SIO->BSM378.bit.VAL
 *  @brief      
 */
#define BSM378_ALL_VAL_Pos (0)
#define BSM378_ALL_VAL_Msk (0xFFFFFFUL << BSM378_ALL_VAL_Pos)

#define BSM378_BIT_VAL

#define BSM378_ALL_VAL_(x) ((x) << BSM378_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM379          VAL
 *  @access     SIO->BSM379.bit.VAL
 *  @brief      
 */
#define BSM379_ALL_VAL_Pos (0)
#define BSM379_ALL_VAL_Msk (0xFFFFFFUL << BSM379_ALL_VAL_Pos)

#define BSM379_BIT_VAL

#define BSM379_ALL_VAL_(x) ((x) << BSM379_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM380          VAL
 *  @access     SIO->BSM380.bit.VAL
 *  @brief      
 */
#define BSM380_ALL_VAL_Pos (0)
#define BSM380_ALL_VAL_Msk (0xFFFFFFUL << BSM380_ALL_VAL_Pos)

#define BSM380_BIT_VAL

#define BSM380_ALL_VAL_(x) ((x) << BSM380_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM381          VAL
 *  @access     SIO->BSM381.bit.VAL
 *  @brief      
 */
#define BSM381_ALL_VAL_Pos (0)
#define BSM381_ALL_VAL_Msk (0xFFFFFFUL << BSM381_ALL_VAL_Pos)

#define BSM381_BIT_VAL

#define BSM381_ALL_VAL_(x) ((x) << BSM381_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM382          VAL
 *  @access     SIO->BSM382.bit.VAL
 *  @brief      
 */
#define BSM382_ALL_VAL_Pos (0)
#define BSM382_ALL_VAL_Msk (0xFFFFFFUL << BSM382_ALL_VAL_Pos)

#define BSM382_BIT_VAL

#define BSM382_ALL_VAL_(x) ((x) << BSM382_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM383          VAL
 *  @access     SIO->BSM383.bit.VAL
 *  @brief      
 */
#define BSM383_ALL_VAL_Pos (0)
#define BSM383_ALL_VAL_Msk (0xFFFFFFUL << BSM383_ALL_VAL_Pos)

#define BSM383_BIT_VAL

#define BSM383_ALL_VAL_(x) ((x) << BSM383_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM384          VAL
 *  @access     SIO->BSM384.bit.VAL
 *  @brief      
 */
#define BSM384_ALL_VAL_Pos (0)
#define BSM384_ALL_VAL_Msk (0xFFFFFFUL << BSM384_ALL_VAL_Pos)

#define BSM384_BIT_VAL

#define BSM384_ALL_VAL_(x) ((x) << BSM384_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM385          VAL
 *  @access     SIO->BSM385.bit.VAL
 *  @brief      
 */
#define BSM385_ALL_VAL_Pos (0)
#define BSM385_ALL_VAL_Msk (0xFFFFFFUL << BSM385_ALL_VAL_Pos)

#define BSM385_BIT_VAL

#define BSM385_ALL_VAL_(x) ((x) << BSM385_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM386          VAL
 *  @access     SIO->BSM386.bit.VAL
 *  @brief      
 */
#define BSM386_ALL_VAL_Pos (0)
#define BSM386_ALL_VAL_Msk (0xFFFFFFUL << BSM386_ALL_VAL_Pos)

#define BSM386_BIT_VAL

#define BSM386_ALL_VAL_(x) ((x) << BSM386_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM387          VAL
 *  @access     SIO->BSM387.bit.VAL
 *  @brief      
 */
#define BSM387_ALL_VAL_Pos (0)
#define BSM387_ALL_VAL_Msk (0xFFFFFFUL << BSM387_ALL_VAL_Pos)

#define BSM387_BIT_VAL

#define BSM387_ALL_VAL_(x) ((x) << BSM387_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM388          VAL
 *  @access     SIO->BSM388.bit.VAL
 *  @brief      
 */
#define BSM388_ALL_VAL_Pos (0)
#define BSM388_ALL_VAL_Msk (0xFFFFFFUL << BSM388_ALL_VAL_Pos)

#define BSM388_BIT_VAL

#define BSM388_ALL_VAL_(x) ((x) << BSM388_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM389          VAL
 *  @access     SIO->BSM389.bit.VAL
 *  @brief      
 */
#define BSM389_ALL_VAL_Pos (0)
#define BSM389_ALL_VAL_Msk (0xFFFFFFUL << BSM389_ALL_VAL_Pos)

#define BSM389_BIT_VAL

#define BSM389_ALL_VAL_(x) ((x) << BSM389_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM390          VAL
 *  @access     SIO->BSM390.bit.VAL
 *  @brief      
 */
#define BSM390_ALL_VAL_Pos (0)
#define BSM390_ALL_VAL_Msk (0xFFFFFFUL << BSM390_ALL_VAL_Pos)

#define BSM390_BIT_VAL

#define BSM390_ALL_VAL_(x) ((x) << BSM390_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM391          VAL
 *  @access     SIO->BSM391.bit.VAL
 *  @brief      
 */
#define BSM391_ALL_VAL_Pos (0)
#define BSM391_ALL_VAL_Msk (0xFFFFFFUL << BSM391_ALL_VAL_Pos)

#define BSM391_BIT_VAL

#define BSM391_ALL_VAL_(x) ((x) << BSM391_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM392          VAL
 *  @access     SIO->BSM392.bit.VAL
 *  @brief      
 */
#define BSM392_ALL_VAL_Pos (0)
#define BSM392_ALL_VAL_Msk (0xFFFFFFUL << BSM392_ALL_VAL_Pos)

#define BSM392_BIT_VAL

#define BSM392_ALL_VAL_(x) ((x) << BSM392_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM393          VAL
 *  @access     SIO->BSM393.bit.VAL
 *  @brief      
 */
#define BSM393_ALL_VAL_Pos (0)
#define BSM393_ALL_VAL_Msk (0xFFFFFFUL << BSM393_ALL_VAL_Pos)

#define BSM393_BIT_VAL

#define BSM393_ALL_VAL_(x) ((x) << BSM393_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM394          VAL
 *  @access     SIO->BSM394.bit.VAL
 *  @brief      
 */
#define BSM394_ALL_VAL_Pos (0)
#define BSM394_ALL_VAL_Msk (0xFFFFFFUL << BSM394_ALL_VAL_Pos)

#define BSM394_BIT_VAL

#define BSM394_ALL_VAL_(x) ((x) << BSM394_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM395          VAL
 *  @access     SIO->BSM395.bit.VAL
 *  @brief      
 */
#define BSM395_ALL_VAL_Pos (0)
#define BSM395_ALL_VAL_Msk (0xFFFFFFUL << BSM395_ALL_VAL_Pos)

#define BSM395_BIT_VAL

#define BSM395_ALL_VAL_(x) ((x) << BSM395_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM396          VAL
 *  @access     SIO->BSM396.bit.VAL
 *  @brief      
 */
#define BSM396_ALL_VAL_Pos (0)
#define BSM396_ALL_VAL_Msk (0xFFFFFFUL << BSM396_ALL_VAL_Pos)

#define BSM396_BIT_VAL

#define BSM396_ALL_VAL_(x) ((x) << BSM396_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM397          VAL
 *  @access     SIO->BSM397.bit.VAL
 *  @brief      
 */
#define BSM397_ALL_VAL_Pos (0)
#define BSM397_ALL_VAL_Msk (0xFFFFFFUL << BSM397_ALL_VAL_Pos)

#define BSM397_BIT_VAL

#define BSM397_ALL_VAL_(x) ((x) << BSM397_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM398          VAL
 *  @access     SIO->BSM398.bit.VAL
 *  @brief      
 */
#define BSM398_ALL_VAL_Pos (0)
#define BSM398_ALL_VAL_Msk (0xFFFFFFUL << BSM398_ALL_VAL_Pos)

#define BSM398_BIT_VAL

#define BSM398_ALL_VAL_(x) ((x) << BSM398_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM399          VAL
 *  @access     SIO->BSM399.bit.VAL
 *  @brief      
 */
#define BSM399_ALL_VAL_Pos (0)
#define BSM399_ALL_VAL_Msk (0xFFFFFFUL << BSM399_ALL_VAL_Pos)

#define BSM399_BIT_VAL

#define BSM399_ALL_VAL_(x) ((x) << BSM399_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM400          VAL
 *  @access     SIO->BSM400.bit.VAL
 *  @brief      
 */
#define BSM400_ALL_VAL_Pos (0)
#define BSM400_ALL_VAL_Msk (0xFFFFFFUL << BSM400_ALL_VAL_Pos)

#define BSM400_BIT_VAL

#define BSM400_ALL_VAL_(x) ((x) << BSM400_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM401          VAL
 *  @access     SIO->BSM401.bit.VAL
 *  @brief      
 */
#define BSM401_ALL_VAL_Pos (0)
#define BSM401_ALL_VAL_Msk (0xFFFFFFUL << BSM401_ALL_VAL_Pos)

#define BSM401_BIT_VAL

#define BSM401_ALL_VAL_(x) ((x) << BSM401_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM402          VAL
 *  @access     SIO->BSM402.bit.VAL
 *  @brief      
 */
#define BSM402_ALL_VAL_Pos (0)
#define BSM402_ALL_VAL_Msk (0xFFFFFFUL << BSM402_ALL_VAL_Pos)

#define BSM402_BIT_VAL

#define BSM402_ALL_VAL_(x) ((x) << BSM402_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM403          VAL
 *  @access     SIO->BSM403.bit.VAL
 *  @brief      
 */
#define BSM403_ALL_VAL_Pos (0)
#define BSM403_ALL_VAL_Msk (0xFFFFFFUL << BSM403_ALL_VAL_Pos)

#define BSM403_BIT_VAL

#define BSM403_ALL_VAL_(x) ((x) << BSM403_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM404          VAL
 *  @access     SIO->BSM404.bit.VAL
 *  @brief      
 */
#define BSM404_ALL_VAL_Pos (0)
#define BSM404_ALL_VAL_Msk (0xFFFFFFUL << BSM404_ALL_VAL_Pos)

#define BSM404_BIT_VAL

#define BSM404_ALL_VAL_(x) ((x) << BSM404_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM405          VAL
 *  @access     SIO->BSM405.bit.VAL
 *  @brief      
 */
#define BSM405_ALL_VAL_Pos (0)
#define BSM405_ALL_VAL_Msk (0xFFFFFFUL << BSM405_ALL_VAL_Pos)

#define BSM405_BIT_VAL

#define BSM405_ALL_VAL_(x) ((x) << BSM405_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM406          VAL
 *  @access     SIO->BSM406.bit.VAL
 *  @brief      
 */
#define BSM406_ALL_VAL_Pos (0)
#define BSM406_ALL_VAL_Msk (0xFFFFFFUL << BSM406_ALL_VAL_Pos)

#define BSM406_BIT_VAL

#define BSM406_ALL_VAL_(x) ((x) << BSM406_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM407          VAL
 *  @access     SIO->BSM407.bit.VAL
 *  @brief      
 */
#define BSM407_ALL_VAL_Pos (0)
#define BSM407_ALL_VAL_Msk (0xFFFFFFUL << BSM407_ALL_VAL_Pos)

#define BSM407_BIT_VAL

#define BSM407_ALL_VAL_(x) ((x) << BSM407_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM408          VAL
 *  @access     SIO->BSM408.bit.VAL
 *  @brief      
 */
#define BSM408_ALL_VAL_Pos (0)
#define BSM408_ALL_VAL_Msk (0xFFFFFFUL << BSM408_ALL_VAL_Pos)

#define BSM408_BIT_VAL

#define BSM408_ALL_VAL_(x) ((x) << BSM408_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM409          VAL
 *  @access     SIO->BSM409.bit.VAL
 *  @brief      
 */
#define BSM409_ALL_VAL_Pos (0)
#define BSM409_ALL_VAL_Msk (0xFFFFFFUL << BSM409_ALL_VAL_Pos)

#define BSM409_BIT_VAL

#define BSM409_ALL_VAL_(x) ((x) << BSM409_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM410          VAL
 *  @access     SIO->BSM410.bit.VAL
 *  @brief      
 */
#define BSM410_ALL_VAL_Pos (0)
#define BSM410_ALL_VAL_Msk (0xFFFFFFUL << BSM410_ALL_VAL_Pos)

#define BSM410_BIT_VAL

#define BSM410_ALL_VAL_(x) ((x) << BSM410_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM411          VAL
 *  @access     SIO->BSM411.bit.VAL
 *  @brief      
 */
#define BSM411_ALL_VAL_Pos (0)
#define BSM411_ALL_VAL_Msk (0xFFFFFFUL << BSM411_ALL_VAL_Pos)

#define BSM411_BIT_VAL

#define BSM411_ALL_VAL_(x) ((x) << BSM411_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM412          VAL
 *  @access     SIO->BSM412.bit.VAL
 *  @brief      
 */
#define BSM412_ALL_VAL_Pos (0)
#define BSM412_ALL_VAL_Msk (0xFFFFFFUL << BSM412_ALL_VAL_Pos)

#define BSM412_BIT_VAL

#define BSM412_ALL_VAL_(x) ((x) << BSM412_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM413          VAL
 *  @access     SIO->BSM413.bit.VAL
 *  @brief      
 */
#define BSM413_ALL_VAL_Pos (0)
#define BSM413_ALL_VAL_Msk (0xFFFFFFUL << BSM413_ALL_VAL_Pos)

#define BSM413_BIT_VAL

#define BSM413_ALL_VAL_(x) ((x) << BSM413_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM414          VAL
 *  @access     SIO->BSM414.bit.VAL
 *  @brief      
 */
#define BSM414_ALL_VAL_Pos (0)
#define BSM414_ALL_VAL_Msk (0xFFFFFFUL << BSM414_ALL_VAL_Pos)

#define BSM414_BIT_VAL

#define BSM414_ALL_VAL_(x) ((x) << BSM414_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM415          VAL
 *  @access     SIO->BSM415.bit.VAL
 *  @brief      
 */
#define BSM415_ALL_VAL_Pos (0)
#define BSM415_ALL_VAL_Msk (0xFFFFFFUL << BSM415_ALL_VAL_Pos)

#define BSM415_BIT_VAL

#define BSM415_ALL_VAL_(x) ((x) << BSM415_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM416          VAL
 *  @access     SIO->BSM416.bit.VAL
 *  @brief      
 */
#define BSM416_ALL_VAL_Pos (0)
#define BSM416_ALL_VAL_Msk (0xFFFFFFUL << BSM416_ALL_VAL_Pos)

#define BSM416_BIT_VAL

#define BSM416_ALL_VAL_(x) ((x) << BSM416_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM417          VAL
 *  @access     SIO->BSM417.bit.VAL
 *  @brief      
 */
#define BSM417_ALL_VAL_Pos (0)
#define BSM417_ALL_VAL_Msk (0xFFFFFFUL << BSM417_ALL_VAL_Pos)

#define BSM417_BIT_VAL

#define BSM417_ALL_VAL_(x) ((x) << BSM417_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM418          VAL
 *  @access     SIO->BSM418.bit.VAL
 *  @brief      
 */
#define BSM418_ALL_VAL_Pos (0)
#define BSM418_ALL_VAL_Msk (0xFFFFFFUL << BSM418_ALL_VAL_Pos)

#define BSM418_BIT_VAL

#define BSM418_ALL_VAL_(x) ((x) << BSM418_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM419          VAL
 *  @access     SIO->BSM419.bit.VAL
 *  @brief      
 */
#define BSM419_ALL_VAL_Pos (0)
#define BSM419_ALL_VAL_Msk (0xFFFFFFUL << BSM419_ALL_VAL_Pos)

#define BSM419_BIT_VAL

#define BSM419_ALL_VAL_(x) ((x) << BSM419_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM420          VAL
 *  @access     SIO->BSM420.bit.VAL
 *  @brief      
 */
#define BSM420_ALL_VAL_Pos (0)
#define BSM420_ALL_VAL_Msk (0xFFFFFFUL << BSM420_ALL_VAL_Pos)

#define BSM420_BIT_VAL

#define BSM420_ALL_VAL_(x) ((x) << BSM420_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM421          VAL
 *  @access     SIO->BSM421.bit.VAL
 *  @brief      
 */
#define BSM421_ALL_VAL_Pos (0)
#define BSM421_ALL_VAL_Msk (0xFFFFFFUL << BSM421_ALL_VAL_Pos)

#define BSM421_BIT_VAL

#define BSM421_ALL_VAL_(x) ((x) << BSM421_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM422          VAL
 *  @access     SIO->BSM422.bit.VAL
 *  @brief      
 */
#define BSM422_ALL_VAL_Pos (0)
#define BSM422_ALL_VAL_Msk (0xFFFFFFUL << BSM422_ALL_VAL_Pos)

#define BSM422_BIT_VAL

#define BSM422_ALL_VAL_(x) ((x) << BSM422_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM423          VAL
 *  @access     SIO->BSM423.bit.VAL
 *  @brief      
 */
#define BSM423_ALL_VAL_Pos (0)
#define BSM423_ALL_VAL_Msk (0xFFFFFFUL << BSM423_ALL_VAL_Pos)

#define BSM423_BIT_VAL

#define BSM423_ALL_VAL_(x) ((x) << BSM423_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM424          VAL
 *  @access     SIO->BSM424.bit.VAL
 *  @brief      
 */
#define BSM424_ALL_VAL_Pos (0)
#define BSM424_ALL_VAL_Msk (0xFFFFFFUL << BSM424_ALL_VAL_Pos)

#define BSM424_BIT_VAL

#define BSM424_ALL_VAL_(x) ((x) << BSM424_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM425          VAL
 *  @access     SIO->BSM425.bit.VAL
 *  @brief      
 */
#define BSM425_ALL_VAL_Pos (0)
#define BSM425_ALL_VAL_Msk (0xFFFFFFUL << BSM425_ALL_VAL_Pos)

#define BSM425_BIT_VAL

#define BSM425_ALL_VAL_(x) ((x) << BSM425_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM426          VAL
 *  @access     SIO->BSM426.bit.VAL
 *  @brief      
 */
#define BSM426_ALL_VAL_Pos (0)
#define BSM426_ALL_VAL_Msk (0xFFFFFFUL << BSM426_ALL_VAL_Pos)

#define BSM426_BIT_VAL

#define BSM426_ALL_VAL_(x) ((x) << BSM426_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM427          VAL
 *  @access     SIO->BSM427.bit.VAL
 *  @brief      
 */
#define BSM427_ALL_VAL_Pos (0)
#define BSM427_ALL_VAL_Msk (0xFFFFFFUL << BSM427_ALL_VAL_Pos)

#define BSM427_BIT_VAL

#define BSM427_ALL_VAL_(x) ((x) << BSM427_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM428          VAL
 *  @access     SIO->BSM428.bit.VAL
 *  @brief      
 */
#define BSM428_ALL_VAL_Pos (0)
#define BSM428_ALL_VAL_Msk (0xFFFFFFUL << BSM428_ALL_VAL_Pos)

#define BSM428_BIT_VAL

#define BSM428_ALL_VAL_(x) ((x) << BSM428_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM429          VAL
 *  @access     SIO->BSM429.bit.VAL
 *  @brief      
 */
#define BSM429_ALL_VAL_Pos (0)
#define BSM429_ALL_VAL_Msk (0xFFFFFFUL << BSM429_ALL_VAL_Pos)

#define BSM429_BIT_VAL

#define BSM429_ALL_VAL_(x) ((x) << BSM429_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM430          VAL
 *  @access     SIO->BSM430.bit.VAL
 *  @brief      
 */
#define BSM430_ALL_VAL_Pos (0)
#define BSM430_ALL_VAL_Msk (0xFFFFFFUL << BSM430_ALL_VAL_Pos)

#define BSM430_BIT_VAL

#define BSM430_ALL_VAL_(x) ((x) << BSM430_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM431          VAL
 *  @access     SIO->BSM431.bit.VAL
 *  @brief      
 */
#define BSM431_ALL_VAL_Pos (0)
#define BSM431_ALL_VAL_Msk (0xFFFFFFUL << BSM431_ALL_VAL_Pos)

#define BSM431_BIT_VAL

#define BSM431_ALL_VAL_(x) ((x) << BSM431_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM432          VAL
 *  @access     SIO->BSM432.bit.VAL
 *  @brief      
 */
#define BSM432_ALL_VAL_Pos (0)
#define BSM432_ALL_VAL_Msk (0xFFFFFFUL << BSM432_ALL_VAL_Pos)

#define BSM432_BIT_VAL

#define BSM432_ALL_VAL_(x) ((x) << BSM432_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM433          VAL
 *  @access     SIO->BSM433.bit.VAL
 *  @brief      
 */
#define BSM433_ALL_VAL_Pos (0)
#define BSM433_ALL_VAL_Msk (0xFFFFFFUL << BSM433_ALL_VAL_Pos)

#define BSM433_BIT_VAL

#define BSM433_ALL_VAL_(x) ((x) << BSM433_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM434          VAL
 *  @access     SIO->BSM434.bit.VAL
 *  @brief      
 */
#define BSM434_ALL_VAL_Pos (0)
#define BSM434_ALL_VAL_Msk (0xFFFFFFUL << BSM434_ALL_VAL_Pos)

#define BSM434_BIT_VAL

#define BSM434_ALL_VAL_(x) ((x) << BSM434_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM435          VAL
 *  @access     SIO->BSM435.bit.VAL
 *  @brief      
 */
#define BSM435_ALL_VAL_Pos (0)
#define BSM435_ALL_VAL_Msk (0xFFFFFFUL << BSM435_ALL_VAL_Pos)

#define BSM435_BIT_VAL

#define BSM435_ALL_VAL_(x) ((x) << BSM435_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM436          VAL
 *  @access     SIO->BSM436.bit.VAL
 *  @brief      
 */
#define BSM436_ALL_VAL_Pos (0)
#define BSM436_ALL_VAL_Msk (0xFFFFFFUL << BSM436_ALL_VAL_Pos)

#define BSM436_BIT_VAL

#define BSM436_ALL_VAL_(x) ((x) << BSM436_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM437          VAL
 *  @access     SIO->BSM437.bit.VAL
 *  @brief      
 */
#define BSM437_ALL_VAL_Pos (0)
#define BSM437_ALL_VAL_Msk (0xFFFFFFUL << BSM437_ALL_VAL_Pos)

#define BSM437_BIT_VAL

#define BSM437_ALL_VAL_(x) ((x) << BSM437_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM438          VAL
 *  @access     SIO->BSM438.bit.VAL
 *  @brief      
 */
#define BSM438_ALL_VAL_Pos (0)
#define BSM438_ALL_VAL_Msk (0xFFFFFFUL << BSM438_ALL_VAL_Pos)

#define BSM438_BIT_VAL

#define BSM438_ALL_VAL_(x) ((x) << BSM438_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM439          VAL
 *  @access     SIO->BSM439.bit.VAL
 *  @brief      
 */
#define BSM439_ALL_VAL_Pos (0)
#define BSM439_ALL_VAL_Msk (0xFFFFFFUL << BSM439_ALL_VAL_Pos)

#define BSM439_BIT_VAL

#define BSM439_ALL_VAL_(x) ((x) << BSM439_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM440          VAL
 *  @access     SIO->BSM440.bit.VAL
 *  @brief      
 */
#define BSM440_ALL_VAL_Pos (0)
#define BSM440_ALL_VAL_Msk (0xFFFFFFUL << BSM440_ALL_VAL_Pos)

#define BSM440_BIT_VAL

#define BSM440_ALL_VAL_(x) ((x) << BSM440_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM441          VAL
 *  @access     SIO->BSM441.bit.VAL
 *  @brief      
 */
#define BSM441_ALL_VAL_Pos (0)
#define BSM441_ALL_VAL_Msk (0xFFFFFFUL << BSM441_ALL_VAL_Pos)

#define BSM441_BIT_VAL

#define BSM441_ALL_VAL_(x) ((x) << BSM441_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM442          VAL
 *  @access     SIO->BSM442.bit.VAL
 *  @brief      
 */
#define BSM442_ALL_VAL_Pos (0)
#define BSM442_ALL_VAL_Msk (0xFFFFFFUL << BSM442_ALL_VAL_Pos)

#define BSM442_BIT_VAL

#define BSM442_ALL_VAL_(x) ((x) << BSM442_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM443          VAL
 *  @access     SIO->BSM443.bit.VAL
 *  @brief      
 */
#define BSM443_ALL_VAL_Pos (0)
#define BSM443_ALL_VAL_Msk (0xFFFFFFUL << BSM443_ALL_VAL_Pos)

#define BSM443_BIT_VAL

#define BSM443_ALL_VAL_(x) ((x) << BSM443_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM444          VAL
 *  @access     SIO->BSM444.bit.VAL
 *  @brief      
 */
#define BSM444_ALL_VAL_Pos (0)
#define BSM444_ALL_VAL_Msk (0xFFFFFFUL << BSM444_ALL_VAL_Pos)

#define BSM444_BIT_VAL

#define BSM444_ALL_VAL_(x) ((x) << BSM444_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM445          VAL
 *  @access     SIO->BSM445.bit.VAL
 *  @brief      
 */
#define BSM445_ALL_VAL_Pos (0)
#define BSM445_ALL_VAL_Msk (0xFFFFFFUL << BSM445_ALL_VAL_Pos)

#define BSM445_BIT_VAL

#define BSM445_ALL_VAL_(x) ((x) << BSM445_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM446          VAL
 *  @access     SIO->BSM446.bit.VAL
 *  @brief      
 */
#define BSM446_ALL_VAL_Pos (0)
#define BSM446_ALL_VAL_Msk (0xFFFFFFUL << BSM446_ALL_VAL_Pos)

#define BSM446_BIT_VAL

#define BSM446_ALL_VAL_(x) ((x) << BSM446_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM447          VAL
 *  @access     SIO->BSM447.bit.VAL
 *  @brief      
 */
#define BSM447_ALL_VAL_Pos (0)
#define BSM447_ALL_VAL_Msk (0xFFFFFFUL << BSM447_ALL_VAL_Pos)

#define BSM447_BIT_VAL

#define BSM447_ALL_VAL_(x) ((x) << BSM447_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM448          VAL
 *  @access     SIO->BSM448.bit.VAL
 *  @brief      
 */
#define BSM448_ALL_VAL_Pos (0)
#define BSM448_ALL_VAL_Msk (0xFFFFFFUL << BSM448_ALL_VAL_Pos)

#define BSM448_BIT_VAL

#define BSM448_ALL_VAL_(x) ((x) << BSM448_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM449          VAL
 *  @access     SIO->BSM449.bit.VAL
 *  @brief      
 */
#define BSM449_ALL_VAL_Pos (0)
#define BSM449_ALL_VAL_Msk (0xFFFFFFUL << BSM449_ALL_VAL_Pos)

#define BSM449_BIT_VAL

#define BSM449_ALL_VAL_(x) ((x) << BSM449_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM450          VAL
 *  @access     SIO->BSM450.bit.VAL
 *  @brief      
 */
#define BSM450_ALL_VAL_Pos (0)
#define BSM450_ALL_VAL_Msk (0xFFFFFFUL << BSM450_ALL_VAL_Pos)

#define BSM450_BIT_VAL

#define BSM450_ALL_VAL_(x) ((x) << BSM450_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM451          VAL
 *  @access     SIO->BSM451.bit.VAL
 *  @brief      
 */
#define BSM451_ALL_VAL_Pos (0)
#define BSM451_ALL_VAL_Msk (0xFFFFFFUL << BSM451_ALL_VAL_Pos)

#define BSM451_BIT_VAL

#define BSM451_ALL_VAL_(x) ((x) << BSM451_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM452          VAL
 *  @access     SIO->BSM452.bit.VAL
 *  @brief      
 */
#define BSM452_ALL_VAL_Pos (0)
#define BSM452_ALL_VAL_Msk (0xFFFFFFUL << BSM452_ALL_VAL_Pos)

#define BSM452_BIT_VAL

#define BSM452_ALL_VAL_(x) ((x) << BSM452_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM453          VAL
 *  @access     SIO->BSM453.bit.VAL
 *  @brief      
 */
#define BSM453_ALL_VAL_Pos (0)
#define BSM453_ALL_VAL_Msk (0xFFFFFFUL << BSM453_ALL_VAL_Pos)

#define BSM453_BIT_VAL

#define BSM453_ALL_VAL_(x) ((x) << BSM453_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM454          VAL
 *  @access     SIO->BSM454.bit.VAL
 *  @brief      
 */
#define BSM454_ALL_VAL_Pos (0)
#define BSM454_ALL_VAL_Msk (0xFFFFFFUL << BSM454_ALL_VAL_Pos)

#define BSM454_BIT_VAL

#define BSM454_ALL_VAL_(x) ((x) << BSM454_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM455          VAL
 *  @access     SIO->BSM455.bit.VAL
 *  @brief      
 */
#define BSM455_ALL_VAL_Pos (0)
#define BSM455_ALL_VAL_Msk (0xFFFFFFUL << BSM455_ALL_VAL_Pos)

#define BSM455_BIT_VAL

#define BSM455_ALL_VAL_(x) ((x) << BSM455_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM456          VAL
 *  @access     SIO->BSM456.bit.VAL
 *  @brief      
 */
#define BSM456_ALL_VAL_Pos (0)
#define BSM456_ALL_VAL_Msk (0xFFFFFFUL << BSM456_ALL_VAL_Pos)

#define BSM456_BIT_VAL

#define BSM456_ALL_VAL_(x) ((x) << BSM456_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM457          VAL
 *  @access     SIO->BSM457.bit.VAL
 *  @brief      
 */
#define BSM457_ALL_VAL_Pos (0)
#define BSM457_ALL_VAL_Msk (0xFFFFFFUL << BSM457_ALL_VAL_Pos)

#define BSM457_BIT_VAL

#define BSM457_ALL_VAL_(x) ((x) << BSM457_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM458          VAL
 *  @access     SIO->BSM458.bit.VAL
 *  @brief      
 */
#define BSM458_ALL_VAL_Pos (0)
#define BSM458_ALL_VAL_Msk (0xFFFFFFUL << BSM458_ALL_VAL_Pos)

#define BSM458_BIT_VAL

#define BSM458_ALL_VAL_(x) ((x) << BSM458_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM459          VAL
 *  @access     SIO->BSM459.bit.VAL
 *  @brief      
 */
#define BSM459_ALL_VAL_Pos (0)
#define BSM459_ALL_VAL_Msk (0xFFFFFFUL << BSM459_ALL_VAL_Pos)

#define BSM459_BIT_VAL

#define BSM459_ALL_VAL_(x) ((x) << BSM459_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM460          VAL
 *  @access     SIO->BSM460.bit.VAL
 *  @brief      
 */
#define BSM460_ALL_VAL_Pos (0)
#define BSM460_ALL_VAL_Msk (0xFFFFFFUL << BSM460_ALL_VAL_Pos)

#define BSM460_BIT_VAL

#define BSM460_ALL_VAL_(x) ((x) << BSM460_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM461          VAL
 *  @access     SIO->BSM461.bit.VAL
 *  @brief      
 */
#define BSM461_ALL_VAL_Pos (0)
#define BSM461_ALL_VAL_Msk (0xFFFFFFUL << BSM461_ALL_VAL_Pos)

#define BSM461_BIT_VAL

#define BSM461_ALL_VAL_(x) ((x) << BSM461_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM462          VAL
 *  @access     SIO->BSM462.bit.VAL
 *  @brief      
 */
#define BSM462_ALL_VAL_Pos (0)
#define BSM462_ALL_VAL_Msk (0xFFFFFFUL << BSM462_ALL_VAL_Pos)

#define BSM462_BIT_VAL

#define BSM462_ALL_VAL_(x) ((x) << BSM462_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM463          VAL
 *  @access     SIO->BSM463.bit.VAL
 *  @brief      
 */
#define BSM463_ALL_VAL_Pos (0)
#define BSM463_ALL_VAL_Msk (0xFFFFFFUL << BSM463_ALL_VAL_Pos)

#define BSM463_BIT_VAL

#define BSM463_ALL_VAL_(x) ((x) << BSM463_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM464          VAL
 *  @access     SIO->BSM464.bit.VAL
 *  @brief      
 */
#define BSM464_ALL_VAL_Pos (0)
#define BSM464_ALL_VAL_Msk (0xFFFFFFUL << BSM464_ALL_VAL_Pos)

#define BSM464_BIT_VAL

#define BSM464_ALL_VAL_(x) ((x) << BSM464_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM465          VAL
 *  @access     SIO->BSM465.bit.VAL
 *  @brief      
 */
#define BSM465_ALL_VAL_Pos (0)
#define BSM465_ALL_VAL_Msk (0xFFFFFFUL << BSM465_ALL_VAL_Pos)

#define BSM465_BIT_VAL

#define BSM465_ALL_VAL_(x) ((x) << BSM465_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM466          VAL
 *  @access     SIO->BSM466.bit.VAL
 *  @brief      
 */
#define BSM466_ALL_VAL_Pos (0)
#define BSM466_ALL_VAL_Msk (0xFFFFFFUL << BSM466_ALL_VAL_Pos)

#define BSM466_BIT_VAL

#define BSM466_ALL_VAL_(x) ((x) << BSM466_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM467          VAL
 *  @access     SIO->BSM467.bit.VAL
 *  @brief      
 */
#define BSM467_ALL_VAL_Pos (0)
#define BSM467_ALL_VAL_Msk (0xFFFFFFUL << BSM467_ALL_VAL_Pos)

#define BSM467_BIT_VAL

#define BSM467_ALL_VAL_(x) ((x) << BSM467_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM468          VAL
 *  @access     SIO->BSM468.bit.VAL
 *  @brief      
 */
#define BSM468_ALL_VAL_Pos (0)
#define BSM468_ALL_VAL_Msk (0xFFFFFFUL << BSM468_ALL_VAL_Pos)

#define BSM468_BIT_VAL

#define BSM468_ALL_VAL_(x) ((x) << BSM468_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM469          VAL
 *  @access     SIO->BSM469.bit.VAL
 *  @brief      
 */
#define BSM469_ALL_VAL_Pos (0)
#define BSM469_ALL_VAL_Msk (0xFFFFFFUL << BSM469_ALL_VAL_Pos)

#define BSM469_BIT_VAL

#define BSM469_ALL_VAL_(x) ((x) << BSM469_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM470          VAL
 *  @access     SIO->BSM470.bit.VAL
 *  @brief      
 */
#define BSM470_ALL_VAL_Pos (0)
#define BSM470_ALL_VAL_Msk (0xFFFFFFUL << BSM470_ALL_VAL_Pos)

#define BSM470_BIT_VAL

#define BSM470_ALL_VAL_(x) ((x) << BSM470_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM471          VAL
 *  @access     SIO->BSM471.bit.VAL
 *  @brief      
 */
#define BSM471_ALL_VAL_Pos (0)
#define BSM471_ALL_VAL_Msk (0xFFFFFFUL << BSM471_ALL_VAL_Pos)

#define BSM471_BIT_VAL

#define BSM471_ALL_VAL_(x) ((x) << BSM471_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM472          VAL
 *  @access     SIO->BSM472.bit.VAL
 *  @brief      
 */
#define BSM472_ALL_VAL_Pos (0)
#define BSM472_ALL_VAL_Msk (0xFFFFFFUL << BSM472_ALL_VAL_Pos)

#define BSM472_BIT_VAL

#define BSM472_ALL_VAL_(x) ((x) << BSM472_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM473          VAL
 *  @access     SIO->BSM473.bit.VAL
 *  @brief      
 */
#define BSM473_ALL_VAL_Pos (0)
#define BSM473_ALL_VAL_Msk (0xFFFFFFUL << BSM473_ALL_VAL_Pos)

#define BSM473_BIT_VAL

#define BSM473_ALL_VAL_(x) ((x) << BSM473_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM474          VAL
 *  @access     SIO->BSM474.bit.VAL
 *  @brief      
 */
#define BSM474_ALL_VAL_Pos (0)
#define BSM474_ALL_VAL_Msk (0xFFFFFFUL << BSM474_ALL_VAL_Pos)

#define BSM474_BIT_VAL

#define BSM474_ALL_VAL_(x) ((x) << BSM474_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM475          VAL
 *  @access     SIO->BSM475.bit.VAL
 *  @brief      
 */
#define BSM475_ALL_VAL_Pos (0)
#define BSM475_ALL_VAL_Msk (0xFFFFFFUL << BSM475_ALL_VAL_Pos)

#define BSM475_BIT_VAL

#define BSM475_ALL_VAL_(x) ((x) << BSM475_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM476          VAL
 *  @access     SIO->BSM476.bit.VAL
 *  @brief      
 */
#define BSM476_ALL_VAL_Pos (0)
#define BSM476_ALL_VAL_Msk (0xFFFFFFUL << BSM476_ALL_VAL_Pos)

#define BSM476_BIT_VAL

#define BSM476_ALL_VAL_(x) ((x) << BSM476_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM477          VAL
 *  @access     SIO->BSM477.bit.VAL
 *  @brief      
 */
#define BSM477_ALL_VAL_Pos (0)
#define BSM477_ALL_VAL_Msk (0xFFFFFFUL << BSM477_ALL_VAL_Pos)

#define BSM477_BIT_VAL

#define BSM477_ALL_VAL_(x) ((x) << BSM477_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM478          VAL
 *  @access     SIO->BSM478.bit.VAL
 *  @brief      
 */
#define BSM478_ALL_VAL_Pos (0)
#define BSM478_ALL_VAL_Msk (0xFFFFFFUL << BSM478_ALL_VAL_Pos)

#define BSM478_BIT_VAL

#define BSM478_ALL_VAL_(x) ((x) << BSM478_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM479          VAL
 *  @access     SIO->BSM479.bit.VAL
 *  @brief      
 */
#define BSM479_ALL_VAL_Pos (0)
#define BSM479_ALL_VAL_Msk (0xFFFFFFUL << BSM479_ALL_VAL_Pos)

#define BSM479_BIT_VAL

#define BSM479_ALL_VAL_(x) ((x) << BSM479_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM480          VAL
 *  @access     SIO->BSM480.bit.VAL
 *  @brief      
 */
#define BSM480_ALL_VAL_Pos (0)
#define BSM480_ALL_VAL_Msk (0xFFFFFFUL << BSM480_ALL_VAL_Pos)

#define BSM480_BIT_VAL

#define BSM480_ALL_VAL_(x) ((x) << BSM480_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM481          VAL
 *  @access     SIO->BSM481.bit.VAL
 *  @brief      
 */
#define BSM481_ALL_VAL_Pos (0)
#define BSM481_ALL_VAL_Msk (0xFFFFFFUL << BSM481_ALL_VAL_Pos)

#define BSM481_BIT_VAL

#define BSM481_ALL_VAL_(x) ((x) << BSM481_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM482          VAL
 *  @access     SIO->BSM482.bit.VAL
 *  @brief      
 */
#define BSM482_ALL_VAL_Pos (0)
#define BSM482_ALL_VAL_Msk (0xFFFFFFUL << BSM482_ALL_VAL_Pos)

#define BSM482_BIT_VAL

#define BSM482_ALL_VAL_(x) ((x) << BSM482_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM483          VAL
 *  @access     SIO->BSM483.bit.VAL
 *  @brief      
 */
#define BSM483_ALL_VAL_Pos (0)
#define BSM483_ALL_VAL_Msk (0xFFFFFFUL << BSM483_ALL_VAL_Pos)

#define BSM483_BIT_VAL

#define BSM483_ALL_VAL_(x) ((x) << BSM483_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM484          VAL
 *  @access     SIO->BSM484.bit.VAL
 *  @brief      
 */
#define BSM484_ALL_VAL_Pos (0)
#define BSM484_ALL_VAL_Msk (0xFFFFFFUL << BSM484_ALL_VAL_Pos)

#define BSM484_BIT_VAL

#define BSM484_ALL_VAL_(x) ((x) << BSM484_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM485          VAL
 *  @access     SIO->BSM485.bit.VAL
 *  @brief      
 */
#define BSM485_ALL_VAL_Pos (0)
#define BSM485_ALL_VAL_Msk (0xFFFFFFUL << BSM485_ALL_VAL_Pos)

#define BSM485_BIT_VAL

#define BSM485_ALL_VAL_(x) ((x) << BSM485_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM486          VAL
 *  @access     SIO->BSM486.bit.VAL
 *  @brief      
 */
#define BSM486_ALL_VAL_Pos (0)
#define BSM486_ALL_VAL_Msk (0xFFFFFFUL << BSM486_ALL_VAL_Pos)

#define BSM486_BIT_VAL

#define BSM486_ALL_VAL_(x) ((x) << BSM486_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM487          VAL
 *  @access     SIO->BSM487.bit.VAL
 *  @brief      
 */
#define BSM487_ALL_VAL_Pos (0)
#define BSM487_ALL_VAL_Msk (0xFFFFFFUL << BSM487_ALL_VAL_Pos)

#define BSM487_BIT_VAL

#define BSM487_ALL_VAL_(x) ((x) << BSM487_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM488          VAL
 *  @access     SIO->BSM488.bit.VAL
 *  @brief      
 */
#define BSM488_ALL_VAL_Pos (0)
#define BSM488_ALL_VAL_Msk (0xFFFFFFUL << BSM488_ALL_VAL_Pos)

#define BSM488_BIT_VAL

#define BSM488_ALL_VAL_(x) ((x) << BSM488_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM489          VAL
 *  @access     SIO->BSM489.bit.VAL
 *  @brief      
 */
#define BSM489_ALL_VAL_Pos (0)
#define BSM489_ALL_VAL_Msk (0xFFFFFFUL << BSM489_ALL_VAL_Pos)

#define BSM489_BIT_VAL

#define BSM489_ALL_VAL_(x) ((x) << BSM489_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM490          VAL
 *  @access     SIO->BSM490.bit.VAL
 *  @brief      
 */
#define BSM490_ALL_VAL_Pos (0)
#define BSM490_ALL_VAL_Msk (0xFFFFFFUL << BSM490_ALL_VAL_Pos)

#define BSM490_BIT_VAL

#define BSM490_ALL_VAL_(x) ((x) << BSM490_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM491          VAL
 *  @access     SIO->BSM491.bit.VAL
 *  @brief      
 */
#define BSM491_ALL_VAL_Pos (0)
#define BSM491_ALL_VAL_Msk (0xFFFFFFUL << BSM491_ALL_VAL_Pos)

#define BSM491_BIT_VAL

#define BSM491_ALL_VAL_(x) ((x) << BSM491_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM492          VAL
 *  @access     SIO->BSM492.bit.VAL
 *  @brief      
 */
#define BSM492_ALL_VAL_Pos (0)
#define BSM492_ALL_VAL_Msk (0xFFFFFFUL << BSM492_ALL_VAL_Pos)

#define BSM492_BIT_VAL

#define BSM492_ALL_VAL_(x) ((x) << BSM492_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM493          VAL
 *  @access     SIO->BSM493.bit.VAL
 *  @brief      
 */
#define BSM493_ALL_VAL_Pos (0)
#define BSM493_ALL_VAL_Msk (0xFFFFFFUL << BSM493_ALL_VAL_Pos)

#define BSM493_BIT_VAL

#define BSM493_ALL_VAL_(x) ((x) << BSM493_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM494          VAL
 *  @access     SIO->BSM494.bit.VAL
 *  @brief      
 */
#define BSM494_ALL_VAL_Pos (0)
#define BSM494_ALL_VAL_Msk (0xFFFFFFUL << BSM494_ALL_VAL_Pos)

#define BSM494_BIT_VAL

#define BSM494_ALL_VAL_(x) ((x) << BSM494_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM495          VAL
 *  @access     SIO->BSM495.bit.VAL
 *  @brief      
 */
#define BSM495_ALL_VAL_Pos (0)
#define BSM495_ALL_VAL_Msk (0xFFFFFFUL << BSM495_ALL_VAL_Pos)

#define BSM495_BIT_VAL

#define BSM495_ALL_VAL_(x) ((x) << BSM495_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM496          VAL
 *  @access     SIO->BSM496.bit.VAL
 *  @brief      
 */
#define BSM496_ALL_VAL_Pos (0)
#define BSM496_ALL_VAL_Msk (0xFFFFFFUL << BSM496_ALL_VAL_Pos)

#define BSM496_BIT_VAL

#define BSM496_ALL_VAL_(x) ((x) << BSM496_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM497          VAL
 *  @access     SIO->BSM497.bit.VAL
 *  @brief      
 */
#define BSM497_ALL_VAL_Pos (0)
#define BSM497_ALL_VAL_Msk (0xFFFFFFUL << BSM497_ALL_VAL_Pos)

#define BSM497_BIT_VAL

#define BSM497_ALL_VAL_(x) ((x) << BSM497_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM498          VAL
 *  @access     SIO->BSM498.bit.VAL
 *  @brief      
 */
#define BSM498_ALL_VAL_Pos (0)
#define BSM498_ALL_VAL_Msk (0xFFFFFFUL << BSM498_ALL_VAL_Pos)

#define BSM498_BIT_VAL

#define BSM498_ALL_VAL_(x) ((x) << BSM498_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM499          VAL
 *  @access     SIO->BSM499.bit.VAL
 *  @brief      
 */
#define BSM499_ALL_VAL_Pos (0)
#define BSM499_ALL_VAL_Msk (0xFFFFFFUL << BSM499_ALL_VAL_Pos)

#define BSM499_BIT_VAL

#define BSM499_ALL_VAL_(x) ((x) << BSM499_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM500          VAL
 *  @access     SIO->BSM500.bit.VAL
 *  @brief      
 */
#define BSM500_ALL_VAL_Pos (0)
#define BSM500_ALL_VAL_Msk (0xFFFFFFUL << BSM500_ALL_VAL_Pos)

#define BSM500_BIT_VAL

#define BSM500_ALL_VAL_(x) ((x) << BSM500_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM501          VAL
 *  @access     SIO->BSM501.bit.VAL
 *  @brief      
 */
#define BSM501_ALL_VAL_Pos (0)
#define BSM501_ALL_VAL_Msk (0xFFFFFFUL << BSM501_ALL_VAL_Pos)

#define BSM501_BIT_VAL

#define BSM501_ALL_VAL_(x) ((x) << BSM501_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM502          VAL
 *  @access     SIO->BSM502.bit.VAL
 *  @brief      
 */
#define BSM502_ALL_VAL_Pos (0)
#define BSM502_ALL_VAL_Msk (0xFFFFFFUL << BSM502_ALL_VAL_Pos)

#define BSM502_BIT_VAL

#define BSM502_ALL_VAL_(x) ((x) << BSM502_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM503          VAL
 *  @access     SIO->BSM503.bit.VAL
 *  @brief      
 */
#define BSM503_ALL_VAL_Pos (0)
#define BSM503_ALL_VAL_Msk (0xFFFFFFUL << BSM503_ALL_VAL_Pos)

#define BSM503_BIT_VAL

#define BSM503_ALL_VAL_(x) ((x) << BSM503_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM504          VAL
 *  @access     SIO->BSM504.bit.VAL
 *  @brief      
 */
#define BSM504_ALL_VAL_Pos (0)
#define BSM504_ALL_VAL_Msk (0xFFFFFFUL << BSM504_ALL_VAL_Pos)

#define BSM504_BIT_VAL

#define BSM504_ALL_VAL_(x) ((x) << BSM504_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM505          VAL
 *  @access     SIO->BSM505.bit.VAL
 *  @brief      
 */
#define BSM505_ALL_VAL_Pos (0)
#define BSM505_ALL_VAL_Msk (0xFFFFFFUL << BSM505_ALL_VAL_Pos)

#define BSM505_BIT_VAL

#define BSM505_ALL_VAL_(x) ((x) << BSM505_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM506          VAL
 *  @access     SIO->BSM506.bit.VAL
 *  @brief      
 */
#define BSM506_ALL_VAL_Pos (0)
#define BSM506_ALL_VAL_Msk (0xFFFFFFUL << BSM506_ALL_VAL_Pos)

#define BSM506_BIT_VAL

#define BSM506_ALL_VAL_(x) ((x) << BSM506_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM507          VAL
 *  @access     SIO->BSM507.bit.VAL
 *  @brief      
 */
#define BSM507_ALL_VAL_Pos (0)
#define BSM507_ALL_VAL_Msk (0xFFFFFFUL << BSM507_ALL_VAL_Pos)

#define BSM507_BIT_VAL

#define BSM507_ALL_VAL_(x) ((x) << BSM507_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM508          VAL
 *  @access     SIO->BSM508.bit.VAL
 *  @brief      
 */
#define BSM508_ALL_VAL_Pos (0)
#define BSM508_ALL_VAL_Msk (0xFFFFFFUL << BSM508_ALL_VAL_Pos)

#define BSM508_BIT_VAL

#define BSM508_ALL_VAL_(x) ((x) << BSM508_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM509          VAL
 *  @access     SIO->BSM509.bit.VAL
 *  @brief      
 */
#define BSM509_ALL_VAL_Pos (0)
#define BSM509_ALL_VAL_Msk (0xFFFFFFUL << BSM509_ALL_VAL_Pos)

#define BSM509_BIT_VAL

#define BSM509_ALL_VAL_(x) ((x) << BSM509_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM510          VAL
 *  @access     SIO->BSM510.bit.VAL
 *  @brief      
 */
#define BSM510_ALL_VAL_Pos (0)
#define BSM510_ALL_VAL_Msk (0xFFFFFFUL << BSM510_ALL_VAL_Pos)

#define BSM510_BIT_VAL

#define BSM510_ALL_VAL_(x) ((x) << BSM510_ALL_VAL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   SIO             BSM511          VAL
 *  @access     SIO->BSM511.bit.VAL
 *  @brief      
 */
#define BSM511_ALL_VAL_Pos (0)
#define BSM511_ALL_VAL_Msk (0xFFFFFFUL << BSM511_ALL_VAL_Pos)

#define BSM511_BIT_VAL

#define BSM511_ALL_VAL_(x) ((x) << BSM511_ALL_VAL_Pos)



#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* SPC1168_REG_H */


#endif /* __SPC1168_REG_H__ */


/************  (C) COPYRIGHT 2021 SPINTROL LIMITED ******* END OF FILE ***/



