/**************************************************************************//**
 * @file     gatedrv.h
 * @brief    GATEDRV module header file.
 * @version  VXX.XX.XX
 * @date     XX-XXX-XXXX
 *
 * @note
 * Copyright (C) 2022 Spintrol Electronic Technology (Shanghai) Co., Ltd.. All rights reserved.
 *
 * @attention
 * THIS SOFTWARE JUST PROVIDES CUSTOMERS WITH CODING INFORMATION REGARDING 
 * THEIR PRODUCTS, WHICH AIMS AT SAVING TIME FOR THEM. SPINTROL SHALL NOT BE
 * LIABLE FOR THE USE OF THE SOFTWARE. SPINTROL DOES NOT GUARANTEE THE 
 * CORRECTNESS OF THIS SOFTWARE AND RESERVES THE RIGHT TO MODIFY THE SOFTWARE 
 * WITHOUT NOTIFICATION.
 *
 ******************************************************************************/

#ifndef GATEDRV_H
#define GATEDRV_H

#ifdef __cplusplus
extern "C" {
#endif


#include "spc1068.h"




/*******************************************************************************
*
* Module Name     GATEDRV
*
******************************************************************************/





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS0          BUCKPFMMODE
 *  @access 
 *  @brief  Buck PFM mode flag
 */
#define GLBSTS0_ALL_BUCKPFMMODE_Pos (4)
#define GLBSTS0_ALL_BUCKPFMMODE_Msk (0x1ul << GLBSTS0_ALL_BUCKPFMMODE_Pos)

#define GLBSTS0_ALL_BUCKPFMMODE_PFM_MODE    (0ul << GLBSTS0_ALL_BUCKPFMMODE_Pos)
#define GLBSTS0_ALL_BUCKPFMMODE_PWM_MODE    (1ul << GLBSTS0_ALL_BUCKPFMMODE_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS0          CPRDY
 *  @access 
 *  @brief  Charge-pump ready flag
 */
#define GLBSTS0_ALL_CPRDY_Pos (3)
#define GLBSTS0_ALL_CPRDY_Msk (0x1ul << GLBSTS0_ALL_CPRDY_Pos)

#define GLBSTS0_ALL_CPRDY_NOT_READY     (0ul << GLBSTS0_ALL_CPRDY_Pos)
#define GLBSTS0_ALL_CPRDY_READY         (1ul << GLBSTS0_ALL_CPRDY_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS0          VDDGRDY
 *  @access 
 *  @brief  VDDG ready flag
 */
#define GLBSTS0_ALL_VDDGRDY_Pos (2)
#define GLBSTS0_ALL_VDDGRDY_Msk (0x1ul << GLBSTS0_ALL_VDDGRDY_Pos)

#define GLBSTS0_ALL_VDDGRDY_NOT_READY     (0ul << GLBSTS0_ALL_VDDGRDY_Pos)
#define GLBSTS0_ALL_VDDGRDY_READY         (1ul << GLBSTS0_ALL_VDDGRDY_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS0          VDD5RDY
 *  @access 
 *  @brief  VDD5 ready flag
 */
#define GLBSTS0_ALL_VDD5RDY_Pos (1)
#define GLBSTS0_ALL_VDD5RDY_Msk (0x1ul << GLBSTS0_ALL_VDD5RDY_Pos)

#define GLBSTS0_ALL_VDD5RDY_NOT_READY     (0ul << GLBSTS0_ALL_VDD5RDY_Pos)
#define GLBSTS0_ALL_VDD5RDY_READY         (1ul << GLBSTS0_ALL_VDD5RDY_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS0          VDD3P3RDY
 *  @access 
 *  @brief  VDD3P3 ready flag
 */
#define GLBSTS0_ALL_VDD3P3RDY_Pos (0)
#define GLBSTS0_ALL_VDD3P3RDY_Msk (0x1ul << GLBSTS0_ALL_VDD3P3RDY_Pos)

#define GLBSTS0_ALL_VDD3P3RDY_NOT_READY     (0ul << GLBSTS0_ALL_VDD3P3RDY_Pos)
#define GLBSTS0_ALL_VDD3P3RDY_READY         (1ul << GLBSTS0_ALL_VDD3P3RDY_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS1          OE
 *  @access 
 *  @brief  Predriver output enabled flag
 */
#define GLBSTS1_ALL_OE_Pos (6)
#define GLBSTS1_ALL_OE_Msk (0x1ul << GLBSTS1_ALL_OE_Pos)

#define GLBSTS1_ALL_OE_PRE_DRIVER_OUTPUT_DISABLED     (0ul << GLBSTS1_ALL_OE_Pos)
#define GLBSTS1_ALL_OE_PRE_DRIVER_OUTPUT_ENABLED      (1ul << GLBSTS1_ALL_OE_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS1          HFET2OFF
 *  @access 
 *  @brief  High-side FET2 turned-off flag
 */
#define GLBSTS1_ALL_HFET2OFF_Pos (5)
#define GLBSTS1_ALL_HFET2OFF_Msk (0x1ul << GLBSTS1_ALL_HFET2OFF_Pos)

#define GLBSTS1_ALL_HFET2OFF_ON     (0ul << GLBSTS1_ALL_HFET2OFF_Pos)
#define GLBSTS1_ALL_HFET2OFF_OFF    (1ul << GLBSTS1_ALL_HFET2OFF_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS1          HFET1OFF
 *  @access 
 *  @brief  High-side FET1 turned-off flag
 */
#define GLBSTS1_ALL_HFET1OFF_Pos (4)
#define GLBSTS1_ALL_HFET1OFF_Msk (0x1ul << GLBSTS1_ALL_HFET1OFF_Pos)

#define GLBSTS1_ALL_HFET1OFF_ON     (0ul << GLBSTS1_ALL_HFET1OFF_Pos)
#define GLBSTS1_ALL_HFET1OFF_OFF    (1ul << GLBSTS1_ALL_HFET1OFF_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS1          HFET0OFF
 *  @access 
 *  @brief  High-side FET0 turned-off flag
 */
#define GLBSTS1_ALL_HFET0OFF_Pos (3)
#define GLBSTS1_ALL_HFET0OFF_Msk (0x1ul << GLBSTS1_ALL_HFET0OFF_Pos)

#define GLBSTS1_ALL_HFET0OFF_ON     (0ul << GLBSTS1_ALL_HFET0OFF_Pos)
#define GLBSTS1_ALL_HFET0OFF_OFF    (1ul << GLBSTS1_ALL_HFET0OFF_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS1          LFET2OFF
 *  @access 
 *  @brief  Low-side FET2 turned-off flag
 */
#define GLBSTS1_ALL_LFET2OFF_Pos (2)
#define GLBSTS1_ALL_LFET2OFF_Msk (0x1ul << GLBSTS1_ALL_LFET2OFF_Pos)

#define GLBSTS1_ALL_LFET2OFF_ON     (0ul << GLBSTS1_ALL_LFET2OFF_Pos)
#define GLBSTS1_ALL_LFET2OFF_OFF    (1ul << GLBSTS1_ALL_LFET2OFF_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS1          LFET1OFF
 *  @access 
 *  @brief  Low-side FET1 turned-off flag
 */
#define GLBSTS1_ALL_LFET1OFF_Pos (1)
#define GLBSTS1_ALL_LFET1OFF_Msk (0x1ul << GLBSTS1_ALL_LFET1OFF_Pos)

#define GLBSTS1_ALL_LFET1OFF_ON     (0ul << GLBSTS1_ALL_LFET1OFF_Pos)
#define GLBSTS1_ALL_LFET1OFF_OFF    (1ul << GLBSTS1_ALL_LFET1OFF_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GLBSTS1          LFET0OFF
 *  @access 
 *  @brief  Low-side FET0 turned-off flag
 */
#define GLBSTS1_ALL_LFET0OFF_Pos (0)
#define GLBSTS1_ALL_LFET0OFF_Msk (0x1ul << GLBSTS1_ALL_LFET0OFF_Pos)

#define GLBSTS1_ALL_LFET0OFF_ON     (0ul << GLBSTS1_ALL_LFET0OFF_Pos)
#define GLBSTS1_ALL_LFET0OFF_OFF    (1ul << GLBSTS1_ALL_LFET0OFF_Pos)









/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS0        HFET2OC
 *  @access 
 *  @brief  High-side FET2 over-current flag
 */
#define FAULTSTS0_ALL_HFET2OC_Pos (7)
#define FAULTSTS0_ALL_HFET2OC_Msk (0x1ul << FAULTSTS0_ALL_HFET2OC_Pos)

#define FAULTSTS0_ALL_HFET2OC_NOT_OCCUR   (0ul << FAULTSTS0_ALL_HFET2OC_Pos)
#define FAULTSTS0_ALL_HFET2OC_OCCUR       (1ul << FAULTSTS0_ALL_HFET2OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS0        HFET1OC
 *  @access 
 *  @brief  High-side FET1 over-current flag
 */
#define FAULTSTS0_ALL_HFET1OC_Pos (6)
#define FAULTSTS0_ALL_HFET1OC_Msk (0x1ul << FAULTSTS0_ALL_HFET1OC_Pos)

#define FAULTSTS0_ALL_HFET1OC_NOT_OCCUR   (0ul << FAULTSTS0_ALL_HFET1OC_Pos)
#define FAULTSTS0_ALL_HFET1OC_OCCUR       (1ul << FAULTSTS0_ALL_HFET1OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS0        HFET0OC
 *  @access 
 *  @brief  High-side FET0 over-current flag
 */
#define FAULTSTS0_ALL_HFET0OC_Pos (5)
#define FAULTSTS0_ALL_HFET0OC_Msk (0x1ul << FAULTSTS0_ALL_HFET0OC_Pos)

#define FAULTSTS0_ALL_HFET0OC_NOT_OCCUR   (0ul << FAULTSTS0_ALL_HFET0OC_Pos)
#define FAULTSTS0_ALL_HFET0OC_OCCUR       (1ul << FAULTSTS0_ALL_HFET0OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS0        LFET2OC
 *  @access 
 *  @brief  Low-side FET2 over-current flag
 */
#define FAULTSTS0_ALL_LFET2OC_Pos (4)
#define FAULTSTS0_ALL_LFET2OC_Msk (0x1ul << FAULTSTS0_ALL_LFET2OC_Pos)

#define FAULTSTS0_ALL_LFET2OC_NOT_OCCUR   (0ul << FAULTSTS0_ALL_LFET2OC_Pos)
#define FAULTSTS0_ALL_LFET2OC_OCCUR       (1ul << FAULTSTS0_ALL_LFET2OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS0        LFET1OC
 *  @access 
 *  @brief  Low-side FET1 over-current flag
 */
#define FAULTSTS0_ALL_LFET1OC_Pos (3)
#define FAULTSTS0_ALL_LFET1OC_Msk (0x1ul << FAULTSTS0_ALL_LFET1OC_Pos)

#define FAULTSTS0_ALL_LFET1OC_NOT_OCCUR   (0ul << FAULTSTS0_ALL_LFET1OC_Pos)
#define FAULTSTS0_ALL_LFET1OC_OCCUR       (1ul << FAULTSTS0_ALL_LFET1OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS0        LFET0OC
 *  @access 
 *  @brief  Low-side FET0 over-current flag
 */
#define FAULTSTS0_ALL_LFET0OC_Pos (2)
#define FAULTSTS0_ALL_LFET0OC_Msk (0x1ul << FAULTSTS0_ALL_LFET0OC_Pos)

#define FAULTSTS0_ALL_LFET0OC_NOT_OCCUR   (0ul << FAULTSTS0_ALL_LFET0OC_Pos)
#define FAULTSTS0_ALL_LFET0OC_OCCUR       (1ul << FAULTSTS0_ALL_LFET0OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS0        VDDGTOOHI
 *  @access 
 *  @brief  VDDG too high flag
 */
#define FAULTSTS0_ALL_VDDGTOOHI_Pos (1)
#define FAULTSTS0_ALL_VDDGTOOHI_Msk (0x1ul << FAULTSTS0_ALL_VDDGTOOHI_Pos)

#define FAULTSTS0_ALL_VDDGTOOHI_NOT_OCCUR   (0ul << FAULTSTS0_ALL_VDDGTOOHI_Pos)
#define FAULTSTS0_ALL_VDDGTOOHI_OCCUR       (1ul << FAULTSTS0_ALL_VDDGTOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV          FAULTSTS0        VDDGTOOLO
 *  @access 
 *  @brief  VDDG too low flag
 */
#define FAULTSTS0_ALL_VDDGTOOLO_Pos (0)
#define FAULTSTS0_ALL_VDDGTOOLO_Msk (0x1ul << FAULTSTS0_ALL_VDDGTOOLO_Pos)

#define FAULTSTS0_ALL_VDDGTOOLO_NOT_OCCUR   (0ul << FAULTSTS0_ALL_VDDGTOOLO_Pos)
#define FAULTSTS0_ALL_VDDGTOOLO_OCCUR       (1ul << FAULTSTS0_ALL_VDDGTOOLO_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS1        PVDD0TOOHI
 *  @access 
 *  @brief  PVDD0 too high flag
 */
#define FAULTSTS1_ALL_PVDD0TOOHI_Pos (7)
#define FAULTSTS1_ALL_PVDD0TOOHI_Msk (0x1ul << FAULTSTS1_ALL_PVDD0TOOHI_Pos)

#define FAULTSTS1_ALL_PVDD0TOOHI_NOT_OCCUR   (0ul << FAULTSTS1_ALL_PVDD0TOOHI_Pos)
#define FAULTSTS1_ALL_PVDD0TOOHI_OCCUR       (1ul << FAULTSTS1_ALL_PVDD0TOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS1        PVDD0TOOLO
 *  @access 
 *  @brief  PVDD0 too low flag
 */
#define FAULTSTS1_ALL_PVDD0TOOLO_Pos (6)
#define FAULTSTS1_ALL_PVDD0TOOLO_Msk (0x1ul << FAULTSTS1_ALL_PVDD0TOOLO_Pos)

#define FAULTSTS1_ALL_PVDD0TOOLO_NOT_OCCUR   (0ul << FAULTSTS1_ALL_PVDD0TOOLO_Pos)
#define FAULTSTS1_ALL_PVDD0TOOLO_OCCUR       (1ul << FAULTSTS1_ALL_PVDD0TOOLO_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS1        PVDD1TOOHI
 *  @access 
 *  @brief  PVDD1 too high flag
 */
#define FAULTSTS1_ALL_PVDD1TOOHI_Pos (5)
#define FAULTSTS1_ALL_PVDD1TOOHI_Msk (0x1ul << FAULTSTS1_ALL_PVDD1TOOHI_Pos)

#define FAULTSTS1_ALL_PVDD1TOOHI_NOT_OCCUR   (0ul << FAULTSTS1_ALL_PVDD1TOOHI_Pos)
#define FAULTSTS1_ALL_PVDD1TOOHI_OCCUR       (1ul << FAULTSTS1_ALL_PVDD1TOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS1        PVDD1TOOLO
 *  @access 
 *  @brief  PVDD1 too low flag
 */
#define FAULTSTS1_ALL_PVDD1TOOLO_Pos (4)
#define FAULTSTS1_ALL_PVDD1TOOLO_Msk (0x1ul << FAULTSTS1_ALL_PVDD1TOOLO_Pos)

#define FAULTSTS1_ALL_PVDD1TOOLO_NOT_OCCUR   (0ul << FAULTSTS1_ALL_PVDD1TOOLO_Pos)
#define FAULTSTS1_ALL_PVDD1TOOLO_OCCUR       (1ul << FAULTSTS1_ALL_PVDD1TOOLO_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS1        PREDRVOTWARN
 *  @access 
 *  @brief  Pre-driver over-temperature warnning flag
 */
#define FAULTSTS1_ALL_PREDRVOTWARN_Pos (3)
#define FAULTSTS1_ALL_PREDRVOTWARN_Msk (0x1ul << FAULTSTS1_ALL_PREDRVOTWARN_Pos)

#define FAULTSTS1_ALL_PREDRVOTWARN_NOT_OCCUR   (0ul << FAULTSTS1_ALL_PREDRVOTWARN_Pos)
#define FAULTSTS1_ALL_PREDRVOTWARN_OCCUR       (1ul << FAULTSTS1_ALL_PREDRVOTWARN_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTSTS1        BUCKOTWARN
 *  @access 
 *  @brief  Buck over-temperature warnning flag
 */
#define FAULTSTS1_ALL_BUCKOTWARN_Pos (1)
#define FAULTSTS1_ALL_BUCKOTWARN_Msk (0x1ul << FAULTSTS1_ALL_BUCKOTWARN_Pos)

#define FAULTSTS1_ALL_BUCKOTWARN_NOT_OCCUR   (0ul << FAULTSTS1_ALL_BUCKOTWARN_Pos)
#define FAULTSTS1_ALL_BUCKOTWARN_OCCUR       (1ul << FAULTSTS1_ALL_BUCKOTWARN_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR0        HFET2OC
 *  @access 
 *  @brief  Clear high-side FET2 over-current flag
 */
#define FAULTCLR0_ALL_HFET2OC_Pos (7)
#define FAULTCLR0_ALL_HFET2OC_Msk (0x1ul << FAULTCLR0_ALL_HFET2OC_Pos)

#define FAULTCLR0_ALL_HFET2OC_NO_EFFECT   (0ul << FAULTCLR0_ALL_HFET2OC_Pos)
#define FAULTCLR0_ALL_HFET2OC_CLEAR       (1ul << FAULTCLR0_ALL_HFET2OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR0        HFET1OC
 *  @access 
 *  @brief  Clear high-side FET1 over-current flag
 */
#define FAULTCLR0_ALL_HFET1OC_Pos (6)
#define FAULTCLR0_ALL_HFET1OC_Msk (0x1ul << FAULTCLR0_ALL_HFET1OC_Pos)

#define FAULTCLR0_ALL_HFET1OC_NO_EFFECT   (0ul << FAULTCLR0_ALL_HFET1OC_Pos)
#define FAULTCLR0_ALL_HFET1OC_CLEAR       (1ul << FAULTCLR0_ALL_HFET1OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR0        HFET0OC
 *  @access 
 *  @brief  Clear high-side FET0 over-current flag
 */
#define FAULTCLR0_ALL_HFET0OC_Pos (5)
#define FAULTCLR0_ALL_HFET0OC_Msk (0x1ul << FAULTCLR0_ALL_HFET0OC_Pos)

#define FAULTCLR0_ALL_HFET0OC_NO_EFFECT   (0ul << FAULTCLR0_ALL_HFET0OC_Pos)
#define FAULTCLR0_ALL_HFET0OC_CLEAR       (1ul << FAULTCLR0_ALL_HFET0OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR0        LFET2OC
 *  @access 
 *  @brief  Clear low-side FET2 over-current flag
 */
#define FAULTCLR0_ALL_LFET2OC_Pos (4)
#define FAULTCLR0_ALL_LFET2OC_Msk (0x1ul << FAULTCLR0_ALL_LFET2OC_Pos)

#define FAULTCLR0_ALL_LFET2OC_NO_EFFECT   (0ul << FAULTCLR0_ALL_LFET2OC_Pos)
#define FAULTCLR0_ALL_LFET2OC_CLEAR       (1ul << FAULTCLR0_ALL_LFET2OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR0        LFET1OC
 *  @access 
 *  @brief  Clear low-side FET1 over-current flag
 */
#define FAULTCLR0_ALL_LFET1OC_Pos (3)
#define FAULTCLR0_ALL_LFET1OC_Msk (0x1ul << FAULTCLR0_ALL_LFET1OC_Pos)

#define FAULTCLR0_ALL_LFET1OC_NO_EFFECT   (0ul << FAULTCLR0_ALL_LFET1OC_Pos)
#define FAULTCLR0_ALL_LFET1OC_CLEAR       (1ul << FAULTCLR0_ALL_LFET1OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR0        LFET0OC
 *  @access 
 *  @brief  Clear low-side FET0 over-current flag
 */
#define FAULTCLR0_ALL_LFET0OC_Pos (2)
#define FAULTCLR0_ALL_LFET0OC_Msk (0x1ul << FAULTCLR0_ALL_LFET0OC_Pos)

#define FAULTCLR0_ALL_LFET0OC_NO_EFFECT   (0ul << FAULTCLR0_ALL_LFET0OC_Pos)
#define FAULTCLR0_ALL_LFET0OC_CLEAR       (1ul << FAULTCLR0_ALL_LFET0OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR0        VDDGTOOHI
 *  @access 
 *  @brief  Clear VDDG too high flag
 */
#define FAULTCLR0_ALL_VDDGTOOHI_Pos (1)
#define FAULTCLR0_ALL_VDDGTOOHI_Msk (0x1ul << FAULTCLR0_ALL_VDDGTOOHI_Pos)

#define FAULTCLR0_ALL_VDDGTOOHI_NO_EFFECT   (0ul << FAULTCLR0_ALL_VDDGTOOHI_Pos)
#define FAULTCLR0_ALL_VDDGTOOHI_CLEAR       (1ul << FAULTCLR0_ALL_VDDGTOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR0        VDDGTOOLO
 *  @access 
 *  @brief  Clear VDDG too low flag
 */
#define FAULTCLR0_ALL_VDDGTOOLO_Pos (0)
#define FAULTCLR0_ALL_VDDGTOOLO_Msk (0x1ul << FAULTCLR0_ALL_VDDGTOOLO_Pos)

#define FAULTCLR0_ALL_VDDGTOOLO_NO_EFFECT   (0ul << FAULTCLR0_ALL_VDDGTOOLO_Pos)
#define FAULTCLR0_ALL_VDDGTOOLO_CLEAR       (1ul << FAULTCLR0_ALL_VDDGTOOLO_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR1        PVDD0TOOHI
 *  @access 
 *  @brief  Clear PVDD0 too high flag
 */
#define FAULTCLR1_ALL_PVDD0TOOHI_Pos (7)
#define FAULTCLR1_ALL_PVDD0TOOHI_Msk (0x1ul << FAULTCLR1_ALL_PVDD0TOOHI_Pos)

#define FAULTCLR1_ALL_PVDD0TOOHI_NO_EFFECT   (0ul << FAULTCLR1_ALL_PVDD0TOOHI_Pos)
#define FAULTCLR1_ALL_PVDD0TOOHI_CLEAR       (1ul << FAULTCLR1_ALL_PVDD0TOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR1        PVDD0TOOLO
 *  @access 
 *  @brief  Clear PVDD0 too low flag
 */
#define FAULTCLR1_ALL_PVDD0TOOLO_Pos (6)
#define FAULTCLR1_ALL_PVDD0TOOLO_Msk (0x1ul << FAULTCLR1_ALL_PVDD0TOOLO_Pos)

#define FAULTCLR1_ALL_PVDD0TOOLO_NO_EFFECT   (0ul << FAULTCLR1_ALL_PVDD0TOOLO_Pos)
#define FAULTCLR1_ALL_PVDD0TOOLO_CLEAR       (1ul << FAULTCLR1_ALL_PVDD0TOOLO_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR1        PVDD1TOOHI
 *  @access 
 *  @brief  Clear PVDD1 too high flag
 */
#define FAULTCLR1_ALL_PVDD1TOOHI_Pos (5)
#define FAULTCLR1_ALL_PVDD1TOOHI_Msk (0x1ul << FAULTCLR1_ALL_PVDD1TOOHI_Pos)

#define FAULTCLR1_ALL_PVDD1TOOHI_NO_EFFECT   (0ul << FAULTCLR1_ALL_PVDD1TOOHI_Pos)
#define FAULTCLR1_ALL_PVDD1TOOHI_CLEAR       (1ul << FAULTCLR1_ALL_PVDD1TOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR1        PVDD1TOOLO
 *  @access 
 *  @brief  Clear PVDD1 too low flag
 */
#define FAULTCLR1_ALL_PVDD1TOOLO_Pos (4)
#define FAULTCLR1_ALL_PVDD1TOOLO_Msk (0x1ul << FAULTCLR1_ALL_PVDD1TOOLO_Pos)

#define FAULTCLR1_ALL_PVDD1TOOLO_NO_EFFECT   (0ul << FAULTCLR1_ALL_PVDD1TOOLO_Pos)
#define FAULTCLR1_ALL_PVDD1TOOLO_CLEAR       (1ul << FAULTCLR1_ALL_PVDD1TOOLO_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR1        PREDRVOTWARN
 *  @access 
 *  @brief  Clear Pre-driver over-temperature warnning flag
 */
#define FAULTCLR1_ALL_PREDRVOTWARN_Pos (3)
#define FAULTCLR1_ALL_PREDRVOTWARN_Msk (0x1ul << FAULTCLR1_ALL_PREDRVOTWARN_Pos)

#define FAULTCLR1_ALL_PREDRVOTWARN_NO_EFFECT   (0ul << FAULTCLR1_ALL_PREDRVOTWARN_Pos)
#define FAULTCLR1_ALL_PREDRVOTWARN_CLEAR       (1ul << FAULTCLR1_ALL_PREDRVOTWARN_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FAULTCLR1        BUCKOTWARN
 *  @access 
 *  @brief  Clear Buck over-temperature warnning flag
 */
#define FAULTCLR1_ALL_BUCKOTWARN_Pos (1)
#define FAULTCLR1_ALL_BUCKOTWARN_Msk (0x1ul << FAULTCLR1_ALL_BUCKOTWARN_Pos)

#define FAULTCLR1_ALL_BUCKOTWARN_NO_EFFECT   (0ul << FAULTCLR1_ALL_BUCKOTWARN_Pos)
#define FAULTCLR1_ALL_BUCKOTWARN_CLEAR       (1ul << FAULTCLR1_ALL_BUCKOTWARN_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL0       HFET2OC
 *  @access 
 *  @brief  Select high-side FET2 over-current flag as fatal fault
 */
#define FFAULTSEL0_ALL_HFET2OC_Pos (7)
#define FFAULTSEL0_ALL_HFET2OC_Msk (0x1ul << FFAULTSEL0_ALL_HFET2OC_Pos)

#define FFAULTSEL0_ALL_HFET2OC_NOT_SELECTE   (0ul << FFAULTSEL0_ALL_HFET2OC_Pos)
#define FFAULTSEL0_ALL_HFET2OC_SELECTE       (1ul << FFAULTSEL0_ALL_HFET2OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL0       HFET1OC
 *  @access 
 *  @brief  Select high-side FET1 over-current flag as fatal fault
 */
#define FFAULTSEL0_ALL_HFET1OC_Pos (6)
#define FFAULTSEL0_ALL_HFET1OC_Msk (0x1ul << FFAULTSEL0_ALL_HFET1OC_Pos)

#define FFAULTSEL0_ALL_HFET1OC_NOT_SELECTE   (0ul << FFAULTSEL0_ALL_HFET1OC_Pos)
#define FFAULTSEL0_ALL_HFET1OC_SELECTE       (1ul << FFAULTSEL0_ALL_HFET1OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL0       HFET0OC
 *  @access 
 *  @brief  Select high-side FET0 over-current flag as fatal fault
 */
#define FFAULTSEL0_ALL_HFET0OC_Pos (5)
#define FFAULTSEL0_ALL_HFET0OC_Msk (0x1ul << FFAULTSEL0_ALL_HFET0OC_Pos)

#define FFAULTSEL0_ALL_HFET0OC_NOT_SELECTE   (0ul << FFAULTSEL0_ALL_HFET0OC_Pos)
#define FFAULTSEL0_ALL_HFET0OC_SELECTE       (1ul << FFAULTSEL0_ALL_HFET0OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL0       LFET2OC
 *  @access 
 *  @brief  Select low-side FET2 over-current flag as fatal fault
 */
#define FFAULTSEL0_ALL_LFET2OC_Pos (4)
#define FFAULTSEL0_ALL_LFET2OC_Msk (0x1ul << FFAULTSEL0_ALL_LFET2OC_Pos)

#define FFAULTSEL0_ALL_LFET2OC_NOT_SELECTE   (0ul << FFAULTSEL0_ALL_LFET2OC_Pos)
#define FFAULTSEL0_ALL_LFET2OC_SELECTE       (1ul << FFAULTSEL0_ALL_LFET2OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL0       LFET1OC
 *  @access 
 *  @brief  Select low-side FET1 over-current flag as fatal fault
 */
#define FFAULTSEL0_ALL_LFET1OC_Pos (3)
#define FFAULTSEL0_ALL_LFET1OC_Msk (0x1ul << FFAULTSEL0_ALL_LFET1OC_Pos)

#define FFAULTSEL0_ALL_LFET1OC_NOT_SELECTE   (0ul << FFAULTSEL0_ALL_LFET1OC_Pos)
#define FFAULTSEL0_ALL_LFET1OC_SELECTE       (1ul << FFAULTSEL0_ALL_LFET1OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL0       LFET0OC
 *  @access 
 *  @brief  Select low-side FET0 over-current flag as fatal fault
 */
#define FFAULTSEL0_ALL_LFET0OC_Pos (2)
#define FFAULTSEL0_ALL_LFET0OC_Msk (0x1ul << FFAULTSEL0_ALL_LFET0OC_Pos)

#define FFAULTSEL0_ALL_LFET0OC_NOT_SELECTE   (0ul << FFAULTSEL0_ALL_LFET0OC_Pos)
#define FFAULTSEL0_ALL_LFET0OC_SELECTE       (1ul << FFAULTSEL0_ALL_LFET0OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL0       VDDGTOOHI
 *  @access 
 *  @brief  Select VDDG too high flag as fatal fault
 */
#define FFAULTSEL0_ALL_VDDGTOOHI_Pos (1)
#define FFAULTSEL0_ALL_VDDGTOOHI_Msk (0x1ul << FFAULTSEL0_ALL_VDDGTOOHI_Pos)

#define FFAULTSEL0_ALL_VDDGTOOHI_NOT_SELECTE   (0ul << FFAULTSEL0_ALL_VDDGTOOHI_Pos)
#define FFAULTSEL0_ALL_VDDGTOOHI_SELECTE       (1ul << FFAULTSEL0_ALL_VDDGTOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL0       VDDGTOOLO
 *  @access 
 *  @brief  Select VDDG too low flag as fatal fault
 */
#define FFAULTSEL0_ALL_VDDGTOOLO_Pos (0)
#define FFAULTSEL0_ALL_VDDGTOOLO_Msk (0x1ul << FFAULTSEL0_ALL_VDDGTOOLO_Pos)

#define FFAULTSEL0_ALL_VDDGTOOLO_NOT_SELECTE   (0ul << FFAULTSEL0_ALL_VDDGTOOLO_Pos)
#define FFAULTSEL0_ALL_VDDGTOOLO_SELECTE       (1ul << FFAULTSEL0_ALL_VDDGTOOLO_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL1       PVDD0TOOHI
 *  @access 
 *  @brief  Select PVDD0 too high flag as fatal fault
 */
#define FFAULTSEL1_ALL_PVDD0TOOHI_Pos (7)
#define FFAULTSEL1_ALL_PVDD0TOOHI_Msk (0x1ul << FFAULTSEL1_ALL_PVDD0TOOHI_Pos)

#define FFAULTSEL1_ALL_PVDD0TOOHI_NOT_SELECTE   (0ul << FFAULTSEL1_ALL_PVDD0TOOHI_Pos)
#define FFAULTSEL1_ALL_PVDD0TOOHI_SELECTE       (1ul << FFAULTSEL1_ALL_PVDD0TOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL1       PVDD0TOOLO
 *  @access 
 *  @brief  Select PVDD0 too low flag as fatal fault
 */
#define FFAULTSEL1_ALL_PVDD0TOOLO_Pos (6)
#define FFAULTSEL1_ALL_PVDD0TOOLO_Msk (0x1ul << FFAULTSEL1_ALL_PVDD0TOOLO_Pos)

#define FFAULTSEL1_ALL_PVDD0TOOLO_NOT_SELECTE   (0ul << FFAULTSEL1_ALL_PVDD0TOOLO_Pos)
#define FFAULTSEL1_ALL_PVDD0TOOLO_SELECTE       (1ul << FFAULTSEL1_ALL_PVDD0TOOLO_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL1       PVDD1TOOHI
 *  @access 
 *  @brief  Select PVDD1 too high flag as fatal fault
 */
#define FFAULTSEL1_ALL_PVDD1TOOHI_Pos (5)
#define FFAULTSEL1_ALL_PVDD1TOOHI_Msk (0x1ul << FFAULTSEL1_ALL_PVDD1TOOHI_Pos)

#define FFAULTSEL1_ALL_PVDD1TOOHI_NOT_SELECTE   (0ul << FFAULTSEL1_ALL_PVDD1TOOHI_Pos)
#define FFAULTSEL1_ALL_PVDD1TOOHI_SELECTE       (1ul << FFAULTSEL1_ALL_PVDD1TOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL1       PVDD1TOOLO
 *  @access 
 *  @brief  Select PVDD1 too low flag as fatal fault
 */
#define FFAULTSEL1_ALL_PVDD1TOOLO_Pos (4)
#define FFAULTSEL1_ALL_PVDD1TOOLO_Msk (0x1ul << FFAULTSEL1_ALL_PVDD1TOOLO_Pos)

#define FFAULTSEL1_ALL_PVDD1TOOLO_NOT_SELECTE   (0ul << FFAULTSEL1_ALL_PVDD1TOOLO_Pos)
#define FFAULTSEL1_ALL_PVDD1TOOLO_SELECTE       (1ul << FFAULTSEL1_ALL_PVDD1TOOLO_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL1       PREDRVOTWARN
 *  @access 
 *  @brief  Select pre-driver over-temperature warnning flag as fatal fault
 */
#define FFAULTSEL1_ALL_PREDRVOTWARN_Pos (3)
#define FFAULTSEL1_ALL_PREDRVOTWARN_Msk (0x1ul << FFAULTSEL1_ALL_PREDRVOTWARN_Pos)

#define FFAULTSEL1_ALL_PREDRVOTWARN_NOT_SELECTE   (0ul << FFAULTSEL1_ALL_PREDRVOTWARN_Pos)
#define FFAULTSEL1_ALL_PREDRVOTWARN_SELECTE       (1ul << FFAULTSEL1_ALL_PREDRVOTWARN_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         FFAULTSEL1       BUCKOTWARN
 *  @access 
 *  @brief  Select buck over-temperature warnning flag as fatal fault
 */
#define FFAULTSEL1_ALL_BUCKOTWARN_Pos (1)
#define FFAULTSEL1_ALL_BUCKOTWARN_Msk (0x1ul << FFAULTSEL1_ALL_BUCKOTWARN_Pos)

#define FFAULTSEL1_ALL_BUCKOTWARN_NOT_SELECTE   (0ul << FFAULTSEL1_ALL_BUCKOTWARN_Pos)
#define FFAULTSEL1_ALL_BUCKOTWARN_SELECTE       (1ul << FFAULTSEL1_ALL_BUCKOTWARN_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL0       HFET2OC
 *  @access 
 *  @brief  Select high-side FET2 over-current flag as general fault
 */
#define GFAULTSEL0_ALL_HFET2OC_Pos (7)
#define GFAULTSEL0_ALL_HFET2OC_Msk (0x1ul << GFAULTSEL0_ALL_HFET2OC_Pos)

#define GFAULTSEL0_ALL_HFET2OC_NOT_SELECTE   (0ul << GFAULTSEL0_ALL_HFET2OC_Pos)
#define GFAULTSEL0_ALL_HFET2OC_SELECTE       (1ul << GFAULTSEL0_ALL_HFET2OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL0       HFET1OC
 *  @access 
 *  @brief  Select high-side FET1 over-current flag as general fault
 */
#define GFAULTSEL0_ALL_HFET1OC_Pos (6)
#define GFAULTSEL0_ALL_HFET1OC_Msk (0x1ul << GFAULTSEL0_ALL_HFET1OC_Pos)

#define GFAULTSEL0_ALL_HFET1OC_NOT_SELECTE   (0ul << GFAULTSEL0_ALL_HFET1OC_Pos)
#define GFAULTSEL0_ALL_HFET1OC_SELECTE       (1ul << GFAULTSEL0_ALL_HFET1OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL0       HFET0OC
 *  @access 
 *  @brief  Select high-side FET0 over-current flag as general fault
 */
#define GFAULTSEL0_ALL_HFET0OC_Pos (5)
#define GFAULTSEL0_ALL_HFET0OC_Msk (0x1ul << GFAULTSEL0_ALL_HFET0OC_Pos)

#define GFAULTSEL0_ALL_HFET0OC_NOT_SELECTE   (0ul << GFAULTSEL0_ALL_HFET0OC_Pos)
#define GFAULTSEL0_ALL_HFET0OC_SELECTE       (1ul << GFAULTSEL0_ALL_HFET0OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL0       LFET2OC
 *  @access 
 *  @brief  Select low-side FET2 over-current flag as fatal fault
 */
#define GFAULTSEL0_ALL_LFET2OC_Pos (4)
#define GFAULTSEL0_ALL_LFET2OC_Msk (0x1ul << GFAULTSEL0_ALL_LFET2OC_Pos)

#define GFAULTSEL0_ALL_LFET2OC_NOT_SELECTE   (0ul << GFAULTSEL0_ALL_LFET2OC_Pos)
#define GFAULTSEL0_ALL_LFET2OC_SELECTE       (1ul << GFAULTSEL0_ALL_LFET2OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL0       LFET1OC
 *  @access 
 *  @brief  Select low-side FET1 over-current flag as fatal fault
 */
#define GFAULTSEL0_ALL_LFET1OC_Pos (3)
#define GFAULTSEL0_ALL_LFET1OC_Msk (0x1ul << GFAULTSEL0_ALL_LFET1OC_Pos)

#define GFAULTSEL0_ALL_LFET1OC_NOT_SELECTE   (0ul << GFAULTSEL0_ALL_LFET1OC_Pos)
#define GFAULTSEL0_ALL_LFET1OC_SELECTE       (1ul << GFAULTSEL0_ALL_LFET1OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL0       LFET0OC
 *  @access 
 *  @brief  Select low-side FET0 over-current flag as fatal fault
 */
#define GFAULTSEL0_ALL_LFET0OC_Pos (2)
#define GFAULTSEL0_ALL_LFET0OC_Msk (0x1ul << GFAULTSEL0_ALL_LFET0OC_Pos)

#define GFAULTSEL0_ALL_LFET0OC_NOT_SELECTE   (0ul << GFAULTSEL0_ALL_LFET0OC_Pos)
#define GFAULTSEL0_ALL_LFET0OC_SELECTE       (1ul << GFAULTSEL0_ALL_LFET0OC_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL0       VDDGTOOHI
 *  @access 
 *  @brief  Select VDDG too high flag as fatal fault
 */
#define GFAULTSEL0_ALL_VDDGTOOHI_Pos (1)
#define GFAULTSEL0_ALL_VDDGTOOHI_Msk (0x1ul << GFAULTSEL0_ALL_VDDGTOOHI_Pos)

#define GFAULTSEL0_ALL_VDDGTOOHI_NOT_SELECTE   (0ul << GFAULTSEL0_ALL_VDDGTOOHI_Pos)
#define GFAULTSEL0_ALL_VDDGTOOHI_SELECTE       (1ul << GFAULTSEL0_ALL_VDDGTOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL0       VDDGTOOLO
 *  @access 
 *  @brief  Select VDDG too low flag as fatal fault
 */
#define GFAULTSEL0_ALL_VDDGTOOLO_Pos (0)
#define GFAULTSEL0_ALL_VDDGTOOLO_Msk (0x1ul << GFAULTSEL0_ALL_VDDGTOOLO_Pos)

#define GFAULTSEL0_ALL_VDDGTOOLO_NOT_SELECTE   (0ul << GFAULTSEL0_ALL_VDDGTOOLO_Pos)
#define GFAULTSEL0_ALL_VDDGTOOLO_SELECTE       (1ul << GFAULTSEL0_ALL_VDDGTOOLO_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL1       PVDD0TOOHI
 *  @access 
 *  @brief  Select PVDD0 too high flag as fatal fault
 */
#define GFAULTSEL1_ALL_PVDD0TOOHI_Pos (7)
#define GFAULTSEL1_ALL_PVDD0TOOHI_Msk (0x1ul << GFAULTSEL1_ALL_PVDD0TOOHI_Pos)

#define GFAULTSEL1_ALL_PVDD0TOOHI_NOT_SELECTE   (0ul << GFAULTSEL1_ALL_PVDD0TOOHI_Pos)
#define GFAULTSEL1_ALL_PVDD0TOOHI_SELECTE       (1ul << GFAULTSEL1_ALL_PVDD0TOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL1       PVDD0TOOLO
 *  @access 
 *  @brief  Select PVDD0 too low flag as fatal fault
 */
#define GFAULTSEL1_ALL_PVDD0TOOLO_Pos (6)
#define GFAULTSEL1_ALL_PVDD0TOOLO_Msk (0x1ul << GFAULTSEL1_ALL_PVDD0TOOLO_Pos)

#define GFAULTSEL1_ALL_PVDD0TOOLO_NOT_SELECTE   (0ul << GFAULTSEL1_ALL_PVDD0TOOLO_Pos)
#define GFAULTSEL1_ALL_PVDD0TOOLO_SELECTE       (1ul << GFAULTSEL1_ALL_PVDD0TOOLO_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL1       PVDD1TOOHI
 *  @access 
 *  @brief  Select PVDD1 too high flag as fatal fault
 */
#define GFAULTSEL1_ALL_PVDD1TOOHI_Pos (5)
#define GFAULTSEL1_ALL_PVDD1TOOHI_Msk (0x1ul << GFAULTSEL1_ALL_PVDD1TOOHI_Pos)

#define GFAULTSEL1_ALL_PVDD1TOOHI_NOT_SELECTE   (0ul << GFAULTSEL1_ALL_PVDD1TOOHI_Pos)
#define GFAULTSEL1_ALL_PVDD1TOOHI_SELECTE       (1ul << GFAULTSEL1_ALL_PVDD1TOOHI_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL1       PVDD1TOOLO
 *  @access 
 *  @brief  Select PVDD1 too low flag as fatal fault
 */
#define GFAULTSEL1_ALL_PVDD1TOOLO_Pos (4)
#define GFAULTSEL1_ALL_PVDD1TOOLO_Msk (0x1ul << GFAULTSEL1_ALL_PVDD1TOOLO_Pos)

#define GFAULTSEL1_ALL_PVDD1TOOLO_NOT_SELECTE   (0ul << GFAULTSEL1_ALL_PVDD1TOOLO_Pos)
#define GFAULTSEL1_ALL_PVDD1TOOLO_SELECTE       (1ul << GFAULTSEL1_ALL_PVDD1TOOLO_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL1       PREDRVOTWARN
 *  @access 
 *  @brief  Select pre-driver over-temperature warnning flag as fatal fault
 */
#define GFAULTSEL1_ALL_PREDRVOTWARN_Pos (3)
#define GFAULTSEL1_ALL_PREDRVOTWARN_Msk (0x1ul << GFAULTSEL1_ALL_PREDRVOTWARN_Pos)

#define GFAULTSEL1_ALL_PREDRVOTWARN_NOT_SELECTE   (0ul << GFAULTSEL1_ALL_PREDRVOTWARN_Pos)
#define GFAULTSEL1_ALL_PREDRVOTWARN_SELECTE       (1ul << GFAULTSEL1_ALL_PREDRVOTWARN_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         GFAULTSEL1       BUCKOTWARN
 *  @access 
 *  @brief  Select buck over-temperature warnning flag as fatal fault
 */
#define GFAULTSEL1_ALL_BUCKOTWARN_Pos (1)
#define GFAULTSEL1_ALL_BUCKOTWARN_Msk (0x1ul << GFAULTSEL1_ALL_BUCKOTWARN_Pos)

#define GFAULTSEL1_ALL_BUCKOTWARN_NOT_SELECTE   (0ul << GFAULTSEL1_ALL_BUCKOTWARN_Pos)
#define GFAULTSEL1_ALL_BUCKOTWARN_SELECTE       (1ul << GFAULTSEL1_ALL_BUCKOTWARN_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         LDOGCTL          VREFSEL
 *  @access 
 *  @brief  Reference voltage select
 */
#define LDOGCTL_ALL_VREFSEL_Pos (3)
#define LDOGCTL_ALL_VREFSEL_Msk (0x7ul << LDOGCTL_ALL_VREFSEL_Pos)

#define LDOGCTL_ALL_VREFSEL_9_V   (2ul << LDOGCTL_ALL_VREFSEL_Pos)
#define LDOGCTL_ALL_VREFSEL_10_V  (3ul << LDOGCTL_ALL_VREFSEL_Pos)
#define LDOGCTL_ALL_VREFSEL_12_V  (4ul << LDOGCTL_ALL_VREFSEL_Pos)
#define LDOGCTL_ALL_VREFSEL_15_V  (5ul << LDOGCTL_ALL_VREFSEL_Pos)
#define LDOGCTL_ALL_VREFSEL_18_V  (6ul << LDOGCTL_ALL_VREFSEL_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         LDOGCTL          VOTREFSEL
 *  @access 
 *  @brief  Over temperature triggering threshold
 */
#define LDOGCTL_ALL_VOTREFSEL_Pos (0)
#define LDOGCTL_ALL_VOTREFSEL_Msk (0x7ul << LDOGCTL_ALL_VOTREFSEL_Pos)

#define LDOGCTL_ALL_VOTREFSEL_146_DEGREE   (0ul << LDOGCTL_ALL_VOTREFSEL_Pos)
#define LDOGCTL_ALL_VOTREFSEL_138_DEGREE   (1ul << LDOGCTL_ALL_VOTREFSEL_Pos)
#define LDOGCTL_ALL_VOTREFSEL_131_DEGREE   (2ul << LDOGCTL_ALL_VOTREFSEL_Pos)
#define LDOGCTL_ALL_VOTREFSEL_122_DEGREE   (3ul << LDOGCTL_ALL_VOTREFSEL_Pos)
#define LDOGCTL_ALL_VOTREFSEL_114_DEGREE   (4ul << LDOGCTL_ALL_VOTREFSEL_Pos)
#define LDOGCTL_ALL_VOTREFSEL_107_DEGREE   (5ul << LDOGCTL_ALL_VOTREFSEL_Pos)
#define LDOGCTL_ALL_VOTREFSEL_99_DEGREE    (6ul << LDOGCTL_ALL_VOTREFSEL_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODCTL           PVDD0BODEN
 *  @access 
 *  @brief  Enable BOD for PVDD0
 */
#define BODCTL_ALL_PVDD0BODEN_Pos (1)
#define BODCTL_ALL_PVDD0BODEN_Msk (0x1ul << BODCTL_ALL_PVDD0BODEN_Pos)

#define BODCTL_ALL_PVDD0BODEN_DISABLE   (0ul << BODCTL_ALL_PVDD0BODEN_Pos)
#define BODCTL_ALL_PVDD0BODEN_ENABLE    (1ul << BODCTL_ALL_PVDD0BODEN_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODCTL           VDDGBODEN
 *  @access 
 *  @brief  Enable BOD for VDDG
 */
#define BODCTL_ALL_VDDGBODEN_Pos (0)
#define BODCTL_ALL_VDDGBODEN_Msk (0x1ul << BODCTL_ALL_VDDGBODEN_Pos)

#define BODCTL_ALL_VDDGBODEN_DISABLE   (0ul << BODCTL_ALL_VDDGBODEN_Pos)
#define BODCTL_ALL_VDDGBODEN_ENABLE    (1ul << BODCTL_ALL_VDDGBODEN_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODVDDGHVTH      H2L
 *  @access 
 *  @brief  Threshold for VDDG_TOO_HIGH to toggle from 1 to 0
 */
#define BODVDDGHVTH_ALL_H2L_Pos (4)
#define BODVDDGHVTH_ALL_H2L_Msk (0xful << BODVDDGHVTH_ALL_H2L_Pos)

#define BODVDDGHVTH_ALL_H2L_1dot6_V   (0ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_3dot2_V   (1ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_4dot8_V   (2ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_6dot4_V   (3ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_8_V       (4ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_9dot6_V   (5ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_11dot2_V  (6ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_12dot8_V  (7ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_14dot4_V  (8ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_16_V      (9ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_17dot6_V  (10ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_19dot2_V  (11ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_20dot8_V  (12ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_22dot4_V  (13ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_24_V      (14ul << BODVDDGHVTH_ALL_H2L_Pos)
#define BODVDDGHVTH_ALL_H2L_25dot6_V  (15ul << BODVDDGHVTH_ALL_H2L_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODVDDGHVTH      L2H
 *  @access 
 *  @brief  Threshold for VDDG_TOO_HIGH to toggle from 0 to 1
 */
#define BODVDDGHVTH_ALL_L2H_Pos (0)
#define BODVDDGHVTH_ALL_L2H_Msk (0xful << BODVDDGHVTH_ALL_L2H_Pos)

#define BODVDDGHVTH_ALL_L2H_1dot6_V   (0ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_3dot2_V   (1ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_4dot8_V   (2ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_6dot4_V   (3ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_8_V       (4ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_9dot6_V   (5ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_11dot2_V  (6ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_12dot8_V  (7ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_14dot4_V  (8ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_16_V      (9ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_17dot6_V  (10ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_19dot2_V  (11ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_20dot8_V  (12ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_22dot4_V  (13ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_24_V      (14ul << BODVDDGHVTH_ALL_L2H_Pos)
#define BODVDDGHVTH_ALL_L2H_25dot6_V  (15ul << BODVDDGHVTH_ALL_L2H_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODVDDGLVTH      H2L
 *  @access 
 *  @brief  Threshold for VDDG_TOO_LOW to toggle from 1 to 0
 */
#define BODVDDGLVTH_ALL_H2L_Pos (4)
#define BODVDDGLVTH_ALL_H2L_Msk (0xful << BODVDDGLVTH_ALL_H2L_Pos)

#define BODVDDGLVTH_ALL_H2L_1dot6_V   (0ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_3dot2_V   (1ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_4dot8_V   (2ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_6dot4_V   (3ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_8_V       (4ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_9dot6_V   (5ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_11dot2_V  (6ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_12dot8_V  (7ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_14dot4_V  (8ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_16_V      (9ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_17dot6_V  (10ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_19dot2_V  (11ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_20dot8_V  (12ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_22dot4_V  (13ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_24_V      (14ul << BODVDDGLVTH_ALL_H2L_Pos)
#define BODVDDGLVTH_ALL_H2L_25dot6_V  (15ul << BODVDDGLVTH_ALL_H2L_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODVDDGLVTH      L2H
 *  @access 
 *  @brief  Threshold for VDDG_TOO_LOW to toggle from 0 to 1
 */
#define BODVDDGLVTH_ALL_L2H_Pos (0)
#define BODVDDGLVTH_ALL_L2H_Msk (0xful << BODVDDGLVTH_ALL_L2H_Pos)

#define BODVDDGLVTH_ALL_L2H_1dot6_V   (0ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_3dot2_V   (1ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_4dot8_V   (2ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_6dot4_V   (3ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_8_V       (4ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_9dot6_V   (5ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_11dot2_V  (6ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_12dot8_V  (7ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_14dot4_V  (8ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_16_V      (9ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_17dot6_V  (10ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_19dot2_V  (11ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_20dot8_V  (12ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_22dot4_V  (13ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_24_V      (14ul << BODVDDGLVTH_ALL_L2H_Pos)
#define BODVDDGLVTH_ALL_L2H_25dot6_V  (15ul << BODVDDGLVTH_ALL_L2H_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODPVDD0HVTH     H2L
 *  @access 
 *  @brief  Threshold for PVDD0_TOO_HIGH to toggle from 1 to 0
 */
#define BODPVDD0HVTH_ALL_H2L_Pos (4)
#define BODPVDD0HVTH_ALL_H2L_Msk (0xful << BODPVDD0HVTH_ALL_H2L_Pos)

#define BODPVDD0HVTH_ALL_H2L_4dot8_V   (0ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_9dot6_V   (1ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_14dot4_V  (2ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_19dot2_V  (3ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_24_V      (4ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_28dot8_V  (5ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_33dot6_V  (6ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_38dot4_V  (7ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_43dot2_V  (8ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_48_V      (9ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_52dot8_V  (10ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_57dot6_V  (11ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_62dot4_V  (12ul << BODPVDD0HVTH_ALL_H2L_Pos)
#define BODPVDD0HVTH_ALL_H2L_67dot2_V  (13ul << BODPVDD0HVTH_ALL_H2L_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODPVDD0HVTH     L2H
 *  @access 
 *  @brief  Threshold for PVDD0_TOO_HIGH to toggle from 0 to 1
 */
#define BODPVDD0HVTH_ALL_L2H_Pos (0)
#define BODPVDD0HVTH_ALL_L2H_Msk (0xful << BODPVDD0HVTH_ALL_L2H_Pos)

#define BODPVDD0HVTH_ALL_L2H_4dot8_V   (0ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_9dot6_V   (1ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_14dot4_V  (2ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_19dot2_V  (3ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_24_V      (4ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_28dot8_V  (5ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_33dot6_V  (6ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_38dot4_V  (7ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_43dot2_V  (8ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_48_V      (9ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_52dot8_V  (10ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_57dot6_V  (11ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_62dot4_V  (12ul << BODPVDD0HVTH_ALL_L2H_Pos)
#define BODPVDD0HVTH_ALL_L2H_67dot2_V  (13ul << BODPVDD0HVTH_ALL_L2H_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODPVDD0LVTH     H2L
 *  @access 
 *  @brief  Threshold for PVDD0_TOO_LOW to toggle from 1 to 0
 */
#define BODPVDD0LVTH_ALL_H2L_Pos (4)
#define BODPVDD0LVTH_ALL_H2L_Msk (0xful << BODPVDD0LVTH_ALL_H2L_Pos)

#define BODPVDD0LVTH_ALL_H2L_4dot8_V   (0ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_9dot6_V   (1ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_14dot4_V  (2ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_19dot2_V  (3ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_24_V      (4ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_28dot8_V  (5ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_33dot6_V  (6ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_38dot4_V  (7ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_43dot2_V  (8ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_48_V      (9ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_52dot8_V  (10ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_57dot6_V  (11ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_62dot4_V  (12ul << BODPVDD0LVTH_ALL_H2L_Pos)
#define BODPVDD0LVTH_ALL_H2L_67dot2_V  (13ul << BODPVDD0LVTH_ALL_H2L_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BODPVDD0LVTH     L2H
 *  @access 
 *  @brief  Threshold for PVDD0_TOO_LOW to toggle from 0 to 1
 */
#define BODPVDD0LVTH_ALL_L2H_Pos (0)
#define BODPVDD0LVTH_ALL_L2H_Msk (0xful << BODPVDD0LVTH_ALL_L2H_Pos)

#define BODPVDD0LVTH_ALL_L2H_4dot8_V   (0ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_9dot6_V   (1ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_14dot4_V  (2ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_19dot2_V  (3ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_24_V      (4ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_28dot8_V  (5ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_33dot6_V  (6ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_38dot4_V  (7ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_43dot2_V  (8ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_48_V      (9ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_52dot8_V  (10ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_57dot6_V  (11ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_62dot4_V  (12ul << BODPVDD0LVTH_ALL_L2H_Pos)
#define BODPVDD0LVTH_ALL_L2H_67dot2_V  (13ul << BODPVDD0LVTH_ALL_L2H_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BUCKCTL0         VOTREFSEL
 *  @access 
 *  @brief  Over temperature triggering threshold
 */
#define BUCKCTL0_ALL_VOTREFSEL_Pos (4)
#define BUCKCTL0_ALL_VOTREFSEL_Msk (0x7ul << BUCKCTL0_ALL_VOTREFSEL_Pos)

#define BUCKCTL0_ALL_VOTREFSEL_146_DEGREE   (0ul << BUCKCTL0_ALL_VOTREFSEL_Pos)
#define BUCKCTL0_ALL_VOTREFSEL_138_DEGREE   (1ul << BUCKCTL0_ALL_VOTREFSEL_Pos)
#define BUCKCTL0_ALL_VOTREFSEL_131_DEGREE   (2ul << BUCKCTL0_ALL_VOTREFSEL_Pos)
#define BUCKCTL0_ALL_VOTREFSEL_122_DEGREE   (3ul << BUCKCTL0_ALL_VOTREFSEL_Pos)
#define BUCKCTL0_ALL_VOTREFSEL_114_DEGREE   (4ul << BUCKCTL0_ALL_VOTREFSEL_Pos)
#define BUCKCTL0_ALL_VOTREFSEL_107_DEGREE   (5ul << BUCKCTL0_ALL_VOTREFSEL_Pos)
#define BUCKCTL0_ALL_VOTREFSEL_99_DEGREE    (6ul << BUCKCTL0_ALL_VOTREFSEL_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BUCKCTL1         FREQSET
 *  @access 
 *  @brief  Select internal resistor to set the Buck DCDC switching frequency
 */
#define BUCKCTL1_ALL_FREQSET_Pos (7)
#define BUCKCTL1_ALL_FREQSET_Msk (0x1ul << BUCKCTL1_ALL_FREQSET_Pos)

#define BUCKCTL1_ALL_FREQSET_SELECT_EXTERNAL_RESISTOR   (0ul << BUCKCTL1_ALL_FREQSET_Pos)
#define BUCKCTL1_ALL_FREQSET_SELECT_INTERNAL_RESISTOR   (1ul << BUCKCTL1_ALL_FREQSET_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BUCKCTL1         HALFFREQ
 *  @access 
 *  @brief  Half the Buck DCDC switching frequency
 */
#define BUCKCTL1_ALL_HALFFREQ_Pos (6)
#define BUCKCTL1_ALL_HALFFREQ_Msk (0x1ul << BUCKCTL1_ALL_HALFFREQ_Pos)

#define BUCKCTL1_ALL_HALFFREQ_420KHZ   (0ul << BUCKCTL1_ALL_HALFFREQ_Pos)
#define BUCKCTL1_ALL_HALFFREQ_210KHZ   (1ul << BUCKCTL1_ALL_HALFFREQ_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BUCKCTL1         OVDISABLE
 *  @access 
 *  @brief  Disable over voltage sensing
 */
#define BUCKCTL1_ALL_OVDISABLE_Pos (4)
#define BUCKCTL1_ALL_OVDISABLE_Msk (0x1ul << BUCKCTL1_ALL_OVDISABLE_Pos)

#define BUCKCTL1_ALL_OVDISABLE_ENABLE_OV_OBSERVE   (0ul << BUCKCTL1_ALL_OVDISABLE_Pos)
#define BUCKCTL1_ALL_OVDISABLE_DISABLE_OV_OBSERVE  (1ul << BUCKCTL1_ALL_OVDISABLE_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BUCKCTL1         DCDCDISABLE
 *  @access 
 *  @brief  Disable DC-DC
 */
#define BUCKCTL1_ALL_DCDCDISABLE_Pos (3)
#define BUCKCTL1_ALL_DCDCDISABLE_Msk (0x1ul << BUCKCTL1_ALL_DCDCDISABLE_Pos)

#define BUCKCTL1_ALL_DCDCDISABLE_ENABLE_DCDC   (0ul << BUCKCTL1_ALL_DCDCDISABLE_Pos)
#define BUCKCTL1_ALL_DCDCDISABLE_DISABLE_DCDC  (1ul << BUCKCTL1_ALL_DCDCDISABLE_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         BUCKCTL1         FRCPWM
 *  @access 
 *  @brief  Force buck into PWM mode
 */
#define BUCKCTL1_ALL_FRCPWM_Pos (2)
#define BUCKCTL1_ALL_FRCPWM_Msk (0x1ul << BUCKCTL1_ALL_FRCPWM_Pos)

#define BUCKCTL1_ALL_FRCPWM_RELEASE   (0ul << BUCKCTL1_ALL_FRCPWM_Pos)
#define BUCKCTL1_ALL_FRCPWM_FORCE     (1ul << BUCKCTL1_ALL_FRCPWM_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         RCOCTL           DIV
 *  @access 
 *  @brief  Clock dividing ratio for glitch filtering on fault signals
 */
#define RCOCTL_ALL_DIV_Pos (3)
#define RCOCTL_ALL_DIV_Msk (0x7ul << RCOCTL_ALL_DIV_Pos)

#define RCOCTL_ALL_DIV_2    (0ul << RCOCTL_ALL_DIV_Pos)
#define RCOCTL_ALL_DIV_4    (1ul << RCOCTL_ALL_DIV_Pos)
#define RCOCTL_ALL_DIV_8    (2ul << RCOCTL_ALL_DIV_Pos)
#define RCOCTL_ALL_DIV_16   (3ul << RCOCTL_ALL_DIV_Pos)
#define RCOCTL_ALL_DIV_32   (4ul << RCOCTL_ALL_DIV_Pos)
#define RCOCTL_ALL_DIV_64   (5ul << RCOCTL_ALL_DIV_Pos)
#define RCOCTL_ALL_DIV_128  (6ul << RCOCTL_ALL_DIV_Pos)
#define RCOCTL_ALL_DIV_256  (7ul << RCOCTL_ALL_DIV_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         CPCTL            CLKDIV
 *  @access 
 *  @brief  Charge pump switching frequency
 */
#define CPCTL_ALL_CLKDIV_Pos (0)
#define CPCTL_ALL_CLKDIV_Msk (0x3ul << CPCTL_ALL_CLKDIV_Pos)

#define CPCTL_ALL_CLKDIV_1250KHZ  (0ul << CPCTL_ALL_CLKDIV_Pos)
#define CPCTL_ALL_CLKDIV_625KHZ   (1ul << CPCTL_ALL_CLKDIV_Pos)
#define CPCTL_ALL_CLKDIV_313KHZ   (2ul << CPCTL_ALL_CLKDIV_Pos)
#define CPCTL_ALL_CLKDIV_156KHZ   (3ul << CPCTL_ALL_CLKDIV_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         PREDRVCTL0       OCVREFSEL
 *  @access 
 *  @brief  Over current protect reference voltage select
 */
#define PREDRVCTL0_ALL_OCVREFSEL_Pos (4)
#define PREDRVCTL0_ALL_OCVREFSEL_Msk (0xful << PREDRVCTL0_ALL_OCVREFSEL_Pos)

#define PREDRVCTL0_ALL_OCVREFSEL_0dot15_V   (0ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_0dot30_V   (1ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_0dot45_V   (2ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_0dot60_V   (3ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_0dot75_V   (4ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_0dot90_V   (5ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_1dot05_V   (6ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_1dot20_V   (7ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_1dot35_V   (8ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_1dot50_V   (9ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_1dot65_V   (10ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_1dot80_V   (11ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_1dot95_V   (12ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_2dot10_V   (13ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_2dot25_V   (14ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)
#define PREDRVCTL0_ALL_OCVREFSEL_2dot40_V   (15ul << PREDRVCTL0_ALL_OCVREFSEL_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         PREDRVCTL0       FILTERWIN
 *  @access 
 *  @brief  De-bouncing filter window size
 */
#define PREDRVCTL0_ALL_FILTERWIN_Pos (2)
#define PREDRVCTL0_ALL_FILTERWIN_Msk (0x3ul << PREDRVCTL0_ALL_FILTERWIN_Pos)

#define PREDRVCTL0_ALL_FILTERWIN_400_NS    (0ul << PREDRVCTL0_ALL_FILTERWIN_Pos)
#define PREDRVCTL0_ALL_FILTERWIN_800_NS    (1ul << PREDRVCTL0_ALL_FILTERWIN_Pos)
#define PREDRVCTL0_ALL_FILTERWIN_1600_NS   (2ul << PREDRVCTL0_ALL_FILTERWIN_Pos)
#define PREDRVCTL0_ALL_FILTERWIN_3200_NS   (3ul << PREDRVCTL0_ALL_FILTERWIN_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         PREDRVCTL0       BLANKWIN
 *  @access 
 *  @brief  Blanking window size
 */
#define PREDRVCTL0_ALL_BLANKWIN_Pos (0)
#define PREDRVCTL0_ALL_BLANKWIN_Msk (0x3ul << PREDRVCTL0_ALL_BLANKWIN_Pos)

#define PREDRVCTL0_ALL_BLANKWIN_400_NS    (0ul << PREDRVCTL0_ALL_BLANKWIN_Pos)
#define PREDRVCTL0_ALL_BLANKWIN_800_NS    (1ul << PREDRVCTL0_ALL_BLANKWIN_Pos)
#define PREDRVCTL0_ALL_BLANKWIN_1600_NS   (2ul << PREDRVCTL0_ALL_BLANKWIN_Pos)
#define PREDRVCTL0_ALL_BLANKWIN_3200_NS   (3ul << PREDRVCTL0_ALL_BLANKWIN_Pos)








/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         PREDRVCTL1       SLEWRATE
 *  @access 
 *  @brief  Define predriver charge/discharge slew rate
 */
#define PREDRVCTL1_ALL_SLEWRATE_Pos (5)
#define PREDRVCTL1_ALL_SLEWRATE_Msk (0x3ul << PREDRVCTL1_ALL_SLEWRATE_Pos)

#define PREDRVCTL1_ALL_SLEWRATE_1A  (0ul << PREDRVCTL1_ALL_SLEWRATE_Pos)
#define PREDRVCTL1_ALL_SLEWRATE_2A  (1ul << PREDRVCTL1_ALL_SLEWRATE_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         PREDRVCTL1       CPCONNEN
 *  @access 
 *  @brief  Define predriver charge/discharge slew rate
 */
#define PREDRVCTL1_ALL_CPCONNEN_Pos (4)
#define PREDRVCTL1_ALL_CPCONNEN_Msk (0x1ul << PREDRVCTL1_ALL_CPCONNEN_Pos)

#define PREDRVCTL1_ALL_CPCONNEN_DISABLE  (0ul << PREDRVCTL1_ALL_CPCONNEN_Pos)
#define PREDRVCTL1_ALL_CPCONNEN_ENABLE   (1ul << PREDRVCTL1_ALL_CPCONNEN_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         PREDRVCTL1       CPPROTECTEN
 *  @access 
 *  @brief  Define predriver charge/discharge slew rate
 */
#define PREDRVCTL1_ALL_CPPROTECTEN_Pos (3)
#define PREDRVCTL1_ALL_CPPROTECTEN_Msk (0x1ul << PREDRVCTL1_ALL_CPPROTECTEN_Pos)

#define PREDRVCTL1_ALL_CPPROTECTEN_DISABLE  (0ul << PREDRVCTL1_ALL_CPPROTECTEN_Pos)
#define PREDRVCTL1_ALL_CPPROTECTEN_ENABLE   (1ul << PREDRVCTL1_ALL_CPPROTECTEN_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         PREDRVCTL1       OE
 *  @access 
 *  @brief  Output enable
 */
#define PREDRVCTL1_ALL_OE_Pos (2)
#define PREDRVCTL1_ALL_OE_Msk (0x1ul << PREDRVCTL1_ALL_OE_Pos)

#define PREDRVCTL1_ALL_OE_OUTPUT_DISABLE  (0ul << PREDRVCTL1_ALL_OE_Pos)
#define PREDRVCTL1_ALL_OE_OUTPUT_ENABLE   (1ul << PREDRVCTL1_ALL_OE_Pos)





/**
 *  @hierarchy       Module          Register         Bitfield
 *                   GATEDRV         PREDRVCTL1       MINNOV
 *  @access 
 *  @brief  Control minimal non-overlap timing for Vgs monitoring mode
 */
#define PREDRVCTL1_ALL_MINNOV_Pos (1)
#define PREDRVCTL1_ALL_MINNOV_Msk (0x1ul << PREDRVCTL1_ALL_MINNOV_Pos)

#define PREDRVCTL1_ALL_MINNOV_ADD_50_NS   (0ul << PREDRVCTL1_ALL_MINNOV_Pos)
#define PREDRVCTL1_ALL_MINNOV_ADD_100_NS  (1ul << PREDRVCTL1_ALL_MINNOV_Pos)




/**
 *  @brief  GATEDRV Pin Interface Definition
 */
#define GPIO_GATEDRV_PWM_U_H       GPIO_8             /*!< GPIO for PWM_U_H           */
#define GPIO_GATEDRV_PWM_U_L       GPIO_9             /*!< GPIO for PWM_U_L           */
#define GPIO_GATEDRV_PWM_V_H       GPIO_10            /*!< GPIO for PWM_V_H           */
#define GPIO_GATEDRV_PWM_V_L       GPIO_11            /*!< GPIO for PWM_V_H           */
#define GPIO_GATEDRV_PWM_W_H       GPIO_12            /*!< GPIO for PWM_W_H           */
#define GPIO_GATEDRV_PWM_W_L       GPIO_13            /*!< GPIO for PWM_W_L           */
#define GPIO_GATEDRV_FAULTN        GPIO_14            /*!< General Fault (Active Low) */
#define GPIO_GATEDRV_ATEST         GPIO_15            /*!< TEST                       */
#define GPIO_GATEDRV_OC_OV         GPIO_16            /*!< Fatal FAULT (Active Low)   */
#define GPIO_GATEDRV_EN            GPIO_17            /*!< Gate Enable                */
#define GPIO_GATEDRV_COM_DIO       GPIO_18            /*!< COM Data Signal            */
#define GPIO_GATEDRV_COM_CLK       GPIO_19            /*!< COM Clock Signal           */
#define GPIO_GATEDRV_COM_CS        GPIO_20            /*!< COM Frame Signal           */




/**
 *  @brief  GATEDRV SSP communication maximum clock
 */
#define GATEDRV_SSP_MAX_CLK          (40000000)




/**
 *  @brief  GATEDRV Communication Command
 */
#define GATEDRV_CMD_READ_ID        (0x514E4944ul)
#define GATEDRV_CMD_WRITE          (0x5740005Aul)
#define GATEDRV_CMD_EXECUTE        (0x45786563ul)
#define GATEDRV_CMD_READ           (0x5240445Aul)




/**
 *  @brief  GATEDRV Masked Response
 */
#define GATEDRV_RESP_READ_ID       (0x4944004Eul)
#define GATEDRV_RESP_WRITE         (0x57A0005Aul)
#define GATEDRV_RESP_EXECUTE       (0x446F6E65ul)
#define GATEDRV_RESP_READ          (0x52A00000ul)




/**
 *  @brief  GATEDRV Register Address
 */
#define IS_GATEDRV_REG_ADDR(u8Addr)  ((u8Addr) <= 0x1F)




/**
 *  @brief  GATEDRV OTP Data Structure Declaration
 */
typedef struct
{
  uint8_t BUCK_REF_SEL;                     /*!< Reference voltage select                      */
  uint8_t LDO5_TRIM;                        /*!< Reference voltage trim                        */
  uint8_t BUCK_TRIM_TON;                    /*!< PWM turn-on time trim                         */
  uint8_t BUCK_TRIM_ILIMIT;                 /*!< Current limit trim for over-current detection */
  uint8_t GATEDRV_OSC_TRIM;                 /*!< RCO frequency trim                            */
} OTPInfoStruct_GATEDRV;




/**
 *  @brief GATEDRV Public Function Declaration
 */
//void GATEDRV_PinInit(void);
//ErrorStatus GATEDRV_ComInit(uint32_t u32Baudrate);
ErrorStatus GATEDRV_Init(uint32_t u32Baudrate, uint8_t *pu8ID, uint32_t u32Timeout);

ErrorStatus GATEDRV_Handshake(uint8_t *pu8ID, uint32_t u32Timeout);
ErrorStatus GATEDRV_Command(uint32_t u32Req, uint32_t *pu32Resp);

ErrorStatus GATEDRV_WriteREG(uint8_t u8Addr, uint8_t u8Data);
ErrorStatus GATEDRV_ReadREG(uint8_t u8Addr, uint8_t *pu8Data);
ErrorStatus GATEDRV_WriteREGBits(uint8_t u8Addr, uint8_t u8Data, uint8_t u8Start, uint8_t u8Len);

ErrorStatus GATEDRV_ResetREG(void);
ErrorStatus GATEDRV_Trim(void);
ErrorStatus GATEDRV_EnableLowVoltageOperation(void);

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* GATEDRV_H */


/******************* Copyright (C) 2022 Spintrol Electronic Technology (Shanghai) Co., Ltd. ***** END OF FILE ****/
