/*******************************************************************************
 * @file     hv_bitfield.h
 * @brief    High voltage module register bit-field definition.
 * @version  V4.0.3
 * @date     30-July-2026
 *
 * @note
 * Copyright (C) 2022 Spintrol Electronic Technology (Shanghai) Co., Ltd.. All rights reserved.
 *
 * @attention
 * THIS SOFTWARE JUST PROVIDES CUSTOMERS WITH CODING INFORMATION REGARDING
 * THEIR PRODUCTS, WHICH AIMS AT SAVING TIME FOR THEM. SPINTROL SHALL NOT BE
 * LIABLE FOR THE USE OF THE SOFTWARE. SPINTROL DOES NOT GUARANTEE THE
 * CORRECTNESS OF THIS SOFTWARE AND RESERVES THE RIGHT TO MODIFY THE SOFTWARE
 * WITHOUT NOTIFICATION.
 *
 ******************************************************************************/


#ifndef HV_BITFIELD_H
#define HV_BITFIELD_H

#ifdef __cplusplus
extern "C" {
#endif




/********************************************************************************
*
* Module Name     HV
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS          PWRUP
 *  @access     
 *  @brief      Global power up flag
 */
#define GLBSTS_ALL_PWRUP_Pos (0)
#define GLBSTS_ALL_PWRUP_Msk (0x1UL << GLBSTS_ALL_PWRUP_Pos)

typedef enum
{
    GLBSTS_BIT_PWRUP_NOT_READY     = 0,  /*!< Pre-driver not power up     */
    GLBSTS_BIT_PWRUP_READY         = 1,  /*!< Pre-driver has powered up   */
} GLBSTS_BIT_PWRUP;

#define GLBSTS_ALL_PWRUP_NOT_READY     ((0x0UL) << GLBSTS_ALL_PWRUP_Pos)
#define GLBSTS_ALL_PWRUP_READY         ((0x1UL) << GLBSTS_ALL_PWRUP_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS          LDOGRDY
 *  @access     
 *  @brief      VDDG LDO ready flag
 */
#define GLBSTS_ALL_LDOGRDY_Pos (1)
#define GLBSTS_ALL_LDOGRDY_Msk (0x1UL << GLBSTS_ALL_LDOGRDY_Pos)

typedef enum
{
    GLBSTS_BIT_LDOGRDY_NOT_READY     = 0,  /*!< VDDG LDO is not ready   */
    GLBSTS_BIT_LDOGRDY_READY         = 1,  /*!< VDDG LDO is ready       */
} GLBSTS_BIT_LDOGRDY;

#define GLBSTS_ALL_LDOGRDY_NOT_READY     ((0x0UL) << GLBSTS_ALL_LDOGRDY_Pos)
#define GLBSTS_ALL_LDOGRDY_READY         ((0x1UL) << GLBSTS_ALL_LDOGRDY_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS          OTWARN
 *  @access     
 *  @brief      Latched over temperature warning status
 */
#define GLBSTS_ALL_OTWARN_Pos (2)
#define GLBSTS_ALL_OTWARN_Msk (0x1UL << GLBSTS_ALL_OTWARN_Pos)

typedef enum
{
    GLBSTS_BIT_OTWARN_NOT_OCCUR     = 0,  /*!< Over temperature warning event not occur      */
    GLBSTS_BIT_OTWARN_OCCUR         = 1,  /*!< Over temperature warning event has occurred   */
} GLBSTS_BIT_OTWARN;

#define GLBSTS_ALL_OTWARN_NOT_OCCUR     ((0x0UL) << GLBSTS_ALL_OTWARN_Pos)
#define GLBSTS_ALL_OTWARN_OCCUR         ((0x1UL) << GLBSTS_ALL_OTWARN_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS          OTERROR
 *  @access     
 *  @brief      Latched over temperature error status
 */
#define GLBSTS_ALL_OTERROR_Pos (3)
#define GLBSTS_ALL_OTERROR_Msk (0x1UL << GLBSTS_ALL_OTERROR_Pos)

typedef enum
{
    GLBSTS_BIT_OTERROR_NOT_OCCUR     = 0,  /*!< Over temperature error event not occur      */
    GLBSTS_BIT_OTERROR_OCCUR         = 1,  /*!< Over temperature error event has occurred   */
} GLBSTS_BIT_OTERROR;

#define GLBSTS_ALL_OTERROR_NOT_OCCUR     ((0x0UL) << GLBSTS_ALL_OTERROR_Pos)
#define GLBSTS_ALL_OTERROR_OCCUR         ((0x1UL) << GLBSTS_ALL_OTERROR_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS          VDDGL
 *  @access     
 *  @brief      Latched VDDG too low status
 */
#define GLBSTS_ALL_VDDGL_Pos (4)
#define GLBSTS_ALL_VDDGL_Msk (0x1UL << GLBSTS_ALL_VDDGL_Pos)

typedef enum
{
    GLBSTS_BIT_VDDGL_NOT_OCCUR     = 0,  /*!< VDDG too low event not occur      */
    GLBSTS_BIT_VDDGL_OCCUR         = 1,  /*!< VDDG too low event has occurred   */
} GLBSTS_BIT_VDDGL;

#define GLBSTS_ALL_VDDGL_NOT_OCCUR     ((0x0UL) << GLBSTS_ALL_VDDGL_Pos)
#define GLBSTS_ALL_VDDGL_OCCUR         ((0x1UL) << GLBSTS_ALL_VDDGL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS          VDDGH
 *  @access     
 *  @brief      Latched VDDG too high status
 */
#define GLBSTS_ALL_VDDGH_Pos (5)
#define GLBSTS_ALL_VDDGH_Msk (0x1UL << GLBSTS_ALL_VDDGH_Pos)

typedef enum
{
    GLBSTS_BIT_VDDGH_NOT_OCCUR     = 0,  /*!< VDDG too high event not occur      */
    GLBSTS_BIT_VDDGH_OCCUR         = 1,  /*!< VDDG too high event has occurred   */
} GLBSTS_BIT_VDDGH;

#define GLBSTS_ALL_VDDGH_NOT_OCCUR     ((0x0UL) << GLBSTS_ALL_VDDGH_Pos)
#define GLBSTS_ALL_VDDGH_OCCUR         ((0x1UL) << GLBSTS_ALL_VDDGH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS          VBATL
 *  @access     
 *  @brief      Latched VBAT too low status
 */
#define GLBSTS_ALL_VBATL_Pos (6)
#define GLBSTS_ALL_VBATL_Msk (0x1UL << GLBSTS_ALL_VBATL_Pos)

typedef enum
{
    GLBSTS_BIT_VBATL_NOT_OCCUR     = 0,  /*!< VBAT too low event not occur      */
    GLBSTS_BIT_VBATL_OCCUR         = 1,  /*!< VBAT too low event has occurred   */
} GLBSTS_BIT_VBATL;

#define GLBSTS_ALL_VBATL_NOT_OCCUR     ((0x0UL) << GLBSTS_ALL_VBATL_Pos)
#define GLBSTS_ALL_VBATL_OCCUR         ((0x1UL) << GLBSTS_ALL_VBATL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS          VBATH
 *  @access     
 *  @brief      Latched VBAT too high status
 */
#define GLBSTS_ALL_VBATH_Pos (7)
#define GLBSTS_ALL_VBATH_Msk (0x1UL << GLBSTS_ALL_VBATH_Pos)

typedef enum
{
    GLBSTS_BIT_VBATH_NOT_OCCUR     = 0,  /*!< VBAT too high event not occur      */
    GLBSTS_BIT_VBATH_OCCUR         = 1,  /*!< VBAT too high event has occurred   */
} GLBSTS_BIT_VBATH;

#define GLBSTS_ALL_VBATH_NOT_OCCUR     ((0x0UL) << GLBSTS_ALL_VBATH_Pos)
#define GLBSTS_ALL_VBATH_OCCUR         ((0x1UL) << GLBSTS_ALL_VBATH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR       OTWARN
 *  @access     
 *  @brief      Latched over temperature warning status clear
 */
#define GLBSTSCLR_ALL_OTWARN_Pos (2)
#define GLBSTSCLR_ALL_OTWARN_Msk (0x1UL << GLBSTSCLR_ALL_OTWARN_Pos)

typedef enum
{
    GLBSTSCLR_BIT_OTWARN_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                               
                                                  Always readback 0.                                    */
    GLBSTSCLR_BIT_OTWARN_CLEAR         = 1,  /*!< Write 1 will clear over temperature warning status.  
                                                  This bit is self-clear to 0.                          */
} GLBSTSCLR_BIT_OTWARN;

#define GLBSTSCLR_ALL_OTWARN_NO_EFFECT     ((0x0UL) << GLBSTSCLR_ALL_OTWARN_Pos)
#define GLBSTSCLR_ALL_OTWARN_CLEAR         ((0x1UL) << GLBSTSCLR_ALL_OTWARN_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR       OTERROR
 *  @access     
 *  @brief      Latched over temperature error status clear
 */
#define GLBSTSCLR_ALL_OTERROR_Pos (3)
#define GLBSTSCLR_ALL_OTERROR_Msk (0x1UL << GLBSTSCLR_ALL_OTERROR_Pos)

typedef enum
{
    GLBSTSCLR_BIT_OTERROR_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                             
                                                   Always readback 0.                                  */
    GLBSTSCLR_BIT_OTERROR_CLEAR         = 1,  /*!< Write 1 will clear over temperature error status.  
                                                   This bit is self-clear to 0.                        */
} GLBSTSCLR_BIT_OTERROR;

#define GLBSTSCLR_ALL_OTERROR_NO_EFFECT     ((0x0UL) << GLBSTSCLR_ALL_OTERROR_Pos)
#define GLBSTSCLR_ALL_OTERROR_CLEAR         ((0x1UL) << GLBSTSCLR_ALL_OTERROR_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR       VDDGL
 *  @access     
 *  @brief      Latched VDDG too low status clear
 */
#define GLBSTSCLR_ALL_VDDGL_Pos (4)
#define GLBSTSCLR_ALL_VDDGL_Msk (0x1UL << GLBSTSCLR_ALL_VDDGL_Pos)

typedef enum
{
    GLBSTSCLR_BIT_VDDGL_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                    
                                                 Always readback 0.                         */
    GLBSTSCLR_BIT_VDDGL_CLEAR         = 1,  /*!< Write 1 will clear VDDG too high status.  
                                                 This bit is self-clear to 0.               */
} GLBSTSCLR_BIT_VDDGL;

#define GLBSTSCLR_ALL_VDDGL_NO_EFFECT     ((0x0UL) << GLBSTSCLR_ALL_VDDGL_Pos)
#define GLBSTSCLR_ALL_VDDGL_CLEAR         ((0x1UL) << GLBSTSCLR_ALL_VDDGL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR       VDDGH
 *  @access     
 *  @brief      Latched VDDG too high status clear
 */
#define GLBSTSCLR_ALL_VDDGH_Pos (5)
#define GLBSTSCLR_ALL_VDDGH_Msk (0x1UL << GLBSTSCLR_ALL_VDDGH_Pos)

typedef enum
{
    GLBSTSCLR_BIT_VDDGH_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                    
                                                 Always readback 0.                         */
    GLBSTSCLR_BIT_VDDGH_CLEAR         = 1,  /*!< Write 1 will clear VDDG too high status.  
                                                 This bit is self-clear to 0.               */
} GLBSTSCLR_BIT_VDDGH;

#define GLBSTSCLR_ALL_VDDGH_NO_EFFECT     ((0x0UL) << GLBSTSCLR_ALL_VDDGH_Pos)
#define GLBSTSCLR_ALL_VDDGH_CLEAR         ((0x1UL) << GLBSTSCLR_ALL_VDDGH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR       VBATL
 *  @access     
 *  @brief      Latched VBAT too low status clear
 */
#define GLBSTSCLR_ALL_VBATL_Pos (6)
#define GLBSTSCLR_ALL_VBATL_Msk (0x1UL << GLBSTSCLR_ALL_VBATL_Pos)

typedef enum
{
    GLBSTSCLR_BIT_VBATL_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                   
                                                 Always readback 0.                        */
    GLBSTSCLR_BIT_VBATL_CLEAR         = 1,  /*!< Write 1 will clear VBAT too low status.  
                                                 This bit is self-clear to 0.              */
} GLBSTSCLR_BIT_VBATL;

#define GLBSTSCLR_ALL_VBATL_NO_EFFECT     ((0x0UL) << GLBSTSCLR_ALL_VBATL_Pos)
#define GLBSTSCLR_ALL_VBATL_CLEAR         ((0x1UL) << GLBSTSCLR_ALL_VBATL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR       VBATH
 *  @access     
 *  @brief      Latched VBAT too high status clear
 */
#define GLBSTSCLR_ALL_VBATH_Pos (7)
#define GLBSTSCLR_ALL_VBATH_Msk (0x1UL << GLBSTSCLR_ALL_VBATH_Pos)

typedef enum
{
    GLBSTSCLR_BIT_VBATH_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                    
                                                 Always readback 0.                         */
    GLBSTSCLR_BIT_VBATH_CLEAR         = 1,  /*!< Write 1 will clear VBAT too high status.  
                                                 This bit is self-clear to 0.               */
} GLBSTSCLR_BIT_VBATH;

#define GLBSTSCLR_ALL_VBATH_NO_EFFECT     ((0x0UL) << GLBSTSCLR_ALL_VBATH_Pos)
#define GLBSTSCLR_ALL_VBATH_CLEAR         ((0x1UL) << GLBSTSCLR_ALL_VBATH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTS         OCU0
 *  @access     
 *  @brief      Latched PDRV0 U-phase over-current status
 */
#define PDRVSTS_ALL_OCU0_Pos (0)
#define PDRVSTS_ALL_OCU0_Msk (0x1UL << PDRVSTS_ALL_OCU0_Pos)

typedef enum
{
    PDRVSTS_BIT_OCU0_NOT_OCCUR     = 0,  /*!< Pre-driver 0 U-phase over-current event not occur      */
    PDRVSTS_BIT_OCU0_OCCUR         = 1,  /*!< Pre-driver 0 U-phase over-current event has occurred   */
} PDRVSTS_BIT_OCU0;

#define PDRVSTS_ALL_OCU0_NOT_OCCUR     ((0x0UL) << PDRVSTS_ALL_OCU0_Pos)
#define PDRVSTS_ALL_OCU0_OCCUR         ((0x1UL) << PDRVSTS_ALL_OCU0_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTS         OCV0
 *  @access     
 *  @brief      Latched PDRV0 V-phase over-current status
 */
#define PDRVSTS_ALL_OCV0_Pos (1)
#define PDRVSTS_ALL_OCV0_Msk (0x1UL << PDRVSTS_ALL_OCV0_Pos)

typedef enum
{
    PDRVSTS_BIT_OCV0_NOT_OCCUR     = 0,  /*!< Pre-driver 0 V-phase over-current event not occur      */
    PDRVSTS_BIT_OCV0_OCCUR         = 1,  /*!< Pre-driver 0 V-phase over-current event has occurred   */
} PDRVSTS_BIT_OCV0;

#define PDRVSTS_ALL_OCV0_NOT_OCCUR     ((0x0UL) << PDRVSTS_ALL_OCV0_Pos)
#define PDRVSTS_ALL_OCV0_OCCUR         ((0x1UL) << PDRVSTS_ALL_OCV0_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTS         OCW0
 *  @access     
 *  @brief      Latched PDRV0 W-phase over-current status
 */
#define PDRVSTS_ALL_OCW0_Pos (2)
#define PDRVSTS_ALL_OCW0_Msk (0x1UL << PDRVSTS_ALL_OCW0_Pos)

typedef enum
{
    PDRVSTS_BIT_OCW0_NOT_OCCUR     = 0,  /*!< Pre-driver 0 W-phase over-current event not occur      */
    PDRVSTS_BIT_OCW0_OCCUR         = 1,  /*!< Pre-driver 0 W-phase over-current event has occurred   */
} PDRVSTS_BIT_OCW0;

#define PDRVSTS_ALL_OCW0_NOT_OCCUR     ((0x0UL) << PDRVSTS_ALL_OCW0_Pos)
#define PDRVSTS_ALL_OCW0_OCCUR         ((0x1UL) << PDRVSTS_ALL_OCW0_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTS         OCU1
 *  @access     
 *  @brief      Latched PDRV1 U-phase over-current status
 */
#define PDRVSTS_ALL_OCU1_Pos (3)
#define PDRVSTS_ALL_OCU1_Msk (0x1UL << PDRVSTS_ALL_OCU1_Pos)

typedef enum
{
    PDRVSTS_BIT_OCU1_NOT_OCCUR     = 0,  /*!< Pre-driver 1 U-phase over-current event not occur      */
    PDRVSTS_BIT_OCU1_OCCUR         = 1,  /*!< Pre-driver 1 U-phase over-current event has occurred   */
} PDRVSTS_BIT_OCU1;

#define PDRVSTS_ALL_OCU1_NOT_OCCUR     ((0x0UL) << PDRVSTS_ALL_OCU1_Pos)
#define PDRVSTS_ALL_OCU1_OCCUR         ((0x1UL) << PDRVSTS_ALL_OCU1_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTS         OCV1
 *  @access     
 *  @brief      Latched PDRV1 V-phase over-current status
 */
#define PDRVSTS_ALL_OCV1_Pos (4)
#define PDRVSTS_ALL_OCV1_Msk (0x1UL << PDRVSTS_ALL_OCV1_Pos)

typedef enum
{
    PDRVSTS_BIT_OCV1_NOT_OCCUR     = 0,  /*!< Pre-driver 1 V-phase over-current event not occur      */
    PDRVSTS_BIT_OCV1_OCCUR         = 1,  /*!< Pre-driver 1 V-phase over-current event has occurred   */
} PDRVSTS_BIT_OCV1;

#define PDRVSTS_ALL_OCV1_NOT_OCCUR     ((0x0UL) << PDRVSTS_ALL_OCV1_Pos)
#define PDRVSTS_ALL_OCV1_OCCUR         ((0x1UL) << PDRVSTS_ALL_OCV1_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTS         OCW1
 *  @access     
 *  @brief      Latched PDRV1 W-phase over-current status
 */
#define PDRVSTS_ALL_OCW1_Pos (5)
#define PDRVSTS_ALL_OCW1_Msk (0x1UL << PDRVSTS_ALL_OCW1_Pos)

typedef enum
{
    PDRVSTS_BIT_OCW1_NOT_OCCUR     = 0,  /*!< Pre-driver 1 W-phase over-current event not occur      */
    PDRVSTS_BIT_OCW1_OCCUR         = 1,  /*!< Pre-driver 1 W-phase over-current event has occurred   */
} PDRVSTS_BIT_OCW1;

#define PDRVSTS_ALL_OCW1_NOT_OCCUR     ((0x0UL) << PDRVSTS_ALL_OCW1_Pos)
#define PDRVSTS_ALL_OCW1_OCCUR         ((0x1UL) << PDRVSTS_ALL_OCW1_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTSCLR      OCU0
 *  @access     
 *  @brief      Latched PDRV0 U-phase over-current status clear
 */
#define PDRVSTSCLR_ALL_OCU0_Pos (0)
#define PDRVSTSCLR_ALL_OCU0_Msk (0x1UL << PDRVSTSCLR_ALL_OCU0_Pos)

typedef enum
{
    PDRVSTSCLR_BIT_OCU0_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                                        
                                                 Always readback 0.                                             */
    PDRVSTSCLR_BIT_OCU0_CLEAR         = 1,  /*!< Write 1 will clear Pre-driver 0 U-phase over-current status.  
                                                 This bit is self-clear to 0.                                   */
} PDRVSTSCLR_BIT_OCU0;

#define PDRVSTSCLR_ALL_OCU0_NO_EFFECT     ((0x0UL) << PDRVSTSCLR_ALL_OCU0_Pos)
#define PDRVSTSCLR_ALL_OCU0_CLEAR         ((0x1UL) << PDRVSTSCLR_ALL_OCU0_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTSCLR      OCV0
 *  @access     
 *  @brief      Latched PDRV0 V-phase over-current status clear
 */
#define PDRVSTSCLR_ALL_OCV0_Pos (1)
#define PDRVSTSCLR_ALL_OCV0_Msk (0x1UL << PDRVSTSCLR_ALL_OCV0_Pos)

typedef enum
{
    PDRVSTSCLR_BIT_OCV0_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                                        
                                                 Always readback 0.                                             */
    PDRVSTSCLR_BIT_OCV0_CLEAR         = 1,  /*!< Write 1 will clear Pre-driver 0 V-phase over-current status.  
                                                 This bit is self-clear to 0.                                   */
} PDRVSTSCLR_BIT_OCV0;

#define PDRVSTSCLR_ALL_OCV0_NO_EFFECT     ((0x0UL) << PDRVSTSCLR_ALL_OCV0_Pos)
#define PDRVSTSCLR_ALL_OCV0_CLEAR         ((0x1UL) << PDRVSTSCLR_ALL_OCV0_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTSCLR      OCW0
 *  @access     
 *  @brief      Latched PDRV0 W-phase over-current status clear
 */
#define PDRVSTSCLR_ALL_OCW0_Pos (2)
#define PDRVSTSCLR_ALL_OCW0_Msk (0x1UL << PDRVSTSCLR_ALL_OCW0_Pos)

typedef enum
{
    PDRVSTSCLR_BIT_OCW0_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                                        
                                                 Always readback 0.                                             */
    PDRVSTSCLR_BIT_OCW0_CLEAR         = 1,  /*!< Write 1 will clear Pre-driver 0 W-phase over-current status.  
                                                 This bit is self-clear to 0.                                   */
} PDRVSTSCLR_BIT_OCW0;

#define PDRVSTSCLR_ALL_OCW0_NO_EFFECT     ((0x0UL) << PDRVSTSCLR_ALL_OCW0_Pos)
#define PDRVSTSCLR_ALL_OCW0_CLEAR         ((0x1UL) << PDRVSTSCLR_ALL_OCW0_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTSCLR      OCU1
 *  @access     
 *  @brief      Latched PDRV1 U-phase over-current status clear
 */
#define PDRVSTSCLR_ALL_OCU1_Pos (3)
#define PDRVSTSCLR_ALL_OCU1_Msk (0x1UL << PDRVSTSCLR_ALL_OCU1_Pos)

typedef enum
{
    PDRVSTSCLR_BIT_OCU1_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                                        
                                                 Always readback 0.                                             */
    PDRVSTSCLR_BIT_OCU1_CLEAR         = 1,  /*!< Write 1 will clear Pre-driver 1 U-phase over-current status.  
                                                 This bit is self-clear to 0.                                   */
} PDRVSTSCLR_BIT_OCU1;

#define PDRVSTSCLR_ALL_OCU1_NO_EFFECT     ((0x0UL) << PDRVSTSCLR_ALL_OCU1_Pos)
#define PDRVSTSCLR_ALL_OCU1_CLEAR         ((0x1UL) << PDRVSTSCLR_ALL_OCU1_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTSCLR      OCV1
 *  @access     
 *  @brief      Latched PDRV1 V-phase over-current status clear
 */
#define PDRVSTSCLR_ALL_OCV1_Pos (4)
#define PDRVSTSCLR_ALL_OCV1_Msk (0x1UL << PDRVSTSCLR_ALL_OCV1_Pos)

typedef enum
{
    PDRVSTSCLR_BIT_OCV1_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                                        
                                                 Always readback 0.                                             */
    PDRVSTSCLR_BIT_OCV1_CLEAR         = 1,  /*!< Write 1 will clear Pre-driver 1 V-phase over-current status.  
                                                 This bit is self-clear to 0.                                   */
} PDRVSTSCLR_BIT_OCV1;

#define PDRVSTSCLR_ALL_OCV1_NO_EFFECT     ((0x0UL) << PDRVSTSCLR_ALL_OCV1_Pos)
#define PDRVSTSCLR_ALL_OCV1_CLEAR         ((0x1UL) << PDRVSTSCLR_ALL_OCV1_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVSTSCLR      OCW1
 *  @access     
 *  @brief      Latched PDRV1 W-phase over-current status clear
 */
#define PDRVSTSCLR_ALL_OCW1_Pos (5)
#define PDRVSTSCLR_ALL_OCW1_Msk (0x1UL << PDRVSTSCLR_ALL_OCW1_Pos)

typedef enum
{
    PDRVSTSCLR_BIT_OCW1_NO_EFFECT     = 0,  /*!< Write 0 has no effect.                                        
                                                 Always readback 0.                                             */
    PDRVSTSCLR_BIT_OCW1_CLEAR         = 1,  /*!< Write 1 will clear Pre-driver 1 W-phase over-current status.  
                                                 This bit is self-clear to 0.                                   */
} PDRVSTSCLR_BIT_OCW1;

#define PDRVSTSCLR_ALL_OCW1_NO_EFFECT     ((0x0UL) << PDRVSTSCLR_ALL_OCW1_Pos)
#define PDRVSTSCLR_ALL_OCW1_CLEAR         ((0x1UL) << PDRVSTSCLR_ALL_OCW1_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0TZEN       OCU
 *  @access     
 *  @brief      Enable U-phase over-current event as PDRV0TZ trigger
 */
#define PDRV0TZEN_ALL_OCU_Pos (0)
#define PDRV0TZEN_ALL_OCU_Msk (0x1UL << PDRV0TZEN_ALL_OCU_Pos)

typedef enum
{
    PDRV0TZEN_BIT_OCU_DISABLE     = 0,  /*!< Disable   */
    PDRV0TZEN_BIT_OCU_ENABLE      = 1,  /*!< Enable    */
} PDRV0TZEN_BIT_OCU;

#define PDRV0TZEN_ALL_OCU_DISABLE     ((0x0UL) << PDRV0TZEN_ALL_OCU_Pos)
#define PDRV0TZEN_ALL_OCU_ENABLE      ((0x1UL) << PDRV0TZEN_ALL_OCU_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0TZEN       OCV
 *  @access     
 *  @brief      Enable V-phase over-current event as PDRV0TZ trigger
 */
#define PDRV0TZEN_ALL_OCV_Pos (1)
#define PDRV0TZEN_ALL_OCV_Msk (0x1UL << PDRV0TZEN_ALL_OCV_Pos)

typedef enum
{
    PDRV0TZEN_BIT_OCV_DISABLE     = 0,  /*!< Disable   */
    PDRV0TZEN_BIT_OCV_ENABLE      = 1,  /*!< Enable    */
} PDRV0TZEN_BIT_OCV;

#define PDRV0TZEN_ALL_OCV_DISABLE     ((0x0UL) << PDRV0TZEN_ALL_OCV_Pos)
#define PDRV0TZEN_ALL_OCV_ENABLE      ((0x1UL) << PDRV0TZEN_ALL_OCV_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0TZEN       OCW
 *  @access     
 *  @brief      Enable W-phase over-current event as PDRV0TZ trigger
 */
#define PDRV0TZEN_ALL_OCW_Pos (2)
#define PDRV0TZEN_ALL_OCW_Msk (0x1UL << PDRV0TZEN_ALL_OCW_Pos)

typedef enum
{
    PDRV0TZEN_BIT_OCW_DISABLE     = 0,  /*!< Disable   */
    PDRV0TZEN_BIT_OCW_ENABLE      = 1,  /*!< Enable    */
} PDRV0TZEN_BIT_OCW;

#define PDRV0TZEN_ALL_OCW_DISABLE     ((0x0UL) << PDRV0TZEN_ALL_OCW_Pos)
#define PDRV0TZEN_ALL_OCW_ENABLE      ((0x1UL) << PDRV0TZEN_ALL_OCW_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0TZEN       OTWARN
 *  @access     
 *  @brief      Enable over-temperature warn event as PDRV0TZ trigger
 */
#define PDRV0TZEN_ALL_OTWARN_Pos (3)
#define PDRV0TZEN_ALL_OTWARN_Msk (0x1UL << PDRV0TZEN_ALL_OTWARN_Pos)

typedef enum
{
    PDRV0TZEN_BIT_OTWARN_DISABLE     = 0,  /*!< Disable   */
    PDRV0TZEN_BIT_OTWARN_ENABLE      = 1,  /*!< Enable    */
} PDRV0TZEN_BIT_OTWARN;

#define PDRV0TZEN_ALL_OTWARN_DISABLE     ((0x0UL) << PDRV0TZEN_ALL_OTWARN_Pos)
#define PDRV0TZEN_ALL_OTWARN_ENABLE      ((0x1UL) << PDRV0TZEN_ALL_OTWARN_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0TZEN       VDDGL
 *  @access     
 *  @brief      Enable VDDG too low event as PDRV0TZ trigger
 */
#define PDRV0TZEN_ALL_VDDGL_Pos (4)
#define PDRV0TZEN_ALL_VDDGL_Msk (0x1UL << PDRV0TZEN_ALL_VDDGL_Pos)

typedef enum
{
    PDRV0TZEN_BIT_VDDGL_DISABLE     = 0,  /*!< Disable   */
    PDRV0TZEN_BIT_VDDGL_ENABLE      = 1,  /*!< Enable    */
} PDRV0TZEN_BIT_VDDGL;

#define PDRV0TZEN_ALL_VDDGL_DISABLE     ((0x0UL) << PDRV0TZEN_ALL_VDDGL_Pos)
#define PDRV0TZEN_ALL_VDDGL_ENABLE      ((0x1UL) << PDRV0TZEN_ALL_VDDGL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0TZEN       VDDGH
 *  @access     
 *  @brief      Enable VDDG too high event as PDRV0TZ trigger
 */
#define PDRV0TZEN_ALL_VDDGH_Pos (5)
#define PDRV0TZEN_ALL_VDDGH_Msk (0x1UL << PDRV0TZEN_ALL_VDDGH_Pos)

typedef enum
{
    PDRV0TZEN_BIT_VDDGH_DISABLE     = 0,  /*!< Disable   */
    PDRV0TZEN_BIT_VDDGH_ENABLE      = 1,  /*!< Enable    */
} PDRV0TZEN_BIT_VDDGH;

#define PDRV0TZEN_ALL_VDDGH_DISABLE     ((0x0UL) << PDRV0TZEN_ALL_VDDGH_Pos)
#define PDRV0TZEN_ALL_VDDGH_ENABLE      ((0x1UL) << PDRV0TZEN_ALL_VDDGH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0TZEN       VBATL
 *  @access     
 *  @brief      Enable VBAT too low event as PDRV0TZ trigger
 */
#define PDRV0TZEN_ALL_VBATL_Pos (6)
#define PDRV0TZEN_ALL_VBATL_Msk (0x1UL << PDRV0TZEN_ALL_VBATL_Pos)

typedef enum
{
    PDRV0TZEN_BIT_VBATL_DISABLE     = 0,  /*!< Disable   */
    PDRV0TZEN_BIT_VBATL_ENABLE      = 1,  /*!< Enable    */
} PDRV0TZEN_BIT_VBATL;

#define PDRV0TZEN_ALL_VBATL_DISABLE     ((0x0UL) << PDRV0TZEN_ALL_VBATL_Pos)
#define PDRV0TZEN_ALL_VBATL_ENABLE      ((0x1UL) << PDRV0TZEN_ALL_VBATL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0TZEN       VBATH
 *  @access     
 *  @brief      Enable VBAT too high event as PDRV0TZ trigger
 */
#define PDRV0TZEN_ALL_VBATH_Pos (7)
#define PDRV0TZEN_ALL_VBATH_Msk (0x1UL << PDRV0TZEN_ALL_VBATH_Pos)

typedef enum
{
    PDRV0TZEN_BIT_VBATH_DISABLE     = 0,  /*!< Disable   */
    PDRV0TZEN_BIT_VBATH_ENABLE      = 1,  /*!< Enable    */
} PDRV0TZEN_BIT_VBATH;

#define PDRV0TZEN_ALL_VBATH_DISABLE     ((0x0UL) << PDRV0TZEN_ALL_VBATH_Pos)
#define PDRV0TZEN_ALL_VBATH_ENABLE      ((0x1UL) << PDRV0TZEN_ALL_VBATH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1TZEN       OCU
 *  @access     
 *  @brief      Enable U-phase over-current event as PDRV1TZ trigger
 */
#define PDRV1TZEN_ALL_OCU_Pos (0)
#define PDRV1TZEN_ALL_OCU_Msk (0x1UL << PDRV1TZEN_ALL_OCU_Pos)

typedef enum
{
    PDRV1TZEN_BIT_OCU_DISABLE     = 0,  /*!< Disable   */
    PDRV1TZEN_BIT_OCU_ENABLE      = 1,  /*!< Enable    */
} PDRV1TZEN_BIT_OCU;

#define PDRV1TZEN_ALL_OCU_DISABLE     ((0x0UL) << PDRV1TZEN_ALL_OCU_Pos)
#define PDRV1TZEN_ALL_OCU_ENABLE      ((0x1UL) << PDRV1TZEN_ALL_OCU_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1TZEN       OCV
 *  @access     
 *  @brief      Enable V-phase over-current event as PDRV1TZ trigger
 */
#define PDRV1TZEN_ALL_OCV_Pos (1)
#define PDRV1TZEN_ALL_OCV_Msk (0x1UL << PDRV1TZEN_ALL_OCV_Pos)

typedef enum
{
    PDRV1TZEN_BIT_OCV_DISABLE     = 0,  /*!< Disable   */
    PDRV1TZEN_BIT_OCV_ENABLE      = 1,  /*!< Enable    */
} PDRV1TZEN_BIT_OCV;

#define PDRV1TZEN_ALL_OCV_DISABLE     ((0x0UL) << PDRV1TZEN_ALL_OCV_Pos)
#define PDRV1TZEN_ALL_OCV_ENABLE      ((0x1UL) << PDRV1TZEN_ALL_OCV_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1TZEN       OCW
 *  @access     
 *  @brief      Enable W-phase over-current event as PDRV1TZ trigger
 */
#define PDRV1TZEN_ALL_OCW_Pos (2)
#define PDRV1TZEN_ALL_OCW_Msk (0x1UL << PDRV1TZEN_ALL_OCW_Pos)

typedef enum
{
    PDRV1TZEN_BIT_OCW_DISABLE     = 0,  /*!< Disable   */
    PDRV1TZEN_BIT_OCW_ENABLE      = 1,  /*!< Enable    */
} PDRV1TZEN_BIT_OCW;

#define PDRV1TZEN_ALL_OCW_DISABLE     ((0x0UL) << PDRV1TZEN_ALL_OCW_Pos)
#define PDRV1TZEN_ALL_OCW_ENABLE      ((0x1UL) << PDRV1TZEN_ALL_OCW_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1TZEN       OTWARN
 *  @access     
 *  @brief      Enable over-temperature warn event as PDRV1TZ trigger
 */
#define PDRV1TZEN_ALL_OTWARN_Pos (3)
#define PDRV1TZEN_ALL_OTWARN_Msk (0x1UL << PDRV1TZEN_ALL_OTWARN_Pos)

typedef enum
{
    PDRV1TZEN_BIT_OTWARN_DISABLE     = 0,  /*!< Disable   */
    PDRV1TZEN_BIT_OTWARN_ENABLE      = 1,  /*!< Enable    */
} PDRV1TZEN_BIT_OTWARN;

#define PDRV1TZEN_ALL_OTWARN_DISABLE     ((0x0UL) << PDRV1TZEN_ALL_OTWARN_Pos)
#define PDRV1TZEN_ALL_OTWARN_ENABLE      ((0x1UL) << PDRV1TZEN_ALL_OTWARN_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1TZEN       VDDGL
 *  @access     
 *  @brief      Enable VDDG too low event as PDRV1TZ trigger
 */
#define PDRV1TZEN_ALL_VDDGL_Pos (4)
#define PDRV1TZEN_ALL_VDDGL_Msk (0x1UL << PDRV1TZEN_ALL_VDDGL_Pos)

typedef enum
{
    PDRV1TZEN_BIT_VDDGL_DISABLE     = 0,  /*!< Disable   */
    PDRV1TZEN_BIT_VDDGL_ENABLE      = 1,  /*!< Enable    */
} PDRV1TZEN_BIT_VDDGL;

#define PDRV1TZEN_ALL_VDDGL_DISABLE     ((0x0UL) << PDRV1TZEN_ALL_VDDGL_Pos)
#define PDRV1TZEN_ALL_VDDGL_ENABLE      ((0x1UL) << PDRV1TZEN_ALL_VDDGL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1TZEN       VDDGH
 *  @access     
 *  @brief      Enable VDDG too high event as PDRV1TZ trigger
 */
#define PDRV1TZEN_ALL_VDDGH_Pos (5)
#define PDRV1TZEN_ALL_VDDGH_Msk (0x1UL << PDRV1TZEN_ALL_VDDGH_Pos)

typedef enum
{
    PDRV1TZEN_BIT_VDDGH_DISABLE     = 0,  /*!< Disable   */
    PDRV1TZEN_BIT_VDDGH_ENABLE      = 1,  /*!< Enable    */
} PDRV1TZEN_BIT_VDDGH;

#define PDRV1TZEN_ALL_VDDGH_DISABLE     ((0x0UL) << PDRV1TZEN_ALL_VDDGH_Pos)
#define PDRV1TZEN_ALL_VDDGH_ENABLE      ((0x1UL) << PDRV1TZEN_ALL_VDDGH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1TZEN       VBATL
 *  @access     
 *  @brief      Enable VBAT too low event as PDRV1TZ trigger
 */
#define PDRV1TZEN_ALL_VBATL_Pos (6)
#define PDRV1TZEN_ALL_VBATL_Msk (0x1UL << PDRV1TZEN_ALL_VBATL_Pos)

typedef enum
{
    PDRV1TZEN_BIT_VBATL_DISABLE     = 0,  /*!< Disable   */
    PDRV1TZEN_BIT_VBATL_ENABLE      = 1,  /*!< Enable    */
} PDRV1TZEN_BIT_VBATL;

#define PDRV1TZEN_ALL_VBATL_DISABLE     ((0x0UL) << PDRV1TZEN_ALL_VBATL_Pos)
#define PDRV1TZEN_ALL_VBATL_ENABLE      ((0x1UL) << PDRV1TZEN_ALL_VBATL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1TZEN       VBATH
 *  @access     
 *  @brief      Enable VBAT too high event as PDRV1TZ trigger
 */
#define PDRV1TZEN_ALL_VBATH_Pos (7)
#define PDRV1TZEN_ALL_VBATH_Msk (0x1UL << PDRV1TZEN_ALL_VBATH_Pos)

typedef enum
{
    PDRV1TZEN_BIT_VBATH_DISABLE     = 0,  /*!< Disable   */
    PDRV1TZEN_BIT_VBATH_ENABLE      = 1,  /*!< Enable    */
} PDRV1TZEN_BIT_VBATH;

#define PDRV1TZEN_ALL_VBATH_DISABLE     ((0x0UL) << PDRV1TZEN_ALL_VBATH_Pos)
#define PDRV1TZEN_ALL_VBATH_ENABLE      ((0x1UL) << PDRV1TZEN_ALL_VBATH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              LDOGCTL         VREFSEL
 *  @access     
 *  @brief      VDDG LDO reference voltage select
 */
#define LDOGCTL_ALL_VREFSEL_Pos (0)
#define LDOGCTL_ALL_VREFSEL_Msk (0x7UL << LDOGCTL_ALL_VREFSEL_Pos)

typedef enum
{
    LDOGCTL_BIT_VREFSEL_9_V      = 2,  /*!< 9V    */
    LDOGCTL_BIT_VREFSEL_10_V     = 3,  /*!< 10V   */
    LDOGCTL_BIT_VREFSEL_12_V     = 4,  /*!< 12V   */
    LDOGCTL_BIT_VREFSEL_15_V     = 5,  /*!< 15V   */
    LDOGCTL_BIT_VREFSEL_18_V     = 6,  /*!< 18V   */
} LDOGCTL_BIT_VREFSEL;

#define LDOGCTL_ALL_VREFSEL_9_V      ((0x2UL) << LDOGCTL_ALL_VREFSEL_Pos)
#define LDOGCTL_ALL_VREFSEL_10_V     ((0x3UL) << LDOGCTL_ALL_VREFSEL_Pos)
#define LDOGCTL_ALL_VREFSEL_12_V     ((0x4UL) << LDOGCTL_ALL_VREFSEL_Pos)
#define LDOGCTL_ALL_VREFSEL_15_V     ((0x5UL) << LDOGCTL_ALL_VREFSEL_Pos)
#define LDOGCTL_ALL_VREFSEL_18_V     ((0x6UL) << LDOGCTL_ALL_VREFSEL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              LDOGCTL         OTWARNTH
 *  @access     
 *  @brief      Threshold for over temperature warning
 */
#define LDOGCTL_ALL_OTWARNTH_Pos (3)
#define LDOGCTL_ALL_OTWARNTH_Msk (0x7UL << LDOGCTL_ALL_OTWARNTH_Pos)

typedef enum
{
    LDOGCTL_BIT_OTWARNTH_146_DEGREE     = 0,  /*!< 146 centigrade degree   */
    LDOGCTL_BIT_OTWARNTH_138_DEGREE     = 1,  /*!< 138 centigrade degree   */
    LDOGCTL_BIT_OTWARNTH_131_DEGREE     = 2,  /*!< 131 centigrade degree   */
    LDOGCTL_BIT_OTWARNTH_122_DEGREE     = 3,  /*!< 122 centigrade degree   */
    LDOGCTL_BIT_OTWARNTH_114_DEGREE     = 4,  /*!< 114 centigrade degree   */
    LDOGCTL_BIT_OTWARNTH_107_DEGREE     = 5,  /*!< 107 centigrade degree   */
    LDOGCTL_BIT_OTWARNTH_99_DEGREE      = 6,  /*!< 99 centigrade degree    */
} LDOGCTL_BIT_OTWARNTH;

#define LDOGCTL_ALL_OTWARNTH_146_DEGREE     ((0x0UL) << LDOGCTL_ALL_OTWARNTH_Pos)
#define LDOGCTL_ALL_OTWARNTH_138_DEGREE     ((0x1UL) << LDOGCTL_ALL_OTWARNTH_Pos)
#define LDOGCTL_ALL_OTWARNTH_131_DEGREE     ((0x2UL) << LDOGCTL_ALL_OTWARNTH_Pos)
#define LDOGCTL_ALL_OTWARNTH_122_DEGREE     ((0x3UL) << LDOGCTL_ALL_OTWARNTH_Pos)
#define LDOGCTL_ALL_OTWARNTH_114_DEGREE     ((0x4UL) << LDOGCTL_ALL_OTWARNTH_Pos)
#define LDOGCTL_ALL_OTWARNTH_107_DEGREE     ((0x5UL) << LDOGCTL_ALL_OTWARNTH_Pos)
#define LDOGCTL_ALL_OTWARNTH_99_DEGREE      ((0x6UL) << LDOGCTL_ALL_OTWARNTH_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODCTL          VDDGEN
 *  @access     
 *  @brief      VDDG BOD enable
 */
#define BODCTL_ALL_VDDGEN_Pos (0)
#define BODCTL_ALL_VDDGEN_Msk (0x1UL << BODCTL_ALL_VDDGEN_Pos)

typedef enum
{
    BODCTL_BIT_VDDGEN_DISABLE     = 0,  /*!< Disable   */
    BODCTL_BIT_VDDGEN_ENABLE      = 1,  /*!< Enable    */
} BODCTL_BIT_VDDGEN;

#define BODCTL_ALL_VDDGEN_DISABLE     ((0x0UL) << BODCTL_ALL_VDDGEN_Pos)
#define BODCTL_ALL_VDDGEN_ENABLE      ((0x1UL) << BODCTL_ALL_VDDGEN_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODCTL          VBATEN
 *  @access     
 *  @brief      VBAT BOD enable
 */
#define BODCTL_ALL_VBATEN_Pos (1)
#define BODCTL_ALL_VBATEN_Msk (0x1UL << BODCTL_ALL_VBATEN_Pos)

typedef enum
{
    BODCTL_BIT_VBATEN_DISABLE     = 0,  /*!< Disable   */
    BODCTL_BIT_VBATEN_ENABLE      = 1,  /*!< Enable    */
} BODCTL_BIT_VBATEN;

#define BODCTL_ALL_VBATEN_DISABLE     ((0x0UL) << BODCTL_ALL_VBATEN_Pos)
#define BODCTL_ALL_VBATEN_ENABLE      ((0x1UL) << BODCTL_ALL_VBATEN_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVDDGLVTH     DEASSERT
 *  @access     
 *  @brief      Threshold to de-assert VDDGL
 */
#define BODVDDGLVTH_ALL_DEASSERT_Pos (0)
#define BODVDDGLVTH_ALL_DEASSERT_Msk (0xFUL << BODVDDGLVTH_ALL_DEASSERT_Pos)

typedef enum
{
    BODVDDGLVTH_BIT_DEASSERT_1dot6_V      = 0,  /*!< 1.6V    */
    BODVDDGLVTH_BIT_DEASSERT_3dot2_V      = 1,  /*!< 3.2V    */
    BODVDDGLVTH_BIT_DEASSERT_4dot8_V      = 2,  /*!< 4.8V    */
    BODVDDGLVTH_BIT_DEASSERT_6dot4_V      = 3,  /*!< 6.4V    */
    BODVDDGLVTH_BIT_DEASSERT_8dot0_V      = 4,  /*!< 8.0V    */
    BODVDDGLVTH_BIT_DEASSERT_9dot6_V      = 5,  /*!< 9.6V    */
    BODVDDGLVTH_BIT_DEASSERT_11dot2_V     = 6,  /*!< 11.2V   */
    BODVDDGLVTH_BIT_DEASSERT_12dot8_V     = 7,  /*!< 12.8V   */
    BODVDDGLVTH_BIT_DEASSERT_14dot4_V     = 8,  /*!< 14.4V   */
    BODVDDGLVTH_BIT_DEASSERT_16dot0_V     = 9,  /*!< 16.0V   */
    BODVDDGLVTH_BIT_DEASSERT_17dot6_V     = 10,  /*!< 17.6V   */
    BODVDDGLVTH_BIT_DEASSERT_19dot2_V     = 11,  /*!< 19.2V   */
    BODVDDGLVTH_BIT_DEASSERT_20dot8_V     = 12,  /*!< 20.8V   */
    BODVDDGLVTH_BIT_DEASSERT_22dot4_V     = 13,  /*!< 22.4V   */
    BODVDDGLVTH_BIT_DEASSERT_24dot0_V     = 14,  /*!< 24.0V   */
    BODVDDGLVTH_BIT_DEASSERT_25dot6_V     = 15,  /*!< 25.6V   */
} BODVDDGLVTH_BIT_DEASSERT;

#define BODVDDGLVTH_ALL_DEASSERT_1dot6_V      ((0x00UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_3dot2_V      ((0x01UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_4dot8_V      ((0x02UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_6dot4_V      ((0x03UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_8dot0_V      ((0x04UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_9dot6_V      ((0x05UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_11dot2_V     ((0x06UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_12dot8_V     ((0x07UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_14dot4_V     ((0x08UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_16dot0_V     ((0x09UL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_17dot6_V     ((0x0AUL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_19dot2_V     ((0x0BUL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_20dot8_V     ((0x0CUL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_22dot4_V     ((0x0DUL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_24dot0_V     ((0x0EUL) << BODVDDGLVTH_ALL_DEASSERT_Pos)
#define BODVDDGLVTH_ALL_DEASSERT_25dot6_V     ((0x0FUL) << BODVDDGLVTH_ALL_DEASSERT_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVDDGLVTH     ASSERT
 *  @access     
 *  @brief      Threshold to assert VDDGL
 */
#define BODVDDGLVTH_ALL_ASSERT_Pos (4)
#define BODVDDGLVTH_ALL_ASSERT_Msk (0xFUL << BODVDDGLVTH_ALL_ASSERT_Pos)

typedef enum
{
    BODVDDGLVTH_BIT_ASSERT_1dot6_V      = 0,  /*!< 1.6V    */
    BODVDDGLVTH_BIT_ASSERT_3dot2_V      = 1,  /*!< 3.2V    */
    BODVDDGLVTH_BIT_ASSERT_4dot8_V      = 2,  /*!< 4.8V    */
    BODVDDGLVTH_BIT_ASSERT_6dot4_V      = 3,  /*!< 6.4V    */
    BODVDDGLVTH_BIT_ASSERT_8dot0_V      = 4,  /*!< 8.0V    */
    BODVDDGLVTH_BIT_ASSERT_9dot6_V      = 5,  /*!< 9.6V    */
    BODVDDGLVTH_BIT_ASSERT_11dot2_V     = 6,  /*!< 11.2V   */
    BODVDDGLVTH_BIT_ASSERT_12dot8_V     = 7,  /*!< 12.8V   */
    BODVDDGLVTH_BIT_ASSERT_14dot4_V     = 8,  /*!< 14.4V   */
    BODVDDGLVTH_BIT_ASSERT_16dot0_V     = 9,  /*!< 16.0V   */
    BODVDDGLVTH_BIT_ASSERT_17dot6_V     = 10,  /*!< 17.6V   */
    BODVDDGLVTH_BIT_ASSERT_19dot2_V     = 11,  /*!< 19.2V   */
    BODVDDGLVTH_BIT_ASSERT_20dot8_V     = 12,  /*!< 20.8V   */
    BODVDDGLVTH_BIT_ASSERT_22dot4_V     = 13,  /*!< 22.4V   */
    BODVDDGLVTH_BIT_ASSERT_24dot0_V     = 14,  /*!< 24.0V   */
    BODVDDGLVTH_BIT_ASSERT_25dot6_V     = 15,  /*!< 25.6V   */
} BODVDDGLVTH_BIT_ASSERT;

#define BODVDDGLVTH_ALL_ASSERT_1dot6_V      ((0x00UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_3dot2_V      ((0x01UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_4dot8_V      ((0x02UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_6dot4_V      ((0x03UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_8dot0_V      ((0x04UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_9dot6_V      ((0x05UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_11dot2_V     ((0x06UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_12dot8_V     ((0x07UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_14dot4_V     ((0x08UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_16dot0_V     ((0x09UL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_17dot6_V     ((0x0AUL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_19dot2_V     ((0x0BUL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_20dot8_V     ((0x0CUL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_22dot4_V     ((0x0DUL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_24dot0_V     ((0x0EUL) << BODVDDGLVTH_ALL_ASSERT_Pos)
#define BODVDDGLVTH_ALL_ASSERT_25dot6_V     ((0x0FUL) << BODVDDGLVTH_ALL_ASSERT_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVDDGHVTH     DEASSERT
 *  @access     
 *  @brief      Threshold to de-assert VDDGH
 */
#define BODVDDGHVTH_ALL_DEASSERT_Pos (0)
#define BODVDDGHVTH_ALL_DEASSERT_Msk (0xFUL << BODVDDGHVTH_ALL_DEASSERT_Pos)

typedef enum
{
    BODVDDGHVTH_BIT_DEASSERT_1dot6_V      = 0,  /*!< 1.6V    */
    BODVDDGHVTH_BIT_DEASSERT_3dot2_V      = 1,  /*!< 3.2V    */
    BODVDDGHVTH_BIT_DEASSERT_4dot8_V      = 2,  /*!< 4.8V    */
    BODVDDGHVTH_BIT_DEASSERT_6dot4_V      = 3,  /*!< 6.4V    */
    BODVDDGHVTH_BIT_DEASSERT_8dot0_V      = 4,  /*!< 8.0V    */
    BODVDDGHVTH_BIT_DEASSERT_9dot6_V      = 5,  /*!< 9.6V    */
    BODVDDGHVTH_BIT_DEASSERT_11dot2_V     = 6,  /*!< 11.2V   */
    BODVDDGHVTH_BIT_DEASSERT_12dot8_V     = 7,  /*!< 12.8V   */
    BODVDDGHVTH_BIT_DEASSERT_14dot4_V     = 8,  /*!< 14.4V   */
    BODVDDGHVTH_BIT_DEASSERT_16dot0_V     = 9,  /*!< 16.0V   */
    BODVDDGHVTH_BIT_DEASSERT_17dot6_V     = 10,  /*!< 17.6V   */
    BODVDDGHVTH_BIT_DEASSERT_19dot2_V     = 11,  /*!< 19.2V   */
    BODVDDGHVTH_BIT_DEASSERT_20dot8_V     = 12,  /*!< 20.8V   */
    BODVDDGHVTH_BIT_DEASSERT_22dot4_V     = 13,  /*!< 22.4V   */
    BODVDDGHVTH_BIT_DEASSERT_24dot0_V     = 14,  /*!< 24.0V   */
    BODVDDGHVTH_BIT_DEASSERT_25dot6_V     = 15,  /*!< 25.6V   */
} BODVDDGHVTH_BIT_DEASSERT;

#define BODVDDGHVTH_ALL_DEASSERT_1dot6_V      ((0x00UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_3dot2_V      ((0x01UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_4dot8_V      ((0x02UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_6dot4_V      ((0x03UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_8dot0_V      ((0x04UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_9dot6_V      ((0x05UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_11dot2_V     ((0x06UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_12dot8_V     ((0x07UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_14dot4_V     ((0x08UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_16dot0_V     ((0x09UL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_17dot6_V     ((0x0AUL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_19dot2_V     ((0x0BUL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_20dot8_V     ((0x0CUL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_22dot4_V     ((0x0DUL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_24dot0_V     ((0x0EUL) << BODVDDGHVTH_ALL_DEASSERT_Pos)
#define BODVDDGHVTH_ALL_DEASSERT_25dot6_V     ((0x0FUL) << BODVDDGHVTH_ALL_DEASSERT_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVDDGHVTH     ASSERT
 *  @access     
 *  @brief      Threshold to assert VDDGH
 */
#define BODVDDGHVTH_ALL_ASSERT_Pos (4)
#define BODVDDGHVTH_ALL_ASSERT_Msk (0xFUL << BODVDDGHVTH_ALL_ASSERT_Pos)

typedef enum
{
    BODVDDGHVTH_BIT_ASSERT_1dot6_V      = 0,  /*!< 1.6V    */
    BODVDDGHVTH_BIT_ASSERT_3dot2_V      = 1,  /*!< 3.2V    */
    BODVDDGHVTH_BIT_ASSERT_4dot8_V      = 2,  /*!< 4.8V    */
    BODVDDGHVTH_BIT_ASSERT_6dot4_V      = 3,  /*!< 6.4V    */
    BODVDDGHVTH_BIT_ASSERT_8dot0_V      = 4,  /*!< 8.0V    */
    BODVDDGHVTH_BIT_ASSERT_9dot6_V      = 5,  /*!< 9.6V    */
    BODVDDGHVTH_BIT_ASSERT_11dot2_V     = 6,  /*!< 11.2V   */
    BODVDDGHVTH_BIT_ASSERT_12dot8_V     = 7,  /*!< 12.8V   */
    BODVDDGHVTH_BIT_ASSERT_14dot4_V     = 8,  /*!< 14.4V   */
    BODVDDGHVTH_BIT_ASSERT_16dot0_V     = 9,  /*!< 16.0V   */
    BODVDDGHVTH_BIT_ASSERT_17dot6_V     = 10,  /*!< 17.6V   */
    BODVDDGHVTH_BIT_ASSERT_19dot2_V     = 11,  /*!< 19.2V   */
    BODVDDGHVTH_BIT_ASSERT_20dot8_V     = 12,  /*!< 20.8V   */
    BODVDDGHVTH_BIT_ASSERT_22dot4_V     = 13,  /*!< 22.4V   */
    BODVDDGHVTH_BIT_ASSERT_24dot0_V     = 14,  /*!< 24.0V   */
    BODVDDGHVTH_BIT_ASSERT_25dot6_V     = 15,  /*!< 25.6V   */
} BODVDDGHVTH_BIT_ASSERT;

#define BODVDDGHVTH_ALL_ASSERT_1dot6_V      ((0x00UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_3dot2_V      ((0x01UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_4dot8_V      ((0x02UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_6dot4_V      ((0x03UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_8dot0_V      ((0x04UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_9dot6_V      ((0x05UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_11dot2_V     ((0x06UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_12dot8_V     ((0x07UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_14dot4_V     ((0x08UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_16dot0_V     ((0x09UL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_17dot6_V     ((0x0AUL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_19dot2_V     ((0x0BUL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_20dot8_V     ((0x0CUL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_22dot4_V     ((0x0DUL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_24dot0_V     ((0x0EUL) << BODVDDGHVTH_ALL_ASSERT_Pos)
#define BODVDDGHVTH_ALL_ASSERT_25dot6_V     ((0x0FUL) << BODVDDGHVTH_ALL_ASSERT_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVBATLVTH     DEASSERT
 *  @access     
 *  @brief      Threshold to de-assert VBATL
 */
#define BODVBATLVTH_ALL_DEASSERT_Pos (0)
#define BODVBATLVTH_ALL_DEASSERT_Msk (0xFUL << BODVBATLVTH_ALL_DEASSERT_Pos)

typedef enum
{
    BODVBATLVTH_BIT_DEASSERT_8dot0_V      = 0,  /*!< 8.0V    */
    BODVBATLVTH_BIT_DEASSERT_9dot6_V      = 1,  /*!< 9.6V    */
    BODVBATLVTH_BIT_DEASSERT_14dot4_V     = 2,  /*!< 14.4V   */
    BODVBATLVTH_BIT_DEASSERT_19dot2_V     = 3,  /*!< 19.2V   */
    BODVBATLVTH_BIT_DEASSERT_24dot0_V     = 4,  /*!< 24.0V   */
    BODVBATLVTH_BIT_DEASSERT_28dot8_V     = 5,  /*!< 28.8V   */
    BODVBATLVTH_BIT_DEASSERT_33dot6_V     = 6,  /*!< 33.6V   */
    BODVBATLVTH_BIT_DEASSERT_38dot4_V     = 7,  /*!< 38.4V   */
    BODVBATLVTH_BIT_DEASSERT_43dot2_V     = 8,  /*!< 43.2V   */
    BODVBATLVTH_BIT_DEASSERT_48dot0_V     = 9,  /*!< 48.0V   */
    BODVBATLVTH_BIT_DEASSERT_52dot8_V     = 10,  /*!< 52.8V   */
    BODVBATLVTH_BIT_DEASSERT_57dot6_V     = 11,  /*!< 57.6V   */
    BODVBATLVTH_BIT_DEASSERT_62dot4_V     = 12,  /*!< 62.4V   */
    BODVBATLVTH_BIT_DEASSERT_67dot2_V     = 13,  /*!< 67.2V   */
    BODVBATLVTH_BIT_DEASSERT_72dot0_V     = 14,  /*!< 72.0V   */
    BODVBATLVTH_BIT_DEASSERT_76dot8_V     = 15,  /*!< 76.8V   */
} BODVBATLVTH_BIT_DEASSERT;

#define BODVBATLVTH_ALL_DEASSERT_8dot0_V      ((0x00UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_9dot6_V      ((0x01UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_14dot4_V     ((0x02UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_19dot2_V     ((0x03UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_24dot0_V     ((0x04UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_28dot8_V     ((0x05UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_33dot6_V     ((0x06UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_38dot4_V     ((0x07UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_43dot2_V     ((0x08UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_48dot0_V     ((0x09UL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_52dot8_V     ((0x0AUL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_57dot6_V     ((0x0BUL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_62dot4_V     ((0x0CUL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_67dot2_V     ((0x0DUL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_72dot0_V     ((0x0EUL) << BODVBATLVTH_ALL_DEASSERT_Pos)
#define BODVBATLVTH_ALL_DEASSERT_76dot8_V     ((0x0FUL) << BODVBATLVTH_ALL_DEASSERT_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVBATLVTH     ASSERT
 *  @access     
 *  @brief      Threshold to assert VBATL
 */
#define BODVBATLVTH_ALL_ASSERT_Pos (4)
#define BODVBATLVTH_ALL_ASSERT_Msk (0xFUL << BODVBATLVTH_ALL_ASSERT_Pos)

typedef enum
{
    BODVBATLVTH_BIT_ASSERT_8dot0_V      = 0,  /*!< 8.0V    */
    BODVBATLVTH_BIT_ASSERT_9dot6_V      = 1,  /*!< 9.6V    */
    BODVBATLVTH_BIT_ASSERT_14dot4_V     = 2,  /*!< 14.4V   */
    BODVBATLVTH_BIT_ASSERT_19dot2_V     = 3,  /*!< 19.2V   */
    BODVBATLVTH_BIT_ASSERT_24dot0_V     = 4,  /*!< 24.0V   */
    BODVBATLVTH_BIT_ASSERT_28dot8_V     = 5,  /*!< 28.8V   */
    BODVBATLVTH_BIT_ASSERT_33dot6_V     = 6,  /*!< 33.6V   */
    BODVBATLVTH_BIT_ASSERT_38dot4_V     = 7,  /*!< 38.4V   */
    BODVBATLVTH_BIT_ASSERT_43dot2_V     = 8,  /*!< 43.2V   */
    BODVBATLVTH_BIT_ASSERT_48dot0_V     = 9,  /*!< 48.0V   */
    BODVBATLVTH_BIT_ASSERT_52dot8_V     = 10,  /*!< 52.8V   */
    BODVBATLVTH_BIT_ASSERT_57dot6_V     = 11,  /*!< 57.6V   */
    BODVBATLVTH_BIT_ASSERT_62dot4_V     = 12,  /*!< 62.4V   */
    BODVBATLVTH_BIT_ASSERT_67dot2_V     = 13,  /*!< 67.2V   */
    BODVBATLVTH_BIT_ASSERT_72dot0_V     = 14,  /*!< 72.0V   */
    BODVBATLVTH_BIT_ASSERT_76dot8_V     = 15,  /*!< 76.8V   */
} BODVBATLVTH_BIT_ASSERT;

#define BODVBATLVTH_ALL_ASSERT_8dot0_V      ((0x00UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_9dot6_V      ((0x01UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_14dot4_V     ((0x02UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_19dot2_V     ((0x03UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_24dot0_V     ((0x04UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_28dot8_V     ((0x05UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_33dot6_V     ((0x06UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_38dot4_V     ((0x07UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_43dot2_V     ((0x08UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_48dot0_V     ((0x09UL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_52dot8_V     ((0x0AUL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_57dot6_V     ((0x0BUL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_62dot4_V     ((0x0CUL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_67dot2_V     ((0x0DUL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_72dot0_V     ((0x0EUL) << BODVBATLVTH_ALL_ASSERT_Pos)
#define BODVBATLVTH_ALL_ASSERT_76dot8_V     ((0x0FUL) << BODVBATLVTH_ALL_ASSERT_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVBATHVTH     DEASSERT
 *  @access     
 *  @brief      Threshold to de-assert VBATH
 */
#define BODVBATHVTH_ALL_DEASSERT_Pos (0)
#define BODVBATHVTH_ALL_DEASSERT_Msk (0xFUL << BODVBATHVTH_ALL_DEASSERT_Pos)

typedef enum
{
    BODVBATHVTH_BIT_DEASSERT_8dot0_V      = 0,  /*!< 8.0V    */
    BODVBATHVTH_BIT_DEASSERT_9dot6_V      = 1,  /*!< 9.6V    */
    BODVBATHVTH_BIT_DEASSERT_14dot4_V     = 2,  /*!< 14.4V   */
    BODVBATHVTH_BIT_DEASSERT_19dot2_V     = 3,  /*!< 19.2V   */
    BODVBATHVTH_BIT_DEASSERT_24dot0_V     = 4,  /*!< 24.0V   */
    BODVBATHVTH_BIT_DEASSERT_28dot8_V     = 5,  /*!< 28.8V   */
    BODVBATHVTH_BIT_DEASSERT_33dot6_V     = 6,  /*!< 33.6V   */
    BODVBATHVTH_BIT_DEASSERT_38dot4_V     = 7,  /*!< 38.4V   */
    BODVBATHVTH_BIT_DEASSERT_43dot2_V     = 8,  /*!< 43.2V   */
    BODVBATHVTH_BIT_DEASSERT_48dot0_V     = 9,  /*!< 48.0V   */
    BODVBATHVTH_BIT_DEASSERT_52dot8_V     = 10,  /*!< 52.8V   */
    BODVBATHVTH_BIT_DEASSERT_57dot6_V     = 11,  /*!< 57.6V   */
    BODVBATHVTH_BIT_DEASSERT_62dot4_V     = 12,  /*!< 62.4V   */
    BODVBATHVTH_BIT_DEASSERT_67dot2_V     = 13,  /*!< 67.2V   */
    BODVBATHVTH_BIT_DEASSERT_72dot0_V     = 14,  /*!< 72.0V   */
    BODVBATHVTH_BIT_DEASSERT_76dot8_V     = 15,  /*!< 76.8V   */
} BODVBATHVTH_BIT_DEASSERT;

#define BODVBATHVTH_ALL_DEASSERT_8dot0_V      ((0x00UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_9dot6_V      ((0x01UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_14dot4_V     ((0x02UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_19dot2_V     ((0x03UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_24dot0_V     ((0x04UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_28dot8_V     ((0x05UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_33dot6_V     ((0x06UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_38dot4_V     ((0x07UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_43dot2_V     ((0x08UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_48dot0_V     ((0x09UL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_52dot8_V     ((0x0AUL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_57dot6_V     ((0x0BUL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_62dot4_V     ((0x0CUL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_67dot2_V     ((0x0DUL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_72dot0_V     ((0x0EUL) << BODVBATHVTH_ALL_DEASSERT_Pos)
#define BODVBATHVTH_ALL_DEASSERT_76dot8_V     ((0x0FUL) << BODVBATHVTH_ALL_DEASSERT_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVBATHVTH     ASSERT
 *  @access     
 *  @brief      Threshold to assert VBATH
 */
#define BODVBATHVTH_ALL_ASSERT_Pos (4)
#define BODVBATHVTH_ALL_ASSERT_Msk (0xFUL << BODVBATHVTH_ALL_ASSERT_Pos)

typedef enum
{
    BODVBATHVTH_BIT_ASSERT_8dot0_V      = 0,  /*!< 8.0V    */
    BODVBATHVTH_BIT_ASSERT_9dot6_V      = 1,  /*!< 9.6V    */
    BODVBATHVTH_BIT_ASSERT_14dot4_V     = 2,  /*!< 14.4V   */
    BODVBATHVTH_BIT_ASSERT_19dot2_V     = 3,  /*!< 19.2V   */
    BODVBATHVTH_BIT_ASSERT_24dot0_V     = 4,  /*!< 24.0V   */
    BODVBATHVTH_BIT_ASSERT_28dot8_V     = 5,  /*!< 28.8V   */
    BODVBATHVTH_BIT_ASSERT_33dot6_V     = 6,  /*!< 33.6V   */
    BODVBATHVTH_BIT_ASSERT_38dot4_V     = 7,  /*!< 38.4V   */
    BODVBATHVTH_BIT_ASSERT_43dot2_V     = 8,  /*!< 43.2V   */
    BODVBATHVTH_BIT_ASSERT_48dot0_V     = 9,  /*!< 48.0V   */
    BODVBATHVTH_BIT_ASSERT_52dot8_V     = 10,  /*!< 52.8V   */
    BODVBATHVTH_BIT_ASSERT_57dot6_V     = 11,  /*!< 57.6V   */
    BODVBATHVTH_BIT_ASSERT_62dot4_V     = 12,  /*!< 62.4V   */
    BODVBATHVTH_BIT_ASSERT_67dot2_V     = 13,  /*!< 67.2V   */
    BODVBATHVTH_BIT_ASSERT_72dot0_V     = 14,  /*!< 72.0V   */
    BODVBATHVTH_BIT_ASSERT_76dot8_V     = 15,  /*!< 76.8V   */
} BODVBATHVTH_BIT_ASSERT;

#define BODVBATHVTH_ALL_ASSERT_8dot0_V      ((0x00UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_9dot6_V      ((0x01UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_14dot4_V     ((0x02UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_19dot2_V     ((0x03UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_24dot0_V     ((0x04UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_28dot8_V     ((0x05UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_33dot6_V     ((0x06UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_38dot4_V     ((0x07UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_43dot2_V     ((0x08UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_48dot0_V     ((0x09UL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_52dot8_V     ((0x0AUL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_57dot6_V     ((0x0BUL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_62dot4_V     ((0x0CUL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_67dot2_V     ((0x0DUL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_72dot0_V     ((0x0EUL) << BODVBATHVTH_ALL_ASSERT_Pos)
#define BODVBATHVTH_ALL_ASSERT_76dot8_V     ((0x0FUL) << BODVBATHVTH_ALL_ASSERT_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0CTL0       MINNOV
 *  @access     
 *  @brief      Control minimal non-overlap timing
 */
#define PDRV0CTL0_ALL_MINNOV_Pos (0)
#define PDRV0CTL0_ALL_MINNOV_Msk (0x3UL << PDRV0CTL0_ALL_MINNOV_Pos)

typedef enum
{
    PDRV0CTL0_BIT_MINNOV_150_NS     = 0,  /*!< 150ns   */
    PDRV0CTL0_BIT_MINNOV_300_NS     = 1,  /*!< 300ns   */
    PDRV0CTL0_BIT_MINNOV_450_NS     = 2,  /*!< 450ns   */
    PDRV0CTL0_BIT_MINNOV_600_NS     = 3,  /*!< 600ns   */
} PDRV0CTL0_BIT_MINNOV;

#define PDRV0CTL0_ALL_MINNOV_150_NS     ((0x0UL) << PDRV0CTL0_ALL_MINNOV_Pos)
#define PDRV0CTL0_ALL_MINNOV_300_NS     ((0x1UL) << PDRV0CTL0_ALL_MINNOV_Pos)
#define PDRV0CTL0_ALL_MINNOV_450_NS     ((0x2UL) << PDRV0CTL0_ALL_MINNOV_Pos)
#define PDRV0CTL0_ALL_MINNOV_600_NS     ((0x3UL) << PDRV0CTL0_ALL_MINNOV_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV0CTL1       OCVREFSEL
 *  @access     
 *  @brief      Over current protect reference voltage select for Vds-monitors
 */
#define PDRV0CTL1_ALL_OCVREFSEL_Pos (4)
#define PDRV0CTL1_ALL_OCVREFSEL_Msk (0xFUL << PDRV0CTL1_ALL_OCVREFSEL_Pos)

typedef enum
{
    PDRV0CTL1_BIT_OCVREFSEL_0dot15_V     = 0,  /*!< 0.15V   */
    PDRV0CTL1_BIT_OCVREFSEL_0dot3_V      = 1,  /*!< 0.3V    */
    PDRV0CTL1_BIT_OCVREFSEL_0dot45_V     = 2,  /*!< 0.45V   */
    PDRV0CTL1_BIT_OCVREFSEL_0dot6_V      = 3,  /*!< 0.6V    */
    PDRV0CTL1_BIT_OCVREFSEL_0dot75_V     = 4,  /*!< 0.75V   */
    PDRV0CTL1_BIT_OCVREFSEL_0dot9_V      = 5,  /*!< 0.9V    */
    PDRV0CTL1_BIT_OCVREFSEL_1dot05_V     = 6,  /*!< 1.05V   */
    PDRV0CTL1_BIT_OCVREFSEL_1dot2_V      = 7,  /*!< 1.2V    */
    PDRV0CTL1_BIT_OCVREFSEL_1dot35_V     = 8,  /*!< 1.35V   */
    PDRV0CTL1_BIT_OCVREFSEL_1dot5_V      = 9,  /*!< 1.5V    */
    PDRV0CTL1_BIT_OCVREFSEL_1dot65_V     = 10,  /*!< 1.65V   */
    PDRV0CTL1_BIT_OCVREFSEL_1dot8_V      = 11,  /*!< 1.8V    */
    PDRV0CTL1_BIT_OCVREFSEL_1dot95_V     = 12,  /*!< 1.95V   */
    PDRV0CTL1_BIT_OCVREFSEL_2dot1_V      = 13,  /*!< 2.1V    */
    PDRV0CTL1_BIT_OCVREFSEL_2dot25_V     = 14,  /*!< 2.25V   */
    PDRV0CTL1_BIT_OCVREFSEL_2dot4_V      = 15,  /*!< 2.4V    */
} PDRV0CTL1_BIT_OCVREFSEL;

#define PDRV0CTL1_ALL_OCVREFSEL_0dot15_V     ((0x00UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_0dot3_V      ((0x01UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_0dot45_V     ((0x02UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_0dot6_V      ((0x03UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_0dot75_V     ((0x04UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_0dot9_V      ((0x05UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_1dot05_V     ((0x06UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_1dot2_V      ((0x07UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_1dot35_V     ((0x08UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_1dot5_V      ((0x09UL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_1dot65_V     ((0x0AUL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_1dot8_V      ((0x0BUL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_1dot95_V     ((0x0CUL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_2dot1_V      ((0x0DUL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_2dot25_V     ((0x0EUL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)
#define PDRV0CTL1_ALL_OCVREFSEL_2dot4_V      ((0x0FUL) << PDRV0CTL1_ALL_OCVREFSEL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1CTL0       MINNOV
 *  @access     
 *  @brief      Control minimal non-overlap timing
 */
#define PDRV1CTL0_ALL_MINNOV_Pos (0)
#define PDRV1CTL0_ALL_MINNOV_Msk (0x3UL << PDRV1CTL0_ALL_MINNOV_Pos)

typedef enum
{
    PDRV1CTL0_BIT_MINNOV_150_NS     = 0,  /*!< 150ns   */
    PDRV1CTL0_BIT_MINNOV_300_NS     = 1,  /*!< 300ns   */
    PDRV1CTL0_BIT_MINNOV_450_NS     = 2,  /*!< 450ns   */
    PDRV1CTL0_BIT_MINNOV_600_NS     = 3,  /*!< 600ns   */
} PDRV1CTL0_BIT_MINNOV;

#define PDRV1CTL0_ALL_MINNOV_150_NS     ((0x0UL) << PDRV1CTL0_ALL_MINNOV_Pos)
#define PDRV1CTL0_ALL_MINNOV_300_NS     ((0x1UL) << PDRV1CTL0_ALL_MINNOV_Pos)
#define PDRV1CTL0_ALL_MINNOV_450_NS     ((0x2UL) << PDRV1CTL0_ALL_MINNOV_Pos)
#define PDRV1CTL0_ALL_MINNOV_600_NS     ((0x3UL) << PDRV1CTL0_ALL_MINNOV_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRV1CTL1       OCVREFSEL
 *  @access     
 *  @brief      Over current protect reference voltage select for Vds-monitors
 */
#define PDRV1CTL1_ALL_OCVREFSEL_Pos (4)
#define PDRV1CTL1_ALL_OCVREFSEL_Msk (0xFUL << PDRV1CTL1_ALL_OCVREFSEL_Pos)

typedef enum
{
    PDRV1CTL1_BIT_OCVREFSEL_0dot15_V     = 0,  /*!< 0.15V   */
    PDRV1CTL1_BIT_OCVREFSEL_0dot3_V      = 1,  /*!< 0.3V    */
    PDRV1CTL1_BIT_OCVREFSEL_0dot45_V     = 2,  /*!< 0.45V   */
    PDRV1CTL1_BIT_OCVREFSEL_0dot6_V      = 3,  /*!< 0.6V    */
    PDRV1CTL1_BIT_OCVREFSEL_0dot75_V     = 4,  /*!< 0.75V   */
    PDRV1CTL1_BIT_OCVREFSEL_0dot9_V      = 5,  /*!< 0.9V    */
    PDRV1CTL1_BIT_OCVREFSEL_1dot05_V     = 6,  /*!< 1.05V   */
    PDRV1CTL1_BIT_OCVREFSEL_1dot2_V      = 7,  /*!< 1.2V    */
    PDRV1CTL1_BIT_OCVREFSEL_1dot35_V     = 8,  /*!< 1.35V   */
    PDRV1CTL1_BIT_OCVREFSEL_1dot5_V      = 9,  /*!< 1.5V    */
    PDRV1CTL1_BIT_OCVREFSEL_1dot65_V     = 10,  /*!< 1.65V   */
    PDRV1CTL1_BIT_OCVREFSEL_1dot8_V      = 11,  /*!< 1.8V    */
    PDRV1CTL1_BIT_OCVREFSEL_1dot95_V     = 12,  /*!< 1.95V   */
    PDRV1CTL1_BIT_OCVREFSEL_2dot1_V      = 13,  /*!< 2.1V    */
    PDRV1CTL1_BIT_OCVREFSEL_2dot25_V     = 14,  /*!< 2.25V   */
    PDRV1CTL1_BIT_OCVREFSEL_2dot4_V      = 15,  /*!< 2.4V    */
} PDRV1CTL1_BIT_OCVREFSEL;

#define PDRV1CTL1_ALL_OCVREFSEL_0dot15_V     ((0x00UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_0dot3_V      ((0x01UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_0dot45_V     ((0x02UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_0dot6_V      ((0x03UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_0dot75_V     ((0x04UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_0dot9_V      ((0x05UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_1dot05_V     ((0x06UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_1dot2_V      ((0x07UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_1dot35_V     ((0x08UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_1dot5_V      ((0x09UL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_1dot65_V     ((0x0AUL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_1dot8_V      ((0x0BUL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_1dot95_V     ((0x0CUL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_2dot1_V      ((0x0DUL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_2dot25_V     ((0x0EUL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)
#define PDRV1CTL1_ALL_OCVREFSEL_2dot4_V      ((0x0FUL) << PDRV1CTL1_ALL_OCVREFSEL_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PWRUPKEY        PUKEY
 *  @access     
 *  @brief      Write 0x9 to power up the chip
 */
#define PWRUPKEY_ALL_PUKEY_Pos (0)
#define PWRUPKEY_ALL_PUKEY_Msk (0xFUL << PWRUPKEY_ALL_PUKEY_Pos)

#define PWRUPKEY_BIT_PUKEY

#define PWRUPKEY_ALL_PUKEY_(x) ((x) << PWRUPKEY_ALL_PUKEY_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PWRUPKEY        SELFPDKEY
 *  @access     
 *  @brief      Write 0x9 to enable self-power-down upon GLBSTS[OTERROR] occur
 */
#define PWRUPKEY_ALL_SELFPDKEY_Pos (4)
#define PWRUPKEY_ALL_SELFPDKEY_Msk (0xFUL << PWRUPKEY_ALL_SELFPDKEY_Pos)

#define PWRUPKEY_BIT_SELFPDKEY

#define PWRUPKEY_ALL_SELFPDKEY_(x) ((x) << PWRUPKEY_ALL_SELFPDKEY_Pos)





/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              CTLKEY          KEY
 *  @access     
 *  @brief      Write 0xac to have write access permission to registers highlighted in red
 */
#define CTLKEY_ALL_KEY_Pos (0)
#define CTLKEY_ALL_KEY_Msk (0xFFUL << CTLKEY_ALL_KEY_Pos)

#define CTLKEY_BIT_KEY

#define CTLKEY_ALL_KEY_(x) ((x) << CTLKEY_ALL_KEY_Pos)




#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* HV_BITFIELD_H */


/******************* Copyright (C) 2022 Spintrol Electronic Technology (Shanghai) Co., Ltd. ***** END OF FILE ****/
