/*******************************************************************************
 * @file     hv_bitfield.h
 * @brief    High voltage module register bit-field definition.
 * @version  V4.0.1
 * @date     30-July-2026
 *
 * @note
 * Copyright (C) 2022 Spintrol Electronic Technology (Shanghai) Co., Ltd.. All rights reserved.
 *
 * @attention
 * THIS SOFTWARE JUST PROVIDES CUSTOMERS WITH CODING INFORMATION REGARDING
 * THEIR PRODUCTS, WHICH AIMS AT SAVING TIME FOR THEM. SPINTROL SHALL NOT BE
 * LIABLE FOR THE USE OF THE SOFTWARE. SPINTROL DOES NOT GUARANTEE THE
 * CORRECTNESS OF THIS SOFTWARE AND RESERVES THE RIGHT TO MODIFY THE SOFTWARE
 * WITHOUT NOTIFICATION.
 *
 ******************************************************************************/


#ifndef HV_BITFIELD_H
#define HV_BITFIELD_H

#ifdef __cplusplus
extern "C" {
#endif




/********************************************************************************
*
* Module Name     HV
*
*
********************************************************************************/



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS0         VBATL
 *  @access     
 *  @brief      Indicate VBAT is too low
 */
#define GLBSTS0_ALL_VBATL_Pos (0)
#define GLBSTS0_ALL_VBATL_Msk (0x1UL << GLBSTS0_ALL_VBATL_Pos)

typedef enum
{
    GLBSTS0_BIT_VBATL_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS0_BIT_VBATL_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS0_BIT_VBATL;

#define GLBSTS0_ALL_VBATL_NOT_OCCUR     ((0x0UL) << GLBSTS0_ALL_VBATL_Pos)
#define GLBSTS0_ALL_VBATL_OCCUR         ((0x1UL) << GLBSTS0_ALL_VBATL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS0         VBATH
 *  @access     
 *  @brief      Indicate VBAT is too high
 */
#define GLBSTS0_ALL_VBATH_Pos (1)
#define GLBSTS0_ALL_VBATH_Msk (0x1UL << GLBSTS0_ALL_VBATH_Pos)

typedef enum
{
    GLBSTS0_BIT_VBATH_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS0_BIT_VBATH_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS0_BIT_VBATH;

#define GLBSTS0_ALL_VBATH_NOT_OCCUR     ((0x0UL) << GLBSTS0_ALL_VBATH_Pos)
#define GLBSTS0_ALL_VBATH_OCCUR         ((0x1UL) << GLBSTS0_ALL_VBATH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS0         VDDGL
 *  @access     
 *  @brief      Indicate VDDG is too low
 */
#define GLBSTS0_ALL_VDDGL_Pos (2)
#define GLBSTS0_ALL_VDDGL_Msk (0x1UL << GLBSTS0_ALL_VDDGL_Pos)

typedef enum
{
    GLBSTS0_BIT_VDDGL_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS0_BIT_VDDGL_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS0_BIT_VDDGL;

#define GLBSTS0_ALL_VDDGL_NOT_OCCUR     ((0x0UL) << GLBSTS0_ALL_VDDGL_Pos)
#define GLBSTS0_ALL_VDDGL_OCCUR         ((0x1UL) << GLBSTS0_ALL_VDDGL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS0         VDDGH
 *  @access     
 *  @brief      Indicate VDDG is too high
 */
#define GLBSTS0_ALL_VDDGH_Pos (3)
#define GLBSTS0_ALL_VDDGH_Msk (0x1UL << GLBSTS0_ALL_VDDGH_Pos)

typedef enum
{
    GLBSTS0_BIT_VDDGH_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS0_BIT_VDDGH_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS0_BIT_VDDGH;

#define GLBSTS0_ALL_VDDGH_NOT_OCCUR     ((0x0UL) << GLBSTS0_ALL_VDDGH_Pos)
#define GLBSTS0_ALL_VDDGH_OCCUR         ((0x1UL) << GLBSTS0_ALL_VDDGH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS0         OTWARN
 *  @access     
 *  @brief      Indicate an over-temperature warning
 */
#define GLBSTS0_ALL_OTWARN_Pos (4)
#define GLBSTS0_ALL_OTWARN_Msk (0x1UL << GLBSTS0_ALL_OTWARN_Pos)

typedef enum
{
    GLBSTS0_BIT_OTWARN_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS0_BIT_OTWARN_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS0_BIT_OTWARN;

#define GLBSTS0_ALL_OTWARN_NOT_OCCUR     ((0x0UL) << GLBSTS0_ALL_OTWARN_Pos)
#define GLBSTS0_ALL_OTWARN_OCCUR         ((0x1UL) << GLBSTS0_ALL_OTWARN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS0         CPRDY
 *  @access     
 *  @brief      Indicate charge-pump is ready
 */
#define GLBSTS0_ALL_CPRDY_Pos (5)
#define GLBSTS0_ALL_CPRDY_Msk (0x1UL << GLBSTS0_ALL_CPRDY_Pos)

typedef enum
{
    GLBSTS0_BIT_CPRDY_NOT_READY     = 0,  /*!< Not ready   */
    GLBSTS0_BIT_CPRDY_READY         = 1,  /*!< Ready       */
} GLBSTS0_BIT_CPRDY;

#define GLBSTS0_ALL_CPRDY_NOT_READY     ((0x0UL) << GLBSTS0_ALL_CPRDY_Pos)
#define GLBSTS0_ALL_CPRDY_READY         ((0x1UL) << GLBSTS0_ALL_CPRDY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS1         OCLU
 *  @access     
 *  @brief      Indicate over-current on low-side of U phase
 */
#define GLBSTS1_ALL_OCLU_Pos (0)
#define GLBSTS1_ALL_OCLU_Msk (0x1UL << GLBSTS1_ALL_OCLU_Pos)

typedef enum
{
    GLBSTS1_BIT_OCLU_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS1_BIT_OCLU_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS1_BIT_OCLU;

#define GLBSTS1_ALL_OCLU_NOT_OCCUR     ((0x0UL) << GLBSTS1_ALL_OCLU_Pos)
#define GLBSTS1_ALL_OCLU_OCCUR         ((0x1UL) << GLBSTS1_ALL_OCLU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS1         OCLV
 *  @access     
 *  @brief      Indicate over-current on low-side of V phase
 */
#define GLBSTS1_ALL_OCLV_Pos (1)
#define GLBSTS1_ALL_OCLV_Msk (0x1UL << GLBSTS1_ALL_OCLV_Pos)

typedef enum
{
    GLBSTS1_BIT_OCLV_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS1_BIT_OCLV_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS1_BIT_OCLV;

#define GLBSTS1_ALL_OCLV_NOT_OCCUR     ((0x0UL) << GLBSTS1_ALL_OCLV_Pos)
#define GLBSTS1_ALL_OCLV_OCCUR         ((0x1UL) << GLBSTS1_ALL_OCLV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS1         OCLW
 *  @access     
 *  @brief      Indicate over-current on low-side of W phase
 */
#define GLBSTS1_ALL_OCLW_Pos (2)
#define GLBSTS1_ALL_OCLW_Msk (0x1UL << GLBSTS1_ALL_OCLW_Pos)

typedef enum
{
    GLBSTS1_BIT_OCLW_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS1_BIT_OCLW_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS1_BIT_OCLW;

#define GLBSTS1_ALL_OCLW_NOT_OCCUR     ((0x0UL) << GLBSTS1_ALL_OCLW_Pos)
#define GLBSTS1_ALL_OCLW_OCCUR         ((0x1UL) << GLBSTS1_ALL_OCLW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS1         OCHU
 *  @access     
 *  @brief      Indicate over-current on high-side of U phase
 */
#define GLBSTS1_ALL_OCHU_Pos (3)
#define GLBSTS1_ALL_OCHU_Msk (0x1UL << GLBSTS1_ALL_OCHU_Pos)

typedef enum
{
    GLBSTS1_BIT_OCHU_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS1_BIT_OCHU_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS1_BIT_OCHU;

#define GLBSTS1_ALL_OCHU_NOT_OCCUR     ((0x0UL) << GLBSTS1_ALL_OCHU_Pos)
#define GLBSTS1_ALL_OCHU_OCCUR         ((0x1UL) << GLBSTS1_ALL_OCHU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS1         OCHV
 *  @access     
 *  @brief      Indicate over-current on high-side of V phase
 */
#define GLBSTS1_ALL_OCHV_Pos (4)
#define GLBSTS1_ALL_OCHV_Msk (0x1UL << GLBSTS1_ALL_OCHV_Pos)

typedef enum
{
    GLBSTS1_BIT_OCHV_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS1_BIT_OCHV_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS1_BIT_OCHV;

#define GLBSTS1_ALL_OCHV_NOT_OCCUR     ((0x0UL) << GLBSTS1_ALL_OCHV_Pos)
#define GLBSTS1_ALL_OCHV_OCCUR         ((0x1UL) << GLBSTS1_ALL_OCHV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTS1         OCHW
 *  @access     
 *  @brief      Indicate over-current on high-side of W phase
 */
#define GLBSTS1_ALL_OCHW_Pos (5)
#define GLBSTS1_ALL_OCHW_Msk (0x1UL << GLBSTS1_ALL_OCHW_Pos)

typedef enum
{
    GLBSTS1_BIT_OCHW_NOT_OCCUR     = 0,  /*!< Not occurred   */
    GLBSTS1_BIT_OCHW_OCCUR         = 1,  /*!< Occurred       */
} GLBSTS1_BIT_OCHW;

#define GLBSTS1_ALL_OCHW_NOT_OCCUR     ((0x0UL) << GLBSTS1_ALL_OCHW_Pos)
#define GLBSTS1_ALL_OCHW_OCCUR         ((0x1UL) << GLBSTS1_ALL_OCHW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR0      VBATL
 *  @access     
 *  @brief      Clear GLBSTS0[VBATL]
 */
#define GLBSTSCLR0_ALL_VBATL_Pos (0)
#define GLBSTSCLR0_ALL_VBATL_Msk (0x1UL << GLBSTSCLR0_ALL_VBATL_Pos)

typedef enum
{
    GLBSTSCLR0_BIT_VBATL_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR0_BIT_VBATL_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR0_BIT_VBATL;

#define GLBSTSCLR0_ALL_VBATL_NO_EFFECT     ((0x0UL) << GLBSTSCLR0_ALL_VBATL_Pos)
#define GLBSTSCLR0_ALL_VBATL_CLEAR         ((0x1UL) << GLBSTSCLR0_ALL_VBATL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR0      VBATH
 *  @access     
 *  @brief      Clear GLBSTS0[VBATH]
 */
#define GLBSTSCLR0_ALL_VBATH_Pos (1)
#define GLBSTSCLR0_ALL_VBATH_Msk (0x1UL << GLBSTSCLR0_ALL_VBATH_Pos)

typedef enum
{
    GLBSTSCLR0_BIT_VBATH_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR0_BIT_VBATH_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR0_BIT_VBATH;

#define GLBSTSCLR0_ALL_VBATH_NO_EFFECT     ((0x0UL) << GLBSTSCLR0_ALL_VBATH_Pos)
#define GLBSTSCLR0_ALL_VBATH_CLEAR         ((0x1UL) << GLBSTSCLR0_ALL_VBATH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR0      VDDGL
 *  @access     
 *  @brief      Clear GLBSTS0[VDDGL]
 */
#define GLBSTSCLR0_ALL_VDDGL_Pos (2)
#define GLBSTSCLR0_ALL_VDDGL_Msk (0x1UL << GLBSTSCLR0_ALL_VDDGL_Pos)

typedef enum
{
    GLBSTSCLR0_BIT_VDDGL_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR0_BIT_VDDGL_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR0_BIT_VDDGL;

#define GLBSTSCLR0_ALL_VDDGL_NO_EFFECT     ((0x0UL) << GLBSTSCLR0_ALL_VDDGL_Pos)
#define GLBSTSCLR0_ALL_VDDGL_CLEAR         ((0x1UL) << GLBSTSCLR0_ALL_VDDGL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR0      VDDGH
 *  @access     
 *  @brief      Clear GLBSTS0[VDDGH]
 */
#define GLBSTSCLR0_ALL_VDDGH_Pos (3)
#define GLBSTSCLR0_ALL_VDDGH_Msk (0x1UL << GLBSTSCLR0_ALL_VDDGH_Pos)

typedef enum
{
    GLBSTSCLR0_BIT_VDDGH_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR0_BIT_VDDGH_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR0_BIT_VDDGH;

#define GLBSTSCLR0_ALL_VDDGH_NO_EFFECT     ((0x0UL) << GLBSTSCLR0_ALL_VDDGH_Pos)
#define GLBSTSCLR0_ALL_VDDGH_CLEAR         ((0x1UL) << GLBSTSCLR0_ALL_VDDGH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR0      OTWARN
 *  @access     
 *  @brief      Clear GLBSTS0[OTWARN]
 */
#define GLBSTSCLR0_ALL_OTWARN_Pos (4)
#define GLBSTSCLR0_ALL_OTWARN_Msk (0x1UL << GLBSTSCLR0_ALL_OTWARN_Pos)

typedef enum
{
    GLBSTSCLR0_BIT_OTWARN_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR0_BIT_OTWARN_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR0_BIT_OTWARN;

#define GLBSTSCLR0_ALL_OTWARN_NO_EFFECT     ((0x0UL) << GLBSTSCLR0_ALL_OTWARN_Pos)
#define GLBSTSCLR0_ALL_OTWARN_CLEAR         ((0x1UL) << GLBSTSCLR0_ALL_OTWARN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR1      OCLU
 *  @access     
 *  @brief      Clear GLBSTS1[OCLU]
 */
#define GLBSTSCLR1_ALL_OCLU_Pos (0)
#define GLBSTSCLR1_ALL_OCLU_Msk (0x1UL << GLBSTSCLR1_ALL_OCLU_Pos)

typedef enum
{
    GLBSTSCLR1_BIT_OCLU_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR1_BIT_OCLU_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR1_BIT_OCLU;

#define GLBSTSCLR1_ALL_OCLU_NO_EFFECT     ((0x0UL) << GLBSTSCLR1_ALL_OCLU_Pos)
#define GLBSTSCLR1_ALL_OCLU_CLEAR         ((0x1UL) << GLBSTSCLR1_ALL_OCLU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR1      OCLV
 *  @access     
 *  @brief      Clear GLBSTS1[OCLV]
 */
#define GLBSTSCLR1_ALL_OCLV_Pos (1)
#define GLBSTSCLR1_ALL_OCLV_Msk (0x1UL << GLBSTSCLR1_ALL_OCLV_Pos)

typedef enum
{
    GLBSTSCLR1_BIT_OCLV_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR1_BIT_OCLV_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR1_BIT_OCLV;

#define GLBSTSCLR1_ALL_OCLV_NO_EFFECT     ((0x0UL) << GLBSTSCLR1_ALL_OCLV_Pos)
#define GLBSTSCLR1_ALL_OCLV_CLEAR         ((0x1UL) << GLBSTSCLR1_ALL_OCLV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR1      OCLW
 *  @access     
 *  @brief      Clear GLBSTS1[OCLW]
 */
#define GLBSTSCLR1_ALL_OCLW_Pos (2)
#define GLBSTSCLR1_ALL_OCLW_Msk (0x1UL << GLBSTSCLR1_ALL_OCLW_Pos)

typedef enum
{
    GLBSTSCLR1_BIT_OCLW_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR1_BIT_OCLW_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR1_BIT_OCLW;

#define GLBSTSCLR1_ALL_OCLW_NO_EFFECT     ((0x0UL) << GLBSTSCLR1_ALL_OCLW_Pos)
#define GLBSTSCLR1_ALL_OCLW_CLEAR         ((0x1UL) << GLBSTSCLR1_ALL_OCLW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR1      OCHU
 *  @access     
 *  @brief      Clear GLBSTS1[OCHU]
 */
#define GLBSTSCLR1_ALL_OCHU_Pos (3)
#define GLBSTSCLR1_ALL_OCHU_Msk (0x1UL << GLBSTSCLR1_ALL_OCHU_Pos)

typedef enum
{
    GLBSTSCLR1_BIT_OCHU_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR1_BIT_OCHU_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR1_BIT_OCHU;

#define GLBSTSCLR1_ALL_OCHU_NO_EFFECT     ((0x0UL) << GLBSTSCLR1_ALL_OCHU_Pos)
#define GLBSTSCLR1_ALL_OCHU_CLEAR         ((0x1UL) << GLBSTSCLR1_ALL_OCHU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR1      OCHV
 *  @access     
 *  @brief      Clear GLBSTS1[OCHV]
 */
#define GLBSTSCLR1_ALL_OCHV_Pos (4)
#define GLBSTSCLR1_ALL_OCHV_Msk (0x1UL << GLBSTSCLR1_ALL_OCHV_Pos)

typedef enum
{
    GLBSTSCLR1_BIT_OCHV_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR1_BIT_OCHV_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR1_BIT_OCHV;

#define GLBSTSCLR1_ALL_OCHV_NO_EFFECT     ((0x0UL) << GLBSTSCLR1_ALL_OCHV_Pos)
#define GLBSTSCLR1_ALL_OCHV_CLEAR         ((0x1UL) << GLBSTSCLR1_ALL_OCHV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              GLBSTSCLR1      OCHW
 *  @access     
 *  @brief      Clear GLBSTS1[OCHW]
 */
#define GLBSTSCLR1_ALL_OCHW_Pos (5)
#define GLBSTSCLR1_ALL_OCHW_Msk (0x1UL << GLBSTSCLR1_ALL_OCHW_Pos)

typedef enum
{
    GLBSTSCLR1_BIT_OCHW_NO_EFFECT     = 0,  /*!< Write a 0 has no effect. Always read back 0   */
    GLBSTSCLR1_BIT_OCHW_CLEAR         = 1,  /*!< Write a 1 clears the bit                      */
} GLBSTSCLR1_BIT_OCHW;

#define GLBSTSCLR1_ALL_OCHW_NO_EFFECT     ((0x0UL) << GLBSTSCLR1_ALL_OCHW_Pos)
#define GLBSTSCLR1_ALL_OCHW_CLEAR         ((0x1UL) << GLBSTSCLR1_ALL_OCHW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL0     VBATL
 *  @access     
 *  @brief      Select VBAT-too-low as PDRVTZ0 event
 */
#define PDRVTZ0SEL0_ALL_VBATL_Pos (0)
#define PDRVTZ0SEL0_ALL_VBATL_Msk (0x1UL << PDRVTZ0SEL0_ALL_VBATL_Pos)

typedef enum
{
    PDRVTZ0SEL0_BIT_VBATL_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL0_BIT_VBATL_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL0_BIT_VBATL;

#define PDRVTZ0SEL0_ALL_VBATL_DISABLE     ((0x0UL) << PDRVTZ0SEL0_ALL_VBATL_Pos)
#define PDRVTZ0SEL0_ALL_VBATL_ENABLE      ((0x1UL) << PDRVTZ0SEL0_ALL_VBATL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL0     VBATH
 *  @access     
 *  @brief      Select VBAT-too-high as PDRVTZ0 event
 */
#define PDRVTZ0SEL0_ALL_VBATH_Pos (1)
#define PDRVTZ0SEL0_ALL_VBATH_Msk (0x1UL << PDRVTZ0SEL0_ALL_VBATH_Pos)

typedef enum
{
    PDRVTZ0SEL0_BIT_VBATH_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL0_BIT_VBATH_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL0_BIT_VBATH;

#define PDRVTZ0SEL0_ALL_VBATH_DISABLE     ((0x0UL) << PDRVTZ0SEL0_ALL_VBATH_Pos)
#define PDRVTZ0SEL0_ALL_VBATH_ENABLE      ((0x1UL) << PDRVTZ0SEL0_ALL_VBATH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL0     VDDGL
 *  @access     
 *  @brief      Select VDDG-too-low as PDRVTZ0 event
 */
#define PDRVTZ0SEL0_ALL_VDDGL_Pos (2)
#define PDRVTZ0SEL0_ALL_VDDGL_Msk (0x1UL << PDRVTZ0SEL0_ALL_VDDGL_Pos)

typedef enum
{
    PDRVTZ0SEL0_BIT_VDDGL_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL0_BIT_VDDGL_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL0_BIT_VDDGL;

#define PDRVTZ0SEL0_ALL_VDDGL_DISABLE     ((0x0UL) << PDRVTZ0SEL0_ALL_VDDGL_Pos)
#define PDRVTZ0SEL0_ALL_VDDGL_ENABLE      ((0x1UL) << PDRVTZ0SEL0_ALL_VDDGL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL0     VDDGH
 *  @access     
 *  @brief      Select VDDG-too-high as PDRVTZ0 event
 */
#define PDRVTZ0SEL0_ALL_VDDGH_Pos (3)
#define PDRVTZ0SEL0_ALL_VDDGH_Msk (0x1UL << PDRVTZ0SEL0_ALL_VDDGH_Pos)

typedef enum
{
    PDRVTZ0SEL0_BIT_VDDGH_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL0_BIT_VDDGH_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL0_BIT_VDDGH;

#define PDRVTZ0SEL0_ALL_VDDGH_DISABLE     ((0x0UL) << PDRVTZ0SEL0_ALL_VDDGH_Pos)
#define PDRVTZ0SEL0_ALL_VDDGH_ENABLE      ((0x1UL) << PDRVTZ0SEL0_ALL_VDDGH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL0     OTWARN
 *  @access     
 *  @brief      Select over-temperature as PDRVTZ0 event
 */
#define PDRVTZ0SEL0_ALL_OTWARN_Pos (4)
#define PDRVTZ0SEL0_ALL_OTWARN_Msk (0x1UL << PDRVTZ0SEL0_ALL_OTWARN_Pos)

typedef enum
{
    PDRVTZ0SEL0_BIT_OTWARN_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL0_BIT_OTWARN_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL0_BIT_OTWARN;

#define PDRVTZ0SEL0_ALL_OTWARN_DISABLE     ((0x0UL) << PDRVTZ0SEL0_ALL_OTWARN_Pos)
#define PDRVTZ0SEL0_ALL_OTWARN_ENABLE      ((0x1UL) << PDRVTZ0SEL0_ALL_OTWARN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL1     OCLU
 *  @access     
 *  @brief      Select over-current on low-side of U phase as PDRVTZ0 event
 */
#define PDRVTZ0SEL1_ALL_OCLU_Pos (0)
#define PDRVTZ0SEL1_ALL_OCLU_Msk (0x1UL << PDRVTZ0SEL1_ALL_OCLU_Pos)

typedef enum
{
    PDRVTZ0SEL1_BIT_OCLU_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL1_BIT_OCLU_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL1_BIT_OCLU;

#define PDRVTZ0SEL1_ALL_OCLU_DISABLE     ((0x0UL) << PDRVTZ0SEL1_ALL_OCLU_Pos)
#define PDRVTZ0SEL1_ALL_OCLU_ENABLE      ((0x1UL) << PDRVTZ0SEL1_ALL_OCLU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL1     OCLV
 *  @access     
 *  @brief      Select over-current on low-side of V phase as PDRVTZ0 event
 */
#define PDRVTZ0SEL1_ALL_OCLV_Pos (1)
#define PDRVTZ0SEL1_ALL_OCLV_Msk (0x1UL << PDRVTZ0SEL1_ALL_OCLV_Pos)

typedef enum
{
    PDRVTZ0SEL1_BIT_OCLV_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL1_BIT_OCLV_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL1_BIT_OCLV;

#define PDRVTZ0SEL1_ALL_OCLV_DISABLE     ((0x0UL) << PDRVTZ0SEL1_ALL_OCLV_Pos)
#define PDRVTZ0SEL1_ALL_OCLV_ENABLE      ((0x1UL) << PDRVTZ0SEL1_ALL_OCLV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL1     OCLW
 *  @access     
 *  @brief      Select over-current on low-side of W phase as PDRVTZ0 event
 */
#define PDRVTZ0SEL1_ALL_OCLW_Pos (2)
#define PDRVTZ0SEL1_ALL_OCLW_Msk (0x1UL << PDRVTZ0SEL1_ALL_OCLW_Pos)

typedef enum
{
    PDRVTZ0SEL1_BIT_OCLW_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL1_BIT_OCLW_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL1_BIT_OCLW;

#define PDRVTZ0SEL1_ALL_OCLW_DISABLE     ((0x0UL) << PDRVTZ0SEL1_ALL_OCLW_Pos)
#define PDRVTZ0SEL1_ALL_OCLW_ENABLE      ((0x1UL) << PDRVTZ0SEL1_ALL_OCLW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL1     OCHU
 *  @access     
 *  @brief      Select over-current on high-side of U phase as PDRVTZ0 event
 */
#define PDRVTZ0SEL1_ALL_OCHU_Pos (3)
#define PDRVTZ0SEL1_ALL_OCHU_Msk (0x1UL << PDRVTZ0SEL1_ALL_OCHU_Pos)

typedef enum
{
    PDRVTZ0SEL1_BIT_OCHU_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL1_BIT_OCHU_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL1_BIT_OCHU;

#define PDRVTZ0SEL1_ALL_OCHU_DISABLE     ((0x0UL) << PDRVTZ0SEL1_ALL_OCHU_Pos)
#define PDRVTZ0SEL1_ALL_OCHU_ENABLE      ((0x1UL) << PDRVTZ0SEL1_ALL_OCHU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL1     OCHV
 *  @access     
 *  @brief      Select over-current on high-side of V phase as PDRVTZ0 event
 */
#define PDRVTZ0SEL1_ALL_OCHV_Pos (4)
#define PDRVTZ0SEL1_ALL_OCHV_Msk (0x1UL << PDRVTZ0SEL1_ALL_OCHV_Pos)

typedef enum
{
    PDRVTZ0SEL1_BIT_OCHV_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL1_BIT_OCHV_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL1_BIT_OCHV;

#define PDRVTZ0SEL1_ALL_OCHV_DISABLE     ((0x0UL) << PDRVTZ0SEL1_ALL_OCHV_Pos)
#define PDRVTZ0SEL1_ALL_OCHV_ENABLE      ((0x1UL) << PDRVTZ0SEL1_ALL_OCHV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ0SEL1     OCHW
 *  @access     
 *  @brief      Select over-current on high-side of W phase as PDRVTZ0 event
 */
#define PDRVTZ0SEL1_ALL_OCHW_Pos (5)
#define PDRVTZ0SEL1_ALL_OCHW_Msk (0x1UL << PDRVTZ0SEL1_ALL_OCHW_Pos)

typedef enum
{
    PDRVTZ0SEL1_BIT_OCHW_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ0SEL1_BIT_OCHW_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ0SEL1_BIT_OCHW;

#define PDRVTZ0SEL1_ALL_OCHW_DISABLE     ((0x0UL) << PDRVTZ0SEL1_ALL_OCHW_Pos)
#define PDRVTZ0SEL1_ALL_OCHW_ENABLE      ((0x1UL) << PDRVTZ0SEL1_ALL_OCHW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL0     VBATL
 *  @access     
 *  @brief      Select VBAT-too-low as PDRVTZ1 event
 */
#define PDRVTZ1SEL0_ALL_VBATL_Pos (0)
#define PDRVTZ1SEL0_ALL_VBATL_Msk (0x1UL << PDRVTZ1SEL0_ALL_VBATL_Pos)

typedef enum
{
    PDRVTZ1SEL0_BIT_VBATL_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL0_BIT_VBATL_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL0_BIT_VBATL;

#define PDRVTZ1SEL0_ALL_VBATL_DISABLE     ((0x0UL) << PDRVTZ1SEL0_ALL_VBATL_Pos)
#define PDRVTZ1SEL0_ALL_VBATL_ENABLE      ((0x1UL) << PDRVTZ1SEL0_ALL_VBATL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL0     VBATH
 *  @access     
 *  @brief      Select VBAT-too-high as PDRVTZ1 event
 */
#define PDRVTZ1SEL0_ALL_VBATH_Pos (1)
#define PDRVTZ1SEL0_ALL_VBATH_Msk (0x1UL << PDRVTZ1SEL0_ALL_VBATH_Pos)

typedef enum
{
    PDRVTZ1SEL0_BIT_VBATH_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL0_BIT_VBATH_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL0_BIT_VBATH;

#define PDRVTZ1SEL0_ALL_VBATH_DISABLE     ((0x0UL) << PDRVTZ1SEL0_ALL_VBATH_Pos)
#define PDRVTZ1SEL0_ALL_VBATH_ENABLE      ((0x1UL) << PDRVTZ1SEL0_ALL_VBATH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL0     VDDGL
 *  @access     
 *  @brief      Select VDDG-too-low as PDRVTZ1 event
 */
#define PDRVTZ1SEL0_ALL_VDDGL_Pos (2)
#define PDRVTZ1SEL0_ALL_VDDGL_Msk (0x1UL << PDRVTZ1SEL0_ALL_VDDGL_Pos)

typedef enum
{
    PDRVTZ1SEL0_BIT_VDDGL_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL0_BIT_VDDGL_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL0_BIT_VDDGL;

#define PDRVTZ1SEL0_ALL_VDDGL_DISABLE     ((0x0UL) << PDRVTZ1SEL0_ALL_VDDGL_Pos)
#define PDRVTZ1SEL0_ALL_VDDGL_ENABLE      ((0x1UL) << PDRVTZ1SEL0_ALL_VDDGL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL0     VDDGH
 *  @access     
 *  @brief      Select VDDG-too-high as PDRVTZ1 event
 */
#define PDRVTZ1SEL0_ALL_VDDGH_Pos (3)
#define PDRVTZ1SEL0_ALL_VDDGH_Msk (0x1UL << PDRVTZ1SEL0_ALL_VDDGH_Pos)

typedef enum
{
    PDRVTZ1SEL0_BIT_VDDGH_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL0_BIT_VDDGH_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL0_BIT_VDDGH;

#define PDRVTZ1SEL0_ALL_VDDGH_DISABLE     ((0x0UL) << PDRVTZ1SEL0_ALL_VDDGH_Pos)
#define PDRVTZ1SEL0_ALL_VDDGH_ENABLE      ((0x1UL) << PDRVTZ1SEL0_ALL_VDDGH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL0     OTWARN
 *  @access     
 *  @brief      Select over-temperature as PDRVTZ1 event
 */
#define PDRVTZ1SEL0_ALL_OTWARN_Pos (4)
#define PDRVTZ1SEL0_ALL_OTWARN_Msk (0x1UL << PDRVTZ1SEL0_ALL_OTWARN_Pos)

typedef enum
{
    PDRVTZ1SEL0_BIT_OTWARN_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL0_BIT_OTWARN_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL0_BIT_OTWARN;

#define PDRVTZ1SEL0_ALL_OTWARN_DISABLE     ((0x0UL) << PDRVTZ1SEL0_ALL_OTWARN_Pos)
#define PDRVTZ1SEL0_ALL_OTWARN_ENABLE      ((0x1UL) << PDRVTZ1SEL0_ALL_OTWARN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL1     OCLU
 *  @access     
 *  @brief      Select over-current on low-side of U phase as PDRVTZ1 event
 */
#define PDRVTZ1SEL1_ALL_OCLU_Pos (0)
#define PDRVTZ1SEL1_ALL_OCLU_Msk (0x1UL << PDRVTZ1SEL1_ALL_OCLU_Pos)

typedef enum
{
    PDRVTZ1SEL1_BIT_OCLU_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL1_BIT_OCLU_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL1_BIT_OCLU;

#define PDRVTZ1SEL1_ALL_OCLU_DISABLE     ((0x0UL) << PDRVTZ1SEL1_ALL_OCLU_Pos)
#define PDRVTZ1SEL1_ALL_OCLU_ENABLE      ((0x1UL) << PDRVTZ1SEL1_ALL_OCLU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL1     OCLV
 *  @access     
 *  @brief      Select over-current on low-side of V phase as PDRVTZ1 event
 */
#define PDRVTZ1SEL1_ALL_OCLV_Pos (1)
#define PDRVTZ1SEL1_ALL_OCLV_Msk (0x1UL << PDRVTZ1SEL1_ALL_OCLV_Pos)

typedef enum
{
    PDRVTZ1SEL1_BIT_OCLV_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL1_BIT_OCLV_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL1_BIT_OCLV;

#define PDRVTZ1SEL1_ALL_OCLV_DISABLE     ((0x0UL) << PDRVTZ1SEL1_ALL_OCLV_Pos)
#define PDRVTZ1SEL1_ALL_OCLV_ENABLE      ((0x1UL) << PDRVTZ1SEL1_ALL_OCLV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL1     OCLW
 *  @access     
 *  @brief      Select over-current on low-side of W phase as PDRVTZ1 event
 */
#define PDRVTZ1SEL1_ALL_OCLW_Pos (2)
#define PDRVTZ1SEL1_ALL_OCLW_Msk (0x1UL << PDRVTZ1SEL1_ALL_OCLW_Pos)

typedef enum
{
    PDRVTZ1SEL1_BIT_OCLW_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL1_BIT_OCLW_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL1_BIT_OCLW;

#define PDRVTZ1SEL1_ALL_OCLW_DISABLE     ((0x0UL) << PDRVTZ1SEL1_ALL_OCLW_Pos)
#define PDRVTZ1SEL1_ALL_OCLW_ENABLE      ((0x1UL) << PDRVTZ1SEL1_ALL_OCLW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL1     OCHU
 *  @access     
 *  @brief      Select over-current on high-side of U phase as PDRVTZ1 event
 */
#define PDRVTZ1SEL1_ALL_OCHU_Pos (3)
#define PDRVTZ1SEL1_ALL_OCHU_Msk (0x1UL << PDRVTZ1SEL1_ALL_OCHU_Pos)

typedef enum
{
    PDRVTZ1SEL1_BIT_OCHU_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL1_BIT_OCHU_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL1_BIT_OCHU;

#define PDRVTZ1SEL1_ALL_OCHU_DISABLE     ((0x0UL) << PDRVTZ1SEL1_ALL_OCHU_Pos)
#define PDRVTZ1SEL1_ALL_OCHU_ENABLE      ((0x1UL) << PDRVTZ1SEL1_ALL_OCHU_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL1     OCHV
 *  @access     
 *  @brief      Select over-current on high-side of V phase as PDRVTZ1 event
 */
#define PDRVTZ1SEL1_ALL_OCHV_Pos (4)
#define PDRVTZ1SEL1_ALL_OCHV_Msk (0x1UL << PDRVTZ1SEL1_ALL_OCHV_Pos)

typedef enum
{
    PDRVTZ1SEL1_BIT_OCHV_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL1_BIT_OCHV_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL1_BIT_OCHV;

#define PDRVTZ1SEL1_ALL_OCHV_DISABLE     ((0x0UL) << PDRVTZ1SEL1_ALL_OCHV_Pos)
#define PDRVTZ1SEL1_ALL_OCHV_ENABLE      ((0x1UL) << PDRVTZ1SEL1_ALL_OCHV_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVTZ1SEL1     OCHW
 *  @access     
 *  @brief      Select over-current on high-side of W phase as PDRVTZ1 event
 */
#define PDRVTZ1SEL1_ALL_OCHW_Pos (5)
#define PDRVTZ1SEL1_ALL_OCHW_Msk (0x1UL << PDRVTZ1SEL1_ALL_OCHW_Pos)

typedef enum
{
    PDRVTZ1SEL1_BIT_OCHW_DISABLE     = 0,  /*!< Disable   */
    PDRVTZ1SEL1_BIT_OCHW_ENABLE      = 1,  /*!< Enable    */
} PDRVTZ1SEL1_BIT_OCHW;

#define PDRVTZ1SEL1_ALL_OCHW_DISABLE     ((0x0UL) << PDRVTZ1SEL1_ALL_OCHW_Pos)
#define PDRVTZ1SEL1_ALL_OCHW_ENABLE      ((0x1UL) << PDRVTZ1SEL1_ALL_OCHW_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVBATVTH      VMIN
 *  @access     
 *  @brief      VBAT-too-low threshold select
 */
#define BODVBATVTH_ALL_VMIN_Pos (0)
#define BODVBATVTH_ALL_VMIN_Msk (0x7UL << BODVBATVTH_ALL_VMIN_Pos)

typedef enum
{
    BODVBATVTH_BIT_VMIN_8dot0_V      = 0,  /*!< Assert if VBAT<8.0V, de-assert if VBAT go back higher by 5-10%    */
    BODVBATVTH_BIT_VMIN_9dot0_V      = 1,  /*!< Assert if VBAT<9.0V, de-assert if VBAT go back higher by 5-10%    */
    BODVBATVTH_BIT_VMIN_14dot2_V     = 2,  /*!< Assert if VBAT<14.2V, de-assert if VBAT go back higher by 5-10%   */
    BODVBATVTH_BIT_VMIN_18dot7_V     = 3,  /*!< Assert if VBAT<18.7V, de-assert if VBAT go back higher by 5-10%   */
    BODVBATVTH_BIT_VMIN_20dot0_V     = 4,  /*!< Assert if VBAT<20.0V, de-assert if VBAT go back higher by 5-10%   */
    BODVBATVTH_BIT_VMIN_27dot5_V     = 5,  /*!< Assert if VBAT<27.5V, de-assert if VBAT go back higher by 5-10%   */
    BODVBATVTH_BIT_VMIN_30dot3_V     = 6,  /*!< Assert if VBAT<30.3V, de-assert if VBAT go back higher by 5-10%   */
    BODVBATVTH_BIT_VMIN_38dot2_V     = 7,  /*!< Assert if VBAT<38.2V, de-assert if VBAT go back higher by 5-10%   */
} BODVBATVTH_BIT_VMIN;

#define BODVBATVTH_ALL_VMIN_8dot0_V      ((0x0UL) << BODVBATVTH_ALL_VMIN_Pos)
#define BODVBATVTH_ALL_VMIN_9dot0_V      ((0x1UL) << BODVBATVTH_ALL_VMIN_Pos)
#define BODVBATVTH_ALL_VMIN_14dot2_V     ((0x2UL) << BODVBATVTH_ALL_VMIN_Pos)
#define BODVBATVTH_ALL_VMIN_18dot7_V     ((0x3UL) << BODVBATVTH_ALL_VMIN_Pos)
#define BODVBATVTH_ALL_VMIN_20dot0_V     ((0x4UL) << BODVBATVTH_ALL_VMIN_Pos)
#define BODVBATVTH_ALL_VMIN_27dot5_V     ((0x5UL) << BODVBATVTH_ALL_VMIN_Pos)
#define BODVBATVTH_ALL_VMIN_30dot3_V     ((0x6UL) << BODVBATVTH_ALL_VMIN_Pos)
#define BODVBATVTH_ALL_VMIN_38dot2_V     ((0x7UL) << BODVBATVTH_ALL_VMIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVBATVTH      VMAX
 *  @access     
 *  @brief      VBAT-too-high threshold
 */
#define BODVBATVTH_ALL_VMAX_Pos (4)
#define BODVBATVTH_ALL_VMAX_Msk (0x7UL << BODVBATVTH_ALL_VMAX_Pos)

typedef enum
{
    BODVBATVTH_BIT_VMAX_16dot6_V     = 0,  /*!< Assert if VBAT>16.6V, de-assert if VBAT go back lower by 5-10%   */
    BODVBATVTH_BIT_VMAX_23dot2_V     = 1,  /*!< Assert if VBAT>23.2V, de-assert if VBAT go back lower by 5-10%   */
    BODVBATVTH_BIT_VMAX_27dot5_V     = 2,  /*!< Assert if VBAT>27.5V, de-assert if VBAT go back lower by 5-10%   */
    BODVBATVTH_BIT_VMAX_30dot4_V     = 3,  /*!< Assert if VBAT>30.4V, de-assert if VBAT go back lower by 5-10%   */
    BODVBATVTH_BIT_VMAX_44dot0_V     = 4,  /*!< Assert if VBAT>44.0V, de-assert if VBAT go back lower by 5-10%   */
    BODVBATVTH_BIT_VMAX_51dot8_V     = 5,  /*!< Assert if VBAT>51.8V, de-assert if VBAT go back lower by 5-10%   */
    BODVBATVTH_BIT_VMAX_62dot9_V     = 6,  /*!< Assert if VBAT>62.9V, de-assert if VBAT go back lower by 5-10%   */
    BODVBATVTH_BIT_VMAX_88dot1_V     = 7,  /*!< Assert if VBAT>88.1V, de-assert if VBAT go back lower by 5-10%   */
} BODVBATVTH_BIT_VMAX;

#define BODVBATVTH_ALL_VMAX_16dot6_V     ((0x0UL) << BODVBATVTH_ALL_VMAX_Pos)
#define BODVBATVTH_ALL_VMAX_23dot2_V     ((0x1UL) << BODVBATVTH_ALL_VMAX_Pos)
#define BODVBATVTH_ALL_VMAX_27dot5_V     ((0x2UL) << BODVBATVTH_ALL_VMAX_Pos)
#define BODVBATVTH_ALL_VMAX_30dot4_V     ((0x3UL) << BODVBATVTH_ALL_VMAX_Pos)
#define BODVBATVTH_ALL_VMAX_44dot0_V     ((0x4UL) << BODVBATVTH_ALL_VMAX_Pos)
#define BODVBATVTH_ALL_VMAX_51dot8_V     ((0x5UL) << BODVBATVTH_ALL_VMAX_Pos)
#define BODVBATVTH_ALL_VMAX_62dot9_V     ((0x6UL) << BODVBATVTH_ALL_VMAX_Pos)
#define BODVBATVTH_ALL_VMAX_88dot1_V     ((0x7UL) << BODVBATVTH_ALL_VMAX_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVDDGVTH      VMIN
 *  @access     
 *  @brief      VDDG-too-low threshold select
 */
#define BODVDDGVTH_ALL_VMIN_Pos (0)
#define BODVDDGVTH_ALL_VMIN_Msk (0x7UL << BODVDDGVTH_ALL_VMIN_Pos)

typedef enum
{
    BODVDDGVTH_BIT_VMIN_7dot7_V      = 0,  /*!< Assert if VDDG<7.7V, de-assert if VDDG go back higher by 5-10%    */
    BODVDDGVTH_BIT_VMIN_8dot0_V      = 1,  /*!< Assert if VDDG<8.0V, de-assert if VDDG go back higher by 5-10%    */
    BODVDDGVTH_BIT_VMIN_8dot3_V      = 2,  /*!< Assert if VDDG<8.3V, de-assert if VDDG go back higher by 5-10%    */
    BODVDDGVTH_BIT_VMIN_8dot6_V      = 3,  /*!< Assert if VDDG<8.6V, de-assert if VDDG go back higher by 5-10%    */
    BODVDDGVTH_BIT_VMIN_8dot9_V      = 4,  /*!< Assert if VDDG<8.9V, de-assert if VDDG go back higher by 5-10%    */
    BODVDDGVTH_BIT_VMIN_9dot2_V      = 5,  /*!< Assert if VDDG<9.2V, de-assert if VDDG go back higher by 5-10%    */
    BODVDDGVTH_BIT_VMIN_9dot6_V      = 6,  /*!< Assert if VDDG<9.6V, de-assert if VDDG go back higher by 5-10%    */
    BODVDDGVTH_BIT_VMIN_10dot0_V     = 7,  /*!< Assert if VDDG<10.0V, de-assert if VDDG go back higher by 5-10%   */
} BODVDDGVTH_BIT_VMIN;

#define BODVDDGVTH_ALL_VMIN_7dot7_V      ((0x0UL) << BODVDDGVTH_ALL_VMIN_Pos)
#define BODVDDGVTH_ALL_VMIN_8dot0_V      ((0x1UL) << BODVDDGVTH_ALL_VMIN_Pos)
#define BODVDDGVTH_ALL_VMIN_8dot3_V      ((0x2UL) << BODVDDGVTH_ALL_VMIN_Pos)
#define BODVDDGVTH_ALL_VMIN_8dot6_V      ((0x3UL) << BODVDDGVTH_ALL_VMIN_Pos)
#define BODVDDGVTH_ALL_VMIN_8dot9_V      ((0x4UL) << BODVDDGVTH_ALL_VMIN_Pos)
#define BODVDDGVTH_ALL_VMIN_9dot2_V      ((0x5UL) << BODVDDGVTH_ALL_VMIN_Pos)
#define BODVDDGVTH_ALL_VMIN_9dot6_V      ((0x6UL) << BODVDDGVTH_ALL_VMIN_Pos)
#define BODVDDGVTH_ALL_VMIN_10dot0_V     ((0x7UL) << BODVDDGVTH_ALL_VMIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BODVDDGVTH      VMAX
 *  @access     
 *  @brief      VDDG-too-high threshold select
 */
#define BODVDDGVTH_ALL_VMAX_Pos (4)
#define BODVDDGVTH_ALL_VMAX_Msk (0x7UL << BODVDDGVTH_ALL_VMAX_Pos)

typedef enum
{
    BODVDDGVTH_BIT_VMAX_14dot1_V     = 0,  /*!< Assert if VDDG>14.1V, de-assert if VDDG go back lower by 5-10%   */
    BODVDDGVTH_BIT_VMAX_16dot0_V     = 1,  /*!< Assert if VDDG>16.0V, de-assert if VDDG go back lower by 5-10%   */
    BODVDDGVTH_BIT_VMAX_17dot1_V     = 2,  /*!< Assert if VDDG>17.1V, de-assert if VDDG go back lower by 5-10%   */
    BODVDDGVTH_BIT_VMAX_17dot4_V     = 3,  /*!< Assert if VDDG>17.4V, de-assert if VDDG go back lower by 5-10%   */
    BODVDDGVTH_BIT_VMAX_18dot4_V     = 4,  /*!< Assert if VDDG>18.4V, de-assert if VDDG go back lower by 5-10%   */
    BODVDDGVTH_BIT_VMAX_18dot8_V     = 5,  /*!< Assert if VDDG>18.8V, de-assert if VDDG go back lower by 5-10%   */
    BODVDDGVTH_BIT_VMAX_19dot5_V     = 6,  /*!< Assert if VDDG>19.5V, de-assert if VDDG go back lower by 5-10%   */
    BODVDDGVTH_BIT_VMAX_20dot0_V     = 7,  /*!< Assert if VDDG>20.0V, de-assert if VDDG go back lower by 5-10%   */
} BODVDDGVTH_BIT_VMAX;

#define BODVDDGVTH_ALL_VMAX_14dot1_V     ((0x0UL) << BODVDDGVTH_ALL_VMAX_Pos)
#define BODVDDGVTH_ALL_VMAX_16dot0_V     ((0x1UL) << BODVDDGVTH_ALL_VMAX_Pos)
#define BODVDDGVTH_ALL_VMAX_17dot1_V     ((0x2UL) << BODVDDGVTH_ALL_VMAX_Pos)
#define BODVDDGVTH_ALL_VMAX_17dot4_V     ((0x3UL) << BODVDDGVTH_ALL_VMAX_Pos)
#define BODVDDGVTH_ALL_VMAX_18dot4_V     ((0x4UL) << BODVDDGVTH_ALL_VMAX_Pos)
#define BODVDDGVTH_ALL_VMAX_18dot8_V     ((0x5UL) << BODVDDGVTH_ALL_VMAX_Pos)
#define BODVDDGVTH_ALL_VMAX_19dot5_V     ((0x6UL) << BODVDDGVTH_ALL_VMAX_Pos)
#define BODVDDGVTH_ALL_VMAX_20dot0_V     ((0x7UL) << BODVDDGVTH_ALL_VMAX_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL0       EN
 *  @access     
 *  @brief      BUCKG enable. This bit is writable only when CTLKEY=0x88
 */
#define BUCKGCTL0_ALL_EN_Pos (0)
#define BUCKGCTL0_ALL_EN_Msk (0x1UL << BUCKGCTL0_ALL_EN_Pos)

typedef enum
{
    BUCKGCTL0_BIT_EN_DISABLE     = 0,  /*!< Disable the BUCKG   */
    BUCKGCTL0_BIT_EN_ENABLE      = 1,  /*!< Enable the BUCKG    */
} BUCKGCTL0_BIT_EN;

#define BUCKGCTL0_ALL_EN_DISABLE     ((0x0UL) << BUCKGCTL0_ALL_EN_Pos)
#define BUCKGCTL0_ALL_EN_ENABLE      ((0x1UL) << BUCKGCTL0_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL0       TZ0EN
 *  @access     
 *  @brief      Enable TZ0 mask on BUCK enable so that the BUCK is self-disabled upon PDRVTZ0 event.
 *              This bit is writable only when CTLKEY=0x88
 */
#define BUCKGCTL0_ALL_TZ0EN_Pos (1)
#define BUCKGCTL0_ALL_TZ0EN_Msk (0x1UL << BUCKGCTL0_ALL_TZ0EN_Pos)

typedef enum
{
    BUCKGCTL0_BIT_TZ0EN_DISABLE     = 0,  /*!< PDRVTZ0 event will not affect the BUCK operation   */
    BUCKGCTL0_BIT_TZ0EN_ENABLE      = 1,  /*!< BUCK is immediatedly disabled upon PDRVTZ0 event   */
} BUCKGCTL0_BIT_TZ0EN;

#define BUCKGCTL0_ALL_TZ0EN_DISABLE     ((0x0UL) << BUCKGCTL0_ALL_TZ0EN_Pos)
#define BUCKGCTL0_ALL_TZ0EN_ENABLE      ((0x1UL) << BUCKGCTL0_ALL_TZ0EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL0       TZ1EN
 *  @access     
 *  @brief      Enable TZ1 mask on BUCK enable so that the BUCK is self-disabled upon PDRVTZ1 event
 *              This bit is writable only when CTLKEY=0x88
 */
#define BUCKGCTL0_ALL_TZ1EN_Pos (2)
#define BUCKGCTL0_ALL_TZ1EN_Msk (0x1UL << BUCKGCTL0_ALL_TZ1EN_Pos)

typedef enum
{
    BUCKGCTL0_BIT_TZ1EN_DISABLE     = 0,  /*!< PDRVTZ1 event will not affect the BUCK operation   */
    BUCKGCTL0_BIT_TZ1EN_ENABLE      = 1,  /*!< BUCK is immediatedly disabled upon PDRVTZ1 event   */
} BUCKGCTL0_BIT_TZ1EN;

#define BUCKGCTL0_ALL_TZ1EN_DISABLE     ((0x0UL) << BUCKGCTL0_ALL_TZ1EN_Pos)
#define BUCKGCTL0_ALL_TZ1EN_ENABLE      ((0x1UL) << BUCKGCTL0_ALL_TZ1EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL0       OVPROTEN
 *  @access     
 *  @brief      BUCKG output (VDDG) over-voltage protection enable
 */
#define BUCKGCTL0_ALL_OVPROTEN_Pos (3)
#define BUCKGCTL0_ALL_OVPROTEN_Msk (0x1UL << BUCKGCTL0_ALL_OVPROTEN_Pos)

typedef enum
{
    BUCKGCTL0_BIT_OVPROTEN_DISABLE     = 0,  /*!< Disable   */
    BUCKGCTL0_BIT_OVPROTEN_ENABLE      = 1,  /*!< Enable    */
} BUCKGCTL0_BIT_OVPROTEN;

#define BUCKGCTL0_ALL_OVPROTEN_DISABLE     ((0x0UL) << BUCKGCTL0_ALL_OVPROTEN_Pos)
#define BUCKGCTL0_ALL_OVPROTEN_ENABLE      ((0x1UL) << BUCKGCTL0_ALL_OVPROTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL0       FRCPWM
 *  @access     
 *  @brief      Force BUCKG operates in PWM mode
 */
#define BUCKGCTL0_ALL_FRCPWM_Pos (4)
#define BUCKGCTL0_ALL_FRCPWM_Msk (0x1UL << BUCKGCTL0_ALL_FRCPWM_Pos)

typedef enum
{
    BUCKGCTL0_BIT_FRCPWM_NO_EFFECT     = 0,  /*!< BUCKG's mode is controlled by the circuits   */
    BUCKGCTL0_BIT_FRCPWM_FORCE         = 1,  /*!< BUCKG is forced to operate in PWM mode       */
} BUCKGCTL0_BIT_FRCPWM;

#define BUCKGCTL0_ALL_FRCPWM_NO_EFFECT     ((0x0UL) << BUCKGCTL0_ALL_FRCPWM_Pos)
#define BUCKGCTL0_ALL_FRCPWM_FORCE         ((0x1UL) << BUCKGCTL0_ALL_FRCPWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL0       FREQSEL
 *  @access     
 *  @brief      BUCKG switching frequency select
 */
#define BUCKGCTL0_ALL_FREQSEL_Pos (5)
#define BUCKGCTL0_ALL_FREQSEL_Msk (0x3UL << BUCKGCTL0_ALL_FREQSEL_Pos)

typedef enum
{
    BUCKGCTL0_BIT_FREQSEL_300_kHz      = 0,  /*!< 300kHz    */
    BUCKGCTL0_BIT_FREQSEL_600_kHz      = 1,  /*!< 600kHz    */
    BUCKGCTL0_BIT_FREQSEL_1200_kHz     = 2,  /*!< 1200kHz   */
    BUCKGCTL0_BIT_FREQSEL_2400_kHz     = 3,  /*!< 2400kHz   */
} BUCKGCTL0_BIT_FREQSEL;

#define BUCKGCTL0_ALL_FREQSEL_300_kHz      ((0x0UL) << BUCKGCTL0_ALL_FREQSEL_Pos)
#define BUCKGCTL0_ALL_FREQSEL_600_kHz      ((0x1UL) << BUCKGCTL0_ALL_FREQSEL_Pos)
#define BUCKGCTL0_ALL_FREQSEL_1200_kHz     ((0x2UL) << BUCKGCTL0_ALL_FREQSEL_Pos)
#define BUCKGCTL0_ALL_FREQSEL_2400_kHz     ((0x3UL) << BUCKGCTL0_ALL_FREQSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL1       MINTOFF
 *  @access     
 *  @brief      BUCKG minimum off-time select
 */
#define BUCKGCTL1_ALL_MINTOFF_Pos (0)
#define BUCKGCTL1_ALL_MINTOFF_Msk (0x3UL << BUCKGCTL1_ALL_MINTOFF_Pos)

typedef enum
{
    BUCKGCTL1_BIT_MINTOFF_150_NS     = 0,  /*!< 150ns   */
    BUCKGCTL1_BIT_MINTOFF_200_NS     = 1,  /*!< 200ns   */
    BUCKGCTL1_BIT_MINTOFF_250_NS     = 2,  /*!< 250ns   */
    BUCKGCTL1_BIT_MINTOFF_300_NS     = 3,  /*!< 300ns   */
} BUCKGCTL1_BIT_MINTOFF;

#define BUCKGCTL1_ALL_MINTOFF_150_NS     ((0x0UL) << BUCKGCTL1_ALL_MINTOFF_Pos)
#define BUCKGCTL1_ALL_MINTOFF_200_NS     ((0x1UL) << BUCKGCTL1_ALL_MINTOFF_Pos)
#define BUCKGCTL1_ALL_MINTOFF_250_NS     ((0x2UL) << BUCKGCTL1_ALL_MINTOFF_Pos)
#define BUCKGCTL1_ALL_MINTOFF_300_NS     ((0x3UL) << BUCKGCTL1_ALL_MINTOFF_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL1       UVTH
 *  @access     
 *  @brief      BUCKG under-voltage threshold select
 */
#define BUCKGCTL1_ALL_UVTH_Pos (2)
#define BUCKGCTL1_ALL_UVTH_Msk (0x3UL << BUCKGCTL1_ALL_UVTH_Pos)

typedef enum
{
    BUCKGCTL1_BIT_UVTH_4dot5_V     = 0,  /*!< 4.5V   */
    BUCKGCTL1_BIT_UVTH_8_V         = 1,  /*!< 8V     */
    BUCKGCTL1_BIT_UVTH_10_V        = 2,  /*!< 10V    */
    BUCKGCTL1_BIT_UVTH_15_V        = 3,  /*!< 15V    */
} BUCKGCTL1_BIT_UVTH;

#define BUCKGCTL1_ALL_UVTH_4dot5_V     ((0x0UL) << BUCKGCTL1_ALL_UVTH_Pos)
#define BUCKGCTL1_ALL_UVTH_8_V         ((0x1UL) << BUCKGCTL1_ALL_UVTH_Pos)
#define BUCKGCTL1_ALL_UVTH_10_V        ((0x2UL) << BUCKGCTL1_ALL_UVTH_Pos)
#define BUCKGCTL1_ALL_UVTH_15_V        ((0x3UL) << BUCKGCTL1_ALL_UVTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL1       FRCUNITY
 *  @access     
 *  @brief      Force buck into unity gain mode
 */
#define BUCKGCTL1_ALL_FRCUNITY_Pos (4)
#define BUCKGCTL1_ALL_FRCUNITY_Msk (0x1UL << BUCKGCTL1_ALL_FRCUNITY_Pos)

typedef enum
{
    BUCKGCTL1_BIT_FRCUNITY_DISABLE     = 0,  /*!<    */
    BUCKGCTL1_BIT_FRCUNITY_ENABLE      = 1,  /*!<    */
} BUCKGCTL1_BIT_FRCUNITY;

#define BUCKGCTL1_ALL_FRCUNITY_DISABLE     ((0x0UL) << BUCKGCTL1_ALL_FRCUNITY_Pos)
#define BUCKGCTL1_ALL_FRCUNITY_ENABLE      ((0x1UL) << BUCKGCTL1_ALL_FRCUNITY_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCKGCTL1       VOUTSEL
 *  @access     
 *  @brief      BUCKG output voltage select
 */
#define BUCKGCTL1_ALL_VOUTSEL_Pos (5)
#define BUCKGCTL1_ALL_VOUTSEL_Msk (0x7UL << BUCKGCTL1_ALL_VOUTSEL_Pos)

typedef enum
{
    BUCKGCTL1_BIT_VOUTSEL_5_V      = 0,  /*!< 5V    */
    BUCKGCTL1_BIT_VOUTSEL_8_V      = 1,  /*!< 8V    */
    BUCKGCTL1_BIT_VOUTSEL_9_V      = 2,  /*!< 9V    */
    BUCKGCTL1_BIT_VOUTSEL_10_V     = 3,  /*!< 10V   */
    BUCKGCTL1_BIT_VOUTSEL_12_V     = 4,  /*!< 12V   */
    BUCKGCTL1_BIT_VOUTSEL_15_V     = 5,  /*!< 15V   */
    BUCKGCTL1_BIT_VOUTSEL_16_V     = 6,  /*!< 16V   */
    BUCKGCTL1_BIT_VOUTSEL_18_V     = 7,  /*!< 18V   */
} BUCKGCTL1_BIT_VOUTSEL;

#define BUCKGCTL1_ALL_VOUTSEL_5_V      ((0x0UL) << BUCKGCTL1_ALL_VOUTSEL_Pos)
#define BUCKGCTL1_ALL_VOUTSEL_8_V      ((0x1UL) << BUCKGCTL1_ALL_VOUTSEL_Pos)
#define BUCKGCTL1_ALL_VOUTSEL_9_V      ((0x2UL) << BUCKGCTL1_ALL_VOUTSEL_Pos)
#define BUCKGCTL1_ALL_VOUTSEL_10_V     ((0x3UL) << BUCKGCTL1_ALL_VOUTSEL_Pos)
#define BUCKGCTL1_ALL_VOUTSEL_12_V     ((0x4UL) << BUCKGCTL1_ALL_VOUTSEL_Pos)
#define BUCKGCTL1_ALL_VOUTSEL_15_V     ((0x5UL) << BUCKGCTL1_ALL_VOUTSEL_Pos)
#define BUCKGCTL1_ALL_VOUTSEL_16_V     ((0x6UL) << BUCKGCTL1_ALL_VOUTSEL_Pos)
#define BUCKGCTL1_ALL_VOUTSEL_18_V     ((0x7UL) << BUCKGCTL1_ALL_VOUTSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCK3CTL        EN
 *  @access     
 *  @brief      BUCK3 enable. This bit is writable only when CTLKEY=0x88
 */
#define BUCK3CTL_ALL_EN_Pos (0)
#define BUCK3CTL_ALL_EN_Msk (0x1UL << BUCK3CTL_ALL_EN_Pos)

typedef enum
{
    BUCK3CTL_BIT_EN_DISABLE     = 0,  /*!< Disable the BUCK3   */
    BUCK3CTL_BIT_EN_ENABLE      = 1,  /*!< Enable the BUCK3    */
} BUCK3CTL_BIT_EN;

#define BUCK3CTL_ALL_EN_DISABLE     ((0x0UL) << BUCK3CTL_ALL_EN_Pos)
#define BUCK3CTL_ALL_EN_ENABLE      ((0x1UL) << BUCK3CTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCK3CTL        OVPROTEN
 *  @access     
 *  @brief      BUCK3 output (VDD33) over-voltage protection enable
 */
#define BUCK3CTL_ALL_OVPROTEN_Pos (1)
#define BUCK3CTL_ALL_OVPROTEN_Msk (0x1UL << BUCK3CTL_ALL_OVPROTEN_Pos)

typedef enum
{
    BUCK3CTL_BIT_OVPROTEN_DISABLE     = 0,  /*!< Disable   */
    BUCK3CTL_BIT_OVPROTEN_ENABLE      = 1,  /*!< Enable    */
} BUCK3CTL_BIT_OVPROTEN;

#define BUCK3CTL_ALL_OVPROTEN_DISABLE     ((0x0UL) << BUCK3CTL_ALL_OVPROTEN_Pos)
#define BUCK3CTL_ALL_OVPROTEN_ENABLE      ((0x1UL) << BUCK3CTL_ALL_OVPROTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCK3CTL        FRCPWM
 *  @access     
 *  @brief      Force BUCK3 operates in PWM mode
 */
#define BUCK3CTL_ALL_FRCPWM_Pos (2)
#define BUCK3CTL_ALL_FRCPWM_Msk (0x1UL << BUCK3CTL_ALL_FRCPWM_Pos)

typedef enum
{
    BUCK3CTL_BIT_FRCPWM_NO_EFFECT     = 0,  /*!< BUCK3's mode is controlled by the circuits   */
    BUCK3CTL_BIT_FRCPWM_FORCE         = 1,  /*!< BUCK3 is forced to operate in PWM mode       */
} BUCK3CTL_BIT_FRCPWM;

#define BUCK3CTL_ALL_FRCPWM_NO_EFFECT     ((0x0UL) << BUCK3CTL_ALL_FRCPWM_Pos)
#define BUCK3CTL_ALL_FRCPWM_FORCE         ((0x1UL) << BUCK3CTL_ALL_FRCPWM_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCK3CTL        FREQSEL
 *  @access     
 *  @brief      BUCK3 switching frequency select
 */
#define BUCK3CTL_ALL_FREQSEL_Pos (3)
#define BUCK3CTL_ALL_FREQSEL_Msk (0x3UL << BUCK3CTL_ALL_FREQSEL_Pos)

typedef enum
{
    BUCK3CTL_BIT_FREQSEL_400_kHz      = 0,  /*!< 400kHz    */
    BUCK3CTL_BIT_FREQSEL_600_kHz      = 1,  /*!< 600kHz    */
    BUCK3CTL_BIT_FREQSEL_1200_kHz     = 2,  /*!< 1200kHz   */
    BUCK3CTL_BIT_FREQSEL_2400_kHz     = 3,  /*!< 2400kHz   */
} BUCK3CTL_BIT_FREQSEL;

#define BUCK3CTL_ALL_FREQSEL_400_kHz      ((0x0UL) << BUCK3CTL_ALL_FREQSEL_Pos)
#define BUCK3CTL_ALL_FREQSEL_600_kHz      ((0x1UL) << BUCK3CTL_ALL_FREQSEL_Pos)
#define BUCK3CTL_ALL_FREQSEL_1200_kHz     ((0x2UL) << BUCK3CTL_ALL_FREQSEL_Pos)
#define BUCK3CTL_ALL_FREQSEL_2400_kHz     ((0x3UL) << BUCK3CTL_ALL_FREQSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              BUCK3CTL        OTWARNTH
 *  @access     
 *  @brief      BUCK3 over-temperature warning threshold select
 */
#define BUCK3CTL_ALL_OTWARNTH_Pos (5)
#define BUCK3CTL_ALL_OTWARNTH_Msk (0x7UL << BUCK3CTL_ALL_OTWARNTH_Pos)

typedef enum
{
    BUCK3CTL_BIT_OTWARNTH_7_DEGREE       = 0,  /*!< 7 centigrade degree     */
    BUCK3CTL_BIT_OTWARNTH_92_DEGREE      = 1,  /*!< 92 centigrade degree    */
    BUCK3CTL_BIT_OTWARNTH_101_DEGREE     = 2,  /*!< 101 centigrade degree   */
    BUCK3CTL_BIT_OTWARNTH_109_DEGREE     = 3,  /*!< 109 centigrade degree   */
    BUCK3CTL_BIT_OTWARNTH_118_DEGREE     = 4,  /*!< 118 centigrade degree   */
    BUCK3CTL_BIT_OTWARNTH_126_DEGREE     = 5,  /*!< 126 centigrade degree   */
    BUCK3CTL_BIT_OTWARNTH_135_DEGREE     = 6,  /*!< 135 centigrade degree   */
    BUCK3CTL_BIT_OTWARNTH_143_DEGREE     = 7,  /*!< 143 centigrade degree   */
} BUCK3CTL_BIT_OTWARNTH;

#define BUCK3CTL_ALL_OTWARNTH_7_DEGREE       ((0x0UL) << BUCK3CTL_ALL_OTWARNTH_Pos)
#define BUCK3CTL_ALL_OTWARNTH_92_DEGREE      ((0x1UL) << BUCK3CTL_ALL_OTWARNTH_Pos)
#define BUCK3CTL_ALL_OTWARNTH_101_DEGREE     ((0x2UL) << BUCK3CTL_ALL_OTWARNTH_Pos)
#define BUCK3CTL_ALL_OTWARNTH_109_DEGREE     ((0x3UL) << BUCK3CTL_ALL_OTWARNTH_Pos)
#define BUCK3CTL_ALL_OTWARNTH_118_DEGREE     ((0x4UL) << BUCK3CTL_ALL_OTWARNTH_Pos)
#define BUCK3CTL_ALL_OTWARNTH_126_DEGREE     ((0x5UL) << BUCK3CTL_ALL_OTWARNTH_Pos)
#define BUCK3CTL_ALL_OTWARNTH_135_DEGREE     ((0x6UL) << BUCK3CTL_ALL_OTWARNTH_Pos)
#define BUCK3CTL_ALL_OTWARNTH_143_DEGREE     ((0x7UL) << BUCK3CTL_ALL_OTWARNTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SSCTL           BUCKGSSEN
 *  @access     
 *  @brief      BUCKG spread-spectrum enable
 */
#define SSCTL_ALL_BUCKGSSEN_Pos (0)
#define SSCTL_ALL_BUCKGSSEN_Msk (0x1UL << SSCTL_ALL_BUCKGSSEN_Pos)

typedef enum
{
    SSCTL_BIT_BUCKGSSEN_DISABLE     = 0,  /*!< Disable   */
    SSCTL_BIT_BUCKGSSEN_ENABLE      = 1,  /*!< Enable    */
} SSCTL_BIT_BUCKGSSEN;

#define SSCTL_ALL_BUCKGSSEN_DISABLE     ((0x0UL) << SSCTL_ALL_BUCKGSSEN_Pos)
#define SSCTL_ALL_BUCKGSSEN_ENABLE      ((0x1UL) << SSCTL_ALL_BUCKGSSEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SSCTL           BUCKGSSAMP
 *  @access     
 *  @brief      BUCKG spread-spectrum amplitude
 */
#define SSCTL_ALL_BUCKGSSAMP_Pos (1)
#define SSCTL_ALL_BUCKGSSAMP_Msk (0x3UL << SSCTL_ALL_BUCKGSSAMP_Pos)

typedef enum
{
    SSCTL_BIT_BUCKGSSAMP_192_TO_360     = 0,  /*!< Cap code is from 192 to 360   */
    SSCTL_BIT_BUCKGSSAMP_171_TO_341     = 1,  /*!< Cap code is from 171 to 341   */
    SSCTL_BIT_BUCKGSSAMP_128_TO_384     = 2,  /*!< Cap code is from 128 to 384   */
    SSCTL_BIT_BUCKGSSAMP_0_TO_511       = 3,  /*!< Cap code is from 0 to 511     */
} SSCTL_BIT_BUCKGSSAMP;

#define SSCTL_ALL_BUCKGSSAMP_192_TO_360     ((0x0UL) << SSCTL_ALL_BUCKGSSAMP_Pos)
#define SSCTL_ALL_BUCKGSSAMP_171_TO_341     ((0x1UL) << SSCTL_ALL_BUCKGSSAMP_Pos)
#define SSCTL_ALL_BUCKGSSAMP_128_TO_384     ((0x2UL) << SSCTL_ALL_BUCKGSSAMP_Pos)
#define SSCTL_ALL_BUCKGSSAMP_0_TO_511       ((0x3UL) << SSCTL_ALL_BUCKGSSAMP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SSCTL           BUCKGSSPRD
 *  @access     
 *  @brief      BUCKG spread-spectrum period
 */
#define SSCTL_ALL_BUCKGSSPRD_Pos (3)
#define SSCTL_ALL_BUCKGSSPRD_Msk (0x1UL << SSCTL_ALL_BUCKGSSPRD_Pos)

typedef enum
{
    SSCTL_BIT_BUCKGSSPRD_1X     = 0,  /*!< Normal period, which is 2 x BUCKGSSAMP clocks     */
    SSCTL_BIT_BUCKGSSPRD_2X     = 1,  /*!< Twice the period, which is 4x BUCKGSSAMP clocks   */
} SSCTL_BIT_BUCKGSSPRD;

#define SSCTL_ALL_BUCKGSSPRD_1X     ((0x0UL) << SSCTL_ALL_BUCKGSSPRD_Pos)
#define SSCTL_ALL_BUCKGSSPRD_2X     ((0x1UL) << SSCTL_ALL_BUCKGSSPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SSCTL           BUCK3SSEN
 *  @access     
 *  @brief      BUCK3 spread-spectrum enable
 */
#define SSCTL_ALL_BUCK3SSEN_Pos (4)
#define SSCTL_ALL_BUCK3SSEN_Msk (0x1UL << SSCTL_ALL_BUCK3SSEN_Pos)

typedef enum
{
    SSCTL_BIT_BUCK3SSEN_DISABLE     = 0,  /*!< Disable   */
    SSCTL_BIT_BUCK3SSEN_ENABLE      = 1,  /*!< Enable    */
} SSCTL_BIT_BUCK3SSEN;

#define SSCTL_ALL_BUCK3SSEN_DISABLE     ((0x0UL) << SSCTL_ALL_BUCK3SSEN_Pos)
#define SSCTL_ALL_BUCK3SSEN_ENABLE      ((0x1UL) << SSCTL_ALL_BUCK3SSEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SSCTL           BUCK3SSAMP
 *  @access     
 *  @brief      BUCK3 spread-spectrum amplitude
 */
#define SSCTL_ALL_BUCK3SSAMP_Pos (5)
#define SSCTL_ALL_BUCK3SSAMP_Msk (0x3UL << SSCTL_ALL_BUCK3SSAMP_Pos)

typedef enum
{
    SSCTL_BIT_BUCK3SSAMP_192_TO_360     = 0,  /*!< Cap code is from 192 to 360   */
    SSCTL_BIT_BUCK3SSAMP_171_TO_341     = 1,  /*!< Cap code is from 171 to 341   */
    SSCTL_BIT_BUCK3SSAMP_128_TO_384     = 2,  /*!< Cap code is from 128 to 384   */
    SSCTL_BIT_BUCK3SSAMP_0_TO_511       = 3,  /*!< Cap code is from 0 to 511     */
} SSCTL_BIT_BUCK3SSAMP;

#define SSCTL_ALL_BUCK3SSAMP_192_TO_360     ((0x0UL) << SSCTL_ALL_BUCK3SSAMP_Pos)
#define SSCTL_ALL_BUCK3SSAMP_171_TO_341     ((0x1UL) << SSCTL_ALL_BUCK3SSAMP_Pos)
#define SSCTL_ALL_BUCK3SSAMP_128_TO_384     ((0x2UL) << SSCTL_ALL_BUCK3SSAMP_Pos)
#define SSCTL_ALL_BUCK3SSAMP_0_TO_511       ((0x3UL) << SSCTL_ALL_BUCK3SSAMP_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SSCTL           BUCK3SSPRD
 *  @access     
 *  @brief      BUCK3 spread-spectrum period
 */
#define SSCTL_ALL_BUCK3SSPRD_Pos (7)
#define SSCTL_ALL_BUCK3SSPRD_Msk (0x1UL << SSCTL_ALL_BUCK3SSPRD_Pos)

typedef enum
{
    SSCTL_BIT_BUCK3SSPRD_1X     = 0,  /*!< Normal period, which is 2 x BUCK3SSAMP clocks     */
    SSCTL_BIT_BUCK3SSPRD_2X     = 1,  /*!< Twice the period, which is 4x BUCK3SSAMP clocks   */
} SSCTL_BIT_BUCK3SSPRD;

#define SSCTL_ALL_BUCK3SSPRD_1X     ((0x0UL) << SSCTL_ALL_BUCK3SSPRD_Pos)
#define SSCTL_ALL_BUCK3SSPRD_2X     ((0x1UL) << SSCTL_ALL_BUCK3SSPRD_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVCTL         EN
 *  @access     
 *  @brief      Pre-driver enable
 *              This bit is writable only when CTLKEY=0x99
 */
#define PDRVCTL_ALL_EN_Pos (0)
#define PDRVCTL_ALL_EN_Msk (0x1UL << PDRVCTL_ALL_EN_Pos)

typedef enum
{
    PDRVCTL_BIT_EN_DISABLE     = 0,  /*!< Disable   */
    PDRVCTL_BIT_EN_ENABLE      = 1,  /*!< Enable    */
} PDRVCTL_BIT_EN;

#define PDRVCTL_ALL_EN_DISABLE     ((0x0UL) << PDRVCTL_ALL_EN_Pos)
#define PDRVCTL_ALL_EN_ENABLE      ((0x1UL) << PDRVCTL_ALL_EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVCTL         TZ0EN
 *  @access     
 *  @brief      Enable TZ0 mask on pre-driver enable so that the pre-driver is self-disabled upon
 *              PDRVTZ0 event.
 *              This bit is writable only when CTLKEY=0x99
 */
#define PDRVCTL_ALL_TZ0EN_Pos (1)
#define PDRVCTL_ALL_TZ0EN_Msk (0x1UL << PDRVCTL_ALL_TZ0EN_Pos)

typedef enum
{
    PDRVCTL_BIT_TZ0EN_DISABLE     = 0,  /*!< PDRVTZ0 event will not affect the pre-driver operation   */
    PDRVCTL_BIT_TZ0EN_ENABLE      = 1,  /*!< Pre-driver is immediatedly disabled upon PDRVTZ0 event   */
} PDRVCTL_BIT_TZ0EN;

#define PDRVCTL_ALL_TZ0EN_DISABLE     ((0x0UL) << PDRVCTL_ALL_TZ0EN_Pos)
#define PDRVCTL_ALL_TZ0EN_ENABLE      ((0x1UL) << PDRVCTL_ALL_TZ0EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVCTL         TZ1EN
 *  @access     
 *  @brief      Enable TZ1 mask on pre-driver enable so that the pre-driver is self-disabled upon
 *              PDRVTZ1 event
 *              This bit is writable only when CTLKEY=0x99
 */
#define PDRVCTL_ALL_TZ1EN_Pos (2)
#define PDRVCTL_ALL_TZ1EN_Msk (0x1UL << PDRVCTL_ALL_TZ1EN_Pos)

typedef enum
{
    PDRVCTL_BIT_TZ1EN_DISABLE     = 0,  /*!< PDRVTZ1 event will not affect the pre-driver operation   */
    PDRVCTL_BIT_TZ1EN_ENABLE      = 1,  /*!< Pre-driver is immediatedly disabled upon PDRVTZ1 event   */
} PDRVCTL_BIT_TZ1EN;

#define PDRVCTL_ALL_TZ1EN_DISABLE     ((0x0UL) << PDRVCTL_ALL_TZ1EN_Pos)
#define PDRVCTL_ALL_TZ1EN_ENABLE      ((0x1UL) << PDRVCTL_ALL_TZ1EN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVCTL         CPPROTEN
 *  @access     
 *  @brief      Pre-driver charge-pump protection enable
 */
#define PDRVCTL_ALL_CPPROTEN_Pos (3)
#define PDRVCTL_ALL_CPPROTEN_Msk (0x1UL << PDRVCTL_ALL_CPPROTEN_Pos)

typedef enum
{
    PDRVCTL_BIT_CPPROTEN_DISABLE     = 0,  /*!< Disable                                                      */
    PDRVCTL_BIT_CPPROTEN_ENABLE      = 1,  /*!< Enable so that charge-pump will be disconnected upon fault   */
} PDRVCTL_BIT_CPPROTEN;

#define PDRVCTL_ALL_CPPROTEN_DISABLE     ((0x0UL) << PDRVCTL_ALL_CPPROTEN_Pos)
#define PDRVCTL_ALL_CPPROTEN_ENABLE      ((0x1UL) << PDRVCTL_ALL_CPPROTEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVCTL         NOVWIN
 *  @access     
 *  @brief      Pre-driver non-overlap time window size
 */
#define PDRVCTL_ALL_NOVWIN_Pos (4)
#define PDRVCTL_ALL_NOVWIN_Msk (0x1UL << PDRVCTL_ALL_NOVWIN_Pos)

typedef enum
{
    PDRVCTL_BIT_NOVWIN_48_NS     = 0,  /*!< 48ns   */
    PDRVCTL_BIT_NOVWIN_96_NS     = 1,  /*!< 96ns   */
} PDRVCTL_BIT_NOVWIN;

#define PDRVCTL_ALL_NOVWIN_48_NS     ((0x0UL) << PDRVCTL_ALL_NOVWIN_Pos)
#define PDRVCTL_ALL_NOVWIN_96_NS     ((0x1UL) << PDRVCTL_ALL_NOVWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVCTL         SLEWRATE
 *  @access     
 *  @brief      Pre-driver slew-rate select
 */
#define PDRVCTL_ALL_SLEWRATE_Pos (5)
#define PDRVCTL_ALL_SLEWRATE_Msk (0x1UL << PDRVCTL_ALL_SLEWRATE_Pos)

typedef enum
{
    PDRVCTL_BIT_SLEWRATE_SLOW     = 0,  /*!< Slow slew rate   */
    PDRVCTL_BIT_SLEWRATE_FAST     = 1,  /*!< Fast slew rate   */
} PDRVCTL_BIT_SLEWRATE;

#define PDRVCTL_ALL_SLEWRATE_SLOW     ((0x0UL) << PDRVCTL_ALL_SLEWRATE_Pos)
#define PDRVCTL_ALL_SLEWRATE_FAST     ((0x1UL) << PDRVCTL_ALL_SLEWRATE_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PDRVOCCTL       OCTH
 *  @access     
 *  @brief      Pre-driver over-current threshold in term of FET Vds
 */
#define PDRVOCCTL_ALL_OCTH_Pos (0)
#define PDRVOCCTL_ALL_OCTH_Msk (0xFUL << PDRVOCCTL_ALL_OCTH_Pos)

typedef enum
{
    PDRVOCCTL_BIT_OCTH_0dot15_V     = 0,  /*!< 0.15V   */
    PDRVOCCTL_BIT_OCTH_0dot30_V     = 1,  /*!< 0.30V   */
    PDRVOCCTL_BIT_OCTH_0dot45_V     = 2,  /*!< 0.45V   */
    PDRVOCCTL_BIT_OCTH_0dot60_V     = 3,  /*!< 0.60V   */
    PDRVOCCTL_BIT_OCTH_0dot75_V     = 4,  /*!< 0.75V   */
    PDRVOCCTL_BIT_OCTH_0dot90_V     = 5,  /*!< 0.90V   */
    PDRVOCCTL_BIT_OCTH_1dot05_V     = 6,  /*!< 1.05V   */
    PDRVOCCTL_BIT_OCTH_1dot20_V     = 7,  /*!< 1.20V   */
    PDRVOCCTL_BIT_OCTH_1dot35_V     = 8,  /*!< 1.35V   */
    PDRVOCCTL_BIT_OCTH_1dot50_V     = 9,  /*!< 1.50V   */
    PDRVOCCTL_BIT_OCTH_1dot65_V     = 10,  /*!< 1.65V   */
    PDRVOCCTL_BIT_OCTH_1dot80_V     = 11,  /*!< 1.80V   */
    PDRVOCCTL_BIT_OCTH_1dot95_V     = 12,  /*!< 1.95V   */
    PDRVOCCTL_BIT_OCTH_2dot10_V     = 13,  /*!< 2.10V   */
    PDRVOCCTL_BIT_OCTH_2dot25_V     = 14,  /*!< 2.25V   */
    PDRVOCCTL_BIT_OCTH_2dot40_V     = 15,  /*!< 2.40V   */
} PDRVOCCTL_BIT_OCTH;

#define PDRVOCCTL_ALL_OCTH_0dot15_V     ((0x00UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_0dot30_V     ((0x01UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_0dot45_V     ((0x02UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_0dot60_V     ((0x03UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_0dot75_V     ((0x04UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_0dot90_V     ((0x05UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_1dot05_V     ((0x06UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_1dot20_V     ((0x07UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_1dot35_V     ((0x08UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_1dot50_V     ((0x09UL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_1dot65_V     ((0x0AUL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_1dot80_V     ((0x0BUL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_1dot95_V     ((0x0CUL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_2dot10_V     ((0x0DUL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_2dot25_V     ((0x0EUL) << PDRVOCCTL_ALL_OCTH_Pos)
#define PDRVOCCTL_ALL_OCTH_2dot40_V     ((0x0FUL) << PDRVOCCTL_ALL_OCTH_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PGACTL          UEN
 *  @access     
 *  @brief      PGA U phase enable
 */
#define PGACTL_ALL_UEN_Pos (0)
#define PGACTL_ALL_UEN_Msk (0x1UL << PGACTL_ALL_UEN_Pos)

typedef enum
{
    PGACTL_BIT_UEN_DISABLE     = 0,  /*!< Disable   */
    PGACTL_BIT_UEN_ENABLE      = 1,  /*!< Enable    */
} PGACTL_BIT_UEN;

#define PGACTL_ALL_UEN_DISABLE     ((0x0UL) << PGACTL_ALL_UEN_Pos)
#define PGACTL_ALL_UEN_ENABLE      ((0x1UL) << PGACTL_ALL_UEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PGACTL          VEN
 *  @access     
 *  @brief      PGA V phase enable
 */
#define PGACTL_ALL_VEN_Pos (1)
#define PGACTL_ALL_VEN_Msk (0x1UL << PGACTL_ALL_VEN_Pos)

typedef enum
{
    PGACTL_BIT_VEN_DISABLE     = 0,  /*!< Disable   */
    PGACTL_BIT_VEN_ENABLE      = 1,  /*!< Enable    */
} PGACTL_BIT_VEN;

#define PGACTL_ALL_VEN_DISABLE     ((0x0UL) << PGACTL_ALL_VEN_Pos)
#define PGACTL_ALL_VEN_ENABLE      ((0x1UL) << PGACTL_ALL_VEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PGACTL          WEN
 *  @access     
 *  @brief      PGA W phase enable
 */
#define PGACTL_ALL_WEN_Pos (2)
#define PGACTL_ALL_WEN_Msk (0x1UL << PGACTL_ALL_WEN_Pos)

typedef enum
{
    PGACTL_BIT_WEN_DISABLE     = 0,  /*!< Disable   */
    PGACTL_BIT_WEN_ENABLE      = 1,  /*!< Enable    */
} PGACTL_BIT_WEN;

#define PGACTL_ALL_WEN_DISABLE     ((0x0UL) << PGACTL_ALL_WEN_Pos)
#define PGACTL_ALL_WEN_ENABLE      ((0x1UL) << PGACTL_ALL_WEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PGACTL          BYPASS
 *  @access     
 *  @brief      Set PGA into bypass mode
 */
#define PGACTL_ALL_BYPASS_Pos (3)
#define PGACTL_ALL_BYPASS_Msk (0x1UL << PGACTL_ALL_BYPASS_Pos)

typedef enum
{
    PGACTL_BIT_BYPASS_DISABLE     = 0,  /*!< Normal operation mode   */
    PGACTL_BIT_BYPASS_ENABLE      = 1,  /*!< Bypass mode             */
} PGACTL_BIT_BYPASS;

#define PGACTL_ALL_BYPASS_DISABLE     ((0x0UL) << PGACTL_ALL_BYPASS_Pos)
#define PGACTL_ALL_BYPASS_ENABLE      ((0x1UL) << PGACTL_ALL_BYPASS_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              PGACTL          GAIN
 *  @access     
 *  @brief      PGA gain
 */
#define PGACTL_ALL_GAIN_Pos (4)
#define PGACTL_ALL_GAIN_Msk (0xFUL << PGACTL_ALL_GAIN_Pos)

typedef enum
{
    PGACTL_BIT_GAIN_1X      = 0,  /*!< 1    */
    PGACTL_BIT_GAIN_2X      = 1,  /*!< 2    */
    PGACTL_BIT_GAIN_4X      = 2,  /*!< 4    */
    PGACTL_BIT_GAIN_8X      = 3,  /*!< 8    */
    PGACTL_BIT_GAIN_12X     = 4,  /*!< 12   */
    PGACTL_BIT_GAIN_16X     = 5,  /*!< 16   */
    PGACTL_BIT_GAIN_32X     = 6,  /*!< 32   */
    PGACTL_BIT_GAIN_64X     = 7,  /*!< 64   */
    // PGACTL_BIT_GAIN_1X   = 8,  /*!< 1    */
    // PGACTL_BIT_GAIN_2X   = 9,  /*!< 2    */
    // PGACTL_BIT_GAIN_4X   = 10,  /*!< 4    */
    // PGACTL_BIT_GAIN_8X   = 11,  /*!< 8    */
    // PGACTL_BIT_GAIN_12X  = 12,  /*!< 12   */
    // PGACTL_BIT_GAIN_16X  = 13,  /*!< 16   */
    // PGACTL_BIT_GAIN_32X  = 14,  /*!< 32   */
    // PGACTL_BIT_GAIN_64X  = 15,  /*!< 64   */
} PGACTL_BIT_GAIN;

#define PGACTL_ALL_GAIN_1X      ((0x00UL) << PGACTL_ALL_GAIN_Pos)
#define PGACTL_ALL_GAIN_2X      ((0x01UL) << PGACTL_ALL_GAIN_Pos)
#define PGACTL_ALL_GAIN_4X      ((0x02UL) << PGACTL_ALL_GAIN_Pos)
#define PGACTL_ALL_GAIN_8X      ((0x03UL) << PGACTL_ALL_GAIN_Pos)
#define PGACTL_ALL_GAIN_12X     ((0x04UL) << PGACTL_ALL_GAIN_Pos)
#define PGACTL_ALL_GAIN_16X     ((0x05UL) << PGACTL_ALL_GAIN_Pos)
#define PGACTL_ALL_GAIN_32X     ((0x06UL) << PGACTL_ALL_GAIN_Pos)
#define PGACTL_ALL_GAIN_64X     ((0x07UL) << PGACTL_ALL_GAIN_Pos)
// #define PGACTL_ALL_GAIN_1X      ((0x08UL) << PGACTL_ALL_GAIN_Pos)
// #define PGACTL_ALL_GAIN_2X      ((0x09UL) << PGACTL_ALL_GAIN_Pos)
// #define PGACTL_ALL_GAIN_4X      ((0x0AUL) << PGACTL_ALL_GAIN_Pos)
// #define PGACTL_ALL_GAIN_8X      ((0x0BUL) << PGACTL_ALL_GAIN_Pos)
// #define PGACTL_ALL_GAIN_12X     ((0x0CUL) << PGACTL_ALL_GAIN_Pos)
// #define PGACTL_ALL_GAIN_16X     ((0x0DUL) << PGACTL_ALL_GAIN_Pos)
// #define PGACTL_ALL_GAIN_32X     ((0x0EUL) << PGACTL_ALL_GAIN_Pos)
// #define PGACTL_ALL_GAIN_64X     ((0x0FUL) << PGACTL_ALL_GAIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SYSCTL          RSTDGWIN
 *  @access     
 *  @brief      XRSTN deglitch time-window select
 */
#define SYSCTL_ALL_RSTDGWIN_Pos (0)
#define SYSCTL_ALL_RSTDGWIN_Msk (0x7UL << SYSCTL_ALL_RSTDGWIN_Pos)

typedef enum
{
    SYSCTL_BIT_RSTDGWIN_4_US           = 0,  /*!< 4us       */
    SYSCTL_BIT_RSTDGWIN_100_US         = 1,  /*!< 100us     */
    SYSCTL_BIT_RSTDGWIN_400_US         = 2,  /*!< 400us     */
    SYSCTL_BIT_RSTDGWIN_1dot6_MS       = 3,  /*!< 1.6ms     */
    SYSCTL_BIT_RSTDGWIN_3dot2_MS       = 4,  /*!< 3.2ms     */
    SYSCTL_BIT_RSTDGWIN_6dot4_MS       = 5,  /*!< 6.4ms     */
    SYSCTL_BIT_RSTDGWIN_25dot6_MS      = 6,  /*!< 25.6ms    */
    SYSCTL_BIT_RSTDGWIN_102dot4_MS     = 7,  /*!< 102.4ms   */
} SYSCTL_BIT_RSTDGWIN;

#define SYSCTL_ALL_RSTDGWIN_4_US           ((0x0UL) << SYSCTL_ALL_RSTDGWIN_Pos)
#define SYSCTL_ALL_RSTDGWIN_100_US         ((0x1UL) << SYSCTL_ALL_RSTDGWIN_Pos)
#define SYSCTL_ALL_RSTDGWIN_400_US         ((0x2UL) << SYSCTL_ALL_RSTDGWIN_Pos)
#define SYSCTL_ALL_RSTDGWIN_1dot6_MS       ((0x3UL) << SYSCTL_ALL_RSTDGWIN_Pos)
#define SYSCTL_ALL_RSTDGWIN_3dot2_MS       ((0x4UL) << SYSCTL_ALL_RSTDGWIN_Pos)
#define SYSCTL_ALL_RSTDGWIN_6dot4_MS       ((0x5UL) << SYSCTL_ALL_RSTDGWIN_Pos)
#define SYSCTL_ALL_RSTDGWIN_25dot6_MS      ((0x6UL) << SYSCTL_ALL_RSTDGWIN_Pos)
#define SYSCTL_ALL_RSTDGWIN_102dot4_MS     ((0x7UL) << SYSCTL_ALL_RSTDGWIN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SYSCTL          VMONEN
 *  @access     
 *  @brief      Voltage monitor enable
 */
#define SYSCTL_ALL_VMONEN_Pos (3)
#define SYSCTL_ALL_VMONEN_Msk (0x1UL << SYSCTL_ALL_VMONEN_Pos)

typedef enum
{
    SYSCTL_BIT_VMONEN_DISABLE     = 0,  /*!< Disable   */
    SYSCTL_BIT_VMONEN_ENABLE      = 1,  /*!< Enable    */
} SYSCTL_BIT_VMONEN;

#define SYSCTL_ALL_VMONEN_DISABLE     ((0x0UL) << SYSCTL_ALL_VMONEN_Pos)
#define SYSCTL_ALL_VMONEN_ENABLE      ((0x1UL) << SYSCTL_ALL_VMONEN_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              SYSCTL          VMONSEL
 *  @access     
 *  @brief      Voltage monitor select
 */
#define SYSCTL_ALL_VMONSEL_Pos (4)
#define SYSCTL_ALL_VMONSEL_Msk (0x1UL << SYSCTL_ALL_VMONSEL_Pos)

typedef enum
{
    SYSCTL_BIT_VMONSEL_VBAT_DIV_30     = 0,  /*!< VBAT/30   */
    SYSCTL_BIT_VMONSEL_VDDG_DIV_10     = 1,  /*!< VDDG/10   */
} SYSCTL_BIT_VMONSEL;

#define SYSCTL_ALL_VMONSEL_VBAT_DIV_30     ((0x0UL) << SYSCTL_ALL_VMONSEL_Pos)
#define SYSCTL_ALL_VMONSEL_VDDG_DIV_10     ((0x1UL) << SYSCTL_ALL_VMONSEL_Pos)



/**
 *  @hierarchy       Module          Register        Bitfield
 *                   HV              CTLKEY          KEY
 *  @access     
 *  @brief      Key for changing critical settings
 */
#define CTLKEY_ALL_KEY_Pos (0)
#define CTLKEY_ALL_KEY_Msk (0xFFUL << CTLKEY_ALL_KEY_Pos)

typedef enum
{
    CTLKEY_BIT_KEY_LOCKKEY     = 0,  /*!< Lock all critical settings                                        */
    CTLKEY_BIT_KEY_SRSTALL     = 119,  /*!< Allow to soft-reset all registers including those marked with *   */
    CTLKEY_BIT_KEY_BUCKGEN     = 136,  /*!< Allow to write BUCKGCTL0[EN]                                      */
    CTLKEY_BIT_KEY_BUCKEN      = 153,  /*!< Allow to write BUCKCTL[EN]                                        */
    CTLKEY_BIT_KEY_ENGR        = 172,  /*!< Allow to write engineering registers                              */
    CTLKEY_BIT_KEY_DPSLP       = 187,  /*!< Allow to response to deep-sleep command                           */
} CTLKEY_BIT_KEY;

#define CTLKEY_ALL_KEY_LOCKKEY     ((0x000UL) << CTLKEY_ALL_KEY_Pos)
#define CTLKEY_ALL_KEY_SRSTALL     ((0x077UL) << CTLKEY_ALL_KEY_Pos)
#define CTLKEY_ALL_KEY_BUCKGEN     ((0x088UL) << CTLKEY_ALL_KEY_Pos)
#define CTLKEY_ALL_KEY_BUCKEN      ((0x099UL) << CTLKEY_ALL_KEY_Pos)
#define CTLKEY_ALL_KEY_ENGR        ((0x0ACUL) << CTLKEY_ALL_KEY_Pos)
#define CTLKEY_ALL_KEY_DPSLP       ((0x0BBUL) << CTLKEY_ALL_KEY_Pos)




#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* HV_BITFIELD_H */


/******************* Copyright (C) 2022 Spintrol Electronic Technology (Shanghai) Co., Ltd. ***** END OF FILE ****/
