/*******************************************************************************
 * @file     hv.h
 * @brief    High voltage module header file.
 * @version  V4.0.1
 * @date     30-July-2026
 *
 * @note
 * Copyright (C) 2022 Spintrol Electronic Technology (Shanghai) Co., Ltd.. All rights reserved.
 *
 * @attention
 * THIS SOFTWARE JUST PROVIDES CUSTOMERS WITH CODING INFORMATION REGARDING
 * THEIR PRODUCTS, WHICH AIMS AT SAVING TIME FOR THEM. SPINTROL SHALL NOT BE
 * LIABLE FOR THE USE OF THE SOFTWARE. SPINTROL DOES NOT GUARANTEE THE
 * CORRECTNESS OF THIS SOFTWARE AND RESERVES THE RIGHT TO MODIFY THE SOFTWARE
 * WITHOUT NOTIFICATION.
 *
 ******************************************************************************/

#ifndef HV_H
#define HV_H

#ifdef __cplusplus
extern "C" {
#endif


#include "epwr.h"
#include "spd1188_hv_bitfield.h"




/**
 *  @brief High Voltage Module Register Address Definition
 */
typedef enum
{
  HV_REG_GLBSTS0                  = 0x00,   /* Global Status Register 0                     */
  HV_REG_GLBSTS1                  = 0x01,   /* Global Status Register 1                     */
  HV_REG_GLBSTSCLR0               = 0x02,   /* Global Status Clear Register 0               */
  HV_REG_GLBSTSCLR1               = 0x03,   /* Global Status Clear Register 1               */
  HV_REG_PDRVTZ0SEL0              = 0x04,   /* PDRVTZ0 Select Register 0                    */
  HV_REG_PDRVTZ0SEL1              = 0x05,   /* PDRVTZ0 Select Register 1                    */
  HV_REG_PDRVTZ1SEL0              = 0x06,   /* PDRVTZ1 Select Register 0                    */
  HV_REG_PDRVTZ1SEL1              = 0x07,   /* PDRVTZ1 Select Register 1                    */
  HV_REG_BODVBATVTH               = 0x08,   /* VBAT BOD Threshold Register                  */
  HV_REG_BODVDDGVTH               = 0x09,   /* VDDG BOD Threshold Register                  */
  HV_REG_BUCKGCTL0                = 0x0A,   /* BUCKG Control Register 0                     */
  HV_REG_BUCKGCTL1                = 0x0B,   /* BUCKG Control Register 1                     */
  HV_REG_BUCK3CTL                 = 0x0C,   /* BUCK3 Control Register                       */
  HV_REG_SSCTL                    = 0x0D,   /* Spread-Spectrum Control Register             */
  HV_REG_PDRVCTL                  = 0x0E,   /* Pre-Driver Control Register                  */
  HV_REG_PDRVOCCTL                = 0x0F,   /* Pre-driver Over-Current Control Register     */
  HV_REG_PGACTL                   = 0x10,   /* PGA Control Register                         */
  HV_REG_SYSCTL                   = 0x11,   /* System Control Register                      */
  HV_REG_CTLKEY                   = 0x12,   /* Control Key Register                         */

  /* Registers For Engineering Test */
  HV_REG_LDOTRIM                  = 0x13,   /* LDO Trim Register                            */
  HV_REG_RCOTRIM                  = 0x14,   /* RCO Trim Register                            */
  HV_REG_BODREFTRIM               = 0x15,   /* BOD Reference Trim Register                  */
  HV_REG_BUCK3TRIM                = 0x16,   /* BUCK3 Trim Register                          */
  HV_REG_TONTRIM                  = 0x17,   /* BUCKG and BUCK3 Ton Trim Register            */
  HV_REG_BUCKGENGR0               = 0x18,   /* BUCKG Engineering Register 0                 */
  HV_REG_BUCKGENGR1               = 0x19,   /* BUCKG Engineering Register 1                 */
  HV_REG_BUCKGENGR2               = 0x1A,   /* BUCKG Engineering Register 2                 */
  HV_REG_BUCK3ENGR0               = 0x1B,   /* BUCK3 Engineering Register 0                 */
  HV_REG_BUCK3ENGR1               = 0x1C,   /* BUCK3 Engineering Register 1                 */
  HV_REG_MISCENGR                 = 0x1D,   /* Charge-Pump and Bandgap Enginnering Register */
  HV_REG_TESTCTL0                 = 0x1E,   /* Test Control Register 0                      */
  HV_REG_TESTCTL1                 = 0x1F    /* Test Control Register 1                      */
} HV_REGS;




/**
 *  @brief  High Voltage Module Chage-pump clock dividing value definition
 */
typedef enum
{
  HV_CHARGEPUMP_CLKDIV_8          = 0x00,    /*!< Divide by 8  */
  HV_CHARGEPUMP_CLKDIV_16         = 0x01,    /*!< Divide by 16 */
  HV_CHARGEPUMP_CLKDIV_32         = 0x02,    /*!< Divide by 32 */
  HV_CHARGEPUMP_CLKDIV_64         = 0x03,    /*!< Divide by 64 */
} HV_ChargePumpClockDivEnum;




/**
 *  @brief  High Voltage Module Pin Interface Definition
 */
#define GPIO_HV_PWM_W_L           GPIO_24   /*!< GPIO for PWM_W_L           */
#define GPIO_HV_PWM_W_H           GPIO_25   /*!< GPIO for PWM_W_H           */
#define GPIO_HV_PWM_V_L           GPIO_26   /*!< GPIO for PWM_V_L           */
#define GPIO_HV_PWM_V_H           GPIO_27   /*!< GPIO for PWM_V_H           */
#define GPIO_HV_PWM_U_L           GPIO_28   /*!< GPIO for PWM_U_L           */
#define GPIO_HV_PWM_U_H           GPIO_29   /*!< GPIO for PWM_U_H           */




/**
 *  @brief  High Voltage Module Communication Command
 */
#define HV_CMD_READ_ID            (0x514E4944UL)
#define HV_CMD_WRITE              (0x5740005AUL)
#define HV_CMD_EXECUTE            (0x45786563UL)
#define HV_CMD_READ               (0x5240445AUL)
#define HV_CMD_RESET              (0x5253544EUL)
#define HV_CMD_DEEP_SLEEP         (0x5057444EUL)




/**
 *  @brief  High Voltage Module Masked Response
 */
#define HV_RESP_READ_ID           (0x49444700UL)
#define HV_RESP_WRITE             (0x57A0005AUL)
#define HV_RESP_EXECUTE           (0x446F6E65UL)
#define HV_RESP_READ              (0x52A00000UL)
#define HV_RESP_RESET             (0x446F6E65UL)
#define HV_RESP_DEEP_SLEEP        (0x446F6E65UL)




/**
 *  @brief  High Voltage Module timeout count number
 */
#define HV_TIMEOUT_MAX            (100000U)




/**
 *  @brief  High Voltage Module SPI Communication Maximum Clock Frequency
 */
#define HV_SPI_MAX_CLK            (40000000)  /*!< 40 MHz */




/**
 *  @brief  High Voltage Module Register Address Check
 */
#define IS_HV_REG(u8Addr)         ((u8Addr) <= 0x1F)




/**
 *  @brief  High Voltage Module Public Function Declaration
 */
ErrorStatus HV_ComInit(uint32_t u32Baudrate);
ErrorStatus HV_Init(uint32_t u32Baudrate, uint8_t *pu8ID, uint32_t u32Timeout);

ErrorStatus HV_Handshake(uint8_t *pu8ID, uint32_t u32Timeout);
ErrorStatus HV_Command(uint32_t u32Req, uint32_t *pu32Resp);

ErrorStatus HV_WriteReg(uint8_t u8Addr, uint8_t u8Data);
ErrorStatus HV_ReadReg(uint8_t u8Addr, uint8_t *pu8Data);
ErrorStatus HV_WriteRegField(uint8_t u8Addr, uint8_t u8Mask, uint8_t u8FieldData);

ErrorStatus HV_InitReg(void);
ErrorStatus HV_ResetReg(void);
ErrorStatus HV_DeepSleep(void);

void HV_ConnectAnalogTestToADC(void);
ErrorStatus HV_ConnectTSensorToAnalogTest(void);

ErrorStatus HV_SetChargePumpClockDiv(HV_ChargePumpClockDivEnum eClockDiv);
ErrorStatus HV_GetChargePumpClockDiv(uint8_t *pu8Data);

#ifdef __cplusplus
}
#endif /* extern "C" */

#endif /* HV_H */


/******************* Copyright (C) 2022 Spintrol Electronic Technology (Shanghai) Co., Ltd. ***** END OF FILE ****/
